From: Heiko Stuebner <heiko@sntech.de> To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, heiko@sntech.de, christoph.muellner@theobroma-systems.com, zhangqing@rock-chips.com, Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Subject: [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll_timeout Date: Tue, 28 Jan 2020 11:02:01 +0100 [thread overview] Message-ID: <20200128100204.1318450-1-heiko@sntech.de> (raw) From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Instead of open coding the polling of the lock status, use the handy readl_poll_timeout for this. As the pll locking is normally blazingly fast and we don't want to incur additional delays, we're not doing any sleeps similar to for example the imx clk-pllv4 and define a very safe but still short timeout of 1ms. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> --- drivers/clk/rockchip/clk-pll.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 198417d56300..43c9fd0086a2 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -585,19 +585,18 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) { u32 pllcon; - int delay = 24000000; + int ret; - /* poll check the lock status in rk3399 xPLLCON2 */ - while (delay > 0) { - pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); - if (pllcon & RK3399_PLLCON2_LOCK_STATUS) - return 0; + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_poll_timeout(pll->reg_base + RK3399_PLLCON(2), pllcon, + pllcon & RK3399_PLLCON2_LOCK_STATUS, 0, 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); - delay--; - } - - pr_err("%s: timeout waiting for pll to lock\n", __func__); - return -ETIMEDOUT; + return ret; } static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: linux-clk@vger.kernel.org Cc: heiko@sntech.de, sboyd@kernel.org, Heiko Stuebner <heiko.stuebner@theobroma-systems.com>, mturquette@baylibre.com, zhangqing@rock-chips.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, christoph.muellner@theobroma-systems.com Subject: [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll_timeout Date: Tue, 28 Jan 2020 11:02:01 +0100 [thread overview] Message-ID: <20200128100204.1318450-1-heiko@sntech.de> (raw) From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Instead of open coding the polling of the lock status, use the handy readl_poll_timeout for this. As the pll locking is normally blazingly fast and we don't want to incur additional delays, we're not doing any sleeps similar to for example the imx clk-pllv4 and define a very safe but still short timeout of 1ms. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> --- drivers/clk/rockchip/clk-pll.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 198417d56300..43c9fd0086a2 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -585,19 +585,18 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = { static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) { u32 pllcon; - int delay = 24000000; + int ret; - /* poll check the lock status in rk3399 xPLLCON2 */ - while (delay > 0) { - pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); - if (pllcon & RK3399_PLLCON2_LOCK_STATUS) - return 0; + /* + * Lock time typical 250, max 500 input clock cycles @24MHz + * So define a very safe maximum of 1000us, meaning 24000 cycles. + */ + ret = readl_poll_timeout(pll->reg_base + RK3399_PLLCON(2), pllcon, + pllcon & RK3399_PLLCON2_LOCK_STATUS, 0, 1000); + if (ret) + pr_err("%s: timeout waiting for pll to lock\n", __func__); - delay--; - } - - pr_err("%s: timeout waiting for pll to lock\n", __func__); - return -ETIMEDOUT; + return ret; } static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2020-01-28 10:02 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-28 10:02 Heiko Stuebner [this message] 2020-01-28 10:02 ` [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll_timeout Heiko Stuebner 2020-01-28 10:02 ` [PATCH 2/3] clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout Heiko Stuebner 2020-01-28 10:02 ` Heiko Stuebner 2020-01-28 10:02 ` [PATCH 3/3] clk: rockchip: convert rk3036 pll type to use internal lock status Heiko Stuebner 2020-01-28 10:02 ` Heiko Stuebner 2020-01-28 15:28 ` [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll_timeout Robin Murphy 2020-01-28 15:28 ` Robin Murphy 2020-01-28 16:29 ` Heiko Stuebner 2020-01-28 16:29 ` Heiko Stuebner 2020-01-28 18:43 ` Robin Murphy 2020-01-28 18:43 ` Robin Murphy
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