From: Kishon Vijay Abraham I <kishon@ti.com> To: Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <kishon@ti.com> Subject: [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Date: Wed, 6 May 2020 20:44:25 +0530 [thread overview] Message-ID: <20200506151429.12255-11-kishon@ti.com> (raw) In-Reply-To: <20200506151429.12255-1-kishon@ti.com> Add host mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..d7b60487c6c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +allOf: + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + vendor-id: + const: 0x104c + + device-id: + const: 0xb00d + + msi-map: true + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - vendor-id + - device-id + - msi-map + - dma-coherent + - dma-ranges + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + #include <dt-bindings/gpio/gpio.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + }; -- 2.17.1
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From: Kishon Vijay Abraham I <kishon@ti.com> To: Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com> Cc: devicetree@vger.kernel.org, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, linux-kernel@vger.kernel.org, kishon@ti.com, linux-pci@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Date: Wed, 6 May 2020 20:44:25 +0530 [thread overview] Message-ID: <20200506151429.12255-11-kishon@ti.com> (raw) In-Reply-To: <20200506151429.12255-1-kishon@ti.com> Add host mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..d7b60487c6c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +allOf: + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + vendor-id: + const: 0x104c + + device-id: + const: 0xb00d + + msi-map: true + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - vendor-id + - device-id + - msi-map + - dma-coherent + - dma-ranges + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + #include <dt-bindings/gpio/gpio.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-06 15:15 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-06 15:14 [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 20:59 ` Rob Herring 2020-05-20 20:59 ` Rob Herring 2020-05-06 15:14 ` [PATCH v4 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 21:00 ` Rob Herring 2020-05-20 21:00 ` Rob Herring 2020-05-06 15:14 ` [PATCH v4 03/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 21:02 ` Rob Herring 2020-05-20 21:02 ` Rob Herring 2020-05-20 22:07 ` Rob Herring 2020-05-20 22:07 ` Rob Herring 2020-05-21 13:33 ` Kishon Vijay Abraham I 2020-05-21 13:33 ` Kishon Vijay Abraham I 2020-05-21 22:17 ` Rob Herring 2020-05-21 22:17 ` Rob Herring 2020-05-22 3:36 ` Kishon Vijay Abraham I 2020-05-22 3:36 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 21:06 ` Rob Herring 2020-05-20 21:06 ` Rob Herring 2020-05-06 15:14 ` [PATCH v4 05/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 21:34 ` Rob Herring 2020-05-20 21:34 ` Rob Herring 2020-05-21 11:34 ` Kishon Vijay Abraham I 2020-05-21 11:34 ` Kishon Vijay Abraham I 2020-05-22 16:45 ` Rob Herring 2020-05-22 16:45 ` Rob Herring 2020-05-23 1:24 ` Kishon Vijay Abraham I 2020-05-23 1:24 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 21:36 ` Rob Herring 2020-05-20 21:36 ` Rob Herring 2020-05-06 15:14 ` [PATCH v4 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I [this message] 2020-05-06 15:14 ` [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-06 15:14 ` [PATCH v4 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 22:12 ` Rob Herring 2020-05-20 22:12 ` Rob Herring 2020-05-06 15:14 ` [PATCH v4 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I 2020-05-06 15:14 ` Kishon Vijay Abraham I 2020-05-20 22:12 ` Rob Herring 2020-05-20 22:12 ` Rob Herring 2020-05-18 11:14 ` [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I 2020-05-18 11:14 ` Kishon Vijay Abraham I
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