From: Kishon Vijay Abraham I <kishon@ti.com> To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>, Rob Herring <robh+dt@kernel.org>, Roger Quadros <rogerq@ti.com>, Lee Jones <lee.jones@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com>, <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 5/7] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Date: Mon, 9 Nov 2020 22:34:07 +0530 [thread overview] Message-ID: <20201109170409.4498-6-kishon@ti.com> (raw) In-Reply-To: <20201109170409.4498-1-kishon@ti.com> Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j7200. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 7668404c178b..38dff212615d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -25,6 +25,14 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -478,6 +486,55 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + cdns,max-outbound-regions = <32>; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com> To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>, Rob Herring <robh+dt@kernel.org>, Roger Quadros <rogerq@ti.com>, Lee Jones <lee.jones@linaro.org> Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I <kishon@ti.com>, Bjorn Helgaas <bhelgaas@google.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/7] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Date: Mon, 9 Nov 2020 22:34:07 +0530 [thread overview] Message-ID: <20201109170409.4498-6-kishon@ti.com> (raw) In-Reply-To: <20201109170409.4498-1-kishon@ti.com> Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j7200. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 7668404c178b..38dff212615d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -25,6 +25,14 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -478,6 +486,55 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + cdns,max-outbound-regions = <32>; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-09 17:04 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-09 17:04 [PATCH v2 0/7] J7200: Add PCIe DT nodes to Enable PCIe Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-09 17:04 ` [PATCH v2 1/7] dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "syscon" Kishon Vijay Abraham I 2020-11-09 17:04 ` [PATCH v2 1/7] dt-bindings: mfd: ti, j721e-system-controller.yaml: " Kishon Vijay Abraham I 2020-11-11 21:28 ` [PATCH v2 1/7] dt-bindings: mfd: ti,j721e-system-controller.yaml: " Rob Herring 2020-11-11 21:28 ` Rob Herring 2020-11-12 5:25 ` Kishon Vijay Abraham I 2020-11-12 5:25 ` [PATCH v2 1/7] dt-bindings: mfd: ti, j721e-system-controller.yaml: " Kishon Vijay Abraham I 2020-11-12 16:46 ` [PATCH v2 1/7] dt-bindings: mfd: ti,j721e-system-controller.yaml: " Rob Herring 2020-11-12 16:46 ` [PATCH v2 1/7] dt-bindings: mfd: ti, j721e-system-controller.yaml: " Rob Herring 2020-11-09 17:04 ` [PATCH v2 2/7] dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-09 17:04 ` [PATCH v2 3/7] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-09 17:04 ` [PATCH v2 4/7] arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I [this message] 2020-11-09 17:04 ` [PATCH v2 5/7] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Kishon Vijay Abraham I 2020-11-12 16:05 ` Vignesh Raghavendra 2020-11-12 16:05 ` Vignesh Raghavendra 2020-11-09 17:04 ` [PATCH v2 6/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-12 15:58 ` Vignesh Raghavendra 2020-11-12 15:58 ` Vignesh Raghavendra 2020-11-09 17:04 ` [PATCH v2 7/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Kishon Vijay Abraham I 2020-11-09 17:04 ` Kishon Vijay Abraham I 2020-11-12 15:56 ` Vignesh Raghavendra 2020-11-12 15:56 ` Vignesh Raghavendra
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20201109170409.4498-6-kishon@ti.com \ --to=kishon@ti.com \ --cc=bhelgaas@google.com \ --cc=devicetree@vger.kernel.org \ --cc=lee.jones@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=nm@ti.com \ --cc=robh+dt@kernel.org \ --cc=rogerq@ti.com \ --cc=t-kristo@ti.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.