From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Peter Rosin <peda@axentia.se>,
Swapnil Jakhade <sjakhade@cadence.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-phy@lists.infradead.org>
Subject: [PATCH v2 3/9] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
Date: Mon, 22 Feb 2021 16:53:08 +0530 [thread overview]
Message-ID: <20210222112314.10772-4-kishon@ti.com> (raw)
In-Reply-To: <20210222112314.10772-1-kishon@ti.com>
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Peter Rosin <peda@axentia.se>
---
include/dt-bindings/mux/ti-serdes.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 9047ec6bd3cf..d417b9268b16 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -90,4 +90,9 @@
#define J7200_SERDES0_LANE3_USB 0x2
#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
+/* AM64 */
+
+#define AM64_SERDES0_LANE0_PCIE0 0x0
+#define AM64_SERDES0_LANE0_USB 0x1
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Peter Rosin <peda@axentia.se>,
Swapnil Jakhade <sjakhade@cadence.com>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/9] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
Date: Mon, 22 Feb 2021 16:53:08 +0530 [thread overview]
Message-ID: <20210222112314.10772-4-kishon@ti.com> (raw)
In-Reply-To: <20210222112314.10772-1-kishon@ti.com>
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Peter Rosin <peda@axentia.se>
---
include/dt-bindings/mux/ti-serdes.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 9047ec6bd3cf..d417b9268b16 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -90,4 +90,9 @@
#define J7200_SERDES0_LANE3_USB 0x2
#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
+/* AM64 */
+
+#define AM64_SERDES0_LANE0_PCIE0 0x0
+#define AM64_SERDES0_LANE0_USB 0x1
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
--
2.17.1
--
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next prev parent reply other threads:[~2021-02-22 11:26 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 11:23 [PATCH v2 0/9] AM64: Add SERDES bindings and driver support Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 1/9] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 1/9] dt-bindings: phy: ti, phy-j721e-wiz: " Kishon Vijay Abraham I
2021-03-04 4:45 ` [PATCH v2 1/9] dt-bindings: phy: ti,phy-j721e-wiz: " Kishon Vijay Abraham I
2021-03-04 4:45 ` Kishon Vijay Abraham I
2021-03-08 17:50 ` Rob Herring
2021-03-08 17:50 ` Rob Herring
2021-02-22 11:23 ` [PATCH v2 2/9] dt-bindings: phy: cadence-torrent: Add binding for refclk driver Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-03-08 17:51 ` Rob Herring
2021-03-08 17:51 ` Rob Herring
2021-02-22 11:23 ` Kishon Vijay Abraham I [this message]
2021-02-22 11:23 ` [PATCH v2 3/9] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Kishon Vijay Abraham I
2021-03-08 17:52 ` Rob Herring
2021-03-08 17:52 ` Rob Herring
2021-02-22 11:23 ` [PATCH v2 4/9] phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 5/9] phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 6/9] phy: ti: j721e-wiz: Configure full rate divider for AM64 Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 7/9] phy: ti: j721e-wiz: Model the internal clocks without device tree input Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 8/9] phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 11:23 ` [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out Kishon Vijay Abraham I
2021-02-22 11:23 ` Kishon Vijay Abraham I
2021-02-22 19:45 ` kernel test robot
2021-02-22 19:45 ` kernel test robot
2021-02-22 19:45 ` kernel test robot
2021-03-09 14:21 ` Swapnil Kashinath Jakhade
2021-03-09 14:21 ` Swapnil Kashinath Jakhade
2021-03-10 10:24 ` Kishon Vijay Abraham I
2021-03-10 10:24 ` Kishon Vijay Abraham I
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