[U-Boot] [PATCH 00/22] U-Boot MMC SPL for OMAP4

[U-Boot] [PATCH 00/22] U-Boot MMC SPL for OMAP4

[Aneesh V]

This series adds mmc SPL support for OMAP4. This is essentially
an up-streaming effort for TI's x-loader for OMAP4 using the SPL
framework

This work partly draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>
and many others

Features supported:
* Clock init - DPLL locking, clock domains/modules enabling
* SDRAM/DMM initialization
* Mux initialization
* MMC raw read support
* MMC FAT read support

Improvments over x-loader:
* Code completely revamped
* DPLL programming that works for all SYS_CLK frequencies
* Automatic SDRAM identification and initialization
* Board dependent parts(especially mux) deferred to u-boot. So, same
  SPL will work for Panda and SDP and most likely on any other board
  that comes along
* Determination of u-boot size to avoid reading extra content while
  loading U-Boot
* Modular apporach to enable future addition of support for all OMAP3/4
  platforms

Aneesh V (21):
  omap: add miscellaneous utility macros for bit-field operations
  omap4: add OMAP4430 revision check
  armv7: start.S: provide a hook for saving boot params
  omap4: save parameters passed by ROM code to SPL
  arm: new labels in the linker script file
  Add generic spl infrastructure
  armv7: start.S: add SPL support
  omap: add spl support
  omap4: add spl support for OMAP4 SDP
  omap4: add serial console support to SPL
  omap4: utility function to identify the context of hw init
  omap4: separate mux settings into essential and non essential parts
  omap4: correct mux data for sdp4430
  omap4: add clock support
  omap4: add sdram init support
  omap4: calculate EMIF register values
  omap4: automatic sdram detection
  armv7: embed u-boot size within u-boot for use from SPL
  omap: add MMC support to SPL
  omap: spl: add FAT support over MMC
  omap4: add spl support for OMAP4 Panda

John Rigby (1):
  mkimage: Add OMAP boot image support

 Makefile                                           |   11 +
 arch/arm/cpu/armv7/cpu.c                           |    7 +
 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 .../{omap4/lowlevel_init.S => omap-common/utils.c} |   58 +-
 arch/arm/cpu/armv7/omap4/Makefile                  |    3 +
 arch/arm/cpu/armv7/omap4/board.c                   |  117 ++-
 arch/arm/cpu/armv7/omap4/clocks.c                  |  717 +++++++++++
 arch/arm/cpu/armv7/omap4/emif.c                    | 1303 ++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  267 ++++
 arch/arm/cpu/armv7/start.S                         |   50 +-
 arch/arm/cpu/armv7/u-boot.lds                      |    4 +
 arch/arm/include/asm/arch-omap4/clocks.h           |  504 ++++++++
 arch/arm/include/asm/arch-omap4/emif.h             | 1021 +++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |   50 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |   60 +-
 .../omap4/lowlevel_init.S => include/asm/armv7.h}  |   32 +-
 arch/arm/include/asm/global_data.h                 |    5 +
 arch/arm/include/asm/omap_common.h                 |  106 ++
 board/ti/panda/panda.c                             |   25 +-
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +-
 board/ti/sdp4430/config.mk                         |    3 +-
 board/ti/sdp4430/sdp.c                             |   25 +-
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +--
 common/image.c                                     |    1 +
 include/configs/omap4_panda.h                      |   24 +
 include/configs/omap4_sdp4430.h                    |   24 +
 include/image.h                                    |    1 +
 spl/board/ti/panda/Makefile                        |  219 ++++
 spl/board/ti/sdp4430/Makefile                      |  219 ++++
 spl/board/ti/spl-omap.c                            |  189 +++
 .../armv7/u-boot.lds => spl/board/ti/spl-omap.lds  |   70 +-
 tools/Makefile                                     |    2 +
 tools/mkimage.c                                    |    2 +
 tools/mkimage.h                                    |    1 +
 tools/omapimage.c                                  |  229 ++++
 .../omap4/lowlevel_init.S => tools/omapimage.h     |   49 +-
 38 files changed, 5390 insertions(+), 320 deletions(-)
 copy arch/arm/cpu/armv7/{omap4/lowlevel_init.S => omap-common/utils.c} (50%)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
 copy arch/arm/{cpu/armv7/omap4/lowlevel_init.S => include/asm/armv7.h} (62%)
 create mode 100644 arch/arm/include/asm/omap_common.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)
 create mode 100644 spl/board/ti/panda/Makefile
 create mode 100644 spl/board/ti/sdp4430/Makefile
 create mode 100644 spl/board/ti/spl-omap.c
 copy arch/arm/cpu/armv7/u-boot.lds => spl/board/ti/spl-omap.lds (57%)
 create mode 100644 tools/omapimage.c
 copy arch/arm/cpu/armv7/omap4/lowlevel_init.S => tools/omapimage.h (53%)

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

From: John Rigby <john.rigby@linaro.org>

Signed-off-by: John Rigby <john.rigby@linaro.org>
---
 common/image.c    |    1 +
 include/image.h   |    1 +
 tools/Makefile    |    2 +
 tools/mkimage.c   |    2 +
 tools/mkimage.h   |    1 +
 tools/omapimage.c |  229 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/omapimage.h |   50 ++++++++++++
 7 files changed, 286 insertions(+), 0 deletions(-)
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

diff --git a/common/image.c b/common/image.c
index f63a2ff..4198d76 100644
--- a/common/image.c
+++ b/common/image.c
@@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index 005e0d2..f74e2b9 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 623f908..a1c4ed7 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
 OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
@@ -180,6 +181,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
 			$(obj)fit_image.o \
 			$(obj)image.o \
 			$(obj)imximage.o \
+			$(obj)omapimage.o \
 			$(obj)kwbimage.o \
 			$(obj)md5.o \
 			$(obj)mkimage.o \
diff --git a/tools/mkimage.c b/tools/mkimage.c
index f5859d7..ec6d75e 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -155,6 +155,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 9033a7d..3b49645 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/omapimage.c b/tools/omapimage.c
new file mode 100644
index 0000000..67fa056
--- /dev/null
+++ b/tools/omapimage.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "omapimage.h"
+
+/* Header size is CH header rounded up to 512 bytes plus GP header */
+#define OMAP_CH_HDR_SIZE 512
+#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+
+static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
+
+static int omapimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_OMAPIMAGE)
+		return EXIT_SUCCESS;
+	else
+		return EXIT_FAILURE;
+}
+
+/*
+ * Only the simplest image type is currently supported:
+ * TOC pointing to CHSETTINGS
+ * TOC terminator
+ * CHSETTINGS
+ *
+ * padding to OMAP_CH_HDR_SIZE bytes
+ *
+ * gp header
+ *   size
+ *   load_addr
+ */
+static int valid_gph_size(uint32_t size)
+{
+	return size;
+}
+
+static int valid_gph_load_addr(uint32_t load_addr)
+{
+	return load_addr;
+}
+
+static int omapimage_verify_header(unsigned char *ptr, int image_size,
+			struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+		if (!offset || !size)
+			return -1;
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			return -1;
+		toc++;
+	}
+	if (!valid_gph_size(gph->size))
+		return -1;
+	if (!valid_gph_load_addr(gph->load_addr))
+		return -1;
+
+	return 0;
+}
+
+static void omapimage_print_section(struct ch_settings *chs)
+{
+	switch (chs->section_key) {
+	case KEY_CHSETTINGS:
+		printf("CHSETTINGS (%x) "
+			"valid:%x "
+			"version:%x "
+			"reserved:%x "
+			"flags:%x\n",
+			chs->section_key,
+			chs->valid,
+			chs->version,
+			chs->reserved,
+			chs->flags);
+		break;
+	default:
+		printf("UNKNOWNKEY (%x) "
+			"valid:%x "
+			"version:%x "
+			"reserved:%x "
+			"flags:%x\n",
+			chs->section_key,
+			chs->valid,
+			chs->version,
+			chs->reserved,
+			chs->flags);
+		break;
+	}
+}
+
+static void omapimage_print_header(const void *ptr)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			exit(EXIT_FAILURE);
+
+		printf("Section %s offset %x length %x\n",
+			toc->section_name,
+			toc->section_offset,
+			toc->section_size);
+
+		omapimage_print_section((struct ch_settings *)(ptr+offset));
+		toc++;
+	}
+
+	if (!valid_gph_size(gph->size)) {
+		fprintf(stderr,
+			"Error: invalid image size %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!valid_gph_load_addr(gph->load_addr)) {
+		fprintf(stderr,
+			"Error: invalid image load address %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	printf("GP Header: Size %x LoadAddr %x\n",
+		gph->size, gph->load_addr);
+}
+
+static int toc_offset(void *hdr, void *member)
+{
+	return member - hdr;
+}
+
+static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct ch_settings *chs = (struct ch_settings *)
+					(ptr + 2 * sizeof(*toc));
+	struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE);
+
+	toc->section_offset = toc_offset(ptr, chs);
+	toc->section_size = sizeof(struct ch_settings);
+	strcpy((char *)toc->section_name, "CHSETTINGS");
+
+	chs->section_key = KEY_CHSETTINGS;
+	chs->valid = 0;
+	chs->version = 1;
+	chs->reserved = 0;
+	chs->flags = 0;
+
+	toc++;
+	memset(toc, 0xff, sizeof(*toc));
+
+	gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
+	gph->load_addr = params->addr;
+}
+
+int omapimage_check_params(struct mkimage_params *params)
+{
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+/*
+ * omapimage parameters
+ */
+static struct image_type_params omapimage_params = {
+	.name		= "TI OMAP CH/GP Boot Image support",
+	.header_size	= OMAP_FILE_HDR_SIZE,
+	.hdr		= (void *)&omapimage_header,
+	.check_image_type = omapimage_check_image_types,
+	.verify_header	= omapimage_verify_header,
+	.print_header	= omapimage_print_header,
+	.set_header	= omapimage_set_header,
+	.check_params	= omapimage_check_params,
+};
+
+void init_omap_image_type(void)
+{
+	mkimage_register(&omapimage_params);
+}
diff --git a/tools/omapimage.h b/tools/omapimage.h
new file mode 100644
index 0000000..7ff5404
--- /dev/null
+++ b/tools/omapimage.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAPIMAGE_H_
+#define _OMAPIMAGE_H_
+
+struct ch_toc {
+	uint32_t section_offset;
+	uint32_t section_size;
+	uint8_t unused[12];
+	uint8_t section_name[12];
+} __attribute__ ((__packed__));
+
+struct ch_settings {
+	uint32_t section_key;
+	uint8_t valid;
+	uint8_t version;
+	uint16_t reserved;
+	uint32_t flags;
+} __attribute__ ((__packed__));
+
+struct gp_header {
+	uint32_t size;
+	uint32_t load_addr;
+} __attribute__ ((__packed__));
+
+#define KEY_CHSETTINGS 0xC0C0C0C1
+#endif /* _OMAPIMAGE_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH 02/22] omap: add miscellaneous utility macros for bit-field operations

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/include/asm/omap_common.h |   51 ++++++++++++++++++++++++++++++++++++
 1 files changed, 51 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..03db2f5
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* extract a bit field from a bit vector */
+#define get_bit_field(nr, start, mask)\
+	(((nr) & (mask)) >> (start))
+
+/* Set a field in a bit vector */
+#define set_bit_field(nr, start, mask, val)\
+	do { \
+		(nr) = ((nr) & ~(mask)) | (((val) << (start)) & (mask));\
+	} while (0);
+
+/*
+ * Utility macro for read-modify-write of a hardware register
+ *	addr - address of the register
+ *	shift - starting bit position of the field to be modified
+ *	msk - mask for the field
+ *	val - value to be shifted masked and written to the field
+ */
+#define modify_reg_32(addr, shift, msk, val) \
+	do {\
+		writel(((readl(addr) & ~(msk))|(((val) << (shift)) & (msk))),\
+		       (addr));\
+	} while (0);
+
+#endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH 03/22] omap4: add OMAP4430 revision check

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c        |   35 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h |   17 +++++++++-----
 arch/arm/include/asm/armv7.h            |   31 +++++++++++++++++++++++++++
 3 files changed, 77 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/armv7.h

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index fcd29a7..7583a0d 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
@@ -127,3 +128,37 @@ int arch_cpu_init(void)
 	set_muxconf_regs();
 	return 0;
 }
+
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+u32 omap4_revision(void)
+{
+	if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1)
+		return OMAP4430_ES2_1;
+	else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2)
+		return OMAP4430_ES2_2;
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int rev = cortex_a9_rev();
+
+	switch (rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		return OMAP4430_ES1_0;
+	case MIDR_CORTEX_A9_R1P2:
+		return OMAP4430_ES2_0;
+	default:
+		return OMAP4430_SILICON_ID_INVALID;
+	}
+}
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..1f88732 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -121,11 +126,11 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0
+#define OMAP4430_ES1_0	1
+#define OMAP4430_ES2_0	2
+#define OMAP4430_ES2_1	3
+#define OMAP4430_ES2_2	4
 
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
new file mode 100644
index 0000000..6c24a80
--- /dev/null
+++ b/arch/arm/include/asm/armv7.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef ARMV7_H
+#define ARMV7_H
+
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+
+#endif /* ARMV7_H */
-- 
1.7.0.4

[U-Boot] [PATCH 04/22] armv7: start.S: provide a hook for saving boot params

[Aneesh V]

Provide a means by which u-boot/SPL can save parameters passed
to it by ROM code or the pre-loader.

A new function 'save_boot_params' has been defined and a default
implentation provided. Please note that we do not have a stack yet.
So, any implementation of this function should not use stack.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/cpu.c   |    7 +++++++
 arch/arm/cpu/armv7/start.S |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index a01e0d6..54533fc 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -41,6 +41,13 @@
 
 static void cache_flush(void);
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	unsigned int i;
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index cb4f92f..3618190 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -103,6 +103,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
-- 
1.7.0.4

[U-Boot] [PATCH 05/22] omap4: save parameters passed by ROM code to SPL

[Aneesh V]

Save boot device information passed by OMAP4 rom code

ROM code in OMAP4 passes information such as the media from
which it picked up the first boot image(SPL in our case),
the mode(raw mode/FAT mode) etc.

Save this information in SPL so that we can use the same media
and mode to bootload u-boot.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c            |   14 ++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S    |   31 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |    8 +++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 arch/arm/include/asm/omap_common.h          |   20 +++++++++++++++++
 5 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 7583a0d..a5d585b 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -35,6 +35,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_PRELOADER
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 /*
  * Routine: s_init
  * Description: Does early system init of muxing and clocks.
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa4..250c73d 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_PRELOADER
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 1f88732..740ca9d 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -133,4 +133,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_1	3
 #define OMAP4430_ES2_2	4
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4813e9e..ce86b36 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -23,6 +23,7 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 03db2f5..06c511c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -48,4 +48,24 @@
 		       (addr));\
 	} while (0);
 
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+/* Magic number passed from SPL to U-Boot */
+#define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
 #endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH 06/22] arm: new labels in the linker script file

[Aneesh V]

_bss_start_ofs is used in start.S to indicate end of copied
image. This may not be correct when we have a discontiguous
memory map. For instance, .bss may be placed in SDRAM for
some SPLS while rest of the image is placed in SRAM.

Define a new label in linker script to indicate the end of the
image copied during relocation and use it appropriately in
start.S.

Also, add a new label to indicate the end of flash image.
This will be useful in identifying the size of flash image

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/start.S    |    6 +++++-
 arch/arm/cpu/armv7/u-boot.lds |    4 ++++
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 3618190..8215d26 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -77,6 +77,10 @@ _TEXT_BASE:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word _end - _start
@@ -172,7 +176,7 @@ stack_setup:
 	beq	clear_bss		/* skip relocation */
 #endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index 5725c30..c3ad587 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
@@ -66,6 +68,8 @@ SECTIONS
 		*(.dynsym)
 	}
 
+	__flash_image_end = .;
+
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
 		*(.bss)
-- 
1.7.0.4

[U-Boot] [PATCH 07/22] Add generic spl infrastructure

[Aneesh V]

Define a new type of SPL that is not tied to any particular media.
- Create a top level directory 'spl' that has a structure similar
  to the existing 'nand_spl'
- Make necessary changes to top-level Makefile to build such an spl

Rationale for this approach:
- There may be SPLs(like the OMAP x-loader) that support booting from
  multiple media.
- Also, there is no harm in keeping SPLs specific to a particular media
  also under this directory. In fact it makes sense to merge all the
  different spl directories into this one.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 Makefile                           |   11 +++++++++++
 arch/arm/include/asm/global_data.h |    5 +++++
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile
index dc2e3d8..21e51c8 100644
--- a/Makefile
+++ b/Makefile
@@ -293,6 +293,11 @@ NAND_SPL = nand_spl
 U_BOOT_NAND = $(obj)u-boot-nand.bin
 endif
 
+ifeq ($(CONFIG_SPL),y)
+.PHONEY : SPL
+ALL += SPL
+endif
+
 ifeq ($(CONFIG_ONENAND_U_BOOT),y)
 ONENAND_IPL = onenand_ipl
 U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
@@ -402,6 +407,9 @@ $(LDSCRIPT):	depend
 $(obj)u-boot.lds: $(LDSCRIPT)
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
+SPL		:$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
+		$(MAKE) -C spl/board/$(BOARDDIR) all
+
 $(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
@@ -1138,6 +1146,7 @@ clean:
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)spl/{u-boot-spl-generated.lds,u-boot-spl,u-boot-spl.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
 	@rm -f $(ONENAND_BIN)
 	@rm -f $(obj)onenand_ipl/u-boot.lds
@@ -1157,12 +1166,14 @@ clobber:	clean
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
 	@rm -f $(obj)u-boot.kwb
 	@rm -f $(obj)u-boot.imx
+	@rm -f $(obj)MLO
 	@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
 	@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+	@[ ! -d $(obj)spl ] || find $(obj)spl -name "*" -type l -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))
 mrproper \
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 2a84d27..2ce020e 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -89,6 +89,11 @@ typedef	struct	global_data {
 #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
 #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
 
+#ifdef CONFIG_PRELOADER
+/* SPL works from internal RAM. gd pointer can be in .data section */
+#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
+#else
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+#endif
 
 #endif /* __ASM_GBL_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH 08/22] armv7: start.S: add SPL support

[Aneesh V]

Changes for supporting SPL

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/start.S |   36 +++++++++++++++++++++++++-----------
 1 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 8215d26..f5f08d9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_PRELOADER
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_PRELOADER */
+
 .global _end_vect
 _end_vect:
 
@@ -171,10 +182,9 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_PRELOADER
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
@@ -224,6 +234,15 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_PRELOADER */
 
 clear_bss:
 	ldr	r0, _bss_start_ofs
@@ -237,7 +256,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_PRELOADER */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -257,13 +275,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -300,6 +311,8 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+
+#ifndef CONFIG_PRELOADER
 /*
  *************************************************************************
  *
@@ -488,3 +501,4 @@ fiq:
 	bl	do_fiq
 
 #endif
+#endif /* CONFIG_PRELOADER */
-- 
1.7.0.4

[U-Boot] [PATCH 09/22] omap: add spl support

[Aneesh V]

Add the basic spl framework and linker script common for OMAP3/4
platforms.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 spl/board/ti/spl-omap.c   |   47 ++++++++++++++++++++++++++++++++++
 spl/board/ti/spl-omap.lds |   62 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 spl/board/ti/spl-omap.c
 create mode 100644 spl/board/ti/spl-omap.lds

diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
new file mode 100644
index 0000000..0e08f4f
--- /dev/null
+++ b/spl/board/ti/spl-omap.c
@@ -0,0 +1,47 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+
+/* Define global data structure pointer to it*/
+gd_t gdata __attribute__ ((section(".data")));
+bd_t bdata __attribute__ ((section(".data")));
+gd_t *gd = &gdata;
+
+void board_init_f(ulong dummy)
+{
+	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}
diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds
new file mode 100644
index 0000000..27b5295
--- /dev/null
+++ b/spl/board/ti/spl-omap.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
+		 LENGTH = CONFIG_SYS_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \
+		  LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	. = ALIGN(32);
+	__start = .;
+	  start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		_end = .;
+	} >.sdram
+}
-- 
1.7.0.4

[U-Boot] [PATCH 10/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Adapted from: nand_spl/board/samsung/smdk6400/Makefile

- Add the SPL makefile for OMAP4430 SDP
- Add the necessary CONFIG flags in the board config file

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 board/ti/sdp4430/config.mk      |    3 +-
 include/configs/omap4_sdp4430.h |   19 ++++++
 spl/board/ti/sdp4430/Makefile   |  120 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 141 insertions(+), 1 deletions(-)
 create mode 100644 spl/board/ti/sdp4430/Makefile

diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
index 33901a7..c62965d 100644
--- a/board/ti/sdp4430/config.mk
+++ b/board/ti/sdp4430/config.mk
@@ -28,4 +28,5 @@
 # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
 # (mem base + reserved)
 
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 9a8bb73..5b20841 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -122,7 +122,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */
@@ -240,4 +242,21 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
new file mode 100644
index 0000000..dd56a40
--- /dev/null
+++ b/spl/board/ti/sdp4430/Makefile
@@ -0,0 +1,120 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+splobj	:= $(OBJTREE)/spl/
+include $(TOPDIR)/config.mk
+SOBJS =
+COBJS =
+
+# armv7
+$(obj)start.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
+
+$(obj)syslib.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@
+
+SOBJS	+= start.o
+COBJS	+= syslib.o
+
+# omap-common
+$(obj)timer.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@
+
+$(obj)reset.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@
+
+$(obj)spl-omap.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@
+
+SOBJS	+= reset.o
+COBJS	+= timer.o spl-omap.o
+
+$(OBJTREE)/MLO:	$(splobj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@
+
+LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds
+
+# omap4
+$(obj)lowlevel_init.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@
+
+$(obj)omap4_mux_data.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@
+
+$(obj)board.c:$(obj)omap4_mux_data.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
+
+SOBJS	+= lowlevel_init.o
+COBJS	+= board.o
+
+# rules
+LDPPFLAGS += -include $(TOPDIR)/include/config.h
+LDSCRIPT = $(splobj)u-boot-spl-generated.lds
+$(LDSCRIPT): $(LDSCRIPT_SOURCE)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) \
+	$(PLATFORM_LDFLAGS) --gc-sections
+AFLAGS	+= -DCONFIG_PRELOADER -Os -ffixed-r8
+CFLAGS	+= -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \
+	-fdata-sections -march=armv7-a -mthumb
+PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \
+		-print-libgcc-file-name`) -lgcc
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/spl/board/$(BOARDDIR)
+
+$(splobj)u-boot-spl.bin:	$(splobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(splobj)u-boot-spl:	$(OBJS) $(LDSCRIPT)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		$(PLATFORM_LIBGCC) \
+		-Map $(splobj)u-boot-spl.map \
+		-o $(splobj)u-boot-spl
+
+ALL	= $(OBJTREE)/MLO
+all:	$(obj).depend $(ALL)
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
-- 
1.7.0.4

[U-Boot] [PATCH 11/22] omap4: add serial console support to SPL

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c   |    3 ++
 arch/arm/include/asm/omap_common.h |    1 +
 spl/board/ti/sdp4430/Makefile      |   40 ++++++++++++++++++++++++++++++++++++
 spl/board/ti/spl-omap.c            |   10 +++++++++
 4 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index a5d585b..da79669 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -57,6 +57,9 @@ u32 omap_boot_mode(void)
 void s_init(void)
 {
 	watchdog_init();
+#ifdef CONFIG_PRELOADER
+	preloader_console_init();
+#endif
 }
 
 /*
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 06c511c..95116f4 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -67,5 +67,6 @@
 
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
+void preloader_console_init(void);
 
 #endif /* _OMAP_COMMON_H_ */
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index dd56a40..6a6aa42 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -28,6 +28,46 @@ include $(TOPDIR)/config.mk
 SOBJS =
 COBJS =
 
+# serial console
+$(obj)eabi_compat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@
+
+$(obj)string.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/string.c $@
+
+$(obj)vsprintf.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/vsprintf.c $@
+
+$(obj)console.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/console.c $@
+
+$(obj)stdio.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/stdio.c $@
+
+$(obj)serial.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/serial.c $@
+
+$(obj)ns16550.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/ns16550.c $@
+
+$(obj)div64.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/div64.c $@
+
+$(obj)ctype.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/ctype.c $@
+
+COBJS	+= serial.o ns16550.o string.o vsprintf.o console.o stdio.o
+COBJS	+= ctype.o eabi_compat.o div64.o
+
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 0e08f4f..57ddb7d 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -45,3 +45,13 @@ void board_init_r(gd_t *id, ulong dummy)
 	for (;;)
 		;
 }
+
+void preloader_console_init(void)
+{
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();		/* serial communications setup */
+	printf("\nU-Boot SPL for Texas Instruments OMAP4 (%s - %s)\n",
+		U_BOOT_DATE, U_BOOT_TIME);
+}
-- 
1.7.0.4

[U-Boot] [PATCH 12/22] omap4: utility function to identify the context of hw init

[Aneesh V]

The basic hardware init of OMAP4(s_init()) can happen in 4
different contexts:
 1. SPL running from SRAM
 2. U-Boot running from FLASH
 3. Non-XIP U-Boot loaded to SDRAM by SPL
 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
    Configuration Header feature

What level of hw initialization gets done depends on this
context. Add a utility function to find this context.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/include/asm/arch-omap4/sys_proto.h |   47 +++++++++++++++++++++++++++
 arch/arm/include/asm/omap_common.h          |    6 +++
 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index ce86b36..19da2e1 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -38,6 +38,53 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_PRELOADER
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH;
+	else
+		return OMAP_INIT_CONTEXT_XIP_UBOOT;
+#endif
+}
+
 extern const struct omap_sysinfo sysinfo;
 
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 95116f4..50247af 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -65,6 +65,12 @@
 /* Magic number passed from SPL to U-Boot */
 #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
 
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_XIP_UBOOT		1
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH	3
+
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 void preloader_console_init(void);
-- 
1.7.0.4

[U-Boot] [PATCH 13/22] omap4: separate mux settings into essential and non essential parts

[Aneesh V]

Do the essential part from SPL and non-essential part from U-Boot
- Essential part is what is essential for u-boot to function
- Essential part is also largely board independent(at least
  as of now)
- So essential part is moved out to SoC directory instead of
  keeping in board directory. This helps in having single SPL
  that works for Panda and SDP.
- Non-essential part is what is set by u-boot for kernel to
  function correctly
- Ideally non-essential part should be phased out eventually

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c               |   53 ++++++++++++++++-
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h      |   76 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    4 +-
 board/ti/panda/panda.c                         |   25 ++------
 board/ti/panda/{panda.h => panda_mux_data.h}   |   45 ++------------
 board/ti/sdp4430/sdp.c                         |   25 ++------
 board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} |   47 ++-------------
 7 files changed, 151 insertions(+), 124 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 rename board/ti/panda/{panda.h => panda_mux_data.h} (83%)
 rename board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} (83%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index da79669..95b6a96 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,9 +32,30 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
 #ifdef CONFIG_PRELOADER
 u32 omap4_boot_device = BOOT_DEVICE_MMC1;
 u32 omap4_boot_mode = MMCSD_MODE_FAT;
@@ -49,14 +70,41 @@ u32 omap_boot_mode(void)
 }
 #endif
 
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_XIP_UBOOT:
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing, clocks, and
+ * sdram. Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration
+ *	Header feature
+ * Please have a look at the respective functions to see what gets done in
+ * each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif
@@ -142,7 +190,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 19da2e1..33a1666 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
@@ -33,7 +34,8 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void invalidate_dcache(u32);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda_mux_data.h
similarity index 83%
rename from board/ti/panda/panda.h
rename to board/ti/panda/panda_mux_data.h
index e3d090e..8bb7fe5 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -24,21 +24,13 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
+#ifndef _PANDA_MUX_DATA_H_
+#define _PANDA_MUX_DATA_H_
 
 #include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +56,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -112,16 +102,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
@@ -144,14 +124,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +131,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -236,14 +204,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
 	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
@@ -252,7 +218,6 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
 	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
@@ -261,4 +226,4 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
 };
 
-#endif
+#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp4430_mux_data.h
similarity index 83%
rename from board/ti/sdp4430/sdp.h
rename to board/ti/sdp4430/sdp4430_mux_data.h
index bf41067..e6081dc 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -112,16 +100,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,7 +216,6 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
@@ -261,4 +224,4 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH 14/22] omap4: correct mux data for sdp4430

[Aneesh V]

sync up mux settings with the latest in x-loader

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 board/ti/panda/panda_mux_data.h     |   89 ++++++++++++++++++-----------------
 board/ti/sdp4430/sdp4430_mux_data.h |   29 ++++++-----
 2 files changed, 61 insertions(+), 57 deletions(-)

diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 8bb7fe5..16cc0ad 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,11 +23,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_MUX_DATA_H_
-#define _PANDA_MUX_DATA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
@@ -45,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -59,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -86,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -106,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -143,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -157,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -173,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -205,25 +203,28 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 };
 
 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif /* _PANDA_MUX_DATA_H_ */
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index e6081dc..16cc0ad 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -84,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -173,11 +173,11 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -222,6 +222,9 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
 #endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH 15/22] omap4: add clock support

[Aneesh V]

Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules

This work draws upon previous work done for x-loader mainly by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/Makefile           |    1 +
 arch/arm/cpu/armv7/omap4/board.c            |    1 +
 arch/arm/cpu/armv7/omap4/clocks.c           |  717 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/clocks.h    |  504 +++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    6 +
 arch/arm/include/asm/omap_common.h          |    3 +
 spl/board/ti/sdp4430/Makefile               |    6 +-
 7 files changed, 1237 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..6154e86 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -30,6 +30,7 @@ SOBJS	+= lowlevel_init.o
 COBJS	+= board.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+COBJS	+= clocks.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 95b6a96..62a59ad 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -105,6 +105,7 @@ void s_init(void)
 {
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..317f30f
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,717 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+static const u32 sys_clk_array[8] = {
+	0,		      /* Uninitialized */
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_opp100 = {
+	0, 0, 1600000, 1, 5, 8, 4, 6, 5
+};
+
+static const struct dpll_params core_dpll_params_opp100_ddr200 = {
+	0, 0, 1600000, 2, 5, 8, 4, 6, 5
+};
+
+static const struct dpll_params core_dpll_params_es1_l3_190 = {
+	0, 0, 1523712, 1, 5, 8, 4, 6, 5
+};
+
+static const struct dpll_params per_dpll_params_opp100 = {
+	0, 0, 1536000, 8, 6, 12, 9, 4, 5
+};
+
+/* TODO - fix MPU mult */
+static const struct dpll_params mpu_dpll_params_600mhz = {
+	0, 0, 1200000, 1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params mpu_dpll_params_1000mhz = {
+	0, 0, 2000000, 1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params = {
+	0, 0, 1920000, 2, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params iva_dpll_params = {
+	0, 0, 1862000, -1, -1, 4, 7, -1, -1
+};
+
+static const struct dpll_params abe_dpll_params = {
+	0, 0, 196608, 1, 1, -1, -1, -1, -1
+};
+
+static const u32 clk_domains_essential[] = {
+	CM_L4PER_CLKSTCTRL,
+	CM_L3INIT_CLKSTCTRL,
+	CM_MEMIF_CLKSTCTRL,
+	CM_L4CFG_CLKSTCTRL,
+	0
+};
+
+static const u32 clk_domains_non_essential[] = {
+	CM_MPU_M3_CLKSTCTRL,
+	CM_IVAHD_CLKSTCTRL,
+	CM_DSP_CLKSTCTRL,
+	CM_DSS_CLKSTCTRL,
+	CM_SGX_CLKSTCTRL,
+	CM1_ABE_CLKSTCTRL,
+	CM_C2C_CLKSTCTRL,
+	CM_CAM_CLKSTCTRL,
+	CM_DSS_CLKSTCTRL,
+	CM_SDMA_CLKSTCTRL,
+	0
+};
+
+static const u32 clk_modules_hw_auto_essential[] = {
+	CM_WKUP_GPIO1_CLKCTRL,
+	CM_L4PER_GPIO2_CLKCTRL,
+	CM_L4PER_GPIO3_CLKCTRL,
+	CM_L4PER_GPIO4_CLKCTRL,
+	CM_L4PER_GPIO5_CLKCTRL,
+	CM_L4PER_GPIO6_CLKCTRL,
+	CM_MEMIF_EMIF_1_CLKCTRL,
+	CM_MEMIF_EMIF_2_CLKCTRL,
+	CM_L3INIT_HSUSBOTG_CLKCTRL,
+	CM_L3INIT_USBPHY_CLKCTRL,
+	CM_L4CFG_L4_CFG_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_hw_auto_non_essential[] = {
+	CM_MPU_M3_MPU_M3_CLKCTRL,
+	CM_IVAHD_IVAHD_CLKCTRL,
+	CM_IVAHD_SL2_CLKCTRL,
+	CM_DSP_DSP_CLKCTRL,
+	CM_L3_2_GPMC_CLKCTRL,
+	CM_L3INSTR_L3_3_CLKCTRL,
+	CM_L3INSTR_L3_INSTR_CLKCTRL,
+	CM_L3INSTR_INTRCONN_WP1_CLKCTRL,
+	CM_L3INIT_HSI_CLKCTRL,
+	CM_L3INIT_HSUSBTLL_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_explicit_en_essential[] = {
+	CM_L4PER_GPTIMER2_CLKCTRL,
+	CM_L3INIT_HSMMC1_CLKCTRL,
+	CM_L3INIT_HSMMC2_CLKCTRL,
+	CM_L4PER_MCSPI1_CLKCTRL,
+	CM_WKUP_GPTIMER1_CLKCTRL,
+	CM_L4PER_I2C1_CLKCTRL,
+	CM_L4PER_I2C2_CLKCTRL,
+	CM_L4PER_I2C3_CLKCTRL,
+	CM_L4PER_I2C4_CLKCTRL,
+	CM_WKUP_WDTIMER2_CLKCTRL,
+	CM_L4PER_UART3_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_explicit_en_non_essential[] = {
+	CM1_ABE_AESS_CLKCTRL,
+	CM1_ABE_PDM_CLKCTRL,
+	CM1_ABE_DMIC_CLKCTRL,
+	CM1_ABE_MCASP_CLKCTRL,
+	CM1_ABE_MCBSP1_CLKCTRL,
+	CM1_ABE_MCBSP2_CLKCTRL,
+	CM1_ABE_MCBSP3_CLKCTRL,
+	CM1_ABE_SLIMBUS_CLKCTRL,
+	CM1_ABE_TIMER5_CLKCTRL,
+	CM1_ABE_TIMER6_CLKCTRL,
+	CM1_ABE_TIMER7_CLKCTRL,
+	CM1_ABE_TIMER8_CLKCTRL,
+	CM1_ABE_WDT3_CLKCTRL,
+	CM_L4PER_GPTIMER9_CLKCTRL,
+	CM_L4PER_GPTIMER10_CLKCTRL,
+	CM_L4PER_GPTIMER11_CLKCTRL,
+	CM_L4PER_GPTIMER3_CLKCTRL,
+	CM_L4PER_GPTIMER4_CLKCTRL,
+	CM_L4PER_HDQ1W_CLKCTRL,
+	CM_L4PER_MCBSP4_CLKCTRL,
+	CM_L4PER_MCSPI2_CLKCTRL,
+	CM_L4PER_MCSPI3_CLKCTRL,
+	CM_L4PER_MCSPI4_CLKCTRL,
+	CM_L4PER_MMCSD3_CLKCTRL,
+	CM_L4PER_MMCSD4_CLKCTRL,
+	CM_L4PER_MMCSD5_CLKCTRL,
+	CM_L4PER_UART1_CLKCTRL,
+	CM_L4PER_UART2_CLKCTRL,
+	CM_L4PER_UART4_CLKCTRL,
+	CM_WKUP_KEYBOARD_CLKCTRL,
+	CM_WKUP_WDTIMER2_CLKCTRL,
+	CM_CAM_ISS_CLKCTRL,
+	CM_CAM_FDIF_CLKCTRL,
+	CM_DSS_DSS_CLKCTRL,
+	CM_SGX_SGX_CLKCTRL,
+	CM_L3INIT_HSUSBHOST_CLKCTRL,
+	CM_L3INIT_FSUSB_CLKCTRL,
+	0
+};
+
+static u32 get_m_n(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n,
+		   u32 tolerance_khz)
+{
+	u32 min_freq = target_freq_khz - tolerance_khz;
+	u32 max_freq = target_freq_khz;
+	u32 freq, freq_old;
+	*n = 1;
+	while (1) {
+		*m = min_freq / ref_freq_khz / 2 * (*n);
+		freq_old = 0;
+		while (1) {
+			freq = ref_freq_khz * 2 * (*m) / (*n);
+			if (abs(target_freq_khz - freq_old) <=
+			    abs(target_freq_khz - freq)) {
+				freq = freq_old;
+				(*m)--;
+				break;
+			}
+			(*m)++;
+			freq_old = freq;
+		}
+		if (freq >= min_freq && freq <= max_freq)
+			break;
+		(*n)++;
+		if ((*n) > OMAP_DPLL_MAX_N + 1)
+			return 1;
+	}
+	(*n)--;
+	return 0;
+}
+
+static u32 __get_syc_clk_freq(void)
+{
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap4_revision() == OMAP4430_ES1_0)
+		return OMAP_SYS_CLK_FREQ_38_4_MHZ;
+	else {
+		u32 sys_clk_ind = readl(CM_SYS_CLKSEL) &
+				  CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
+		return sys_clk_array[sys_clk_ind];
+	}
+}
+
+static inline void do_bypass_dpll(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS);
+}
+
+static inline void wait_for_bypass(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	while (readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK)
+		;
+}
+
+static inline void do_lock_dpll(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_LOCK);
+}
+
+static inline void wait_for_lock(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	while (!(readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK))
+		;
+}
+
+static void do_setup_dpll(u32 base, const struct dpll_params *params,
+			  u32 ref_clk_khz, u32 tolerance, u8 lock)
+{
+	u32 temp, m, n;
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	do_bypass_dpll(base);
+
+	/* Get the M & N values */
+	m = params->m;
+	n = params->n;
+	/* if m & n are not specified calculate them */
+	if (!(m && n)) {
+		if (get_m_n(params->locked_freq_khz, ref_clk_khz,
+			    &m, &n, tolerance)) {
+			/* DPLL locking is critical if it fails just hang */
+			for (;;)
+				;
+			return;
+		}
+	}
+
+	/* Wait till the DPLL is in BYPASS */
+	wait_for_bypass(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+	set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK, m);
+	set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK, n);
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	switch (omap4_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_l3_190;
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		return &core_dpll_params_opp100_ddr200; /* safest */
+	case OMAP4430_ES2_1:
+	case OMAP4430_ES2_2:
+		return &core_dpll_params_opp100;
+	default:
+		return NULL;
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = core_dpll_params->locked_freq_khz / 4 / core_dpll_params->m2;
+	ddr_clk *= 1000;	/* convert to Hz */
+	return ddr_clk;
+}
+
+static void setup_dplls(void)
+{
+	u32 sys_clk_khz, temp;
+	const struct dpll_params *params;
+
+	sys_clk_khz = get_syc_clk_freq() / 1000;
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(CM_CLKMODE_DPLL_CORE, params, sys_clk_khz,
+		      DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, CM_CLKSEL_CORE);
+
+	/* lock PER dpll */
+	do_setup_dpll(CM_CLKMODE_DPLL_PER, &per_dpll_params_opp100, sys_clk_khz,
+		      DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK);
+
+	/* MPU dpll */
+	if (omap4_revision() == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_600mhz;
+	else
+		params = &mpu_dpll_params_1000mhz;
+	do_setup_dpll(CM_CLKMODE_DPLL_MPU, params, sys_clk_khz,
+		      DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK);
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, temp, abe_ref_clk;
+	u32 m, n, sd_div, num, den;
+	struct dpll_params tmp_params;
+
+	sys_clk_khz = get_syc_clk_freq() / 1000;
+
+	/* IVA */
+	do_setup_dpll(CM_CLKMODE_DPLL_IVA, &iva_dpll_params, sys_clk_khz,
+		      DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ, CONFIGURE_AND_LOCK);
+
+	/* USB */
+	tmp_params = usb_dpll_params;
+	get_m_n(tmp_params.locked_freq_khz, sys_clk_khz, &m, &n,
+		DPLL_LOCKED_FREQ_TOLERANCE_0);
+	/*
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and@the same time no overflow
+	 */
+	num = m * sys_clk_khz;
+	den = (n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	temp = readl(CM_CLKSEL_DPLL_USB);
+	set_bit_field(temp, CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT,
+		      CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div);
+	writel(temp, CM_CLKSEL_DPLL_USB);
+	/* Now setup the dpll with the regular function */
+	tmp_params.m = m;
+	tmp_params.n = n;
+	do_setup_dpll(CM_CLKMODE_DPLL_USB, &tmp_params, sys_clk_khz,
+		      DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK);
+
+	/* ABE dpll */
+	tmp_params = abe_dpll_params;
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	abe_ref_clk = sys_clk_khz;
+#else
+	/* Enable REGM4XEN to achieve 196.608MHz from 32768 Hz */
+	writel(readl(CM_CLKMODE_DPLL_ABE) | CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK,
+		CM_CLKMODE_DPLL_ABE);
+
+	/*
+	 * Converting the input clock 32768 Hz to KHz would result in accuracy
+	 * loss. Instead make both target frequency and reference clock to be
+	 * in terms of Hz.
+	 *
+	 * Also, REGM4XEN is enabled so there is an additional
+	 * multiplier of 4 for M. So adjust for this while passing target
+	 * frequency to get_m_n()
+	 */
+	tmp_params.locked_freq_khz = tmp_params.locked_freq_khz * 1000 / 4;
+	abe_ref_clk = OMAP_32K_CLK_FREQ;
+#endif
+	temp = (abe_ref_clk == OMAP_32K_CLK_FREQ) ?
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK :
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+	/* Select the right reference clk */
+	modify_reg_32(CM_ABE_PLL_REF_CLKSEL,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			temp);
+	/* Lock the dpll */
+	do_setup_dpll(CM_CLKMODE_DPLL_ABE, &tmp_params, abe_ref_clk,
+		      DPLL_LOCKED_FREQ_TOLERANCE_0, CONFIGURE_AND_LOCK);
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt)
+{
+	u32 temp;
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (volt << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, PRM_VC_VAL_BYPASS);
+	while (readl(PRM_VC_VAL_BYPASS) & PRM_VC_VAL_BYPASS_VALID_BIT)
+		;
+}
+
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+	u32 omap4_rev = omap4_revision();
+
+	sys_clk_khz = get_syc_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, PRM_VC_CFG_I2C_CLK);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, PRM_VC_CFG_I2C_MODE);
+
+	/* VCORE 1 */
+	if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1))
+		volt = SMPS_VOLT_1_3500_V;
+	else
+		volt = SMPS_VOLT_1_5000_V;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+	/* VCORE 2 */
+	if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1))
+		volt = SMPS_VOLT_1_1000_V;
+	else
+		volt = SMPS_VOLT_1_2000_V;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/* VCORE 3 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		volt = SMPS_VOLT_1_1000_V;
+	else if (omap4_rev == OMAP4430_ES2_1)
+		volt = SMPS_VOLT_1_1125_V;
+	else
+		volt = SMPS_VOLT_1_2000_V;
+
+	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+}
+
+static void enable_clock_domain(u32 clkctrl_reg, u32 enable_mode)
+{
+	modify_reg_32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_SHIFT,
+		      CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode);
+}
+
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
+{
+	u32 idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+	       (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		idlest = readl(clkctrl_addr);
+		idlest = get_bit_field(idlest, MODULE_CLKCTRL_IDLEST_SHIFT,
+				       MODULE_CLKCTRL_IDLEST_MASK);
+	}
+}
+
+static void enable_clock_module(u32 clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	modify_reg_32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable a set of clock domains and clock modules associated with them
+ */
+static void enable_clocks(const u32 *clock_domains,
+			  const u32 *clock_modules_hw_auto,
+			  const u32 *clock_modules_explicit_en,
+			  u32 wait_for_enable)
+{
+	int i = 0, max = 100;
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clock_domains[i]; i++) {
+		enable_clock_domain(clock_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clock_modules_hw_auto[i]; i++) {
+		enable_clock_module(clock_modules_hw_auto[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clock_modules_explicit_en[i]; i++) {
+		enable_clock_module(clock_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clock_domains[i]; i++) {
+		enable_clock_domain(clock_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	/* Enable optional additional functional clock for GPIO4 */
+	writel(readl(CM_L4PER_GPIO4_CLKCTRL) | GPIO4_CLKCTRL_OPTFCLKEN_SHIFT,
+	       CM_L4PER_GPIO4_CLKCTRL);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	writel(readl(CM_L3INIT_HSMMC1_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_SHIFT,
+	       CM_L3INIT_HSMMC1_CLKCTRL);
+	writel(readl(CM_L3INIT_HSMMC2_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_SHIFT,
+	       CM_L3INIT_HSMMC2_CLKCTRL);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	writel(readl(CM_WKUP_GPTIMER1_CLKCTRL) | GPTIMER1_CLKCTRL_CLKSEL_SHIFT,
+	       CM_WKUP_GPTIMER1_CLKCTRL);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	writel(readl(CM_L3INIT_USBPHY_CLKCTRL) |
+	       USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK, CM_L3INIT_USBPHY_CLKCTRL);
+
+	/* Enable all essential clock domains and modules */
+	enable_clocks(clk_domains_essential,
+		      clk_modules_hw_auto_essential,
+		      clk_modules_explicit_en_essential, 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 tmp;
+	/* Enable optional functional clock for ISS */
+	writel(readl(CM_CAM_ISS_CLKCTRL) | ISS_CLKCTRL_OPTFCLKEN_SHIFT,
+	       CM_CAM_ISS_CLKCTRL);
+
+	/* Enable all optional functional clocks of DSS */
+	writel(readl(CM_DSS_DSS_CLKCTRL) | DSS_CLKCTRL_OPTFCLKEN_MASK,
+	       CM_DSS_DSS_CLKCTRL);
+
+	/* Enable all non-essential clock domains and modules */
+	enable_clocks(clk_domains_non_essential,
+		      clk_modules_hw_auto_non_essential,
+		      clk_modules_explicit_en_non_essential, 0);
+
+	/* Put camera module in no sleep mode */
+	tmp = readl(CM_CAM_CLKSTCTRL);
+	set_bit_field(tmp, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+		      MODULE_CLKCTRL_MODULEMODE_MASK,
+		      CD_CLKCTRL_CLKTRCTRL_NO_SLEEP);
+	writel(tmp, CM_CAM_CLKSTCTRL);
+}
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL);
+	wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT,
+		      SHADOW_FREQ_CONFIG1_DPLL_EN_MASK, DPLL_EN_LOCK);
+
+	set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT,
+		      SHADOW_FREQ_CONFIG1_M2_DIV_MASK, core_dpll_params->m2);
+
+	writel(freq_config1, CM_SHADOW_FREQ_CONFIG1);
+	while (readl(CM_SHADOW_FREQ_CONFIG1) &
+		SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK)
+		;
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL);
+	wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL);
+}
+
+void bypass_dpll(u32 base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+u32 get_syc_clk_freq(void)
+	__attribute__ ((weak, alias("__get_syc_clk_freq")));
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL:
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	case OMAP_INIT_CONTEXT_XIP_UBOOT:
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	}
+}
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..fdbe632
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,504 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+
+/* PRM.CKGEN module registers */
+#define CM_ABE_PLL_REF_CLKSEL		(OMAP44XX_L4_WKUP_BASE + 0x610C)
+#define CM_SYS_CLKSEL			(OMAP44XX_L4_WKUP_BASE + 0x6110)
+
+/* PRM.WKUP_CM module registers */
+#define CM_WKUP_CLKSTCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7800)
+#define CM_WKUP_L4WKUP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7820)
+#define CM_WKUP_WDTIMER1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7828)
+#define CM_WKUP_WDTIMER2_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7830)
+#define CM_WKUP_GPIO1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7838)
+#define CM_WKUP_GPTIMER1_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7840)
+#define CM_WKUP_GPTIMER12_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7848)
+#define CM_WKUP_SYNCTIMER_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7850)
+#define CM_WKUP_USIM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7858)
+#define CM_WKUP_SARRAM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7860)
+#define CM_WKUP_KEYBOARD_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7878)
+#define CM_WKUP_RTC_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7880)
+#define CM_WKUP_BANDGAP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7888)
+
+/* DEVICE_PRM Registers */
+#define PRM_VC_VAL_BYPASS		(OMAP44XX_L4_WKUP_BASE + 0x7BA0)
+#define PRM_VC_CFG_CHANNEL		(OMAP44XX_L4_WKUP_BASE + 0x7BA4)
+#define PRM_VC_CFG_I2C_MODE		(OMAP44XX_L4_WKUP_BASE + 0x7BA8)
+#define PRM_VC_CFG_I2C_CLK		(OMAP44XX_L4_WKUP_BASE + 0x7BAC)
+
+/* CM1.CKGEN module registers */
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+#define CM_CLKSEL_ABE			(OMAP44XX_L4_CORE_BASE + 0x4108)
+#define CM_DLL_CTRL			(OMAP44XX_L4_CORE_BASE + 0x4110)
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_IDLEST_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4124)
+#define CM_AUTOIDLE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4128)
+#define CM_CLKSEL_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x412c)
+#define CM_DIV_M2_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4130)
+#define CM_DIV_M3_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4134)
+#define CM_DIV_M4_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4138)
+#define CM_DIV_M5_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x413c)
+#define CM_DIV_M6_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4140)
+#define CM_DIV_M7_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4144)
+#define CM_SSC_DELTAMSTEP_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4148)
+#define CM_SSC_MODFREQDIV_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x414c)
+#define CM_EMU_OVERRIDE_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4150)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_IDLEST_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4164)
+#define CM_AUTOIDLE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4168)
+#define CM_CLKSEL_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x416c)
+#define CM_DIV_M2_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4170)
+#define CM_SSC_DELTAMSTEP_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x4188)
+#define CM_SSC_MODFREQDIV_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x418c)
+#define CM_BYPCLK_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x419c)
+#define CM_CLKMODE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a0)
+#define CM_IDLEST_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a4)
+#define CM_AUTOIDLE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a8)
+#define CM_CLKSEL_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41ac)
+#define CM_DIV_M4_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41b8)
+#define CM_DIV_M5_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41bc)
+#define CM_SSC_DELTAMSTEP_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41c8)
+#define CM_SSC_MODFREQDIV_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41cc)
+#define CM_BYPCLK_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41dc)
+#define CM_CLKMODE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e0)
+#define CM_IDLEST_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e4)
+#define CM_AUTOIDLE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e8)
+#define CM_CLKSEL_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41ec)
+#define CM_DIV_M2_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f0)
+#define CM_DIV_M3_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f4)
+#define CM_SSC_DELTAMSTEP_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x4208)
+#define CM_SSC_MODFREQDIV_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x420c)
+#define CM_CLKMODE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4220)
+#define CM_IDLEST_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4224)
+#define CM_AUTOIDLE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4228)
+#define CM_CLKSEL_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x422c)
+#define CM_DIV_M2_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4230)
+#define CM_DIV_M4_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4238)
+#define CM_DIV_M5_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x423c)
+#define CM_DIV_M6_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4240)
+#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY	(OMAP44XX_L4_CORE_BASE + 0x4248)
+#define CM_SHADOW_FREQ_CONFIG1		(OMAP44XX_L4_CORE_BASE + 0x4260)
+
+/* CM1.ABE register offsets */
+#define CM1_ABE_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x4500)
+#define CM1_ABE_L4ABE_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4520)
+#define CM1_ABE_AESS_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4528)
+#define CM1_ABE_PDM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4530)
+#define CM1_ABE_DMIC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4538)
+#define CM1_ABE_MCASP_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4540)
+#define CM1_ABE_MCBSP1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4548)
+#define CM1_ABE_MCBSP2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4550)
+#define CM1_ABE_MCBSP3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4558)
+#define CM1_ABE_SLIMBUS_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4560)
+#define CM1_ABE_TIMER5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4568)
+#define CM1_ABE_TIMER6_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4570)
+#define CM1_ABE_TIMER7_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4578)
+#define CM1_ABE_TIMER8_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4580)
+#define CM1_ABE_WDT3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4588)
+
+/* CM1.DSP register offsets */
+#define CM_DSP_CLKSTCTRL			(OMAP44XX_L4_CORE_BASE + 0x4400)
+#define	CM_DSP_DSP_CLKCTRL			(OMAP44XX_L4_CORE_BASE + 0x4420)
+
+/* CM2.CKGEN module registers */
+#define CM_CLKSEL_MPU_M3_ISS_ROOT	(OMAP44XX_L4_CORE_BASE + 0x8100)
+#define CM_CLKSEL_USB_60MHz		(OMAP44XX_L4_CORE_BASE + 0x8104)
+#define CM_SCALE_FCLK			(OMAP44XX_L4_CORE_BASE + 0x8108)
+#define CM_CORE_DVFS_PERF1		(OMAP44XX_L4_CORE_BASE + 0x8110)
+#define CM_CORE_DVFS_PERF2		(OMAP44XX_L4_CORE_BASE + 0x8114)
+#define CM_CORE_DVFS_PERF3		(OMAP44XX_L4_CORE_BASE + 0x8118)
+#define CM_CORE_DVFS_PERF4		(OMAP44XX_L4_CORE_BASE + 0x811c)
+#define CM_CORE_DVFS_CURRENT		(OMAP44XX_L4_CORE_BASE + 0x8124)
+#define CM_IVA_DVFS_PERF_TESLA		(OMAP44XX_L4_CORE_BASE + 0x8128)
+#define CM_IVA_DVFS_PERF_IVAHD		(OMAP44XX_L4_CORE_BASE + 0x812c)
+#define CM_IVA_DVFS_PERF_ABE		(OMAP44XX_L4_CORE_BASE + 0x8130)
+#define CM_IVA_DVFS_CURRENT		(OMAP44XX_L4_CORE_BASE + 0x8138)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_IDLEST_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8144)
+#define CM_AUTOIDLE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8148)
+#define CM_CLKSEL_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x814c)
+#define CM_DIV_M2_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8150)
+#define CM_DIV_M3_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8154)
+#define CM_DIV_M4_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8158)
+#define CM_DIV_M5_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x815c)
+#define CM_DIV_M6_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8160)
+#define CM_DIV_M7_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8164)
+#define CM_SSC_DELTAMSTEP_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x8168)
+#define CM_SSC_MODFREQDIV_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x816c)
+#define CM_EMU_OVERRIDE_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x8170)
+#define CM_CLKMODE_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8180)
+#define CM_IDLEST_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8184)
+#define CM_AUTOIDLE_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8188)
+#define CM_CLKSEL_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x818c)
+#define CM_DIV_M2_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8190)
+#define CM_SSC_DELTAMSTEP_DPLL_USB	(OMAP44XX_L4_CORE_BASE + 0x81a8)
+#define CM_SSC_MODFREQDIV_DPLL_USB	(OMAP44XX_L4_CORE_BASE + 0x81ac)
+#define CM_CLKDCOLDO_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x81b4)
+#define CM_CLKMODE_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c0)
+#define CM_IDLEST_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c4)
+#define CM_AUTOIDLE_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c8)
+#define CM_CLKSEL_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81cc)
+#define CM_DIV_M2_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81d0)
+#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO	(OMAP44XX_L4_CORE_BASE + 0x81e8)
+#define CM_SSC_MODFREQDIV_DPLL_UNIPRO	(OMAP44XX_L4_CORE_BASE + 0x81ec)
+
+/* CM2.CORE module registers */
+#define CM_L3_1_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8700)
+#define CM_L3_1_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8708)
+#define CM_L3_1_L3_1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8720)
+#define CM_L3_2_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8800)
+#define CM_L3_2_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8808)
+#define CM_L3_2_L3_2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8820)
+#define CM_L3_2_GPMC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8828)
+#define CM_L3_2_OCMC_RAM_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8830)
+#define CM_MPU_M3_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8900)
+#define CM_MPU_M3_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8904)
+#define CM_MPU_M3_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8908)
+#define CM_MPU_M3_MPU_M3_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8920)
+#define CM_SDMA_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8a00)
+#define CM_SDMA_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8a04)
+#define CM_SDMA_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8a08)
+#define CM_SDMA_SDMA_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8a20)
+#define CM_MEMIF_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b00)
+#define CM_MEMIF_DMM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b20)
+#define CM_MEMIF_EMIF_FW_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b28)
+#define CM_MEMIF_EMIF_1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b30)
+#define CM_MEMIF_EMIF_2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b38)
+#define CM_MEMIF_DLL_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b40)
+#define CM_MEMIF_EMIF_H1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b50)
+#define CM_MEMIF_EMIF_H2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b58)
+#define CM_MEMIF_DLL_H_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b60)
+#define CM_C2C_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c00)
+#define CM_C2C_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8c04)
+#define CM_C2C_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8c08)
+#define CM_C2C_SAD2D_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c20)
+#define CM_C2C_MODEM_ICR_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8c28)
+#define CM_C2C_SAD2D_FW_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c30)
+#define CM_L4CFG_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d00)
+#define CM_L4CFG_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8d08)
+#define CM_L4CFG_L4_CFG_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d20)
+#define CM_L4CFG_HW_SEM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d28)
+#define CM_L4CFG_MAILBOX_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8d30)
+#define CM_L4CFG_SAR_ROM_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8d38)
+#define CM_L3INSTR_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8e00)
+#define CM_L3INSTR_L3_3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8e20)
+#define CM_L3INSTR_L3_INSTR_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8e28)
+#define CM_L3INSTR_INTRCONN_WP1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8e40)
+
+/* CM2.L3INIT register offsets */
+#define CM_L3INIT_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9300)
+
+/* CM2.L4PER register offsets */
+#define CM_L4PER_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9400)
+#define CM_L4PER_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x9408)
+#define CM_L4PER_ADC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9420)
+#define CM_L4PER_GPTIMER10_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9428)
+#define CM_L4PER_GPTIMER11_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9430)
+#define CM_L4PER_GPTIMER2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9438)
+#define CM_L4PER_GPTIMER3_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9440)
+#define CM_L4PER_GPTIMER4_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9448)
+#define CM_L4PER_GPTIMER9_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9450)
+#define CM_L4PER_ELM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9458)
+#define CM_L4PER_GPIO2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9460)
+#define CM_L4PER_GPIO3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9468)
+#define CM_L4PER_GPIO4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9470)
+#define CM_L4PER_GPIO5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9478)
+#define CM_L4PER_GPIO6_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9480)
+#define CM_L4PER_HDQ1W_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9488)
+#define CM_L4PER_HECC1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9490)
+#define CM_L4PER_HECC2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9498)
+#define CM_L4PER_I2C1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94a0)
+#define CM_L4PER_I2C2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94a8)
+#define CM_L4PER_I2C3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94b0)
+#define CM_L4PER_I2C4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94b8)
+#define CM_L4PER_L4PER_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94c0)
+#define CM_L4PER_MCASP2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94d0)
+#define CM_L4PER_MCASP3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94d8)
+#define CM_L4PER_MCBSP4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94e0)
+#define CM_L4PER_MGATE_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94e8)
+#define CM_L4PER_MCSPI1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94f0)
+#define CM_L4PER_MCSPI2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94f8)
+#define CM_L4PER_MCSPI3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9500)
+#define CM_L4PER_MCSPI4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9508)
+#define CM_L4PER_MMCSD3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9520)
+#define CM_L4PER_MMCSD4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9528)
+#define CM_L4PER_MSPROHG_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9530)
+#define CM_L4PER_SLIMBUS2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9538)
+#define CM_L4PER_UART1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9540)
+#define CM_L4PER_UART2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9548)
+#define CM_L4PER_UART3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9550)
+#define CM_L4PER_UART4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9558)
+#define CM_L4PER_MMCSD5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9560)
+#define CM_L4PER_I2C5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9568)
+#define CM_L4SEC_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9580)
+#define CM_L4SEC_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x9584)
+#define CM_L4SEC_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x9588)
+#define CM_L4SEC_AES1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95a0)
+#define CM_L4SEC_AES2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95a8)
+#define CM_L4SEC_DES3DES_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95b0)
+#define CM_L4SEC_PKAEIP29_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95b8)
+#define CM_L4SEC_RNG_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95c0)
+#define CM_L4SEC_SHA2MD51_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95c8)
+#define CM_L4SEC_CRYPTODMA_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95d8)
+
+/* CM2.IVAHD */
+#define CM_IVAHD_CLKSTCTRL			(OMAP44XX_L4_CORE_BASE + 0x8f00)
+#define CM_IVAHD_IVAHD_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8f20)
+#define CM_IVAHD_SL2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8f28)
+
+/* CM2.L3INIT */
+#define CM_L3INIT_HSMMC1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9328)
+#define CM_L3INIT_HSMMC2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9330)
+#define CM_L3INIT_HSI_CLKCTRL           (OMAP44XX_L4_CORE_BASE + 0x9338)
+#define CM_L3INIT_HSUSBHOST_CLKCTRL     (OMAP44XX_L4_CORE_BASE + 0x9358)
+#define CM_L3INIT_HSUSBOTG_CLKCTRL      (OMAP44XX_L4_CORE_BASE + 0x9360)
+#define CM_L3INIT_HSUSBTLL_CLKCTRL      (OMAP44XX_L4_CORE_BASE + 0x9368)
+#define CM_L3INIT_P1500_CLKCTRL         (OMAP44XX_L4_CORE_BASE + 0x9378)
+#define CM_L3INIT_FSUSB_CLKCTRL         (OMAP44XX_L4_CORE_BASE + 0x93d0)
+#define CM_L3INIT_USBPHY_CLKCTRL        (OMAP44XX_L4_CORE_BASE + 0x93e0)
+
+/* CM2.CAM */
+#define CM_CAM_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9000)
+#define CM_CAM_ISS_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9020)
+#define CM_CAM_FDIF_CLKCTRL             (OMAP44XX_L4_CORE_BASE + 0x9028)
+
+/* CM2.DSS */
+#define CM_DSS_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9100)
+#define CM_DSS_DSS_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9120)
+
+/* CM2.SGX */
+#define CM_SGX_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9200)
+#define CM_SGX_SGX_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9220)
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK	11
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_SHIFT		8
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_SHIFT		24
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_SHIFT		24
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_SHIFT		8
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define SMPS_VOLT_1_0000_V	0x21
+#define SMPS_VOLT_1_0125_V	0x22
+#define SMPS_VOLT_1_0250_V	0x23
+#define SMPS_VOLT_1_0375_V	0x24
+#define SMPS_VOLT_1_0500_V	0x25
+#define SMPS_VOLT_1_0625_V	0x26
+#define SMPS_VOLT_1_0750_V	0x27
+#define SMPS_VOLT_1_0875_V	0x28
+#define SMPS_VOLT_1_1000_V	0x29
+#define SMPS_VOLT_1_1125_V	0x2A
+#define SMPS_VOLT_1_1250_V	0x2B
+#define SMPS_VOLT_1_1375_V	0x2C
+#define SMPS_VOLT_1_1500_V	0x2D
+#define SMPS_VOLT_1_1625_V	0x2E
+#define SMPS_VOLT_1_1750_V	0x2F
+#define SMPS_VOLT_1_1875_V	0x30
+#define SMPS_VOLT_1_2000_V	0x31
+#define SMPS_VOLT_1_2125_V	0x32
+#define SMPS_VOLT_1_2250_V	0x33
+#define SMPS_VOLT_1_2375_V	0x34
+#define SMPS_VOLT_1_2500_V	0x35
+#define SMPS_VOLT_1_2625_V	0x36
+#define SMPS_VOLT_1_2750_V	0x37
+#define SMPS_VOLT_1_2875_V	0x38
+#define SMPS_VOLT_1_3000_V	0x39
+#define SMPS_VOLT_1_3500_V	0x3A
+#define SMPS_VOLT_1_5000_V	0x3B
+#define SMPS_VOLT_1_5000_V	0x3B
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define CONFIGURE_NO_LOCK	0
+#define CONFIGURE_AND_LOCK	1
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	s32 m;
+	s32 n;
+	u32 locked_freq_khz;
+	s32 m2;
+	s32 m3;
+	s32 m4;
+	s32 m5;
+	s32 m6;
+	s32 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 33a1666..fd21afd 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -39,6 +39,12 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
+void prcm_init(void);
+void bypass_dpll(u32 base);
+void freq_update_core(void);
+u32 get_syc_clk_freq(void);
+u32 omap4_ddr_clk(void);
+u32 omap4_revision(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 50247af..49daa85 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* extract a bit field from a bit vector */
 #define get_bit_field(nr, start, mask)\
 	(((nr) & (mask)) >> (start))
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index 6a6aa42..40e3e79 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -115,8 +115,12 @@ $(obj)board.c:$(obj)omap4_mux_data.h
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
 
+$(obj)clocks.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@
+
 SOBJS	+= lowlevel_init.o
-COBJS	+= board.o
+COBJS	+= board.o clocks.o
 
 # rules
 LDPPFLAGS += -include $(TOPDIR)/include/config.h
-- 
1.7.0.4

[U-Boot] [PATCH 16/22] omap4: add sdram init support

[Aneesh V]

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/Makefile           |    3 +
 arch/arm/cpu/armv7/omap4/board.c            |    2 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  281 +++++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  118 +++++
 arch/arm/include/asm/arch-omap4/emif.h      |  719 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |   11 +
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_sdp4430.h             |    5 -
 spl/board/ti/sdp4430/Makefile               |   10 +-
 9 files changed, 1143 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 6154e86..d9714fe 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -31,6 +31,9 @@ COBJS	+= board.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 COBJS	+= clocks.o
+COBJS	+= emif.o
+COBJS	+= sdram_elpida.o
+
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 62a59ad..89b1213 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -109,6 +109,7 @@ void s_init(void)
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif
+	sdram_init();
 }
 
 /*
@@ -169,7 +170,6 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
 	gd->ram_size = sdram_size();
 
 	return 0;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..ee77743
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,281 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap4_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	sdelay(10);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 nvm;
+
+	/* Not NVM */
+	nvm = readl(&emif->emif_lpddr2_nvm_config);
+	nvm &= (~OMAP44XX_REG_CS1NVMEN_MASK);
+	writel(nvm, &emif->emif_lpddr2_nvm_config);
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap4_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/*
+	 * Workaround:
+	 * In a specific situation, the OCP interface between the DMM and
+	 * EMIF may hang.
+	 * 1. A TILER port is used to perform 2D burst writes of
+	 *       width 1 and height 8
+	 * 2. ELLAn port is used to perform reads
+	 * 3. All accesses are routed to the same EMIF controller
+	 *
+	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
+	 * be kept higher than default 0x7. As per recommondation 0x0A will
+	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
+	 */
+	if (omap4_revision() == OMAP4430_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
+		       &emif->emif_l3_config);
+	}
+}
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs, *tmp_regs;
+	u32 in_sdram, emif_nr;
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+	emif_get_reg_dump(&regs, &tmp_regs);
+	regs = (emif_nr == 1) ? regs : tmp_regs;
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	u32 omap4_rev = omap4_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, CONTROL_LPDDR2IO1_0);
+	writel(lpddr2io, CONTROL_LPDDR2IO1_1);
+	writel(lpddr2io, CONTROL_LPDDR2IO1_2);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_0);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_1);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap4_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+	emif_get_dmm_regs(&lisa_map_regs);
+
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram;
+
+	in_sdram = running_from_sdram();
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(CM_CLKMODE_DPLL_CORE);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..37e808c
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,118 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
+{
+	u32 omap4_rev = omap4_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0) {
+		*emif1_regs = &emif_regs_elpida_380_mhz_1cs;
+		*emif2_regs = &emif_regs_elpida_380_mhz_1cs;
+	} else if (omap4_rev == OMAP4430_ES2_0) {
+		*emif1_regs = &emif_regs_elpida_200_mhz_2cs;
+		*emif2_regs = &emif_regs_elpida_200_mhz_2cs;
+	} else {
+		*emif1_regs = &emif_regs_elpida_400_mhz_2cs;
+		*emif2_regs = &emif_regs_elpida_400_mhz_2cs;
+	}
+}
+void emif_get_reg_dump(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	u32 omap_rev = omap4_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..f2d54cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,719 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_BASE		0x4E000000
+#define OMAP44XX_DMM_LISA_MAP_BASE		(0x4E000000 + 0x40)
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct __attribute__ ((__packed__)) emif_reg_struct{
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* Read Latency used by the device@reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value for ES1*/
+#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO reg values */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+void emif_get_reg_dump(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 740ca9d..a1c4883 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,17 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO1_0	(CONTROL_PADCONF_CORE + 0x0638)
+#define CONTROL_LPDDR2IO1_1	(CONTROL_PADCONF_CORE + 0x063C)
+#define CONTROL_LPDDR2IO1_2	(CONTROL_PADCONF_CORE + 0x0640)
+#define CONTROL_LPDDR2IO1_3	(CONTROL_PADCONF_CORE + 0x0644)
+#define CONTROL_LPDDR2IO2_0	(CONTROL_PADCONF_CORE + 0x0648)
+#define CONTROL_LPDDR2IO2_1	(CONTROL_PADCONF_CORE + 0x064C)
+#define CONTROL_LPDDR2IO2_2	(CONTROL_PADCONF_CORE + 0x0650)
+#define CONTROL_LPDDR2IO2_3	(CONTROL_PADCONF_CORE + 0x0654)
+#define CONTROL_EFUSE_2		(CONTROL_PADCONF_CORE + 0x0704)
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index fd21afd..4beff42 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_syc_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
 u32 omap4_revision(void);
 
 static inline u32 running_from_sdram(void)
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 5b20841..07d45a0 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -245,11 +245,6 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
-/* Defines for SDRAM init */
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
-#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
-
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index 40e3e79..1f25f77 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -115,12 +115,20 @@ $(obj)board.c:$(obj)omap4_mux_data.h
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
 
+$(obj)emif.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@
+
+$(obj)sdram_elpida.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@
+
 $(obj)clocks.c:
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@
 
 SOBJS	+= lowlevel_init.o
-COBJS	+= board.o clocks.o
+COBJS	+= board.o clocks.o emif.o sdram_elpida.o
 
 # rules
 LDPPFLAGS += -include $(TOPDIR)/include/config.h
-- 
1.7.0.4

[U-Boot] [PATCH 17/22] omap4: calculate EMIF register values

[Aneesh V]

Calculate EMIF register values based on AC timing parameters
from the SDRAM datasheet and the DDR frequency rather than
using the hard-coded values.

For a new board the user doen't have to go through the tedious
process of calculating the register values. Instead, just
provide the AC timings from the device data sheet as input
and the driver will automatically calculate the register values.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap-common/Makefile     |    1 +
 arch/arm/cpu/armv7/omap-common/utils.c      |   61 ++
 arch/arm/cpu/armv7/omap4/Makefile           |    1 -
 arch/arm/cpu/armv7/omap4/board.c            |    9 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  861 ++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  152 +++++-
 arch/arm/include/asm/arch-omap4/emif.h      |  304 ++++++++++-
 arch/arm/include/asm/arch-omap4/omap4.h     |   18 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 arch/arm/include/asm/omap_common.h          |   21 +
 include/configs/omap4_sdp4430.h             |    5 +
 spl/board/ti/sdp4430/Makefile               |    6 +-
 12 files changed, 1424 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..8f698f8 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..7dce7f1
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,61 @@
+/*
+ * Utility functions for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index d9714fe..0b525e1 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -34,7 +34,6 @@ COBJS	+= clocks.o
 COBJS	+= emif.o
 COBJS	+= sdram_elpida.o
 
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 89b1213..925601d 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -148,13 +149,13 @@ u32 sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index ee77743..1bdb1d2 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -31,6 +31,589 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	set_bit_field(config_reg, OMAP44XX_REG_SDRAM_TYPE_SHIFT,
+		      OMAP44XX_REG_SDRAM_TYPE_MASK, cs0_device->type + 4);
+
+	set_bit_field(config_reg, OMAP44XX_REG_IBANK_POS_SHIFT,
+		      OMAP44XX_REG_IBANK_POS_MASK,
+		      EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING);
+
+	set_bit_field(config_reg, OMAP44XX_REG_NARROW_MODE_SHIFT,
+		      OMAP44XX_REG_NARROW_MODE_MASK, cs0_device->io_width);
+
+	set_bit_field(config_reg, OMAP44XX_REG_CL_SHIFT, OMAP44XX_REG_CL_MASK,
+		      RL);
+
+	set_bit_field(config_reg, OMAP44XX_REG_ROWSIZE_SHIFT,
+		      OMAP44XX_REG_ROWSIZE_MASK,
+		      addressing->row_sz[cs0_device->io_width]);
+
+	set_bit_field(config_reg, OMAP44XX_REG_IBANK_SHIFT,
+		      OMAP44XX_REG_IBANK_MASK, addressing->num_banks);
+
+	set_bit_field(config_reg, OMAP44XX_REG_EBANK_SHIFT,
+		      OMAP44XX_REG_EBANK_MASK,
+		      (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS));
+
+	set_bit_field(config_reg, OMAP44XX_REG_PAGESIZE_SHIFT,
+		      OMAP44XX_REG_PAGESIZE_MASK,
+		      addressing->col_sz[cs0_device->io_width]);
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	set_bit_field(ref_ctrl, OMAP44XX_REG_REFRESH_RATE_SHIFT,
+		      OMAP44XX_REG_REFRESH_RATE_MASK, val);
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_WTR_SHIFT, OMAP44XX_REG_T_WTR_MASK,
+		      val);
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	set_bit_field(tim1, OMAP44XX_REG_T_RRD_SHIFT, OMAP44XX_REG_T_RRD_MASK,
+		      val);
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RC_SHIFT, OMAP44XX_REG_T_RC_MASK,
+		      val);
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RAS_SHIFT, OMAP44XX_REG_T_RAS_MASK,
+		      val);
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_WR_SHIFT, OMAP44XX_REG_T_WR_MASK,
+		      val);
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RCD_SHIFT, OMAP44XX_REG_T_RCD_MASK,
+		      val);
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RP_SHIFT, OMAP44XX_REG_T_RP_MASK,
+		      val);
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_CKE_SHIFT, OMAP44XX_REG_T_CKE_MASK,
+		      val);
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_RTP_SHIFT, OMAP44XX_REG_T_RTP_MASK,
+		      val);
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_XSRD_SHIFT, OMAP44XX_REG_T_XSRD_MASK,
+		      val);
+	set_bit_field(tim2, OMAP44XX_REG_T_XSNR_SHIFT, OMAP44XX_REG_T_XSNR_MASK,
+		      val);
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_XP_SHIFT, OMAP44XX_REG_T_XP_MASK,
+		      val);
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	set_bit_field(tim3, OMAP44XX_REG_T_RAS_MAX_SHIFT,
+		      OMAP44XX_REG_T_RAS_MAX_MASK, val);
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_RFC_SHIFT, OMAP44XX_REG_T_RFC_MASK,
+		      val);
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_TDQSCKMAX_SHIFT,
+		      OMAP44XX_REG_T_TDQSCKMAX_MASK, val);
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_ZQ_ZQCS_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQCS_MASK, val);
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_CKESR_SHIFT,
+		      OMAP44XX_REG_T_CKESR_MASK, val);
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	set_bit_field(zq, OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT,
+		      OMAP44XX_REG_ZQ_REFINTERVAL_MASK, val);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQCL_MULT_MASK, REG_ZQ_ZQCL_MULT - 1);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK, REG_ZQ_ZQINIT_MULT - 1);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_SFEXITEN_SHIFT,
+		      OMAP44XX_REG_ZQ_SFEXITEN_MASK, REG_ZQ_SFEXITEN_ENABLE);
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	set_bit_field(zq, OMAP44XX_REG_ZQ_DUALCALEN_SHIFT,
+		      OMAP44XX_REG_ZQ_DUALCALEN_MASK, REG_ZQ_DUALCALEN_DISABLE);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_CS0EN_SHIFT,
+		      OMAP44XX_REG_ZQ_CS0EN_MASK, REG_ZQ_CS0EN_ENABLE);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_CS1EN_SHIFT,
+		      OMAP44XX_REG_ZQ_CS1EN_MASK, (cs1_device ? 1 : 0));
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	set_bit_field(alert, OMAP44XX_REG_TA_REFINTERVAL_SHIFT,
+		      OMAP44XX_REG_TA_REFINTERVAL_MASK, interval);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_DEVCNT_SHIFT,
+		      OMAP44XX_REG_TA_DEVCNT_MASK, TEMP_ALERT_CONFIG_DEVCT_1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_DEVWDT_SHIFT,
+		      OMAP44XX_REG_TA_DEVWDT_MASK, TEMP_ALERT_CONFIG_DEVWDT_32);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_SFEXITEN_SHIFT,
+		      OMAP44XX_REG_TA_SFEXITEN_MASK, 1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_CS0EN_SHIFT,
+		      OMAP44XX_REG_TA_CS0EN_MASK, 1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_CS1EN_SHIFT,
+		      OMAP44XX_REG_TA_CS1EN_MASK, (cs1_device ? 1 : 0));
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	set_bit_field(idle, OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT,
+		      OMAP44XX_REG_READ_IDLE_INTERVAL_MASK, val);
+
+	set_bit_field(idle, OMAP44XX_REG_READ_IDLE_LEN_SHIFT,
+		      OMAP44XX_REG_READ_IDLE_LEN_MASK,
+		      EMIF_REG_READ_IDLE_LEN_VAL);
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	set_bit_field(phy, OMAP44XX_REG_READ_LATENCY_SHIFT,
+		      OMAP44XX_REG_READ_LATENCY_MASK, RL + 2);
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	set_bit_field(phy, OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT,
+		      OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK, val);
+
+	/* Other fields are constant magic values. Hardcode them together */
+	set_bit_field(phy, OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT,
+		      OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK,
+		      EMIF_DDR_PHY_CTRL_1_BASE_VAL);
+
+	return phy;
+}
+
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
 static inline u32 emif_num(u32 base)
 {
 	if (base == OMAP44XX_EMIF1)
@@ -65,6 +648,127 @@ static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
 	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
 	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
 }
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_syc_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
 void emif_reset_phy(u32 base)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -158,14 +862,66 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 
 static void do_sdram_init(u32 base)
 {
-	const struct emif_regs *regs, *tmp_regs;
+	struct emif_device_details dev_details;
+	const struct emif_regs *regs;
+
 	u32 in_sdram, emif_nr;
 
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	const struct emif_regs *tmp_regs;
 	emif_get_reg_dump(&regs, &tmp_regs);
 	regs = (emif_nr == 1) ? regs : tmp_regs;
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+
+	const struct emif_device_details *dev_details_user_provided;
+	const struct emif_device_details *tmp_details;
+	struct emif_regs calculated_regs;
+
+	/* We need some input about the devices from the user */
+	emif_get_device_details(&dev_details_user_provided, &tmp_details);
+	dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided
+						   : tmp_details;
+	if (!dev_details_user_provided)
+		return;
+
+	dev_details.cs0_device_details =
+			dev_details_user_provided->cs0_device_details;
+	dev_details.cs1_device_details =
+			dev_details_user_provided->cs1_device_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+	/* Use the base timings specified by JESD209-2 */
+	dev_details.cs0_device_timings = &jedec_default_timings;
+	dev_details.cs1_device_timings = &jedec_default_timings;
+
+#else /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+	dev_details.cs0_device_timings =
+			dev_details_user_provided->cs0_device_timings;
+	dev_details.cs1_device_timings =
+			dev_details_user_provided->cs1_device_timings;
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
 	 * Initializing the LPDDR2 device can not happen from SDRAM.
@@ -215,12 +971,111 @@ static void emif_post_init_config(u32 base)
 		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
 }
 
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
 static void dmm_init(u32 base)
 {
 	const struct dmm_lisa_map_regs *lisa_map_regs;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated;
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
 
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				0);
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+				OMAP44XX_SYS_SIZE_MASK,
+				get_dmm_section_size_map(mapped_size * 2));
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+				OMAP44XX_SYS_SIZE_MASK,
+				get_dmm_section_size_map(emif1_size));
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				mapped_size >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+			      OMAP44XX_SYS_SIZE_MASK,
+			      get_dmm_section_size_map(emif2_size));
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				mapped_size >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
 	    (struct dmm_lisa_map_regs *)base;
 
@@ -258,8 +1113,10 @@ static void dmm_init(u32 base)
  */
 void sdram_init(void)
 {
-	u32 in_sdram;
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL)
+		return;
 
+	u32 in_sdram;
 	in_sdram = running_from_sdram();
 
 	if (!in_sdram) {
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 37e808c..e7d2bd5 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -29,6 +29,8 @@
 #include <asm/arch/emif.h>
 #include <asm/arch/sys_proto.h>
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
@@ -86,6 +88,131 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 
 void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs)
+
+#else
+
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz,
+};
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+static const struct emif_device_details elpida_2G_S4_x_2 = {
+	.cs0_device_details = &elpida_2G_S4_details,
+	.cs1_device_details = &elpida_2G_S4_details,
+	.cs0_device_timings = &elpida_2G_S4_timings,
+	.cs1_device_timings = &elpida_2G_S4_timings
+};
+
+static const struct emif_device_details elpida_2G_S4_x_1 = {
+	.cs0_device_details = &elpida_2G_S4_details,
+	.cs1_device_details = NULL,
+	.cs0_device_timings = &elpida_2G_S4_timings,
+	.cs1_device_timings = NULL
+};
+
+#endif /* ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+static void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
 {
 	u32 omap4_rev = omap4_revision();
 
@@ -104,7 +231,8 @@ void emif_get_reg_dump(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
 
-void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
 {
 	u32 omap_rev = omap4_revision();
 
@@ -116,3 +244,25 @@ void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static void emif_get_device_details_sdp(
+			const struct emif_device_details **emif1_details,
+			const struct emif_device_details **emif2_details)
+{
+	u32 omap_rev = omap4_revision();
+
+	if (omap_rev == OMAP4430_ES1_0) {
+		*emif1_details = &elpida_2G_S4_x_1;
+		*emif2_details = &elpida_2G_S4_x_1;
+	} else {
+		*emif1_details = &elpida_2G_S4_x_2;
+		*emif2_details = &elpida_2G_S4_x_2;
+	}
+}
+
+void emif_get_device_details(const struct emif_device_details **emif1_details,
+			     const struct emif_device_details **emif2_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index f2d54cb..8cc3230 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -591,10 +591,142 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 
 #define CS0	0
 #define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
 /* Read Latency used by the device at reset */
 #define RL_BOOT		3
 /* Read Latency for the highest frequency you want to use */
 #define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
 /* EMIF_PWR_MGMT_CTRL register */
 /* Low power modes */
 #define LP_MODE_DISABLE		0
@@ -634,6 +766,16 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 
 /* EMIF_L3_CONFIG register value for ES1*/
 #define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
 
 /*
 * MR1 value:
@@ -657,16 +799,51 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 #define MR10_ZQ_ZQINIT		0xFF
 #define MR10_ZQ_ZQRESET		0xC3
 
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
 /* MR16 value: refresh full array(no partial array self refresh) */
 #define MR16_REF_FULL_ARRAY	0
 
-/* LPDDR2 IO reg values */
+/* LPDDR2 IO regs */
 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
 
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
 /* Mode register numbers */
 #define LPDDR2_MR0	0
 #define LPDDR2_MR1	1
@@ -692,6 +869,119 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 #define LPDDR2_MR0_DNVI_SHIFT	2
 #define LPDDR2_MR0_DNVI_MASK	(1 << 2)
 
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen@lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
 /*
  * Structure containing shadow of important registers in EMIF
  * The calculation function fills in this structure to be later used for
@@ -712,8 +1002,20 @@ struct emif_regs {
 	u32 emif_ddr_phy_ctlr_1;
 };
 
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 void emif_get_reg_dump(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(const struct emif_device_details **emif1_details,
+			     const struct emif_device_details **emif2_details);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a1c4883..fd8fb10 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -86,12 +86,7 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
+
 /*
  * Hardware Register Details
  */
@@ -137,6 +132,17 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+
+/*
+ * SRAM scratch space entries
+ */
+
+/* Boot parameter passed from SPL to U-Boot */
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0x8)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0
 #define OMAP4430_ES1_0	1
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4beff42..211d3b8 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_syc_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_revision(void);
 
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 49daa85..9f2616c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -51,6 +51,27 @@
 		       (addr));\
 	} while (0);
 
+/* find log2 of number n - rounded up */
+static inline u32 log_2_n_round_up(u32 n)
+{
+	u32 clz;
+	/* count leading zeros */
+	asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n));
+	if (n & (n - 1))
+		return 31 - clz; /* power of 2 */
+	else
+		return 32 - clz; /* not power of 2 - round up */
+}
+
+/* find log2 of number n - rounded down */
+static inline u32 log_2_n_round_down(u32 n)
+{
+	u32 clz;
+	/* count leading zeros */
+	asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n));
+	return 31 - clz;
+}
+
 /* Boot device */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 07d45a0..c29b184 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -245,6 +245,11 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index 1f25f77..d89dea0 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -81,6 +81,10 @@ SOBJS	+= start.o
 COBJS	+= syslib.o
 
 # omap-common
+$(obj)utils.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@
+
 $(obj)timer.c:
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@
@@ -94,7 +98,7 @@ $(obj)spl-omap.c:
 	@ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@
 
 SOBJS	+= reset.o
-COBJS	+= timer.o spl-omap.o
+COBJS	+= utils.o timer.o spl-omap.o
 
 $(OBJTREE)/MLO:	$(splobj)u-boot-spl.bin
 	$(OBJTREE)/tools/mkimage -T omapimage \
-- 
1.7.0.4

[U-Boot] [PATCH 18/22] omap4: automatic sdram detection

[Aneesh V]

Identify SDRAM devices connected to EMIF automatically:
LPDDR2 devices have some Mode Registers that provide details
about the device such as the type, density, bus width
etc. EMIF has the capability to read these registers. If there
are not devices connected to a given chip-select reading mode
registers will return junk values. After reading as many such
registers as possible and matching with expected ranges of
values the driver can identify if there is a device connected
to the respective CS. If we identify that a device is connected
the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2
allows us to do a complete automatic initialization of
SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2
will be safe for all devices but not necessarily optimal. However,
for the Elpida devices used on Panda and SDP the default timings
are both safe and optimal.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/emif.c         |  177 +++++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |    9 +-
 include/configs/omap4_sdp4430.h         |    1 +
 3 files changed, 176 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 1bdb1d2..006d065 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -165,7 +165,8 @@ static const struct lpddr2_min_tck min_tck_jedec = {
 	.tFAW = 8
 };
 
-static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
 	&timings_jedec_200_mhz,
 	&timings_jedec_333_mhz,
 	&timings_jedec_400_mhz
@@ -779,6 +780,146 @@ void emif_reset_phy(u32 base)
 	writel(iodft, &emif->emif_iodft_tlgc);
 }
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, LPDDR2_MR0_DI_SHIFT, LPDDR2_MR0_DI_MASK);
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = get_bit_field(mr, LPDDR2_MR0_DNVI_SHIFT, LPDDR2_MR0_DNVI_MASK);
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, MR8_TYPE_SHIFT, MR8_TYPE_MASK);
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = get_bit_field(mr, MR8_DENSITY_SHIFT, MR8_DENSITY_MASK);
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = get_bit_field(mr, MR8_IO_WIDTH_SHIFT, MR8_IO_WIDTH_MASK);
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_syc_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_lpddr2_init(u32 base, u32 cs)
 {
 	u32 mr_addr;
@@ -862,9 +1003,7 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 
 static void do_sdram_init(u32 base)
 {
-	struct emif_device_details dev_details;
 	const struct emif_regs *regs;
-
 	u32 in_sdram, emif_nr;
 
 	in_sdram = running_from_sdram();
@@ -872,6 +1011,7 @@ static void do_sdram_init(u32 base)
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	const struct emif_regs *tmp_regs;
+
 	emif_get_reg_dump(&regs, &tmp_regs);
 	regs = (emif_nr == 1) ? regs : tmp_regs;
 #else
@@ -879,23 +1019,48 @@ static void do_sdram_init(u32 base)
 	 * The user has not provided the register values. We need to
 	 * calculate it based on the timings and the DDR frequency
 	 */
+	struct emif_device_details dev_details = { NULL, NULL };
+	struct emif_regs calculated_regs;
 
+#if !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
+
+	/* We need some input about the devices from the user */
 	const struct emif_device_details *dev_details_user_provided;
 	const struct emif_device_details *tmp_details;
-	struct emif_regs calculated_regs;
 
-	/* We need some input about the devices from the user */
 	emif_get_device_details(&dev_details_user_provided, &tmp_details);
 	dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided
 						   : tmp_details;
 	if (!dev_details_user_provided)
 		return;
+#endif
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+
+	/* Automatically find the device details */
+	if (!in_sdram) {
+		dev_details.cs0_device_details =
+		    get_lpddr2_details(base, CS0, &cs0_dev_details);
+		dev_details.cs1_device_details =
+		    get_lpddr2_details(base, CS1, &cs1_dev_details);
+		/*
+		 * Reset the PHY - if there is nothing connected on any
+		 * of the chip selects(typically CS1) mode register reads
+		 * will mess up with the PHY state and subsequent
+		 * initialization won't work. PHY reset brings back PHY to
+		 * a good state.
+		 */
+		emif_reset_phy(base);
+	}
+#else
 	dev_details.cs0_device_details =
 			dev_details_user_provided->cs0_device_details;
 	dev_details.cs1_device_details =
 			dev_details_user_provided->cs1_device_details;
 
+#endif
 	/* Return if no devices on this EMIF */
 	if (!dev_details.cs0_device_details &&
 	    !dev_details.cs1_device_details) {
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index e7d2bd5..8dfe6f9 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -86,10 +86,8 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 	.dmm_lisa_map_3 = 0x80640300
 };
 
-void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
-			const struct emif_regs **emif2_regs)
-
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 	.max_freq	= 400000000,
@@ -245,7 +243,8 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static void emif_get_device_details_sdp(
 			const struct emif_device_details **emif1_details,
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index c29b184..a4332b7 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -247,6 +247,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH 19/22] armv7: embed u-boot size within u-boot for use from SPL

[Aneesh V]

Embed the u-boot flash image size at a known offset from the
start of u-boot so that SPL can use it while loading u-boot
from a non-XIP media.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/start.S |    6 +++++-
 spl/board/ti/spl-omap.lds  |    1 +
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f5f08d9..1cbd128 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -64,8 +64,12 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
 
 .global _end_vect
 _end_vect:
+.global	_u_boot_size
+_u_boot_size:
+	.word	0xDEADBEEF
+	.word	__flash_image_end - _start
 
-	.balignl 16,0xdeadbeef
+.balignl 16,0xdeadbeef
 /*************************************************************************
  *
  * Startup Code (reset vector)
diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds
index 27b5295..64eb4c9 100644
--- a/spl/board/ti/spl-omap.lds
+++ b/spl/board/ti/spl-omap.lds
@@ -50,6 +50,7 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
 	__image_copy_end = .;
+	__flash_image_end = .;
 
 	.bss :
 	{
-- 
1.7.0.4

[U-Boot] [PATCH 20/22] omap: add MMC support to SPL

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/start.S         |    1 +
 arch/arm/include/asm/omap_common.h |    4 +
 include/configs/omap4_sdp4430.h    |    7 ++-
 spl/board/ti/sdp4430/Makefile      |   35 +++++++++++
 spl/board/ti/spl-omap.c            |  112 +++++++++++++++++++++++++++++++++++-
 5 files changed, 156 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 1cbd128..927476c 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -64,6 +64,7 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
 
 .global _end_vect
 _end_vect:
+/* This label should be at the same location for SPL and U-Boot */
 .global	_u_boot_size
 _u_boot_size:
 	.word	0xDEADBEEF
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 9f2616c..c2efa7c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -99,4 +99,8 @@ u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 void preloader_console_init(void);
 
+/* symbols from start.S */
+extern u32 _u_boot_size;
+extern u32 _start;
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index a4332b7..0ed474d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -257,7 +257,10 @@
 #define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
 #define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
-#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index d89dea0..18c5b8e 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -68,6 +68,41 @@ $(obj)ctype.c:
 COBJS	+= serial.o ns16550.o string.o vsprintf.o console.o stdio.o
 COBJS	+= ctype.o eabi_compat.o div64.o
 
+
+# mmc
+$(obj)mmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/mmc.c $@
+
+$(obj)omap_hsmmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@
+
+$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@
+
+$(obj)omap24xx_i2c.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@
+
+$(obj)time.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/time.c $@
+
+$(obj)part.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part.c $@
+
+$(obj)part_dos.c: $(obj)part_dos.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.c $@
+
+$(obj)part_dos.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.h $@
+
+COBJS	+= omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 57ddb7d..b64eac9 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -28,24 +28,134 @@
 #include <common.h>
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
+#include <mmc.h>
 #include <timestamp_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
 
 /* Define global data structure pointer to it*/
 gd_t gdata __attribute__ ((section(".data")));
 bd_t bdata __attribute__ ((section(".data")));
 gd_t *gd = &gdata;
 
+typedef void (*u_boot_entry_t)(void)__attribute__ ((noreturn));
+
 void board_init_f(ulong dummy)
 {
 	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
 }
 
-void board_init_r(gd_t *id, ulong dummy)
+inline void hang(void)
 {
+	puts("### ERROR ### Please RESET the board ###\n");
 	for (;;)
 		;
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
+
+static void mmc_load_uboot_raw(struct mmc *mmc, u32 mmc_dev)
+{
+	u32 u_boot_size_sectors, err;
+	u32 *u_boot_size = (u32 *)(CONFIG_SYS_TEXT_BASE +
+				(u32) &_u_boot_size - (u32) &_start);
+
+	/* read one sector first to find u-boot size */
+	err = mmc->block_dev.block_read(mmc_dev,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)CONFIG_SYS_TEXT_BASE);
+	if (err <= 0)
+		goto end;
+
+	if (*u_boot_size != 0xDEADBEEF) {
+		err = 0xDEADBEEF;
+		goto end;
+	}
+
+	/* move to the next word that has size */
+	u_boot_size++;
+
+	/*
+	 * convert size to sectors - round down is fine because we have
+	 * already read 1 sector
+	 */
+	u_boot_size_sectors = *u_boot_size/MMCSD_SECTOR_SIZE;
+	debug("spl: u-boot raw sectors - %d\n", u_boot_size_sectors + 1);
+	/* read one sector first to find u-boot size */
+	err = mmc->block_dev.block_read(mmc_dev,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + 1,
+			u_boot_size_sectors,
+			(void *)(CONFIG_SYS_TEXT_BASE + MMCSD_SECTOR_SIZE));
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_uboot(u32 mmc_dev)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	mmc = find_mmc_device(mmc_dev);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: mmc_dev - %d err - %d\n",
+			mmc_dev, err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW)
+		mmc_load_uboot_raw(mmc, mmc_dev);
+	else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	u32 boot_device;
+	u_boot_entry_t u_boot_entry = (u_boot_entry_t) CONFIG_SYS_TEXT_BASE;
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	boot_device = omap_boot_device();
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1);
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	/*
+	 * Jump to u-boot with magic number as input to indicate that it
+	 * was loaded by SPL
+	 */
+	u_boot_entry();
+}
+
 void preloader_console_init(void)
 {
 	gd->bd = &bdata;
-- 
1.7.0.4

[U-Boot] [PATCH 21/22] omap: spl: add FAT support over MMC

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 include/configs/omap4_sdp4430.h |    1 +
 spl/board/ti/sdp4430/Makefile   |    8 ++++++++
 spl/board/ti/spl-omap.c         |   22 ++++++++++++++++++++++
 3 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 0ed474d..dcc9e39 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -259,6 +259,7 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 
 #define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
 #define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
diff --git a/spl/board/ti/sdp4430/Makefile b/spl/board/ti/sdp4430/Makefile
index 18c5b8e..8310db9 100644
--- a/spl/board/ti/sdp4430/Makefile
+++ b/spl/board/ti/sdp4430/Makefile
@@ -103,6 +103,14 @@ $(obj)part_dos.h:
 	@ln -s $(TOPDIR)/disk/part_dos.h $@
 
 COBJS	+= omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o
+
+# fat
+$(obj)fat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/fs/fat/fat.c $@
+
+COBJS	+=  fat.o
+
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index b64eac9..3612434 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -29,6 +29,7 @@
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mmc_host_def.h>
@@ -101,6 +102,25 @@ end:
 	}
 }
 
+static void mmc_load_uboot_fat(struct mmc *mmc)
+{
+	s32 err;
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read("u-boot.bin", (u8 *)CONFIG_SYS_TEXT_BASE, 0);
+
+	if (err <= 0) {
+		printf("spl: error reading u-boot.bin - %d\n", err);
+		hang();
+	}
+}
+
 static void mmc_load_uboot(u32 mmc_dev)
 {
 	struct mmc *mmc;
@@ -124,6 +144,8 @@ static void mmc_load_uboot(u32 mmc_dev)
 	boot_mode = omap_boot_mode();
 	if (boot_mode == MMCSD_MODE_RAW)
 		mmc_load_uboot_raw(mmc, mmc_dev);
+	else if (boot_mode == MMCSD_MODE_FAT)
+		mmc_load_uboot_fat(mmc);
 	else {
 		puts("spl: wrong MMC boot mode\n");
 		hang();
-- 
1.7.0.4

[U-Boot] [PATCH 22/22] omap4: add spl support for OMAP4 Panda

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/include/asm/arch-omap4/emif.h |   10 +-
 include/configs/omap4_panda.h          |   24 ++++
 spl/board/ti/panda/Makefile            |  219 ++++++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+), 5 deletions(-)
 create mode 100644 spl/board/ti/panda/Makefile

diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 8cc3230..b95e545 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -520,11 +520,11 @@
 
 /* Trap for invalid TILER PAT entries */
 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
-		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
-		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
-		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
-		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
-		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
 
 
 /* Reg mapping structure */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 2b03b0f..b389035 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -117,7 +117,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */
@@ -234,4 +236,26 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/panda/Makefile b/spl/board/ti/panda/Makefile
new file mode 100644
index 0000000..8310db9
--- /dev/null
+++ b/spl/board/ti/panda/Makefile
@@ -0,0 +1,219 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+splobj	:= $(OBJTREE)/spl/
+include $(TOPDIR)/config.mk
+SOBJS =
+COBJS =
+
+# serial console
+$(obj)eabi_compat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@
+
+$(obj)string.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/string.c $@
+
+$(obj)vsprintf.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/vsprintf.c $@
+
+$(obj)console.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/console.c $@
+
+$(obj)stdio.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/stdio.c $@
+
+$(obj)serial.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/serial.c $@
+
+$(obj)ns16550.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/ns16550.c $@
+
+$(obj)div64.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/div64.c $@
+
+$(obj)ctype.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/ctype.c $@
+
+COBJS	+= serial.o ns16550.o string.o vsprintf.o console.o stdio.o
+COBJS	+= ctype.o eabi_compat.o div64.o
+
+
+# mmc
+$(obj)mmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/mmc.c $@
+
+$(obj)omap_hsmmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@
+
+$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@
+
+$(obj)omap24xx_i2c.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@
+
+$(obj)time.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/time.c $@
+
+$(obj)part.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part.c $@
+
+$(obj)part_dos.c: $(obj)part_dos.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.c $@
+
+$(obj)part_dos.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.h $@
+
+COBJS	+= omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o
+
+# fat
+$(obj)fat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/fs/fat/fat.c $@
+
+COBJS	+=  fat.o
+
+# armv7
+$(obj)start.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
+
+$(obj)syslib.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@
+
+SOBJS	+= start.o
+COBJS	+= syslib.o
+
+# omap-common
+$(obj)utils.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@
+
+$(obj)timer.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@
+
+$(obj)reset.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@
+
+$(obj)spl-omap.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@
+
+SOBJS	+= reset.o
+COBJS	+= utils.o timer.o spl-omap.o
+
+$(OBJTREE)/MLO:	$(splobj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@
+
+LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds
+
+# omap4
+$(obj)lowlevel_init.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@
+
+$(obj)omap4_mux_data.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@
+
+$(obj)board.c:$(obj)omap4_mux_data.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
+
+$(obj)emif.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@
+
+$(obj)sdram_elpida.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@
+
+$(obj)clocks.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@
+
+SOBJS	+= lowlevel_init.o
+COBJS	+= board.o clocks.o emif.o sdram_elpida.o
+
+# rules
+LDPPFLAGS += -include $(TOPDIR)/include/config.h
+LDSCRIPT = $(splobj)u-boot-spl-generated.lds
+$(LDSCRIPT): $(LDSCRIPT_SOURCE)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) \
+	$(PLATFORM_LDFLAGS) --gc-sections
+AFLAGS	+= -DCONFIG_PRELOADER -Os -ffixed-r8
+CFLAGS	+= -DCONFIG_PRELOADER -Os -ffixed-r8 -ffunction-sections \
+	-fdata-sections -march=armv7-a -mthumb
+PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \
+		-print-libgcc-file-name`) -lgcc
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/spl/board/$(BOARDDIR)
+
+$(splobj)u-boot-spl.bin:	$(splobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(splobj)u-boot-spl:	$(OBJS) $(LDSCRIPT)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		$(PLATFORM_LIBGCC) \
+		-Map $(splobj)u-boot-spl.map \
+		-o $(splobj)u-boot-spl
+
+ALL	= $(OBJTREE)/MLO
+all:	$(obj).depend $(ALL)
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
-- 
1.7.0.4

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Bedia, Vaibhav]

Aneesh,

On Monday, February 28, 2011 5:16 PM, V, Aneesh wrote:
> From: John Rigby <john.rigby@linaro.org>
> 
> Signed-off-by: John Rigby <john.rigby@linaro.org>
> ---
>  common/image.c    |    1 +
>  include/image.h   |    1 +
>  tools/Makefile    |    2 +
>  tools/mkimage.c   |    2 +
>  tools/mkimage.h   |    1 +
>  tools/omapimage.c |  229
>  +++++++++++++++++++++++++++++++++++++++++++++++++++++
>  tools/omapimage.h |   50 ++++++++++++ 7 files changed, 286
> insertions(+), 0 deletions(-)  create mode 100644
> tools/omapimage.c  create mode 100644 tools/omapimage.h  

As pointed in the RFC[1] which was posted by John, we should separate out the
configuration header part as that is optional. We should also consider renaming
it to make it generic. What do you think?

Regards,
Vaibhav

[1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/91511/focus=91808

[U-Boot] [PATCH 04/22] armv7: start.S: provide a hook for saving boot params

[Bedia, Vaibhav]

On Monday, February 28, 2011 5:16 PM, V, Aneesh wrote:
> Provide a means by which u-boot/SPL can save parameters passed
> to it by ROM code or the pre-loader. 
> 
> A new function 'save_boot_params' has been defined and a
> default implentation provided. Please note that we do not have
> a stack yet. So, any implementation of this function should
> not use stack.  
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---

This is an essential feature when there no x-loader in the picture.
Thanks for posting a patch for this :)

Regards,
Vaibhav

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[John Rigby]

On Tue, Mar 1, 2011 at 7:24 AM, Bedia, Vaibhav <vaibhav.bedia@ti.com> wrote:
> Aneesh,
>
> On Monday, February 28, 2011 5:16 PM, V, Aneesh wrote:
>> From: John Rigby <john.rigby@linaro.org>
>>
>> Signed-off-by: John Rigby <john.rigby@linaro.org>
>> ---
>> ?common/image.c ? ?| ? ?1 +
>> ?include/image.h ? | ? ?1 +
>> ?tools/Makefile ? ?| ? ?2 +
>> ?tools/mkimage.c ? | ? ?2 +
>> ?tools/mkimage.h ? | ? ?1 +
>> ?tools/omapimage.c | ?229
>> ?+++++++++++++++++++++++++++++++++++++++++++++++++++++
>> ?tools/omapimage.h | ? 50 ++++++++++++ 7 files changed, 286
>> insertions(+), 0 deletions(-) ?create mode 100644
>> tools/omapimage.c ?create mode 100644 tools/omapimage.h
>
> As pointed in the RFC[1] which was posted by John, we should separate out the
> configuration header part as that is optional. We should also consider renaming
> it to make it generic. What do you think?
>
Vaibhav,

If you submit a patch that does this I will gladly ack it.

John

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Vaibhav,

On Tuesday 01 March 2011 07:54 PM, Bedia, Vaibhav wrote:
> Aneesh,
>
> On Monday, February 28, 2011 5:16 PM, V, Aneesh wrote:
>> From: John Rigby<john.rigby@linaro.org>
>>
>> Signed-off-by: John Rigby<john.rigby@linaro.org>
>> ---
>>   common/image.c    |    1 +
>>   include/image.h   |    1 +
>>   tools/Makefile    |    2 +
>>   tools/mkimage.c   |    2 +
>>   tools/mkimage.h   |    1 +
>>   tools/omapimage.c |  229
>>   +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   tools/omapimage.h |   50 ++++++++++++ 7 files changed, 286
>> insertions(+), 0 deletions(-)  create mode 100644
>> tools/omapimage.c  create mode 100644 tools/omapimage.h
>
> As pointed in the RFC[1] which was posted by John, we should separate out the
> configuration header part as that is optional. We should also consider renaming
> it to make it generic. What do you think?

For OMAP4:
1. An 8 byte GP header is enough for booting from external MMC FAT
    partition
2. A dummy CH with a dummy CHSETTINGS is essential for booting from
    the RAW partition of eMMC or external MMC. This works for FAT
    booting too.
3. A full configuration with proper CHSETTINGS and CHRAM will help us
    in directly booting from SDRAM avoiding the SPL, but this is not
    supported on all revisions of OMAP3/4

IMHO, let's have one image type(what John has created now) for (1) and
(2). It doesn't really harm to have 512 bytes of additional header
attached to your image when it makes it suitable for different types of
booting.

For 3, if that is supported in U-Boot in future, we will need a new
image type, maybe something like omapchimage.

Let me know if you had any special considerations for your SoC.

Best regards,
Aneesh

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Bedia, Vaibhav]

On Tuesday, March 01, 2011 8:20 PM, V, Aneesh wrote:
[...]
> For OMAP4:
> 1. An 8 byte GP header is enough for booting from external MMC
>     FAT partition
> 2. A dummy CH with a dummy CHSETTINGS is essential for booting
>     from the RAW partition of eMMC or external MMC. This works
>     for FAT booting too.
> 3. A full configuration with proper CHSETTINGS and CHRAM will
>     help us in directly booting from SDRAM avoiding the SPL,
>     but this is not supported on all revisions of OMAP3/4
> 
> IMHO, let's have one image type(what John has created now) for
> (1) and (2). It doesn't really harm to have 512 bytes of
> additional header attached to your image when it makes it
> suitable for different types of booting.   
> 
> For 3, if that is supported in U-Boot in future, we will need
> a new image type, maybe something like omapchimage. 
> 
> Let me know if you had any special considerations for your SoC.

(My response on this yesterday bounced back for some reason)

I will try out this patch and see if the additional 512 bytes works for us also.

Regards,
Vaibhav

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Bedia, Vaibhav]

Aneesh,

On Tuesday, March 01, 2011 8:34 PM, Bedia, Vaibhav wrote:
> On Tuesday, March 01, 2011 8:20 PM, V, Aneesh wrote:
>> 
>> For OMAP4:
>> 1. An 8 byte GP header is enough for booting from external
>> MMC     FAT partition 
>> 2. A dummy CH with a dummy CHSETTINGS is essential for booting
>>     from the RAW partition of eMMC or external MMC. This
>> works     for FAT booting too. 
>> 3. A full configuration with proper CHSETTINGS and CHRAM will
>>     help us in directly booting from SDRAM avoiding the SPL,
>>     but this is not supported on all revisions of OMAP3/4
>> 
>> IMHO, let's have one image type(what John has created now) for
>> (1) and (2). It doesn't really harm to have 512 bytes of
>> additional header attached to your image when it makes it
>> suitable for different types of booting.
>> 
>> For 3, if that is supported in U-Boot in future, we will need
>> a new image type, maybe something like omapchimage.
>> 
>> Let me know if you had any special considerations for your
>> SoC. 
> 
> I will have to check if the additional 512 bytes will cause a
> problem for TI81XX GP devices. We haven't tried with the extra
> 512 bytes yet.  
> 

I checked the image with the additional 512bytes on TI81XX. It does not work.

If its fine with you I'll work on using a version flag for attaching the 512byte.
How about something on the lines of what was done for imximage did recently?

Regards,
Vaibhav

[U-Boot] [PATCH 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Vaibhav,

On Friday 04 March 2011 10:57 AM, Bedia, Vaibhav wrote:
> Aneesh,
>
> On Tuesday, March 01, 2011 8:34 PM, Bedia, Vaibhav wrote:
>> On Tuesday, March 01, 2011 8:20 PM, V, Aneesh wrote:
>>>
>>> For OMAP4:
>>> 1. An 8 byte GP header is enough for booting from external
>>> MMC     FAT partition
>>> 2. A dummy CH with a dummy CHSETTINGS is essential for booting
>>>      from the RAW partition of eMMC or external MMC. This
>>> works     for FAT booting too.
>>> 3. A full configuration with proper CHSETTINGS and CHRAM will
>>>      help us in directly booting from SDRAM avoiding the SPL,
>>>      but this is not supported on all revisions of OMAP3/4
>>>
>>> IMHO, let's have one image type(what John has created now) for
>>> (1) and (2). It doesn't really harm to have 512 bytes of
>>> additional header attached to your image when it makes it
>>> suitable for different types of booting.
>>>
>>> For 3, if that is supported in U-Boot in future, we will need
>>> a new image type, maybe something like omapchimage.
>>>
>>> Let me know if you had any special considerations for your
>>> SoC.
>>
>> I will have to check if the additional 512 bytes will cause a
>> problem for TI81XX GP devices. We haven't tried with the extra
>> 512 bytes yet.
>>
>
> I checked the image with the additional 512bytes on TI81XX. It does not work.
>
> If its fine with you I'll work on using a version flag for attaching the 512byte.
> How about something on the lines of what was done for imximage did recently?

I really don't know what this scheme is. But if it works it will be
really great.

Best regards,
Aneesh

[U-Boot] [PATCH 06/22] arm: new labels in the linker script file

[Po-Yu Chuang]

Hi Aneesh,

On Mon, Feb 28, 2011 at 7:46 PM, Aneesh V <aneesh@ti.com> wrote:
> _bss_start_ofs is used in start.S to indicate end of copied
> image. This may not be correct when we have a discontiguous
> memory map. For instance, .bss may be placed in SDRAM for
> some SPLS while rest of the image is placed in SRAM.
>
> Define a new label in linker script to indicate the end of the
> image copied during relocation and use it appropriately in
> start.S.
>
> Also, add a new label to indicate the end of flash image.
> This will be useful in identifying the size of flash image
>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> ?arch/arm/cpu/armv7/start.S ? ?| ? ?6 +++++-
> ?arch/arm/cpu/armv7/u-boot.lds | ? ?4 ++++
> ?2 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 3618190..8215d26 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -77,6 +77,10 @@ _TEXT_BASE:
> ?_bss_start_ofs:
> ? ? ? ?.word __bss_start - _start
>
> +.global ? ? ? ?_image_copy_end_ofs
> +_image_copy_end_ofs:
> + ? ? ? .word ? __image_copy_end - _start
> +
> ?.globl _bss_end_ofs
> ?_bss_end_ofs:
> ? ? ? ?.word _end - _start
> @@ -172,7 +176,7 @@ stack_setup:
> ? ? ? ?beq ? ? clear_bss ? ? ? ? ? ? ? /* skip relocation */
> ?#endif
> ? ? ? ?mov ? ? r1, r6 ? ? ? ? ? ? ? ? ?/* r1 <- scratch for copy_loop */
> - ? ? ? ldr ? ? r3, _bss_start_ofs
> + ? ? ? ldr ? ? r3, _image_copy_end_ofs
> ? ? ? ?add ? ? r2, r0, r3 ? ? ? ? ? ? ?/* r2 <- source end address ? ? ? ? */
>
> ?copy_loop:
> diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
> index 5725c30..c3ad587 100644
> --- a/arch/arm/cpu/armv7/u-boot.lds
> +++ b/arch/arm/cpu/armv7/u-boot.lds
> @@ -55,6 +55,8 @@ SECTIONS
>
> ? ? ? ?. = ALIGN(4);
>
> + ? ? ? __image_copy_end = .;
> +
> ? ? ? ?.rel.dyn : {
> ? ? ? ? ? ? ? ?__rel_dyn_start = .;
> ? ? ? ? ? ? ? ?*(.rel*)
> @@ -66,6 +68,8 @@ SECTIONS
> ? ? ? ? ? ? ? ?*(.dynsym)
> ? ? ? ?}
>
> + ? ? ? __flash_image_end = .;
> +
> ? ? ? ?.bss __rel_dyn_start (OVERLAY) : {
> ? ? ? ? ? ? ? ?__bss_start = .;
> ? ? ? ? ? ? ? ?*(.bss)

There is a patch series which makes _end as end of image and
has been applied to arm branch.

[U-Boot] [PATCH 1/2 v2] rename _end to __bss_end__
http://lists.denx.de/pipermail/u-boot/2011-March/088166.html

[U-Boot] [PATCH 2/2 v2] arm: fix incorrect monitor protection	region in FLASH
http://lists.denx.de/pipermail/u-boot/2011-March/088139.html

You can use the newly added symbol _end_ofs to replace your
__flash_image_end here.

best regards,
Po-Yu Chuang

[U-Boot] [PATCH 06/22] arm: new labels in the linker script file

[Aneesh V]

On Tuesday 08 March 2011 03:42 PM, Po-Yu Chuang wrote:
> Hi Aneesh,
>
[snip ..]
>> +       __flash_image_end = .;
>> +
>>         .bss __rel_dyn_start (OVERLAY) : {
>>                 __bss_start = .;
>>                 *(.bss)
>
> There is a patch series which makes _end as end of image and
> has been applied to arm branch.
>
> [U-Boot] [PATCH 1/2 v2] rename _end to __bss_end__
> http://lists.denx.de/pipermail/u-boot/2011-March/088166.html
>
> [U-Boot] [PATCH 2/2 v2] arm: fix incorrect monitor protection	region in FLASH
> http://lists.denx.de/pipermail/u-boot/2011-March/088139.html
>
> You can use the newly added symbol _end_ofs to replace your
> __flash_image_end here.

Thanks for the pointer. I will do that in v2.

best regards,
Aneesh

[U-Boot] [PATCH 17/22] omap4: calculate EMIF register values

[John Rigby]

On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V <aneesh@ti.com> wrote:
> Calculate EMIF register values based on AC timing parameters
> from the SDRAM datasheet and the DDR frequency rather than
> using the hard-coded values.
>
> For a new board the user doen't have to go through the tedious
> process of calculating the register values. Instead, just
> provide the AC timings from the device data sheet as input
> and the driver will automatically calculate the register values.
>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---


I get some warnings from arch/arm/cpu/armv7/omap4/emif.c:
emif.c: In function ?sdram_init?:
emif.c:1164:43: warning: ?section_map? may be used uninitialized in
this function
emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
be used uninitialized in this function
emif.c: In function ?sdram_init?:
emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
be used uninitialized in this function

Looking at the code I see that these are initialized but the compiler
can't firgure that out.

John

[U-Boot] [PATCH 17/22] omap4: calculate EMIF register values

[Aneesh V]

On Wednesday 09 March 2011 10:16 AM, John Rigby wrote:
> On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V<aneesh@ti.com>  wrote:
>> Calculate EMIF register values based on AC timing parameters
>> from the SDRAM datasheet and the DDR frequency rather than
>> using the hard-coded values.
>>
>> For a new board the user doen't have to go through the tedious
>> process of calculating the register values. Instead, just
>> provide the AC timings from the device data sheet as input
>> and the driver will automatically calculate the register values.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>
>
> I get some warnings from arch/arm/cpu/armv7/omap4/emif.c:
> emif.c: In function ?sdram_init?:
> emif.c:1164:43: warning: ?section_map? may be used uninitialized in
> this function
> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
> be used uninitialized in this function
> emif.c: In function ?sdram_init?:
> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
> be used uninitialized in this function
>
> Looking at the code I see that these are initialized but the compiler
> can't firgure that out.

I don't see the warnings with my tool-chain ((Sourcery G++ Lite
2010q1-202) GCC 4.4.1)

I tried immediately after this patch and also after applying all the
patches. Which compiler are you using?

best regards,
Aneesh

[U-Boot] [PATCH 17/22] omap4: calculate EMIF register values

[John Rigby]

On Tue, Mar 8, 2011 at 10:08 PM, Aneesh V <aneesh@ti.com> wrote:
> On Wednesday 09 March 2011 10:16 AM, John Rigby wrote:
>>
>> On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V<aneesh@ti.com> ?wrote:
>>>
>>> Calculate EMIF register values based on AC timing parameters
>>> from the SDRAM datasheet and the DDR frequency rather than
>>> using the hard-coded values.
>>>
>>> For a new board the user doen't have to go through the tedious
>>> process of calculating the register values. Instead, just
>>> provide the AC timings from the device data sheet as input
>>> and the driver will automatically calculate the register values.
>>>
>>> Signed-off-by: Aneesh V<aneesh@ti.com>
>>> ---
>>
>>
>> I get some warnings from arch/arm/cpu/armv7/omap4/emif.c:
>> emif.c: In function ?sdram_init?:
>> emif.c:1164:43: warning: ?section_map? may be used uninitialized in
>> this function
>> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
>> be used uninitialized in this function
>> emif.c: In function ?sdram_init?:
>> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
>> be used uninitialized in this function
>>
>> Looking at the code I see that these are initialized but the compiler
>> can't firgure that out.
>
> I don't see the warnings with my tool-chain ((Sourcery G++ Lite
> 2010q1-202) GCC 4.4.1)
>
> I tried immediately after this patch and also after applying all the
> patches. Which compiler are you using?

The latest Linaro cross toolchain:

$ arm-linux-gnueabi-gcc --version
arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.5.2-1ubuntu3ppa1) 4.5.2

>
> best regards,
> Aneesh
>

[U-Boot] [PATCH 17/22] omap4: calculate EMIF register values

[Aneesh V]

On Wednesday 09 March 2011 10:16 AM, John Rigby wrote:
> On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V<aneesh@ti.com>  wrote:
>> Calculate EMIF register values based on AC timing parameters
>> from the SDRAM datasheet and the DDR frequency rather than
>> using the hard-coded values.
>>
>> For a new board the user doen't have to go through the tedious
>> process of calculating the register values. Instead, just
>> provide the AC timings from the device data sheet as input
>> and the driver will automatically calculate the register values.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>
>
> I get some warnings from arch/arm/cpu/armv7/omap4/emif.c:

I installed Linaro GCC 4.5.2 and I see these warnings now.

> emif.c: In function ?sdram_init?:
> emif.c:1164:43: warning: ?section_map? may be used uninitialized in

Technically, I think this is a false alarm. Although section_map is
initialized conditionally the use is also conditional. So, if the
compiler had done proper data flow analysis it could see that this
won't happen (I don't know if compilers do that kind of analysis)
Nevertheless, we could avoid it. I will fix it in v2.

> this function
> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
> be used uninitialized in this function
> emif.c: In function ?sdram_init?:
> emif.c:1166:27: warning: ?lis_map_regs_calculated$dmm_lisa_map_3? may
> be used uninitialized in this function

This is genuine. In one path it may be used uninitialized(this
path is not expected in real scenarios). I will fix this.

Thanks,
Aneesh

[U-Boot] [PATCH 00/22] U-Boot MMC SPL for OMAP4

[Aneesh V]

Hi,

Are there anymore comments on this series?

On Monday 28 February 2011 05:16 PM, Aneesh V wrote:
> This series adds mmc SPL support for OMAP4. This is essentially
> an up-streaming effort for TI's x-loader for OMAP4 using the SPL
> framework
>
> This work partly draws upon previous work done for x-loader by:
> 	Santosh Shilimkar<santosh.shilimkar@ti.com>
> 	Rajendra Nayak<rnayak@ti.com>
> and many others
>
> Features supported:
> * Clock init - DPLL locking, clock domains/modules enabling
> * SDRAM/DMM initialization
> * Mux initialization
> * MMC raw read support
> * MMC FAT read support
>
> Improvments over x-loader:
> * Code completely revamped
> * DPLL programming that works for all SYS_CLK frequencies
> * Automatic SDRAM identification and initialization
> * Board dependent parts(especially mux) deferred to u-boot. So, same
>    SPL will work for Panda and SDP and most likely on any other board
>    that comes along
> * Determination of u-boot size to avoid reading extra content while
>    loading U-Boot
> * Modular apporach to enable future addition of support for all OMAP3/4
>    platforms
>
> Aneesh V (21):
>    omap: add miscellaneous utility macros for bit-field operations
>    omap4: add OMAP4430 revision check
>    armv7: start.S: provide a hook for saving boot params
>    omap4: save parameters passed by ROM code to SPL
>    arm: new labels in the linker script file
>    Add generic spl infrastructure
>    armv7: start.S: add SPL support
>    omap: add spl support
>    omap4: add spl support for OMAP4 SDP
>    omap4: add serial console support to SPL
>    omap4: utility function to identify the context of hw init
>    omap4: separate mux settings into essential and non essential parts
>    omap4: correct mux data for sdp4430
>    omap4: add clock support
>    omap4: add sdram init support
>    omap4: calculate EMIF register values
>    omap4: automatic sdram detection
>    armv7: embed u-boot size within u-boot for use from SPL
>    omap: add MMC support to SPL
>    omap: spl: add FAT support over MMC
>    omap4: add spl support for OMAP4 Panda
>
> John Rigby (1):
>    mkimage: Add OMAP boot image support
>
>   Makefile                                           |   11 +
>   arch/arm/cpu/armv7/cpu.c                           |    7 +
>   arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
>   .../{omap4/lowlevel_init.S =>  omap-common/utils.c} |   58 +-
>   arch/arm/cpu/armv7/omap4/Makefile                  |    3 +
>   arch/arm/cpu/armv7/omap4/board.c                   |  117 ++-
>   arch/arm/cpu/armv7/omap4/clocks.c                  |  717 +++++++++++
>   arch/arm/cpu/armv7/omap4/emif.c                    | 1303 ++++++++++++++++++++
>   arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
>   arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
>   arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  267 ++++
>   arch/arm/cpu/armv7/start.S                         |   50 +-
>   arch/arm/cpu/armv7/u-boot.lds                      |    4 +
>   arch/arm/include/asm/arch-omap4/clocks.h           |  504 ++++++++
>   arch/arm/include/asm/arch-omap4/emif.h             | 1021 +++++++++++++++
>   arch/arm/include/asm/arch-omap4/omap4.h            |   50 +-
>   arch/arm/include/asm/arch-omap4/sys_proto.h        |   60 +-
>   .../omap4/lowlevel_init.S =>  include/asm/armv7.h}  |   32 +-
>   arch/arm/include/asm/global_data.h                 |    5 +
>   arch/arm/include/asm/omap_common.h                 |  106 ++
>   board/ti/panda/panda.c                             |   25 +-
>   board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} |   76 +-
>   board/ti/sdp4430/config.mk                         |    3 +-
>   board/ti/sdp4430/sdp.c                             |   25 +-
>   .../{panda/panda.h =>  sdp4430/sdp4430_mux_data.h}  |  128 +--
>   common/image.c                                     |    1 +
>   include/configs/omap4_panda.h                      |   24 +
>   include/configs/omap4_sdp4430.h                    |   24 +
>   include/image.h                                    |    1 +
>   spl/board/ti/panda/Makefile                        |  219 ++++
>   spl/board/ti/sdp4430/Makefile                      |  219 ++++
>   spl/board/ti/spl-omap.c                            |  189 +++
>   .../armv7/u-boot.lds =>  spl/board/ti/spl-omap.lds  |   70 +-
>   tools/Makefile                                     |    2 +
>   tools/mkimage.c                                    |    2 +
>   tools/mkimage.h                                    |    1 +
>   tools/omapimage.c                                  |  229 ++++
>   .../omap4/lowlevel_init.S =>  tools/omapimage.h     |   49 +-
>   38 files changed, 5390 insertions(+), 320 deletions(-)
>   copy arch/arm/cpu/armv7/{omap4/lowlevel_init.S =>  omap-common/utils.c} (50%)
>   create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
>   create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
>   create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
>   create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
>   create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
>   create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
>   copy arch/arm/{cpu/armv7/omap4/lowlevel_init.S =>  include/asm/armv7.h} (62%)
>   create mode 100644 arch/arm/include/asm/omap_common.h
>   rename board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} (76%)
>   rename board/ti/{panda/panda.h =>  sdp4430/sdp4430_mux_data.h} (67%)
>   create mode 100644 spl/board/ti/panda/Makefile
>   create mode 100644 spl/board/ti/sdp4430/Makefile
>   create mode 100644 spl/board/ti/spl-omap.c
>   copy arch/arm/cpu/armv7/u-boot.lds =>  spl/board/ti/spl-omap.lds (57%)
>   create mode 100644 tools/omapimage.c
>   copy arch/arm/cpu/armv7/omap4/lowlevel_init.S =>  tools/omapimage.h (53%)
>

[U-Boot] [PATCH 00/22] U-Boot MMC SPL for OMAP4

[Chander M. Kashyap]

Hi,
1. Please change spl directory name to mmc_spl in line with nand_spl.
regards,
chander



On Mon, Mar 21, 2011 at 1:51 PM, Aneesh V <aneesh@ti.com> wrote:

> Hi,
>
> Are there anymore comments on this series?
>
> On Monday 28 February 2011 05:16 PM, Aneesh V wrote:
> > This series adds mmc SPL support for OMAP4. This is essentially
> > an up-streaming effort for TI's x-loader for OMAP4 using the SPL
> > framework
> >
> > This work partly draws upon previous work done for x-loader by:
> >       Santosh Shilimkar<santosh.shilimkar@ti.com>
> >       Rajendra Nayak<rnayak@ti.com>
> > and many others
> >
> > Features supported:
> > * Clock init - DPLL locking, clock domains/modules enabling
> > * SDRAM/DMM initialization
> > * Mux initialization
> > * MMC raw read support
> > * MMC FAT read support
> >
> > Improvments over x-loader:
> > * Code completely revamped
> > * DPLL programming that works for all SYS_CLK frequencies
> > * Automatic SDRAM identification and initialization
> > * Board dependent parts(especially mux) deferred to u-boot. So, same
> >    SPL will work for Panda and SDP and most likely on any other board
> >    that comes along
> > * Determination of u-boot size to avoid reading extra content while
> >    loading U-Boot
> > * Modular apporach to enable future addition of support for all OMAP3/4
> >    platforms
> >
> > Aneesh V (21):
> >    omap: add miscellaneous utility macros for bit-field operations
> >    omap4: add OMAP4430 revision check
> >    armv7: start.S: provide a hook for saving boot params
> >    omap4: save parameters passed by ROM code to SPL
> >    arm: new labels in the linker script file
> >    Add generic spl infrastructure
> >    armv7: start.S: add SPL support
> >    omap: add spl support
> >    omap4: add spl support for OMAP4 SDP
> >    omap4: add serial console support to SPL
> >    omap4: utility function to identify the context of hw init
> >    omap4: separate mux settings into essential and non essential parts
> >    omap4: correct mux data for sdp4430
> >    omap4: add clock support
> >    omap4: add sdram init support
> >    omap4: calculate EMIF register values
> >    omap4: automatic sdram detection
> >    armv7: embed u-boot size within u-boot for use from SPL
> >    omap: add MMC support to SPL
> >    omap: spl: add FAT support over MMC
> >    omap4: add spl support for OMAP4 Panda
> >
> > John Rigby (1):
> >    mkimage: Add OMAP boot image support
> >
> >   Makefile                                           |   11 +
> >   arch/arm/cpu/armv7/cpu.c                           |    7 +
> >   arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
> >   .../{omap4/lowlevel_init.S =>  omap-common/utils.c} |   58 +-
> >   arch/arm/cpu/armv7/omap4/Makefile                  |    3 +
> >   arch/arm/cpu/armv7/omap4/board.c                   |  117 ++-
> >   arch/arm/cpu/armv7/omap4/clocks.c                  |  717 +++++++++++
> >   arch/arm/cpu/armv7/omap4/emif.c                    | 1303
> ++++++++++++++++++++
> >   arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
> >   arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
> >   arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  267 ++++
> >   arch/arm/cpu/armv7/start.S                         |   50 +-
> >   arch/arm/cpu/armv7/u-boot.lds                      |    4 +
> >   arch/arm/include/asm/arch-omap4/clocks.h           |  504 ++++++++
> >   arch/arm/include/asm/arch-omap4/emif.h             | 1021
> +++++++++++++++
> >   arch/arm/include/asm/arch-omap4/omap4.h            |   50 +-
> >   arch/arm/include/asm/arch-omap4/sys_proto.h        |   60 +-
> >   .../omap4/lowlevel_init.S =>  include/asm/armv7.h}  |   32 +-
> >   arch/arm/include/asm/global_data.h                 |    5 +
> >   arch/arm/include/asm/omap_common.h                 |  106 ++
> >   board/ti/panda/panda.c                             |   25 +-
> >   board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} |   76 +-
> >   board/ti/sdp4430/config.mk                         |    3 +-
> >   board/ti/sdp4430/sdp.c                             |   25 +-
> >   .../{panda/panda.h =>  sdp4430/sdp4430_mux_data.h}  |  128 +--
> >   common/image.c                                     |    1 +
> >   include/configs/omap4_panda.h                      |   24 +
> >   include/configs/omap4_sdp4430.h                    |   24 +
> >   include/image.h                                    |    1 +
> >   spl/board/ti/panda/Makefile                        |  219 ++++
> >   spl/board/ti/sdp4430/Makefile                      |  219 ++++
> >   spl/board/ti/spl-omap.c                            |  189 +++
> >   .../armv7/u-boot.lds =>  spl/board/ti/spl-omap.lds  |   70 +-
> >   tools/Makefile                                     |    2 +
> >   tools/mkimage.c                                    |    2 +
> >   tools/mkimage.h                                    |    1 +
> >   tools/omapimage.c                                  |  229 ++++
> >   .../omap4/lowlevel_init.S =>  tools/omapimage.h     |   49 +-
> >   38 files changed, 5390 insertions(+), 320 deletions(-)
> >   copy arch/arm/cpu/armv7/{omap4/lowlevel_init.S =>  omap-common/utils.c}
> (50%)
> >   create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
> >   create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
> >   create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
> >   create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
> >   create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
> >   create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
> >   copy arch/arm/{cpu/armv7/omap4/lowlevel_init.S =>  include/asm/armv7.h}
> (62%)
> >   create mode 100644 arch/arm/include/asm/omap_common.h
> >   rename board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} (76%)
> >   rename board/ti/{panda/panda.h =>  sdp4430/sdp4430_mux_data.h} (67%)
> >   create mode 100644 spl/board/ti/panda/Makefile
> >   create mode 100644 spl/board/ti/sdp4430/Makefile
> >   create mode 100644 spl/board/ti/spl-omap.c
> >   copy arch/arm/cpu/armv7/u-boot.lds =>  spl/board/ti/spl-omap.lds (57%)
> >   create mode 100644 tools/omapimage.c
> >   copy arch/arm/cpu/armv7/omap4/lowlevel_init.S =>  tools/omapimage.h
> (53%)
> >
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>



-- 
thanks and regards,
Chander M. Kashyap
Contact Number: +919740798700
------- TENSION LENE KA NAHI, DENE KE-----

[U-Boot] [PATCH 00/22] U-Boot MMC SPL for OMAP4

[Aneesh V]

Chander,

On Tuesday 22 March 2011 02:20 PM, Chander M. Kashyap wrote:
> Hi,
> 1. Please change spl directory name to mmc_spl in line with nand_spl.
> regards,
> chander

Please have a look at the commit message of 07/22.
This is done intentionally to be generic enough to be used for any
media. We intend to add NAND support to the same SPL for OMAP3/4. You
can potentially have the same SPL support MMC *and* NAND. Where it
loads the U-Boot from will depend on a switch setting on the board.

best regards,
Aneesh

>
>
>
> On Mon, Mar 21, 2011 at 1:51 PM, Aneesh V <aneesh@ti.com
> <mailto:aneesh@ti.com>> wrote:
>
>     Hi,
>
>     Are there anymore comments on this series?
>
>     On Monday 28 February 2011 05:16 PM, Aneesh V wrote:
>      > This series adds mmc SPL support for OMAP4. This is essentially
>      > an up-streaming effort for TI's x-loader for OMAP4 using the SPL
>      > framework
>      >
>      > This work partly draws upon previous work done for x-loader by:
>      >       Santosh Shilimkar<santosh.shilimkar@ti.com
>     <mailto:santosh.shilimkar@ti.com>>
>      >       Rajendra Nayak<rnayak at ti.com <mailto:rnayak@ti.com>>
>      > and many others
>      >
>      > Features supported:
>      > * Clock init - DPLL locking, clock domains/modules enabling
>      > * SDRAM/DMM initialization
>      > * Mux initialization
>      > * MMC raw read support
>      > * MMC FAT read support
>      >
>      > Improvments over x-loader:
>      > * Code completely revamped
>      > * DPLL programming that works for all SYS_CLK frequencies
>      > * Automatic SDRAM identification and initialization
>      > * Board dependent parts(especially mux) deferred to u-boot. So, same
>      >    SPL will work for Panda and SDP and most likely on any other board
>      >    that comes along
>      > * Determination of u-boot size to avoid reading extra content while
>      >    loading U-Boot
>      > * Modular apporach to enable future addition of support for all
>     OMAP3/4
>      >    platforms
>      >
>      > Aneesh V (21):
>      >    omap: add miscellaneous utility macros for bit-field operations
>      >    omap4: add OMAP4430 revision check
>      >    armv7: start.S: provide a hook for saving boot params
>      >    omap4: save parameters passed by ROM code to SPL
>      >    arm: new labels in the linker script file
>      >    Add generic spl infrastructure
>      >    armv7: start.S: add SPL support
>      >    omap: add spl support
>      >    omap4: add spl support for OMAP4 SDP
>      >    omap4: add serial console support to SPL
>      >    omap4: utility function to identify the context of hw init
>      >    omap4: separate mux settings into essential and non essential
>     parts
>      >    omap4: correct mux data for sdp4430
>      >    omap4: add clock support
>      >    omap4: add sdram init support
>      >    omap4: calculate EMIF register values
>      >    omap4: automatic sdram detection
>      >    armv7: embed u-boot size within u-boot for use from SPL
>      >    omap: add MMC support to SPL
>      >    omap: spl: add FAT support over MMC
>      >    omap4: add spl support for OMAP4 Panda
>      >
>      > John Rigby (1):
>      >    mkimage: Add OMAP boot image support
>      >
>      >   Makefile                                           |   11 +
>      >   arch/arm/cpu/armv7/cpu.c                           |    7 +
>      >   arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
>      >   .../{omap4/lowlevel_init.S =>  omap-common/utils.c} |   58 +-
>      >   arch/arm/cpu/armv7/omap4/Makefile                  |    3 +
>      >   arch/arm/cpu/armv7/omap4/board.c                   |  117 ++-
>      >   arch/arm/cpu/armv7/omap4/clocks.c                  |  717
>     +++++++++++
>      >   arch/arm/cpu/armv7/omap4/emif.c                    | 1303
>     ++++++++++++++++++++
>      >   arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
>      >   arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
>      >   arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  267 ++++
>      >   arch/arm/cpu/armv7/start.S                         |   50 +-
>      >   arch/arm/cpu/armv7/u-boot.lds                      |    4 +
>      >   arch/arm/include/asm/arch-omap4/clocks.h           |  504 ++++++++
>      >   arch/arm/include/asm/arch-omap4/emif.h             | 1021
>     +++++++++++++++
>      >   arch/arm/include/asm/arch-omap4/omap4.h            |   50 +-
>      >   arch/arm/include/asm/arch-omap4/sys_proto.h        |   60 +-
>      >   .../omap4/lowlevel_init.S =>  include/asm/armv7.h}  |   32 +-
>      >   arch/arm/include/asm/global_data.h                 |    5 +
>      >   arch/arm/include/asm/omap_common.h                 |  106 ++
>      >   board/ti/panda/panda.c                             |   25 +-
>      >   board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} |   76 +-
>      >   board/ti/sdp4430/config.mk <http://config.mk>
>            |    3 +-
>      >   board/ti/sdp4430/sdp.c                             |   25 +-
>      >   .../{panda/panda.h =>  sdp4430/sdp4430_mux_data.h}  |  128 +--
>      >   common/image.c                                     |    1 +
>      >   include/configs/omap4_panda.h                      |   24 +
>      >   include/configs/omap4_sdp4430.h                    |   24 +
>      >   include/image.h                                    |    1 +
>      >   spl/board/ti/panda/Makefile                        |  219 ++++
>      >   spl/board/ti/sdp4430/Makefile                      |  219 ++++
>      >   spl/board/ti/spl-omap.c                            |  189 +++
>      >   .../armv7/u-boot.lds =>  spl/board/ti/spl-omap.lds  |   70 +-
>      >   tools/Makefile                                     |    2 +
>      >   tools/mkimage.c                                    |    2 +
>      >   tools/mkimage.h                                    |    1 +
>      >   tools/omapimage.c                                  |  229 ++++
>      >   .../omap4/lowlevel_init.S =>  tools/omapimage.h     |   49 +-
>      >   38 files changed, 5390 insertions(+), 320 deletions(-)
>      >   copy arch/arm/cpu/armv7/{omap4/lowlevel_init.S =>
>       omap-common/utils.c} (50%)
>      >   create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
>      >   create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
>      >   create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
>      >   create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
>      >   create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
>      >   create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
>      >   copy arch/arm/{cpu/armv7/omap4/lowlevel_init.S =>
>       include/asm/armv7.h} (62%)
>      >   create mode 100644 arch/arm/include/asm/omap_common.h
>      >   rename board/ti/{sdp4430/sdp.h =>  panda/panda_mux_data.h} (76%)
>      >   rename board/ti/{panda/panda.h =>  sdp4430/sdp4430_mux_data.h}
>     (67%)
>      >   create mode 100644 spl/board/ti/panda/Makefile
>      >   create mode 100644 spl/board/ti/sdp4430/Makefile
>      >   create mode 100644 spl/board/ti/spl-omap.c
>      >   copy arch/arm/cpu/armv7/u-boot.lds =>
>       spl/board/ti/spl-omap.lds (57%)
>      >   create mode 100644 tools/omapimage.c
>      >   copy arch/arm/cpu/armv7/omap4/lowlevel_init.S =>
>       tools/omapimage.h (53%)
>      >
>     _______________________________________________
>     U-Boot mailing list
>     U-Boot at lists.denx.de <mailto:U-Boot@lists.denx.de>
>     http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
>
> --
> thanks and regards,
> Chander M. Kashyap
> Contact Number: +919740798700
> ------- TENSION LENE KA NAHI, DENE KE-----

[U-Boot] [PATCH v2 00/22] U-Boot MMC SPL for OMAP4

[Aneesh V]

This series adds mmc SPL support for OMAP4. This is essentially
an up-streaming effort for TI's x-loader for OMAP4 using the SPL
framework

This work partly draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>
and many others

This series is depedent on the following series:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/95550

Features supported:
* Clock init - DPLL locking, clock domains/modules enabling
* SDRAM/DMM initialization
* Mux initialization
* MMC raw read support
* MMC FAT read support

Improvments over x-loader:
* Code completely revamped
* DPLL programming that works for all SYS_CLK frequencies
* Automatic SDRAM identification and initialization
* Board dependent parts(especially mux) deferred to u-boot. So, same
  SPL will work for Panda and SDP and most likely on any other board
  that comes along
* Determination of u-boot size to avoid reading extra content while
  loading U-Boot
* Modular apporach to enable future addition of support for all OMAP3/4
  platforms

V2:
* Some fixes in SDRAM init, clock init
* Use of pre-calculated M & N values for DPLL locking instead
  run-time calculation
* Change in make files to allow reuse of common rules
  between boards
* Console initialization moved further earlier in the boot
  allowing traces from even clock initialization code
* Reuse utility macros from a previous series

Aneesh V (21):
  omap4: add OMAP4430 revision check
  armv7: start.S: provide a hook for saving boot params
  omap4: save parameters passed by ROM code to SPL
  arm: new labels in the linker script file
  Add generic spl infrastructure
  armv7: start.S: add SPL support
  omap: add spl support
  omap4: add spl support for OMAP4 SDP
  omap4: utility function to identify the context of hw init
  omap4: separate mux settings into essential and non essential parts
  omap4: correct mux data for sdp4430
  omap4: add clock support
  omap4: add serial console support to SPL
  omap4: add sdram init support
  omap4: calculate EMIF register values
  omap4: automatic sdram detection
  armv7: embed u-boot size within u-boot for use from SPL
  omap: add MMC support to SPL
  omap: spl: add FAT support over MMC
  omap4: add spl support for OMAP4 Panda
  omap: spl: add more debug traces

John Rigby (1):
  mkimage: Add OMAP boot image support

 Makefile                                           |   24 +
 arch/arm/cpu/armv7/cpu.c                           |    7 +
 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 .../{omap4/lowlevel_init.S => omap-common/utils.c} |   76 +-
 arch/arm/cpu/armv7/omap4/Makefile                  |    3 +
 arch/arm/cpu/armv7/omap4/board.c                   |  140 ++-
 arch/arm/cpu/armv7/omap4/clocks.c                  |  764 +++++++++++
 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c          |  154 +++
 arch/arm/cpu/armv7/omap4/emif.c                    | 1340 ++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  267 ++++
 arch/arm/cpu/armv7/start.S                         |   50 +-
 arch/arm/cpu/armv7/u-boot.lds                      |    2 +
 arch/arm/include/asm/arch-omap4/clocks.h           |  506 ++++++++
 arch/arm/include/asm/arch-omap4/emif.h             | 1021 +++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |   50 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |   62 +-
 arch/arm/include/asm/armv7.h                       |    6 +-
 arch/arm/include/asm/global_data.h                 |    5 +
 arch/arm/include/asm/omap_common.h                 |   62 +
 arch/arm/include/asm/utils.h                       |    6 +
 board/ti/panda/panda.c                             |   25 +-
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +-
 board/ti/sdp4430/config.mk                         |    3 +-
 board/ti/sdp4430/sdp.c                             |   25 +-
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +--
 common/image.c                                     |    1 +
 include/configs/omap4_panda.h                      |   24 +
 include/configs/omap4_sdp4430.h                    |   24 +
 include/image.h                                    |    1 +
 spl/board/ti/omap4.mk                              |  176 +++
 .../config.mk => spl/board/ti/panda/Makefile       |   21 +-
 spl/board/ti/rules-omap.mk                         |   74 ++
 .../config.mk => spl/board/ti/sdp4430/Makefile     |   21 +-
 spl/board/ti/spl-omap.c                            |  206 +++
 .../armv7/u-boot.lds => spl/board/ti/spl-omap.lds  |   69 +-
 tools/Makefile                                     |    2 +
 tools/mkimage.c                                    |    2 +
 tools/mkimage.h                                    |    1 +
 tools/omapimage.c                                  |  229 ++++
 tools/omapimage.h                                  |   50 +
 42 files changed, 5498 insertions(+), 313 deletions(-)
 copy arch/arm/cpu/armv7/{omap4/lowlevel_init.S => omap-common/utils.c} (50%)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
 create mode 100644 arch/arm/include/asm/omap_common.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)
 create mode 100644 spl/board/ti/omap4.mk
 copy board/ti/sdp4430/config.mk => spl/board/ti/panda/Makefile (63%)
 create mode 100644 spl/board/ti/rules-omap.mk
 copy board/ti/sdp4430/config.mk => spl/board/ti/sdp4430/Makefile (63%)
 create mode 100644 spl/board/ti/spl-omap.c
 copy arch/arm/cpu/armv7/u-boot.lds => spl/board/ti/spl-omap.lds (57%)
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

From: John Rigby <john.rigby@linaro.org>

Signed-off-by: John Rigby <john.rigby@linaro.org>
---
 common/image.c    |    1 +
 include/image.h   |    1 +
 tools/Makefile    |    2 +
 tools/mkimage.c   |    2 +
 tools/mkimage.h   |    1 +
 tools/omapimage.c |  229 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 tools/omapimage.h |   50 ++++++++++++
 7 files changed, 286 insertions(+), 0 deletions(-)
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

diff --git a/common/image.c b/common/image.c
index e542a57..7f6fe1c 100644
--- a/common/image.c
+++ b/common/image.c
@@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index c31e862..c606644 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 623f908..a1c4ed7 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
 OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
@@ -180,6 +181,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
 			$(obj)fit_image.o \
 			$(obj)image.o \
 			$(obj)imximage.o \
+			$(obj)omapimage.o \
 			$(obj)kwbimage.o \
 			$(obj)md5.o \
 			$(obj)mkimage.o \
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 60f7263..b6a7cb7 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -156,6 +156,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 9033a7d..3b49645 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/omapimage.c b/tools/omapimage.c
new file mode 100644
index 0000000..67fa056
--- /dev/null
+++ b/tools/omapimage.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "omapimage.h"
+
+/* Header size is CH header rounded up to 512 bytes plus GP header */
+#define OMAP_CH_HDR_SIZE 512
+#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+
+static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
+
+static int omapimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_OMAPIMAGE)
+		return EXIT_SUCCESS;
+	else
+		return EXIT_FAILURE;
+}
+
+/*
+ * Only the simplest image type is currently supported:
+ * TOC pointing to CHSETTINGS
+ * TOC terminator
+ * CHSETTINGS
+ *
+ * padding to OMAP_CH_HDR_SIZE bytes
+ *
+ * gp header
+ *   size
+ *   load_addr
+ */
+static int valid_gph_size(uint32_t size)
+{
+	return size;
+}
+
+static int valid_gph_load_addr(uint32_t load_addr)
+{
+	return load_addr;
+}
+
+static int omapimage_verify_header(unsigned char *ptr, int image_size,
+			struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+		if (!offset || !size)
+			return -1;
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			return -1;
+		toc++;
+	}
+	if (!valid_gph_size(gph->size))
+		return -1;
+	if (!valid_gph_load_addr(gph->load_addr))
+		return -1;
+
+	return 0;
+}
+
+static void omapimage_print_section(struct ch_settings *chs)
+{
+	switch (chs->section_key) {
+	case KEY_CHSETTINGS:
+		printf("CHSETTINGS (%x) "
+			"valid:%x "
+			"version:%x "
+			"reserved:%x "
+			"flags:%x\n",
+			chs->section_key,
+			chs->valid,
+			chs->version,
+			chs->reserved,
+			chs->flags);
+		break;
+	default:
+		printf("UNKNOWNKEY (%x) "
+			"valid:%x "
+			"version:%x "
+			"reserved:%x "
+			"flags:%x\n",
+			chs->section_key,
+			chs->valid,
+			chs->version,
+			chs->reserved,
+			chs->flags);
+		break;
+	}
+}
+
+static void omapimage_print_header(const void *ptr)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			exit(EXIT_FAILURE);
+
+		printf("Section %s offset %x length %x\n",
+			toc->section_name,
+			toc->section_offset,
+			toc->section_size);
+
+		omapimage_print_section((struct ch_settings *)(ptr+offset));
+		toc++;
+	}
+
+	if (!valid_gph_size(gph->size)) {
+		fprintf(stderr,
+			"Error: invalid image size %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!valid_gph_load_addr(gph->load_addr)) {
+		fprintf(stderr,
+			"Error: invalid image load address %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	printf("GP Header: Size %x LoadAddr %x\n",
+		gph->size, gph->load_addr);
+}
+
+static int toc_offset(void *hdr, void *member)
+{
+	return member - hdr;
+}
+
+static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct ch_settings *chs = (struct ch_settings *)
+					(ptr + 2 * sizeof(*toc));
+	struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE);
+
+	toc->section_offset = toc_offset(ptr, chs);
+	toc->section_size = sizeof(struct ch_settings);
+	strcpy((char *)toc->section_name, "CHSETTINGS");
+
+	chs->section_key = KEY_CHSETTINGS;
+	chs->valid = 0;
+	chs->version = 1;
+	chs->reserved = 0;
+	chs->flags = 0;
+
+	toc++;
+	memset(toc, 0xff, sizeof(*toc));
+
+	gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
+	gph->load_addr = params->addr;
+}
+
+int omapimage_check_params(struct mkimage_params *params)
+{
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+/*
+ * omapimage parameters
+ */
+static struct image_type_params omapimage_params = {
+	.name		= "TI OMAP CH/GP Boot Image support",
+	.header_size	= OMAP_FILE_HDR_SIZE,
+	.hdr		= (void *)&omapimage_header,
+	.check_image_type = omapimage_check_image_types,
+	.verify_header	= omapimage_verify_header,
+	.print_header	= omapimage_print_header,
+	.set_header	= omapimage_set_header,
+	.check_params	= omapimage_check_params,
+};
+
+void init_omap_image_type(void)
+{
+	mkimage_register(&omapimage_params);
+}
diff --git a/tools/omapimage.h b/tools/omapimage.h
new file mode 100644
index 0000000..7ff5404
--- /dev/null
+++ b/tools/omapimage.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAPIMAGE_H_
+#define _OMAPIMAGE_H_
+
+struct ch_toc {
+	uint32_t section_offset;
+	uint32_t section_size;
+	uint8_t unused[12];
+	uint8_t section_name[12];
+} __attribute__ ((__packed__));
+
+struct ch_settings {
+	uint32_t section_key;
+	uint8_t valid;
+	uint8_t version;
+	uint16_t reserved;
+	uint32_t flags;
+} __attribute__ ((__packed__));
+
+struct gp_header {
+	uint32_t size;
+	uint32_t load_addr;
+} __attribute__ ((__packed__));
+
+#define KEY_CHSETTINGS 0xC0C0C0C1
+#endif /* _OMAPIMAGE_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Added a revision string in addition to the revision number
  Helps in printing out the OMAP revision at bootup
---
 arch/arm/cpu/armv7/omap4/board.c        |   58 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h |   17 ++++++---
 arch/arm/include/asm/armv7.h            |    6 +++-
 3 files changed, 74 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index fcd29a7..8ab7306 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
@@ -127,3 +128,60 @@ int arch_cpu_init(void)
 	set_muxconf_regs();
 	return 0;
 }
+
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+u32 omap4_revision(void)
+{
+	if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1)
+		return OMAP4430_ES2_1;
+	else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2)
+		return OMAP4430_ES2_2;
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int rev = cortex_a9_rev();
+
+	switch (rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		return OMAP4430_ES1_0;
+	case MIDR_CORTEX_A9_R1P2:
+		return OMAP4430_ES2_0;
+	default:
+		return OMAP4430_SILICON_ID_INVALID;
+	}
+}
+
+const char *omap4_rev_string(void)
+{
+	const char *omap4_rev = NULL;
+	switch (omap4_revision()) {
+	case OMAP4430_ES1_0:
+		omap4_rev = "OMAP4430 ES1.0";
+		break;
+	case OMAP4430_ES2_0:
+		omap4_rev = "OMAP4430 ES2.0";
+		break;
+	case OMAP4430_ES2_1:
+		omap4_rev = "OMAP4430 ES2.1";
+		break;
+	case OMAP4430_ES2_2:
+		omap4_rev = "OMAP4430 ES2.2";
+		break;
+	default:
+		omap4_rev = "OMAP4 - Unknown Rev";
+		break;
+	}
+	return omap4_rev;
+}
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..1f88732 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -121,11 +126,11 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0
+#define OMAP4430_ES1_0	1
+#define OMAP4430_ES2_0	2
+#define OMAP4430_ES2_1	3
+#define OMAP4430_ES2_2	4
 
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 50cc167..772435b 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -26,6 +26,10 @@
 #define ARMV7_H
 #include <linux/types.h>
 
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
 #define CCSIDR_LINE_SIZE_MASK		0x7
@@ -65,4 +69,4 @@ void v7_outer_cache_inval_all(void);
 void v7_outer_cache_flush_range(u32 start, u32 end);
 void v7_outer_cache_inval_range(u32 start, u32 end);
 
-#endif
+#endif /* ARMV7_H */
-- 
1.7.0.4

[U-Boot] [PATCH v2 03/22] armv7: start.S: provide a hook for saving boot params

[Aneesh V]

Provide a means by which u-boot/SPL can save parameters passed
to it by ROM code or the pre-loader.

A new function 'save_boot_params' has been defined and a default
implentation provided. Please note that we do not have a stack yet.
So, any implementation of this function should not use stack.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/cpu.c   |    7 +++++++
 arch/arm/cpu/armv7/start.S |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 5c69d04..1c9e297 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -36,6 +36,13 @@
 #include <asm/system.h>
 #include <asm/armv7.h>
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 13e2d44..e6e05e9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -119,6 +119,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
-- 
1.7.0.4

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Aneesh V]

Save boot device information passed by OMAP4 rom code

ROM code in OMAP4 passes information such as the media from
which it picked up the first boot image(SPL in our case),
the mode(raw mode/FAT mode) etc.

Save this information in SPL so that we can use the same media
and mode to bootload u-boot.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c                   |   14 +++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |    8 ++++
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    1 +
 .../asm/{arch-omap4/sys_proto.h => omap_common.h}  |   41 +++++++++++--------
 5 files changed, 78 insertions(+), 17 deletions(-)
 copy arch/arm/include/asm/{arch-omap4/sys_proto.h => omap_common.h} (54%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 8ab7306..046e3bf 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -35,6 +35,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_PRELOADER
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 /*
  * Routine: s_init
  * Description: Does early system init of muxing and clocks.
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 5e6c16f..d26d6e6 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_PRELOADER
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 1f88732..740ca9d 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -133,4 +133,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_1	3
 #define OMAP4430_ES2_2	4
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 017f216..0026b75 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -23,6 +23,7 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/omap_common.h
similarity index 54%
copy from arch/arm/include/asm/arch-omap4/sys_proto.h
copy to arch/arm/include/asm/omap_common.h
index 017f216..7e28e28 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -2,6 +2,11 @@
  * (C) Copyright 2010
  * Texas Instruments, <www.ti.com>
  *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -17,25 +22,27 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
 
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include <asm/arch/omap4.h>
-#include <asm/io.h>
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
 
-struct omap_sysinfo {
-	char *board_string;
-};
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
 
-void gpmc_init(void);
-void watchdog_init(void);
-u32 get_device_type(void);
-void set_muxconf_regs(void);
-void sr32(void *, u32, u32, u32);
-u32 wait_on_value(u32, u32, void *, u32);
-void sdelay(unsigned long);
+/* Magic number passed from SPL to U-Boot */
+#define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
 
-extern const struct omap_sysinfo sysinfo;
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
 
-#endif
+#endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v2 05/22] arm: new labels in the linker script file

[Aneesh V]

_bss_start_ofs is used in start.S to indicate end of copied
image. This may not be correct when we have a discontiguous
memory map. For instance, .bss may be placed in SDRAM for
some SPLS while rest of the image is placed in SRAM.

Define a new label in linker script to indicate the end of the
image copied during relocation and use it appropriately in
start.S.

Also, add a new label to indicate the end of flash image.
This will be useful in identifying the size of flash image

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Removed the label __flash_image_end because _end serves the
  same purpose after rebasing to latest mainline
---
 arch/arm/cpu/armv7/start.S    |    6 +++++-
 arch/arm/cpu/armv7/u-boot.lds |    2 ++
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index e6e05e9..13178cd 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -89,6 +89,10 @@ _armboot_start:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -188,7 +192,7 @@ stack_setup:
 	beq	clear_bss		/* skip relocation */
 #endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index dbae54d..40ecf78 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
-- 
1.7.0.4

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Define a new type of SPL that is not tied to any particular media.
- Create a top level directory 'spl' that has a structure similar
  to the existing 'nand_spl'
- Make necessary changes to top-level Makefile to build such an spl

Rationale for this approach:
- There may be SPLs(like the OMAP x-loader) that support booting from
  multiple media.
- Also, there is no harm in keeping SPLs specific to a particular media
  also under this directory. In fact it makes sense to merge all the
  different spl directories into this one.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
This patch generates 1 checkpatch warning due to declaration
of DECLARE_GLOBAL_DATA_PTR. This is un-avoidable
---
 Makefile                           |   24 ++++++++++++++++++++++++
 arch/arm/include/asm/global_data.h |    5 +++++
 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile
index 384a59e..d3f4bef 100644
--- a/Makefile
+++ b/Makefile
@@ -289,6 +289,22 @@ LDPPFLAGS += \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+NAND_SPL = nand_spl
+U_BOOT_NAND = $(obj)u-boot-nand.bin
+endif
+
+ifeq ($(CONFIG_SPL),y)
+.PHONEY : SPL
+ALL += SPL
+endif
+
+ifeq ($(CONFIG_ONENAND_U_BOOT),y)
+ONENAND_IPL = onenand_ipl
+U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
+ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
 
@@ -402,8 +418,13 @@ $(obj)u-boot.lds: $(LDSCRIPT)
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
 nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
+
+$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
+SPL		:$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
+		$(MAKE) -C spl/board/$(BOARDDIR) all
+
 $(obj)u-boot-nand.bin:	nand_spl $(obj)u-boot.bin
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
@@ -1122,6 +1143,7 @@ clean:
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)spl/{u-boot-spl-generated.lds,u-boot-spl,u-boot-spl.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
 	@rm -f $(ONENAND_BIN)
 	@rm -f $(obj)onenand_ipl/u-boot.lds
@@ -1141,12 +1163,14 @@ clobber:	clean
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
 	@rm -f $(obj)u-boot.kwb
 	@rm -f $(obj)u-boot.imx
+	@rm -f $(obj)MLO
 	@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
 	@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+	@[ ! -d $(obj)spl ] || find $(obj)spl -name "*" -type l -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))
 mrproper \
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 2a84d27..2ce020e 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -89,6 +89,11 @@ typedef	struct	global_data {
 #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
 #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
 
+#ifdef CONFIG_PRELOADER
+/* SPL works from internal RAM. gd pointer can be in .data section */
+#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
+#else
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+#endif
 
 #endif /* __ASM_GBL_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v2 07/22] armv7: start.S: add SPL support

[Aneesh V]

Changes for supporting SPL

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/start.S |   36 +++++++++++++++++++++++++-----------
 1 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 13178cd..f92c6d9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_PRELOADER
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_PRELOADER */
+
 .global _end_vect
 _end_vect:
 
@@ -187,10 +198,9 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_PRELOADER
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
@@ -240,6 +250,15 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_PRELOADER */
 
 clear_bss:
 	ldr	r0, _bss_start_ofs
@@ -253,7 +272,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_PRELOADER */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -281,13 +299,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -332,6 +343,8 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+
+#ifndef CONFIG_PRELOADER
 /*
  *************************************************************************
  *
@@ -520,3 +533,4 @@ fiq:
 	bl	do_fiq
 
 #endif
+#endif /* CONFIG_PRELOADER */
-- 
1.7.0.4

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Add the basic spl framework and linker script common for OMAP3/4
platforms.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 spl/board/ti/spl-omap.c   |   47 ++++++++++++++++++++++++++++++++++
 spl/board/ti/spl-omap.lds |   62 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 spl/board/ti/spl-omap.c
 create mode 100644 spl/board/ti/spl-omap.lds

diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
new file mode 100644
index 0000000..0e08f4f
--- /dev/null
+++ b/spl/board/ti/spl-omap.c
@@ -0,0 +1,47 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+
+/* Define global data structure pointer to it*/
+gd_t gdata __attribute__ ((section(".data")));
+bd_t bdata __attribute__ ((section(".data")));
+gd_t *gd = &gdata;
+
+void board_init_f(ulong dummy)
+{
+	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}
diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds
new file mode 100644
index 0000000..674ef05
--- /dev/null
+++ b/spl/board/ti/spl-omap.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
+		 LENGTH = CONFIG_SYS_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \
+		  LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
-- 
1.7.0.4

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Adapted from: nand_spl/board/samsung/smdk6400/Makefile

- Add the SPL makefile for OMAP4430 SDP
- Add the necessary CONFIG flags in the board config file

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
 * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 from
   0x40304360. This exact address is needed for EMU
   devices.
 * Removed un-necessary compiler options from CFLAGS and AFLAGS.
   These are already set by .mk files in U-Boot
 * Reorganize the make files to re-use common rules between
   boards
---
 board/ti/sdp4430/config.mk                         |    3 +-
 include/configs/omap4_sdp4430.h                    |   19 +++++
 spl/board/ti/omap4.mk                              |   77 ++++++++++++++++++++
 spl/board/ti/rules-omap.mk                         |   74 +++++++++++++++++++
 .../config.mk => spl/board/ti/sdp4430/Makefile     |   21 +++---
 5 files changed, 183 insertions(+), 11 deletions(-)
 create mode 100644 spl/board/ti/omap4.mk
 create mode 100644 spl/board/ti/rules-omap.mk
 copy board/ti/sdp4430/config.mk => spl/board/ti/sdp4430/Makefile (63%)

diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
index 33901a7..c62965d 100644
--- a/board/ti/sdp4430/config.mk
+++ b/board/ti/sdp4430/config.mk
@@ -28,4 +28,5 @@
 # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
 # (mem base + reserved)
 
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 0fd08b3..99247df 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -121,7 +121,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */
@@ -244,4 +246,21 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
new file mode 100644
index 0000000..dffb53b
--- /dev/null
+++ b/spl/board/ti/omap4.mk
@@ -0,0 +1,77 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+# Aneesh V <aneesh@ti.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+splobj	:= $(OBJTREE)/spl/
+include $(TOPDIR)/config.mk
+SOBJS =
+COBJS =
+
+# armv7
+$(obj)start.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
+
+$(obj)syslib.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/syslib.c $@
+
+SOBJS	+= start.o
+COBJS	+= syslib.o
+
+# omap-common
+$(obj)timer.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/timer.c $@
+
+$(obj)reset.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/reset.S $@
+
+$(obj)spl-omap.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@
+
+SOBJS	+= reset.o
+COBJS	+= timer.o spl-omap.o
+
+# omap4
+$(obj)lowlevel_init.S:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/lowlevel_init.S $@
+
+$(obj)omap4_mux_data.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/omap4_mux_data.h $@
+
+$(obj)board.c:$(obj)omap4_mux_data.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
+
+SOBJS	+= lowlevel_init.o
+COBJS	+= board.o
diff --git a/spl/board/ti/rules-omap.mk b/spl/board/ti/rules-omap.mk
new file mode 100644
index 0000000..b1d0ae6
--- /dev/null
+++ b/spl/board/ti/rules-omap.mk
@@ -0,0 +1,74 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+# Aneesh V <aneesh@ti.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LDSCRIPT_SOURCE = $(TOPDIR)/spl/board/ti/spl-omap.lds
+LDPPFLAGS += -include $(TOPDIR)/include/config.h
+LDSCRIPT = $(splobj)u-boot-spl-generated.lds
+$(LDSCRIPT): $(LDSCRIPT_SOURCE)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) \
+	$(PLATFORM_LDFLAGS) --gc-sections
+AFLAGS	+= -DCONFIG_PRELOADER
+CFLAGS	+= -DCONFIG_PRELOADER -ffunction-sections -fdata-sections \
+	   $(call cc-option,-march=armv7-a -mthumb -mthumb-interwork,)
+PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) \
+		-print-libgcc-file-name`) -lgcc
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/spl/board/$(BOARDDIR)
+
+$(splobj)u-boot-spl.bin:	$(splobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(splobj)u-boot-spl:	$(OBJS) $(LDSCRIPT)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		$(PLATFORM_LIBGCC) \
+		-Map $(splobj)u-boot-spl.map \
+		-o $(splobj)u-boot-spl
+
+$(OBJTREE)/MLO:	$(splobj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@
+
+ALL	= $(OBJTREE)/MLO
+all:	$(obj).depend $(ALL)
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/ti/sdp4430/config.mk b/spl/board/ti/sdp4430/Makefile
similarity index 63%
copy from board/ti/sdp4430/config.mk
copy to spl/board/ti/sdp4430/Makefile
index 33901a7..81bf51c 100644
--- a/board/ti/sdp4430/config.mk
+++ b/spl/board/ti/sdp4430/Makefile
@@ -1,9 +1,13 @@
 #
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
 #
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+# Aneesh V <aneesh@ti.com>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -15,7 +19,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -23,9 +27,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
 
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+include $(SRCTREE)/spl/board/$(VENDOR)/omap4.mk
+include $(SRCTREE)/spl/board/$(VENDOR)/rules-omap.mk
-- 
1.7.0.4

[U-Boot] [PATCH v2 10/22] omap4: utility function to identify the context of hw init

[Aneesh V]

The basic hardware init of OMAP4(s_init()) can happen in 4
different contexts:
 1. SPL running from SRAM
 2. U-Boot running from FLASH
 3. Non-XIP U-Boot loaded to SDRAM by SPL
 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
    Configuration Header feature

What level of hw initialization gets done depends on this
context. Add a utility function to find this context.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/include/asm/arch-omap4/sys_proto.h |   47 +++++++++++++++++++++++++++
 arch/arm/include/asm/omap_common.h          |    6 +++
 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 0026b75..fb4c72f 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -37,6 +37,53 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_PRELOADER
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH;
+	else
+		return OMAP_INIT_CONTEXT_XIP_UBOOT;
+#endif
+}
+
 extern const struct omap_sysinfo sysinfo;
 
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 7e28e28..2063c36 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -42,6 +42,12 @@
 /* Magic number passed from SPL to U-Boot */
 #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
 
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_XIP_UBOOT		1
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH	3
+
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 
-- 
1.7.0.4

[U-Boot] [PATCH v2 11/22] omap4: separate mux settings into essential and non essential parts

[Aneesh V]

Do the essential part from SPL and non-essential part from U-Boot
- Essential part is what is essential for u-boot to function
- Essential part is also largely board independent(at least
  as of now)
- So essential part is moved out to SoC directory instead of
  keeping in board directory. This helps in having single SPL
  that works for Panda and SDP.
- Non-essential part is what is set by u-boot for kernel to
  function correctly
- Ideally non-essential part should be phased out eventually

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c               |   53 ++++++++++++++++-
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h      |   76 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    4 +-
 board/ti/panda/panda.c                         |   25 ++------
 board/ti/panda/{panda.h => panda_mux_data.h}   |   45 ++------------
 board/ti/sdp4430/sdp.c                         |   25 ++------
 board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} |   47 ++-------------
 7 files changed, 151 insertions(+), 124 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 rename board/ti/panda/{panda.h => panda_mux_data.h} (83%)
 rename board/ti/sdp4430/{sdp.h => sdp4430_mux_data.h} (83%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 046e3bf..30bf801 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,9 +32,30 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
 #ifdef CONFIG_PRELOADER
 u32 omap4_boot_device = BOOT_DEVICE_MMC1;
 u32 omap4_boot_mode = MMCSD_MODE_FAT;
@@ -49,14 +70,41 @@ u32 omap_boot_mode(void)
 }
 #endif
 
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_XIP_UBOOT:
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing, clocks, and
+ * sdram. Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration
+ *	Header feature
+ * Please have a look at the respective functions to see what gets done in
+ * each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 }
 
 /*
@@ -139,7 +187,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index fb4c72f..ebd5b7a 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
@@ -32,7 +33,8 @@ struct omap_sysinfo {
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda_mux_data.h
similarity index 83%
rename from board/ti/panda/panda.h
rename to board/ti/panda/panda_mux_data.h
index e3d090e..8bb7fe5 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -24,21 +24,13 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
+#ifndef _PANDA_MUX_DATA_H_
+#define _PANDA_MUX_DATA_H_
 
 #include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +56,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -112,16 +102,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
@@ -144,14 +124,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +131,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -236,14 +204,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
 	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
@@ -252,7 +218,6 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
 	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
@@ -261,4 +226,4 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
 };
 
-#endif
+#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp4430_mux_data.h
similarity index 83%
rename from board/ti/sdp4430/sdp.h
rename to board/ti/sdp4430/sdp4430_mux_data.h
index bf41067..e6081dc 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -112,16 +100,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,7 +216,6 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
@@ -261,4 +224,4 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v2 12/22] omap4: correct mux data for sdp4430

[Aneesh V]

sync up mux settings with the latest in x-loader

Signed-off-by: Aneesh V <aneesh@ti.com>
---
Several checkpatch warnings of lines over 80 characters in this
patch. These are due to formatting of mux data array, which only makes
it more readable.
---
 board/ti/panda/panda_mux_data.h     |   89 ++++++++++++++++++-----------------
 board/ti/sdp4430/sdp4430_mux_data.h |   29 ++++++-----
 2 files changed, 61 insertions(+), 57 deletions(-)

diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 8bb7fe5..16cc0ad 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,11 +23,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_MUX_DATA_H_
-#define _PANDA_MUX_DATA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
@@ -45,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -59,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -86,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -106,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -143,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -157,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -173,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -205,25 +203,28 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 };
 
 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif /* _PANDA_MUX_DATA_H_ */
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index e6081dc..16cc0ad 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -84,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -173,11 +173,11 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -222,6 +222,9 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
 #endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules

This work draws upon previous work done for x-loader mainly by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Use pre-calculated M & N values instead of calculated ones
* Changes due to make file changes
* Some corrections
* Do all clock initialization in SPL itself instead of differing some
  work to u-boot
---
 arch/arm/cpu/armv7/omap4/Makefile           |    1 +
 arch/arm/cpu/armv7/omap4/board.c            |    1 +
 arch/arm/cpu/armv7/omap4/clocks.c           |  731 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c   |  154 ++++++
 arch/arm/include/asm/arch-omap4/clocks.h    |  506 ++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    6 +
 arch/arm/include/asm/omap_common.h          |    3 +
 spl/board/ti/omap4.mk                       |    7 +-
 8 files changed, 1408 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..6154e86 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -30,6 +30,7 @@ SOBJS	+= lowlevel_init.o
 COBJS	+= board.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+COBJS	+= clocks.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 30bf801..f83b6d7 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -105,6 +105,7 @@ void s_init(void)
 {
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..802917f
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,731 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+static const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+	{250, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{1000, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{119, 1, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{625, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{500, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{1000, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{625, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_es1_600mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
+	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1
+};
+
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const u32 clk_domains_essential[] = {
+	CM_L4PER_CLKSTCTRL,
+	CM_L3INIT_CLKSTCTRL,
+	CM_MEMIF_CLKSTCTRL,
+	CM_L4CFG_CLKSTCTRL,
+	0
+};
+
+static const u32 clk_domains_non_essential[] = {
+	CM_MPU_M3_CLKSTCTRL,
+	CM_IVAHD_CLKSTCTRL,
+	CM_DSP_CLKSTCTRL,
+	CM_DSS_CLKSTCTRL,
+	CM_SGX_CLKSTCTRL,
+	CM1_ABE_CLKSTCTRL,
+	CM_C2C_CLKSTCTRL,
+	CM_CAM_CLKSTCTRL,
+	CM_DSS_CLKSTCTRL,
+	CM_SDMA_CLKSTCTRL,
+	0
+};
+
+static const u32 clk_modules_hw_auto_essential[] = {
+	CM_WKUP_GPIO1_CLKCTRL,
+	CM_L4PER_GPIO2_CLKCTRL,
+	CM_L4PER_GPIO3_CLKCTRL,
+	CM_L4PER_GPIO4_CLKCTRL,
+	CM_L4PER_GPIO5_CLKCTRL,
+	CM_L4PER_GPIO6_CLKCTRL,
+	CM_MEMIF_EMIF_1_CLKCTRL,
+	CM_MEMIF_EMIF_2_CLKCTRL,
+	CM_L3INIT_HSUSBOTG_CLKCTRL,
+	CM_L3INIT_USBPHY_CLKCTRL,
+	CM_L4CFG_L4_CFG_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_hw_auto_non_essential[] = {
+	CM_MPU_M3_MPU_M3_CLKCTRL,
+	CM_IVAHD_IVAHD_CLKCTRL,
+	CM_IVAHD_SL2_CLKCTRL,
+	CM_DSP_DSP_CLKCTRL,
+	CM_L3_2_GPMC_CLKCTRL,
+	CM_L3INSTR_L3_3_CLKCTRL,
+	CM_L3INSTR_L3_INSTR_CLKCTRL,
+	CM_L3INSTR_INTRCONN_WP1_CLKCTRL,
+	CM_L3INIT_HSI_CLKCTRL,
+	CM_L3INIT_HSUSBTLL_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_explicit_en_essential[] = {
+	CM_L4PER_GPTIMER2_CLKCTRL,
+	CM_L3INIT_HSMMC1_CLKCTRL,
+	CM_L3INIT_HSMMC2_CLKCTRL,
+	CM_L4PER_MCSPI1_CLKCTRL,
+	CM_WKUP_GPTIMER1_CLKCTRL,
+	CM_L4PER_I2C1_CLKCTRL,
+	CM_L4PER_I2C2_CLKCTRL,
+	CM_L4PER_I2C3_CLKCTRL,
+	CM_L4PER_I2C4_CLKCTRL,
+	CM_WKUP_WDTIMER2_CLKCTRL,
+	CM_L4PER_UART3_CLKCTRL,
+	0
+};
+
+static const u32 clk_modules_explicit_en_non_essential[] = {
+	CM1_ABE_AESS_CLKCTRL,
+	CM1_ABE_PDM_CLKCTRL,
+	CM1_ABE_DMIC_CLKCTRL,
+	CM1_ABE_MCASP_CLKCTRL,
+	CM1_ABE_MCBSP1_CLKCTRL,
+	CM1_ABE_MCBSP2_CLKCTRL,
+	CM1_ABE_MCBSP3_CLKCTRL,
+	CM1_ABE_SLIMBUS_CLKCTRL,
+	CM1_ABE_TIMER5_CLKCTRL,
+	CM1_ABE_TIMER6_CLKCTRL,
+	CM1_ABE_TIMER7_CLKCTRL,
+	CM1_ABE_TIMER8_CLKCTRL,
+	CM1_ABE_WDT3_CLKCTRL,
+	CM_L4PER_GPTIMER9_CLKCTRL,
+	CM_L4PER_GPTIMER10_CLKCTRL,
+	CM_L4PER_GPTIMER11_CLKCTRL,
+	CM_L4PER_GPTIMER3_CLKCTRL,
+	CM_L4PER_GPTIMER4_CLKCTRL,
+	CM_L4PER_HDQ1W_CLKCTRL,
+	CM_L4PER_MCBSP4_CLKCTRL,
+	CM_L4PER_MCSPI2_CLKCTRL,
+	CM_L4PER_MCSPI3_CLKCTRL,
+	CM_L4PER_MCSPI4_CLKCTRL,
+	CM_L4PER_MMCSD3_CLKCTRL,
+	CM_L4PER_MMCSD4_CLKCTRL,
+	CM_L4PER_MMCSD5_CLKCTRL,
+	CM_L4PER_UART1_CLKCTRL,
+	CM_L4PER_UART2_CLKCTRL,
+	CM_L4PER_UART4_CLKCTRL,
+	CM_WKUP_KEYBOARD_CLKCTRL,
+	CM_WKUP_WDTIMER2_CLKCTRL,
+	CM_CAM_ISS_CLKCTRL,
+	CM_CAM_FDIF_CLKCTRL,
+	CM_DSS_DSS_CLKCTRL,
+	CM_SGX_SGX_CLKCTRL,
+	CM_L3INIT_HSUSBHOST_CLKCTRL,
+	CM_L3INIT_FSUSB_CLKCTRL,
+	0
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	u32 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap4_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl(CM_SYS_CLKSEL) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK)
+			- 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS);
+}
+
+static inline void wait_for_bypass(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	while (readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK)
+		;
+}
+
+static inline void do_lock_dpll(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_LOCK);
+}
+
+static inline void wait_for_lock(u32 base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	while (!(readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK))
+		;
+}
+
+static void do_setup_dpll(u32 base, const struct dpll_params *params, u8 lock)
+{
+	u32 temp;
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+	set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK,
+			params->m);
+	set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK,
+			params->n);
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	switch (omap4_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_1524mhz[sysclk_ind];
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		 /* safest */
+		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+	default:
+		return &core_dpll_params_1600mhz[sysclk_ind];
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz;
+	const struct dpll_params *core_dpll_params;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params();
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+static void setup_dplls(void)
+{
+	u32 sysclk_ind, temp;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(CM_CLKMODE_DPLL_CORE, params, DPLL_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, CM_CLKSEL_CORE);
+
+	/* lock PER dpll */
+	do_setup_dpll(CM_CLKMODE_DPLL_PER,
+			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+
+	/* MPU dpll */
+	if (omap4_revision() == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_es1_600mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1ghz[sysclk_ind];
+	do_setup_dpll(CM_CLKMODE_DPLL_MPU, params, DPLL_LOCK);
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, temp, abe_ref_clk;
+	u32 sysclk_ind, sd_div, num, den;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/* IVA */
+	do_setup_dpll(CM_CLKMODE_DPLL_IVA, &iva_dpll_params_1862mhz[sysclk_ind],
+			DPLL_LOCK);
+
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and@the same time no overflow
+	 */
+	params = &usb_dpll_params_1920mhz[sysclk_ind];
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	temp = readl(CM_CLKSEL_DPLL_USB);
+	set_bit_field(temp, CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT,
+		      CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div);
+	writel(temp, CM_CLKSEL_DPLL_USB);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(CM_CLKMODE_DPLL_USB, params, DPLL_LOCK);
+
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+	params = &abe_dpll_params_32k_196608khz;
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+
+	/*
+	 * Enable REGM4XEN to achieve 196.608MHz from 32768 Hz
+	 * We need an additional multiplier of 4 on the input frequency
+	 * since the input frequency is very low
+	 */
+	writel(readl(CM_CLKMODE_DPLL_ABE) | CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK,
+		CM_CLKMODE_DPLL_ABE);
+#endif
+
+	/* Select the right reference clk */
+	modify_reg_32(CM_ABE_PLL_REF_CLKSEL,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			abe_ref_clk);
+	/* Lock the dpll */
+	do_setup_dpll(CM_CLKMODE_DPLL_ABE, params, DPLL_LOCK);
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt)
+{
+	u32 temp;
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (volt << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, PRM_VC_VAL_BYPASS);
+	while (readl(PRM_VC_VAL_BYPASS) & PRM_VC_VAL_BYPASS_VALID_BIT)
+		;
+}
+
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+	u32 omap4_rev = omap4_revision();
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, PRM_VC_CFG_I2C_CLK);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, PRM_VC_CFG_I2C_MODE);
+
+	/* VCORE 1 */
+	if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1))
+		volt = SMPS_VOLT_1_3500_V;
+	else
+		volt = SMPS_VOLT_1_5000_V;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+	/* VCORE 2 */
+	if ((omap4_rev == OMAP4430_ES2_0) || (omap4_rev == OMAP4430_ES2_1))
+		volt = SMPS_VOLT_1_1000_V;
+	else
+		volt = SMPS_VOLT_1_2000_V;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/* VCORE 3 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		volt = SMPS_VOLT_1_1000_V;
+	else if (omap4_rev == OMAP4430_ES2_1)
+		volt = SMPS_VOLT_1_1125_V;
+	else
+		volt = SMPS_VOLT_1_2000_V;
+
+	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+}
+
+static void enable_clock_domain(u32 clkctrl_reg, u32 enable_mode)
+{
+	modify_reg_32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_SHIFT,
+		      CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode);
+}
+
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
+{
+	u32 idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+	       (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		idlest = readl(clkctrl_addr);
+		idlest = get_bit_field(idlest, MODULE_CLKCTRL_IDLEST_SHIFT,
+				       MODULE_CLKCTRL_IDLEST_MASK);
+	}
+}
+
+static void enable_clock_module(u32 clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	modify_reg_32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable a set of clock domains and clock modules associated with them
+ */
+static void enable_clocks(const u32 *clock_domains,
+			  const u32 *clock_modules_hw_auto,
+			  const u32 *clock_modules_explicit_en,
+			  u32 wait_for_enable)
+{
+	int i = 0, max = 100;
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clock_domains[i]; i++) {
+		enable_clock_domain(clock_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clock_modules_hw_auto[i]; i++) {
+		enable_clock_module(clock_modules_hw_auto[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clock_modules_explicit_en[i]; i++) {
+		enable_clock_module(clock_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clock_domains[i]; i++) {
+		enable_clock_domain(clock_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	/* Enable optional additional functional clock for GPIO4 */
+	writel(readl(CM_L4PER_GPIO4_CLKCTRL) | GPIO4_CLKCTRL_OPTFCLKEN_MASK,
+	       CM_L4PER_GPIO4_CLKCTRL);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	writel(readl(CM_L3INIT_HSMMC1_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_MASK,
+	       CM_L3INIT_HSMMC1_CLKCTRL);
+	writel(readl(CM_L3INIT_HSMMC2_CLKCTRL) | HSMMC_CLKCTRL_CLKSEL_MASK,
+	       CM_L3INIT_HSMMC2_CLKCTRL);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	writel(readl(CM_WKUP_GPTIMER1_CLKCTRL) | GPTIMER1_CLKCTRL_CLKSEL_MASK,
+	       CM_WKUP_GPTIMER1_CLKCTRL);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	writel(readl(CM_L3INIT_USBPHY_CLKCTRL) |
+	       USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK, CM_L3INIT_USBPHY_CLKCTRL);
+
+	/* Enable all essential clock domains and modules */
+	enable_clocks(clk_domains_essential,
+		      clk_modules_hw_auto_essential,
+		      clk_modules_explicit_en_essential, 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 tmp;
+	/* Enable optional functional clock for ISS */
+	writel(readl(CM_CAM_ISS_CLKCTRL) | ISS_CLKCTRL_OPTFCLKEN_MASK,
+	       CM_CAM_ISS_CLKCTRL);
+
+	/* Enable all optional functional clocks of DSS */
+	writel(readl(CM_DSS_DSS_CLKCTRL) | DSS_CLKCTRL_OPTFCLKEN_MASK,
+	       CM_DSS_DSS_CLKCTRL);
+
+	/* Enable all non-essential clock domains and modules */
+	enable_clocks(clk_domains_non_essential,
+		      clk_modules_hw_auto_non_essential,
+		      clk_modules_explicit_en_non_essential, 0);
+
+	/* Put camera module in no sleep mode */
+	tmp = readl(CM_CAM_CLKSTCTRL);
+	set_bit_field(tmp, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+		      MODULE_CLKCTRL_MODULEMODE_MASK,
+		      CD_CLKCTRL_CLKTRCTRL_NO_SLEEP);
+	writel(tmp, CM_CAM_CLKSTCTRL);
+}
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL);
+	wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT,
+		      SHADOW_FREQ_CONFIG1_DPLL_EN_MASK, DPLL_EN_LOCK);
+
+	set_bit_field(freq_config1, SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT,
+		      SHADOW_FREQ_CONFIG1_M2_DIV_MASK, core_dpll_params->m2);
+
+	writel(freq_config1, CM_SHADOW_FREQ_CONFIG1);
+	while (readl(CM_SHADOW_FREQ_CONFIG1) &
+		SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK)
+		;
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(CM_MEMIF_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(CM_MEMIF_EMIF_1_CLKCTRL);
+	wait_for_clk_enable(CM_MEMIF_EMIF_2_CLKCTRL);
+}
+
+void bypass_dpll(u32 base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_XIP_UBOOT:
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
new file mode 100644
index 0000000..777ec11
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
@@ -0,0 +1,154 @@
+/*
+ * Program for finding M & N values for DPLLs
+ * To be run on Host PC
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <stdlib.h>
+#include <stdio.h>
+typedef unsigned int u32;
+#define MAX_N	127
+int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n,
+			u32 n_max_limit, u32 tolerance_khz)
+{
+	u32 min_freq = target_freq_khz - tolerance_khz;
+	u32 max_freq = target_freq_khz;
+	u32 freq, freq_old;
+	*n = 1;
+	while (1) {
+		*m = min_freq / ref_freq_khz / 2 * (*n) ;
+		freq_old = 0;
+		while (1) {
+			freq = ref_freq_khz * 2 * (*m) / (*n);
+			if (abs(target_freq_khz - freq_old) <=
+				abs(target_freq_khz - freq)) {
+				freq = freq_old;
+				(*m)--;
+				break;
+			}
+			(*m)++;
+			freq_old = freq;
+		}
+		if (freq >= min_freq && freq <= max_freq)
+			break;
+		(*n)++;
+		if ((*n) > MAX_N + 1) {
+			printf("ref %d m %d n %d target %d : ",
+				ref_freq_khz, *m, *n, target_freq_khz);
+			printf("can not find m & n - please consider"
+				" increasing tolerance\n");
+			return -1;
+		}
+	}
+	(*n)--;
+	printf("ref %d m %d n %d target %d locked %d\n",
+		ref_freq_khz, *m, *n, target_freq_khz, freq);
+	if ((ref_freq_khz / (*n + 1)) < 1000) {
+		printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than"
+			" ideal, locking time will be high!\n");
+	}
+	return 0;
+}
+
+void main(void)
+{
+	u32 m, n;
+	printf("\nMPU - 2000000\n");
+	get_m_n_optimized(2000000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(2000000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(2000000, 16800, &m, &n, 128, 800);
+	get_m_n_optimized(2000000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(2000000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(2000000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(2000000, 38400, &m, &n, 128, 0);
+
+	printf("\nMPU - 1200000\n");
+	get_m_n_optimized(1200000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(1200000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1200000, 16800, &m, &n, 128, 800);
+	get_m_n_optimized(1200000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(1200000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1200000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(1200000, 38400, &m, &n, 128, 0);
+
+	printf("\nCore 1600000\n");
+	get_m_n_optimized(1600000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(1600000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1600000, 16800, &m, &n, 128, 200);
+	get_m_n_optimized(1600000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(1600000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1600000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(1600000, 38400, &m, &n, 128, 0);
+
+	printf("\nPER 1536000\n");
+	get_m_n_optimized(1536000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 16800, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(1536000, 38400, &m, &n, 128, 0);
+
+	printf("\nIVA 1862000\n");
+	get_m_n_optimized(1862000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(1862000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1862000, 16800, &m, &n, 128, 0);
+	get_m_n_optimized(1862000, 19200, &m, &n, 128, 900);
+	get_m_n_optimized(1862000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1862000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(1862000, 38400, &m, &n, 128, 800);
+
+	printf("\nABE 196608 sys clk\n");
+	get_m_n_optimized(196608, 12000, &m, &n, 128, 700);
+	get_m_n_optimized(196608, 13000, &m, &n, 128, 200);
+	get_m_n_optimized(196608, 16800, &m, &n, 128, 700);
+	get_m_n_optimized(196608, 19200, &m, &n, 128, 400);
+	get_m_n_optimized(196608, 26000, &m, &n, 128, 200);
+	get_m_n_optimized(196608, 27000, &m, &n, 128, 900);
+	get_m_n_optimized(196608, 38400, &m, &n, 128, 0);
+
+	printf("\nABE 196608 32K\n");
+	get_m_n_optimized(196608000/4, 32768, &m, &n, 128, 0);
+
+	printf("\nUSB 1920000\n");
+	get_m_n_optimized(1920000, 12000, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 16800, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 27000, &m, &n, 128, 0);
+	get_m_n_optimized(1920000, 38400, &m, &n, 128, 0);
+
+	printf("\nCore ES1 1523712\n");
+	get_m_n_optimized(1524000, 12000, &m, &n, 128, 100);
+	get_m_n_optimized(1524000, 13000, &m, &n, 128, 0);
+	get_m_n_optimized(1524000, 16800, &m, &n, 128, 0);
+	get_m_n_optimized(1524000, 19200, &m, &n, 128, 0);
+	get_m_n_optimized(1524000, 26000, &m, &n, 128, 0);
+	get_m_n_optimized(1524000, 27000, &m, &n, 128, 0);
+
+	/* exact recommendation for SDPs */
+	get_m_n_optimized(1523712, 38400, &m, &n, 128, 0);
+
+}
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..aec1241
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+
+/* PRM.CKGEN module registers */
+#define CM_ABE_PLL_REF_CLKSEL		(OMAP44XX_L4_WKUP_BASE + 0x610C)
+#define CM_SYS_CLKSEL			(OMAP44XX_L4_WKUP_BASE + 0x6110)
+
+/* PRM.WKUP_CM module registers */
+#define CM_WKUP_CLKSTCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7800)
+#define CM_WKUP_L4WKUP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7820)
+#define CM_WKUP_WDTIMER1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7828)
+#define CM_WKUP_WDTIMER2_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7830)
+#define CM_WKUP_GPIO1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7838)
+#define CM_WKUP_GPTIMER1_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7840)
+#define CM_WKUP_GPTIMER12_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7848)
+#define CM_WKUP_SYNCTIMER_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7850)
+#define CM_WKUP_USIM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7858)
+#define CM_WKUP_SARRAM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7860)
+#define CM_WKUP_KEYBOARD_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7878)
+#define CM_WKUP_RTC_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7880)
+#define CM_WKUP_BANDGAP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7888)
+
+/* DEVICE_PRM Registers */
+#define PRM_VC_VAL_BYPASS		(OMAP44XX_L4_WKUP_BASE + 0x7BA0)
+#define PRM_VC_CFG_CHANNEL		(OMAP44XX_L4_WKUP_BASE + 0x7BA4)
+#define PRM_VC_CFG_I2C_MODE		(OMAP44XX_L4_WKUP_BASE + 0x7BA8)
+#define PRM_VC_CFG_I2C_CLK		(OMAP44XX_L4_WKUP_BASE + 0x7BAC)
+
+/* CM1.CKGEN module registers */
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+#define CM_CLKSEL_ABE			(OMAP44XX_L4_CORE_BASE + 0x4108)
+#define CM_DLL_CTRL			(OMAP44XX_L4_CORE_BASE + 0x4110)
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_IDLEST_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4124)
+#define CM_AUTOIDLE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4128)
+#define CM_CLKSEL_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x412c)
+#define CM_DIV_M2_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4130)
+#define CM_DIV_M3_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4134)
+#define CM_DIV_M4_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4138)
+#define CM_DIV_M5_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x413c)
+#define CM_DIV_M6_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4140)
+#define CM_DIV_M7_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4144)
+#define CM_SSC_DELTAMSTEP_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4148)
+#define CM_SSC_MODFREQDIV_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x414c)
+#define CM_EMU_OVERRIDE_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4150)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_IDLEST_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4164)
+#define CM_AUTOIDLE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4168)
+#define CM_CLKSEL_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x416c)
+#define CM_DIV_M2_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4170)
+#define CM_SSC_DELTAMSTEP_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x4188)
+#define CM_SSC_MODFREQDIV_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x418c)
+#define CM_BYPCLK_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x419c)
+#define CM_CLKMODE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a0)
+#define CM_IDLEST_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a4)
+#define CM_AUTOIDLE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a8)
+#define CM_CLKSEL_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41ac)
+#define CM_DIV_M4_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41b8)
+#define CM_DIV_M5_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41bc)
+#define CM_SSC_DELTAMSTEP_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41c8)
+#define CM_SSC_MODFREQDIV_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41cc)
+#define CM_BYPCLK_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41dc)
+#define CM_CLKMODE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e0)
+#define CM_IDLEST_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e4)
+#define CM_AUTOIDLE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e8)
+#define CM_CLKSEL_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41ec)
+#define CM_DIV_M2_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f0)
+#define CM_DIV_M3_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f4)
+#define CM_SSC_DELTAMSTEP_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x4208)
+#define CM_SSC_MODFREQDIV_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x420c)
+#define CM_CLKMODE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4220)
+#define CM_IDLEST_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4224)
+#define CM_AUTOIDLE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4228)
+#define CM_CLKSEL_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x422c)
+#define CM_DIV_M2_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4230)
+#define CM_DIV_M4_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4238)
+#define CM_DIV_M5_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x423c)
+#define CM_DIV_M6_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4240)
+#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY	(OMAP44XX_L4_CORE_BASE + 0x4248)
+#define CM_SHADOW_FREQ_CONFIG1		(OMAP44XX_L4_CORE_BASE + 0x4260)
+
+/* CM1.ABE register offsets */
+#define CM1_ABE_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x4500)
+#define CM1_ABE_L4ABE_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4520)
+#define CM1_ABE_AESS_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4528)
+#define CM1_ABE_PDM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4530)
+#define CM1_ABE_DMIC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4538)
+#define CM1_ABE_MCASP_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4540)
+#define CM1_ABE_MCBSP1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4548)
+#define CM1_ABE_MCBSP2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4550)
+#define CM1_ABE_MCBSP3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4558)
+#define CM1_ABE_SLIMBUS_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4560)
+#define CM1_ABE_TIMER5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4568)
+#define CM1_ABE_TIMER6_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4570)
+#define CM1_ABE_TIMER7_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4578)
+#define CM1_ABE_TIMER8_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4580)
+#define CM1_ABE_WDT3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x4588)
+
+/* CM1.DSP register offsets */
+#define CM_DSP_CLKSTCTRL			(OMAP44XX_L4_CORE_BASE + 0x4400)
+#define	CM_DSP_DSP_CLKCTRL			(OMAP44XX_L4_CORE_BASE + 0x4420)
+
+/* CM2.CKGEN module registers */
+#define CM_CLKSEL_MPU_M3_ISS_ROOT	(OMAP44XX_L4_CORE_BASE + 0x8100)
+#define CM_CLKSEL_USB_60MHz		(OMAP44XX_L4_CORE_BASE + 0x8104)
+#define CM_SCALE_FCLK			(OMAP44XX_L4_CORE_BASE + 0x8108)
+#define CM_CORE_DVFS_PERF1		(OMAP44XX_L4_CORE_BASE + 0x8110)
+#define CM_CORE_DVFS_PERF2		(OMAP44XX_L4_CORE_BASE + 0x8114)
+#define CM_CORE_DVFS_PERF3		(OMAP44XX_L4_CORE_BASE + 0x8118)
+#define CM_CORE_DVFS_PERF4		(OMAP44XX_L4_CORE_BASE + 0x811c)
+#define CM_CORE_DVFS_CURRENT		(OMAP44XX_L4_CORE_BASE + 0x8124)
+#define CM_IVA_DVFS_PERF_TESLA		(OMAP44XX_L4_CORE_BASE + 0x8128)
+#define CM_IVA_DVFS_PERF_IVAHD		(OMAP44XX_L4_CORE_BASE + 0x812c)
+#define CM_IVA_DVFS_PERF_ABE		(OMAP44XX_L4_CORE_BASE + 0x8130)
+#define CM_IVA_DVFS_CURRENT		(OMAP44XX_L4_CORE_BASE + 0x8138)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_IDLEST_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8144)
+#define CM_AUTOIDLE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8148)
+#define CM_CLKSEL_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x814c)
+#define CM_DIV_M2_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8150)
+#define CM_DIV_M3_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8154)
+#define CM_DIV_M4_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8158)
+#define CM_DIV_M5_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x815c)
+#define CM_DIV_M6_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8160)
+#define CM_DIV_M7_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8164)
+#define CM_SSC_DELTAMSTEP_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x8168)
+#define CM_SSC_MODFREQDIV_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x816c)
+#define CM_EMU_OVERRIDE_DPLL_PER	(OMAP44XX_L4_CORE_BASE + 0x8170)
+#define CM_CLKMODE_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8180)
+#define CM_IDLEST_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8184)
+#define CM_AUTOIDLE_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8188)
+#define CM_CLKSEL_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x818c)
+#define CM_DIV_M2_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x8190)
+#define CM_SSC_DELTAMSTEP_DPLL_USB	(OMAP44XX_L4_CORE_BASE + 0x81a8)
+#define CM_SSC_MODFREQDIV_DPLL_USB	(OMAP44XX_L4_CORE_BASE + 0x81ac)
+#define CM_CLKDCOLDO_DPLL_USB		(OMAP44XX_L4_CORE_BASE + 0x81b4)
+#define CM_CLKMODE_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c0)
+#define CM_IDLEST_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c4)
+#define CM_AUTOIDLE_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81c8)
+#define CM_CLKSEL_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81cc)
+#define CM_DIV_M2_DPLL_UNIPRO		(OMAP44XX_L4_CORE_BASE + 0x81d0)
+#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO	(OMAP44XX_L4_CORE_BASE + 0x81e8)
+#define CM_SSC_MODFREQDIV_DPLL_UNIPRO	(OMAP44XX_L4_CORE_BASE + 0x81ec)
+
+/* CM2.CORE module registers */
+#define CM_L3_1_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8700)
+#define CM_L3_1_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8708)
+#define CM_L3_1_L3_1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8720)
+#define CM_L3_2_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8800)
+#define CM_L3_2_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8808)
+#define CM_L3_2_L3_2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8820)
+#define CM_L3_2_GPMC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8828)
+#define CM_L3_2_OCMC_RAM_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8830)
+#define CM_MPU_M3_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8900)
+#define CM_MPU_M3_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8904)
+#define CM_MPU_M3_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8908)
+#define CM_MPU_M3_MPU_M3_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8920)
+#define CM_SDMA_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8a00)
+#define CM_SDMA_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8a04)
+#define CM_SDMA_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8a08)
+#define CM_SDMA_SDMA_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8a20)
+#define CM_MEMIF_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b00)
+#define CM_MEMIF_DMM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b20)
+#define CM_MEMIF_EMIF_FW_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b28)
+#define CM_MEMIF_EMIF_1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b30)
+#define CM_MEMIF_EMIF_2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b38)
+#define CM_MEMIF_DLL_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b40)
+#define CM_MEMIF_EMIF_H1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b50)
+#define CM_MEMIF_EMIF_H2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8b58)
+#define CM_MEMIF_DLL_H_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8b60)
+#define CM_C2C_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c00)
+#define CM_C2C_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x8c04)
+#define CM_C2C_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8c08)
+#define CM_C2C_SAD2D_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c20)
+#define CM_C2C_MODEM_ICR_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8c28)
+#define CM_C2C_SAD2D_FW_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8c30)
+#define CM_L4CFG_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d00)
+#define CM_L4CFG_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x8d08)
+#define CM_L4CFG_L4_CFG_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d20)
+#define CM_L4CFG_HW_SEM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8d28)
+#define CM_L4CFG_MAILBOX_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8d30)
+#define CM_L4CFG_SAR_ROM_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8d38)
+#define CM_L3INSTR_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x8e00)
+#define CM_L3INSTR_L3_3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8e20)
+#define CM_L3INSTR_L3_INSTR_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8e28)
+#define CM_L3INSTR_INTRCONN_WP1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x8e40)
+
+/* CM2.L3INIT register offsets */
+#define CM_L3INIT_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9300)
+
+/* CM2.L4PER register offsets */
+#define CM_L4PER_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9400)
+#define CM_L4PER_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x9408)
+#define CM_L4PER_ADC_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9420)
+#define CM_L4PER_GPTIMER10_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9428)
+#define CM_L4PER_GPTIMER11_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9430)
+#define CM_L4PER_GPTIMER2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9438)
+#define CM_L4PER_GPTIMER3_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9440)
+#define CM_L4PER_GPTIMER4_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9448)
+#define CM_L4PER_GPTIMER9_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9450)
+#define CM_L4PER_ELM_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9458)
+#define CM_L4PER_GPIO2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9460)
+#define CM_L4PER_GPIO3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9468)
+#define CM_L4PER_GPIO4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9470)
+#define CM_L4PER_GPIO5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9478)
+#define CM_L4PER_GPIO6_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9480)
+#define CM_L4PER_HDQ1W_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9488)
+#define CM_L4PER_HECC1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9490)
+#define CM_L4PER_HECC2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9498)
+#define CM_L4PER_I2C1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94a0)
+#define CM_L4PER_I2C2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94a8)
+#define CM_L4PER_I2C3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94b0)
+#define CM_L4PER_I2C4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94b8)
+#define CM_L4PER_L4PER_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94c0)
+#define CM_L4PER_MCASP2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94d0)
+#define CM_L4PER_MCASP3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94d8)
+#define CM_L4PER_MCBSP4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94e0)
+#define CM_L4PER_MGATE_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94e8)
+#define CM_L4PER_MCSPI1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94f0)
+#define CM_L4PER_MCSPI2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x94f8)
+#define CM_L4PER_MCSPI3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9500)
+#define CM_L4PER_MCSPI4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9508)
+#define CM_L4PER_MMCSD3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9520)
+#define CM_L4PER_MMCSD4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9528)
+#define CM_L4PER_MSPROHG_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9530)
+#define CM_L4PER_SLIMBUS2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9538)
+#define CM_L4PER_UART1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9540)
+#define CM_L4PER_UART2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9548)
+#define CM_L4PER_UART3_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9550)
+#define CM_L4PER_UART4_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9558)
+#define CM_L4PER_MMCSD5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9560)
+#define CM_L4PER_I2C5_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x9568)
+#define CM_L4SEC_CLKSTCTRL		(OMAP44XX_L4_CORE_BASE + 0x9580)
+#define CM_L4SEC_STATICDEP		(OMAP44XX_L4_CORE_BASE + 0x9584)
+#define CM_L4SEC_DYNAMICDEP		(OMAP44XX_L4_CORE_BASE + 0x9588)
+#define CM_L4SEC_AES1_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95a0)
+#define CM_L4SEC_AES2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95a8)
+#define CM_L4SEC_DES3DES_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95b0)
+#define CM_L4SEC_PKAEIP29_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95b8)
+#define CM_L4SEC_RNG_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x95c0)
+#define CM_L4SEC_SHA2MD51_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95c8)
+#define CM_L4SEC_CRYPTODMA_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x95d8)
+
+/* CM2.IVAHD */
+#define CM_IVAHD_CLKSTCTRL			(OMAP44XX_L4_CORE_BASE + 0x8f00)
+#define CM_IVAHD_IVAHD_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8f20)
+#define CM_IVAHD_SL2_CLKCTRL		(OMAP44XX_L4_CORE_BASE + 0x8f28)
+
+/* CM2.L3INIT */
+#define CM_L3INIT_HSMMC1_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9328)
+#define CM_L3INIT_HSMMC2_CLKCTRL	(OMAP44XX_L4_CORE_BASE + 0x9330)
+#define CM_L3INIT_HSI_CLKCTRL           (OMAP44XX_L4_CORE_BASE + 0x9338)
+#define CM_L3INIT_HSUSBHOST_CLKCTRL     (OMAP44XX_L4_CORE_BASE + 0x9358)
+#define CM_L3INIT_HSUSBOTG_CLKCTRL      (OMAP44XX_L4_CORE_BASE + 0x9360)
+#define CM_L3INIT_HSUSBTLL_CLKCTRL      (OMAP44XX_L4_CORE_BASE + 0x9368)
+#define CM_L3INIT_P1500_CLKCTRL         (OMAP44XX_L4_CORE_BASE + 0x9378)
+#define CM_L3INIT_FSUSB_CLKCTRL         (OMAP44XX_L4_CORE_BASE + 0x93d0)
+#define CM_L3INIT_USBPHY_CLKCTRL        (OMAP44XX_L4_CORE_BASE + 0x93e0)
+
+/* CM2.CAM */
+#define CM_CAM_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9000)
+#define CM_CAM_ISS_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9020)
+#define CM_CAM_FDIF_CLKCTRL             (OMAP44XX_L4_CORE_BASE + 0x9028)
+
+/* CM2.DSS */
+#define CM_DSS_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9100)
+#define CM_DSS_DSS_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9120)
+
+/* CM2.SGX */
+#define CM_SGX_CLKSTCTRL                (OMAP44XX_L4_CORE_BASE + 0x9200)
+#define CM_SGX_SGX_CLKCTRL              (OMAP44XX_L4_CORE_BASE + 0x9220)
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_DPLL_REGM4XEN_MASK	11
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define SMPS_VOLT_1_0000_V	0x21
+#define SMPS_VOLT_1_0125_V	0x22
+#define SMPS_VOLT_1_0250_V	0x23
+#define SMPS_VOLT_1_0375_V	0x24
+#define SMPS_VOLT_1_0500_V	0x25
+#define SMPS_VOLT_1_0625_V	0x26
+#define SMPS_VOLT_1_0750_V	0x27
+#define SMPS_VOLT_1_0875_V	0x28
+#define SMPS_VOLT_1_1000_V	0x29
+#define SMPS_VOLT_1_1125_V	0x2A
+#define SMPS_VOLT_1_1250_V	0x2B
+#define SMPS_VOLT_1_1375_V	0x2C
+#define SMPS_VOLT_1_1500_V	0x2D
+#define SMPS_VOLT_1_1625_V	0x2E
+#define SMPS_VOLT_1_1750_V	0x2F
+#define SMPS_VOLT_1_1875_V	0x30
+#define SMPS_VOLT_1_2000_V	0x31
+#define SMPS_VOLT_1_2125_V	0x32
+#define SMPS_VOLT_1_2250_V	0x33
+#define SMPS_VOLT_1_2375_V	0x34
+#define SMPS_VOLT_1_2500_V	0x35
+#define SMPS_VOLT_1_2625_V	0x36
+#define SMPS_VOLT_1_2750_V	0x37
+#define SMPS_VOLT_1_2875_V	0x38
+#define SMPS_VOLT_1_3000_V	0x39
+#define SMPS_VOLT_1_3500_V	0x3A
+#define SMPS_VOLT_1_5000_V	0x3B
+#define SMPS_VOLT_1_5000_V	0x3B
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#define NUM_SYS_CLKS	7
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	u32 m;
+	u32 n;
+	u8 m2;
+	u8 m3;
+	u8 m4;
+	u8 m5;
+	u8 m6;
+	u8 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index ebd5b7a..4ba0ee0 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -38,6 +38,12 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
+void prcm_init(void);
+void bypass_dpll(u32 base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
+u32 omap4_revision(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2063c36..787dd88 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* Boot device */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index dffb53b..0374534 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -73,5 +73,10 @@ $(obj)board.c:$(obj)omap4_mux_data.h
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/board.c $@
 
+$(obj)clocks.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@
+
+
 SOBJS	+= lowlevel_init.o
-COBJS	+= board.o
+COBJS	+= board.o clocks.o
-- 
1.7.0.4

[U-Boot] [PATCH v2 14/22] omap4: add serial console support to SPL

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/board.c            |    3 ++
 arch/arm/cpu/armv7/omap4/clocks.c           |   27 ++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    2 +
 arch/arm/include/asm/omap_common.h          |    1 +
 spl/board/ti/omap4.mk                       |   40 +++++++++++++++++++++++++++
 spl/board/ti/spl-omap.c                     |   20 +++++++++++++
 6 files changed, 93 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index f83b6d7..4a37171 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -105,6 +105,9 @@ void s_init(void)
 {
 	watchdog_init();
 	set_mux_conf_regs();
+#ifdef CONFIG_PRELOADER
+	preloader_console_init();
+#endif
 	prcm_init();
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index 802917f..c405b5c 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -713,6 +713,33 @@ void lock_dpll(u32 base)
 	wait_for_lock(base);
 }
 
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	modify_reg_32(CM_L4PER_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SHIFT,
+		      CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+
+	/* Enable all UARTs - console will be on one of them */
+	modify_reg_32(CM_L4PER_UART1_CLKCTRL, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN);
+
+	modify_reg_32(CM_L4PER_UART2_CLKCTRL, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN);
+
+	modify_reg_32(CM_L4PER_UART3_CLKCTRL, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN);
+
+	modify_reg_32(CM_L4PER_UART3_CLKCTRL, MODULE_CLKCTRL_MODULEMODE_SHIFT,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN);
+
+	modify_reg_32(CM_L4PER_CLKSTCTRL, CD_CLKCTRL_CLKTRCTRL_SHIFT,
+		      CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+}
+
 void prcm_init(void)
 {
 	switch (omap4_hw_init_context()) {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4ba0ee0..3ac972d 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -38,12 +38,14 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
+void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
 u32 omap4_revision(void);
+const char *omap4_rev_string(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 787dd88..10fc9c8 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -53,5 +53,6 @@
 
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
+void preloader_console_init(void);
 
 #endif /* _OMAP_COMMON_H_ */
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index 0374534..508dc3b 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -32,6 +32,46 @@ include $(TOPDIR)/config.mk
 SOBJS =
 COBJS =
 
+# serial console
+$(obj)eabi_compat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/lib/eabi_compat.c $@
+
+$(obj)string.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/string.c $@
+
+$(obj)vsprintf.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/vsprintf.c $@
+
+$(obj)console.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/console.c $@
+
+$(obj)stdio.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/common/stdio.c $@
+
+$(obj)serial.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/serial.c $@
+
+$(obj)ns16550.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/serial/ns16550.c $@
+
+$(obj)div64.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/div64.c $@
+
+$(obj)ctype.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/ctype.c $@
+
+COBJS	+= serial.o ns16550.o string.o vsprintf.o console.o stdio.o
+COBJS	+= ctype.o eabi_compat.o div64.o
+
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 0e08f4f..855572f 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -29,6 +29,7 @@
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
 #include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
 
 /* Define global data structure pointer to it*/
 gd_t gdata __attribute__ ((section(".data")));
@@ -45,3 +46,22 @@ void board_init_r(gd_t *id, ulong dummy)
 	for (;;)
 		;
 }
+
+void preloader_console_init(void)
+{
+	const char *u_boot_rev = U_BOOT_VERSION;
+
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	setup_clocks_for_console();
+	serial_init();		/* serial communications setup */
+
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+
+	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+		U_BOOT_TIME);
+	printf("Texas Instruments %s\n", omap4_rev_string());
+}
-- 
1.7.0.4

[U-Boot] [PATCH v2 15/22] omap4: add sdram init support

[Aneesh V]

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
* Changes for makefile changes
* Minor corrections in do_lpddr2_init()
* Minor corrections to read_idle interval calculation
* Sanity test of memory after doing the initialization
* Fixed warnings reported with with latest GCC compilers
---
 arch/arm/cpu/armv7/omap4/Makefile           |    3 +
 arch/arm/cpu/armv7/omap4/board.c            |    2 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  298 +++++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  118 +++++
 arch/arm/include/asm/arch-omap4/emif.h      |  719 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |   11 +
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_sdp4430.h             |    5 -
 spl/board/ti/omap4.mk                       |    9 +-
 9 files changed, 1159 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 6154e86..d9714fe 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -31,6 +31,9 @@ COBJS	+= board.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 COBJS	+= clocks.o
+COBJS	+= emif.o
+COBJS	+= sdram_elpida.o
+
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 4a37171..7add46b 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -109,6 +109,7 @@ void s_init(void)
 	preloader_console_init();
 #endif
 	prcm_init();
+	sdram_init();
 }
 
 /*
@@ -169,7 +170,6 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
 	gd->ram_size = sdram_size();
 
 	return 0;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..9591fb0
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,298 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap4_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+	sdelay(2000);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	modify_reg_32(&emif->emif_lpddr2_nvm_config,
+		OMAP44XX_REG_CS1NVMEN_SHIFT, OMAP44XX_REG_CS1NVMEN_MASK, 0);
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	modify_reg_32(&emif->emif_sdram_ref_ctrl,
+		OMAP44XX_REG_INITREF_DIS_SHIFT,
+		OMAP44XX_REG_INITREF_DIS_MASK, 1);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	modify_reg_32(&emif->emif_sdram_ref_ctrl,
+		OMAP44XX_REG_INITREF_DIS_SHIFT,
+		OMAP44XX_REG_INITREF_DIS_MASK, 0);
+
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap4_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/*
+	 * Workaround:
+	 * In a specific situation, the OCP interface between the DMM and
+	 * EMIF may hang.
+	 * 1. A TILER port is used to perform 2D burst writes of
+	 *       width 1 and height 8
+	 * 2. ELLAn port is used to perform reads
+	 * 3. All accesses are routed to the same EMIF controller
+	 *
+	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
+	 * be kept higher than default 0x7. As per recommondation 0x0A will
+	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
+	 */
+	if (omap4_revision() == OMAP4430_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
+		       &emif->emif_l3_config);
+	}
+}
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs, *tmp_regs;
+	u32 in_sdram, emif_nr;
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+	emif_get_reg_dump(&regs, &tmp_regs);
+	regs = (emif_nr == 1) ? regs : tmp_regs;
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	u32 omap4_rev = omap4_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, CONTROL_LPDDR2IO1_0);
+	writel(lpddr2io, CONTROL_LPDDR2IO1_1);
+	writel(lpddr2io, CONTROL_LPDDR2IO1_2);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_0);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_1);
+	writel(lpddr2io, CONTROL_LPDDR2IO2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap4_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+	emif_get_dmm_regs(&lisa_map_regs);
+
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram;
+
+	in_sdram = running_from_sdram();
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(CM_CLKMODE_DPLL_CORE);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..37e808c
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,118 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
+{
+	u32 omap4_rev = omap4_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0) {
+		*emif1_regs = &emif_regs_elpida_380_mhz_1cs;
+		*emif2_regs = &emif_regs_elpida_380_mhz_1cs;
+	} else if (omap4_rev == OMAP4430_ES2_0) {
+		*emif1_regs = &emif_regs_elpida_200_mhz_2cs;
+		*emif2_regs = &emif_regs_elpida_200_mhz_2cs;
+	} else {
+		*emif1_regs = &emif_regs_elpida_400_mhz_2cs;
+		*emif2_regs = &emif_regs_elpida_400_mhz_2cs;
+	}
+}
+void emif_get_reg_dump(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	u32 omap_rev = omap4_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..f2d54cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,719 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_BASE		0x4E000000
+#define OMAP44XX_DMM_LISA_MAP_BASE		(0x4E000000 + 0x40)
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct __attribute__ ((__packed__)) emif_reg_struct{
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* Read Latency used by the device@reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value for ES1*/
+#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO reg values */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+void emif_get_reg_dump(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 740ca9d..a1c4883 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,17 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO1_0	(CONTROL_PADCONF_CORE + 0x0638)
+#define CONTROL_LPDDR2IO1_1	(CONTROL_PADCONF_CORE + 0x063C)
+#define CONTROL_LPDDR2IO1_2	(CONTROL_PADCONF_CORE + 0x0640)
+#define CONTROL_LPDDR2IO1_3	(CONTROL_PADCONF_CORE + 0x0644)
+#define CONTROL_LPDDR2IO2_0	(CONTROL_PADCONF_CORE + 0x0648)
+#define CONTROL_LPDDR2IO2_1	(CONTROL_PADCONF_CORE + 0x064C)
+#define CONTROL_LPDDR2IO2_2	(CONTROL_PADCONF_CORE + 0x0650)
+#define CONTROL_LPDDR2IO2_3	(CONTROL_PADCONF_CORE + 0x0654)
+#define CONTROL_EFUSE_2		(CONTROL_PADCONF_CORE + 0x0704)
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3ac972d..3fce576 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
 u32 omap4_revision(void);
 const char *omap4_rev_string(void);
 
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 99247df..ae009d6 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -249,11 +249,6 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
-/* Defines for SDRAM init */
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
-#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
-
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index 508dc3b..85b40ca 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -117,6 +117,13 @@ $(obj)clocks.c:
 	@rm -f $@
 	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/clocks.c $@
 
+$(obj)emif.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/emif.c $@
+
+$(obj)sdram_elpida.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap4/sdram_elpida.c $@
 
 SOBJS	+= lowlevel_init.o
-COBJS	+= board.o clocks.o
+COBJS	+= board.o clocks.o emif.o sdram_elpida.o
-- 
1.7.0.4

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Aneesh V]

Calculate EMIF register values based on AC timing parameters
from the SDRAM datasheet and the DDR frequency rather than
using the hard-coded values.

For a new board the user doen't have to go through the tedious
process of calculating the register values. Instead, just
provide the AC timings from the device data sheet as input
and the driver will automatically calculate the register values.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Changes for the make file changes
---
 arch/arm/cpu/armv7/omap-common/Makefile     |    1 +
 arch/arm/cpu/armv7/omap-common/utils.c      |   61 ++
 arch/arm/cpu/armv7/omap4/Makefile           |    1 -
 arch/arm/cpu/armv7/omap4/board.c            |    9 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  861 ++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  152 +++++-
 arch/arm/include/asm/arch-omap4/emif.h      |  304 ++++++++++-
 arch/arm/include/asm/arch-omap4/omap4.h     |   18 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_sdp4430.h             |    5 +
 spl/board/ti/omap4.mk                       |    7 +-
 11 files changed, 1404 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..8f698f8 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..7dce7f1
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,61 @@
+/*
+ * Utility functions for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index d9714fe..0b525e1 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -34,7 +34,6 @@ COBJS	+= clocks.o
 COBJS	+= emif.o
 COBJS	+= sdram_elpida.o
 
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 7add46b..a51d1bb 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -148,13 +149,13 @@ u32 sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 9591fb0..baa5ed6 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -32,6 +32,589 @@
 #include <asm/omap_common.h>
 #include <asm/utils.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	set_bit_field(config_reg, OMAP44XX_REG_SDRAM_TYPE_SHIFT,
+		      OMAP44XX_REG_SDRAM_TYPE_MASK, cs0_device->type + 4);
+
+	set_bit_field(config_reg, OMAP44XX_REG_IBANK_POS_SHIFT,
+		      OMAP44XX_REG_IBANK_POS_MASK,
+		      EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING);
+
+	set_bit_field(config_reg, OMAP44XX_REG_NARROW_MODE_SHIFT,
+		      OMAP44XX_REG_NARROW_MODE_MASK, cs0_device->io_width);
+
+	set_bit_field(config_reg, OMAP44XX_REG_CL_SHIFT, OMAP44XX_REG_CL_MASK,
+		      RL);
+
+	set_bit_field(config_reg, OMAP44XX_REG_ROWSIZE_SHIFT,
+		      OMAP44XX_REG_ROWSIZE_MASK,
+		      addressing->row_sz[cs0_device->io_width]);
+
+	set_bit_field(config_reg, OMAP44XX_REG_IBANK_SHIFT,
+		      OMAP44XX_REG_IBANK_MASK, addressing->num_banks);
+
+	set_bit_field(config_reg, OMAP44XX_REG_EBANK_SHIFT,
+		      OMAP44XX_REG_EBANK_MASK,
+		      (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS));
+
+	set_bit_field(config_reg, OMAP44XX_REG_PAGESIZE_SHIFT,
+		      OMAP44XX_REG_PAGESIZE_MASK,
+		      addressing->col_sz[cs0_device->io_width]);
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	set_bit_field(ref_ctrl, OMAP44XX_REG_REFRESH_RATE_SHIFT,
+		      OMAP44XX_REG_REFRESH_RATE_MASK, val);
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_WTR_SHIFT, OMAP44XX_REG_T_WTR_MASK,
+		      val);
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	set_bit_field(tim1, OMAP44XX_REG_T_RRD_SHIFT, OMAP44XX_REG_T_RRD_MASK,
+		      val);
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RC_SHIFT, OMAP44XX_REG_T_RC_MASK,
+		      val);
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RAS_SHIFT, OMAP44XX_REG_T_RAS_MASK,
+		      val);
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_WR_SHIFT, OMAP44XX_REG_T_WR_MASK,
+		      val);
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RCD_SHIFT, OMAP44XX_REG_T_RCD_MASK,
+		      val);
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	set_bit_field(tim1, OMAP44XX_REG_T_RP_SHIFT, OMAP44XX_REG_T_RP_MASK,
+		      val);
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_CKE_SHIFT, OMAP44XX_REG_T_CKE_MASK,
+		      val);
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_RTP_SHIFT, OMAP44XX_REG_T_RTP_MASK,
+		      val);
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_XSRD_SHIFT, OMAP44XX_REG_T_XSRD_MASK,
+		      val);
+	set_bit_field(tim2, OMAP44XX_REG_T_XSNR_SHIFT, OMAP44XX_REG_T_XSNR_MASK,
+		      val);
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	set_bit_field(tim2, OMAP44XX_REG_T_XP_SHIFT, OMAP44XX_REG_T_XP_MASK,
+		      val);
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	set_bit_field(tim3, OMAP44XX_REG_T_RAS_MAX_SHIFT,
+		      OMAP44XX_REG_T_RAS_MAX_MASK, val);
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_RFC_SHIFT, OMAP44XX_REG_T_RFC_MASK,
+		      val);
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_TDQSCKMAX_SHIFT,
+		      OMAP44XX_REG_T_TDQSCKMAX_MASK, val);
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_ZQ_ZQCS_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQCS_MASK, val);
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	set_bit_field(tim3, OMAP44XX_REG_T_CKESR_SHIFT,
+		      OMAP44XX_REG_T_CKESR_MASK, val);
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	set_bit_field(zq, OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT,
+		      OMAP44XX_REG_ZQ_REFINTERVAL_MASK, val);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQCL_MULT_MASK, REG_ZQ_ZQCL_MULT - 1);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT,
+		      OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK, REG_ZQ_ZQINIT_MULT - 1);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_SFEXITEN_SHIFT,
+		      OMAP44XX_REG_ZQ_SFEXITEN_MASK, REG_ZQ_SFEXITEN_ENABLE);
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	set_bit_field(zq, OMAP44XX_REG_ZQ_DUALCALEN_SHIFT,
+		      OMAP44XX_REG_ZQ_DUALCALEN_MASK, REG_ZQ_DUALCALEN_DISABLE);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_CS0EN_SHIFT,
+		      OMAP44XX_REG_ZQ_CS0EN_MASK, REG_ZQ_CS0EN_ENABLE);
+
+	set_bit_field(zq, OMAP44XX_REG_ZQ_CS1EN_SHIFT,
+		      OMAP44XX_REG_ZQ_CS1EN_MASK, (cs1_device ? 1 : 0));
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	set_bit_field(alert, OMAP44XX_REG_TA_REFINTERVAL_SHIFT,
+		      OMAP44XX_REG_TA_REFINTERVAL_MASK, interval);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_DEVCNT_SHIFT,
+		      OMAP44XX_REG_TA_DEVCNT_MASK, TEMP_ALERT_CONFIG_DEVCT_1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_DEVWDT_SHIFT,
+		      OMAP44XX_REG_TA_DEVWDT_MASK, TEMP_ALERT_CONFIG_DEVWDT_32);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_SFEXITEN_SHIFT,
+		      OMAP44XX_REG_TA_SFEXITEN_MASK, 1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_CS0EN_SHIFT,
+		      OMAP44XX_REG_TA_CS0EN_MASK, 1);
+
+	set_bit_field(alert, OMAP44XX_REG_TA_CS1EN_SHIFT,
+		      OMAP44XX_REG_TA_CS1EN_MASK, (cs1_device ? 1 : 0));
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	set_bit_field(idle, OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT,
+		      OMAP44XX_REG_READ_IDLE_INTERVAL_MASK, val);
+
+	set_bit_field(idle, OMAP44XX_REG_READ_IDLE_LEN_SHIFT,
+		      OMAP44XX_REG_READ_IDLE_LEN_MASK,
+		      EMIF_REG_READ_IDLE_LEN_VAL);
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	set_bit_field(phy, OMAP44XX_REG_READ_LATENCY_SHIFT,
+		      OMAP44XX_REG_READ_LATENCY_MASK, RL + 2);
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	set_bit_field(phy, OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT,
+		      OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK, val);
+
+	/* Other fields are constant magic values. Hardcode them together */
+	set_bit_field(phy, OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT,
+		      OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK,
+		      EMIF_DDR_PHY_CTRL_1_BASE_VAL);
+
+	return phy;
+}
+
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
 static inline u32 emif_num(u32 base)
 {
 	if (base == OMAP44XX_EMIF1)
@@ -66,6 +649,127 @@ static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
 	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
 	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
 }
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
 void emif_reset_phy(u32 base)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -175,14 +879,66 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 
 static void do_sdram_init(u32 base)
 {
-	const struct emif_regs *regs, *tmp_regs;
+	struct emif_device_details dev_details;
+	const struct emif_regs *regs;
+
 	u32 in_sdram, emif_nr;
 
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	const struct emif_regs *tmp_regs;
 	emif_get_reg_dump(&regs, &tmp_regs);
 	regs = (emif_nr == 1) ? regs : tmp_regs;
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+
+	const struct emif_device_details *dev_details_user_provided;
+	const struct emif_device_details *tmp_details;
+	struct emif_regs calculated_regs;
+
+	/* We need some input about the devices from the user */
+	emif_get_device_details(&dev_details_user_provided, &tmp_details);
+	dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided
+						   : tmp_details;
+	if (!dev_details_user_provided)
+		return;
+
+	dev_details.cs0_device_details =
+			dev_details_user_provided->cs0_device_details;
+	dev_details.cs1_device_details =
+			dev_details_user_provided->cs1_device_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+	/* Use the base timings specified by JESD209-2 */
+	dev_details.cs0_device_timings = &jedec_default_timings;
+	dev_details.cs1_device_timings = &jedec_default_timings;
+
+#else /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+	dev_details.cs0_device_timings =
+			dev_details_user_provided->cs0_device_timings;
+	dev_details.cs1_device_timings =
+			dev_details_user_provided->cs1_device_timings;
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
 	 * Initializing the LPDDR2 device can not happen from SDRAM.
@@ -232,12 +988,111 @@ static void emif_post_init_config(u32 base)
 		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
 }
 
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
 static void dmm_init(u32 base)
 {
 	const struct dmm_lisa_map_regs *lisa_map_regs;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated;
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
 
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				0);
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+				OMAP44XX_SYS_SIZE_MASK,
+				get_dmm_section_size_map(mapped_size * 2));
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+				OMAP44XX_SYS_SIZE_MASK,
+				get_dmm_section_size_map(emif1_size));
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				mapped_size >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		set_bit_field(section_map, OMAP44XX_SYS_SIZE_SHIFT,
+			      OMAP44XX_SYS_SIZE_MASK,
+			      get_dmm_section_size_map(emif2_size));
+		set_bit_field(section_map, OMAP44XX_SDRC_ADDR_SHIFT,
+				OMAP44XX_SDRC_ADDR_MASK,
+				mapped_size >> 24); /* only MSB */
+		set_bit_field(section_map, OMAP44XX_SYS_ADDR_SHIFT,
+				OMAP44XX_SYS_ADDR_MASK,
+				sys_addr >> 24); /* only MSB */
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
 	    (struct dmm_lisa_map_regs *)base;
 
@@ -275,8 +1130,10 @@ static void dmm_init(u32 base)
  */
 void sdram_init(void)
 {
-	u32 in_sdram;
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL)
+		return;
 
+	u32 in_sdram;
 	in_sdram = running_from_sdram();
 
 	if (!in_sdram) {
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 37e808c..e7d2bd5 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -29,6 +29,8 @@
 #include <asm/arch/emif.h>
 #include <asm/arch/sys_proto.h>
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
@@ -86,6 +88,131 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 
 void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs)
+
+#else
+
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz,
+};
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+static const struct emif_device_details elpida_2G_S4_x_2 = {
+	.cs0_device_details = &elpida_2G_S4_details,
+	.cs1_device_details = &elpida_2G_S4_details,
+	.cs0_device_timings = &elpida_2G_S4_timings,
+	.cs1_device_timings = &elpida_2G_S4_timings
+};
+
+static const struct emif_device_details elpida_2G_S4_x_1 = {
+	.cs0_device_details = &elpida_2G_S4_details,
+	.cs1_device_details = NULL,
+	.cs0_device_timings = &elpida_2G_S4_timings,
+	.cs1_device_timings = NULL
+};
+
+#endif /* ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+static void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
+			const struct emif_regs **emif2_regs)
 {
 	u32 omap4_rev = omap4_revision();
 
@@ -104,7 +231,8 @@ void emif_get_reg_dump(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
 
-void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
 {
 	u32 omap_rev = omap4_revision();
 
@@ -116,3 +244,25 @@ void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static void emif_get_device_details_sdp(
+			const struct emif_device_details **emif1_details,
+			const struct emif_device_details **emif2_details)
+{
+	u32 omap_rev = omap4_revision();
+
+	if (omap_rev == OMAP4430_ES1_0) {
+		*emif1_details = &elpida_2G_S4_x_1;
+		*emif2_details = &elpida_2G_S4_x_1;
+	} else {
+		*emif1_details = &elpida_2G_S4_x_2;
+		*emif2_details = &elpida_2G_S4_x_2;
+	}
+}
+
+void emif_get_device_details(const struct emif_device_details **emif1_details,
+			     const struct emif_device_details **emif2_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index f2d54cb..8cc3230 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -591,10 +591,142 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 
 #define CS0	0
 #define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
 /* Read Latency used by the device at reset */
 #define RL_BOOT		3
 /* Read Latency for the highest frequency you want to use */
 #define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
 /* EMIF_PWR_MGMT_CTRL register */
 /* Low power modes */
 #define LP_MODE_DISABLE		0
@@ -634,6 +766,16 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 
 /* EMIF_L3_CONFIG register value for ES1*/
 #define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
 
 /*
 * MR1 value:
@@ -657,16 +799,51 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 #define MR10_ZQ_ZQINIT		0xFF
 #define MR10_ZQ_ZQRESET		0xC3
 
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
 /* MR16 value: refresh full array(no partial array self refresh) */
 #define MR16_REF_FULL_ARRAY	0
 
-/* LPDDR2 IO reg values */
+/* LPDDR2 IO regs */
 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
 
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
 /* Mode register numbers */
 #define LPDDR2_MR0	0
 #define LPDDR2_MR1	1
@@ -692,6 +869,119 @@ struct __attribute__ ((__packed__)) dmm_lisa_map_regs {
 #define LPDDR2_MR0_DNVI_SHIFT	2
 #define LPDDR2_MR0_DNVI_MASK	(1 << 2)
 
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen@lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
 /*
  * Structure containing shadow of important registers in EMIF
  * The calculation function fills in this structure to be later used for
@@ -712,8 +1002,20 @@ struct emif_regs {
 	u32 emif_ddr_phy_ctlr_1;
 };
 
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 void emif_get_reg_dump(const struct emif_regs **emif1_regs,
 			const struct emif_regs **emif2_regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(const struct emif_device_details **emif1_details,
+			     const struct emif_device_details **emif2_details);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a1c4883..fd8fb10 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -86,12 +86,7 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
+
 /*
  * Hardware Register Details
  */
@@ -137,6 +132,17 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+
+/*
+ * SRAM scratch space entries
+ */
+
+/* Boot parameter passed from SPL to U-Boot */
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0x8)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0
 #define OMAP4430_ES1_0	1
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3fce576..46064f1 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_revision(void);
 const char *omap4_rev_string(void);
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index ae009d6..d5f98dc 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -249,6 +249,11 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index 85b40ca..a0e2142 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -97,8 +97,13 @@ $(obj)spl-omap.c:
 	@rm -f $@
 	@ln -s $(TOPDIR)/spl/board/ti/spl-omap.c $@
 
+$(obj)utils.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/arch/arm/cpu/armv7/omap-common/utils.c $@
+
+
 SOBJS	+= reset.o
-COBJS	+= timer.o spl-omap.o
+COBJS	+= timer.o spl-omap.o utils.o
 
 # omap4
 $(obj)lowlevel_init.S:
-- 
1.7.0.4

[U-Boot] [PATCH v2 17/22] omap4: automatic sdram detection

[Aneesh V]

Identify SDRAM devices connected to EMIF automatically:
LPDDR2 devices have some Mode Registers that provide details
about the device such as the type, density, bus width
etc. EMIF has the capability to read these registers. If there
are not devices connected to a given chip-select reading mode
registers will return junk values. After reading as many such
registers as possible and matching with expected ranges of
values the driver can identify if there is a device connected
to the respective CS. If we identify that a device is connected
the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2
allows us to do a complete automatic initialization of
SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2
will be safe for all devices but not necessarily optimal. However,
for the Elpida devices used on Panda and SDP the default timings
are both safe and optimal.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/emif.c         |  177 +++++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/sdram_elpida.c |    9 +-
 include/configs/omap4_sdp4430.h         |    1 +
 3 files changed, 176 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index baa5ed6..b09aa8f 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -166,7 +166,8 @@ static const struct lpddr2_min_tck min_tck_jedec = {
 	.tFAW = 8
 };
 
-static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
 	&timings_jedec_200_mhz,
 	&timings_jedec_333_mhz,
 	&timings_jedec_400_mhz
@@ -780,6 +781,146 @@ void emif_reset_phy(u32 base)
 	writel(iodft, &emif->emif_iodft_tlgc);
 }
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, LPDDR2_MR0_DI_SHIFT, LPDDR2_MR0_DI_MASK);
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = get_bit_field(mr, LPDDR2_MR0_DNVI_SHIFT, LPDDR2_MR0_DNVI_MASK);
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, MR8_TYPE_SHIFT, MR8_TYPE_MASK);
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = get_bit_field(mr, MR8_DENSITY_SHIFT, MR8_DENSITY_MASK);
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = get_bit_field(mr, MR8_IO_WIDTH_SHIFT, MR8_IO_WIDTH_MASK);
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_lpddr2_init(u32 base, u32 cs)
 {
 	u32 mr_addr;
@@ -879,9 +1020,7 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 
 static void do_sdram_init(u32 base)
 {
-	struct emif_device_details dev_details;
 	const struct emif_regs *regs;
-
 	u32 in_sdram, emif_nr;
 
 	in_sdram = running_from_sdram();
@@ -889,6 +1028,7 @@ static void do_sdram_init(u32 base)
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	const struct emif_regs *tmp_regs;
+
 	emif_get_reg_dump(&regs, &tmp_regs);
 	regs = (emif_nr == 1) ? regs : tmp_regs;
 #else
@@ -896,23 +1036,48 @@ static void do_sdram_init(u32 base)
 	 * The user has not provided the register values. We need to
 	 * calculate it based on the timings and the DDR frequency
 	 */
+	struct emif_device_details dev_details = { NULL, NULL };
+	struct emif_regs calculated_regs;
 
+#if !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
+
+	/* We need some input about the devices from the user */
 	const struct emif_device_details *dev_details_user_provided;
 	const struct emif_device_details *tmp_details;
-	struct emif_regs calculated_regs;
 
-	/* We need some input about the devices from the user */
 	emif_get_device_details(&dev_details_user_provided, &tmp_details);
 	dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided
 						   : tmp_details;
 	if (!dev_details_user_provided)
 		return;
+#endif
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+
+	/* Automatically find the device details */
+	if (!in_sdram) {
+		dev_details.cs0_device_details =
+		    get_lpddr2_details(base, CS0, &cs0_dev_details);
+		dev_details.cs1_device_details =
+		    get_lpddr2_details(base, CS1, &cs1_dev_details);
+		/*
+		 * Reset the PHY - if there is nothing connected on any
+		 * of the chip selects(typically CS1) mode register reads
+		 * will mess up with the PHY state and subsequent
+		 * initialization won't work. PHY reset brings back PHY to
+		 * a good state.
+		 */
+		emif_reset_phy(base);
+	}
+#else
 	dev_details.cs0_device_details =
 			dev_details_user_provided->cs0_device_details;
 	dev_details.cs1_device_details =
 			dev_details_user_provided->cs1_device_details;
 
+#endif
 	/* Return if no devices on this EMIF */
 	if (!dev_details.cs0_device_details &&
 	    !dev_details.cs1_device_details) {
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index e7d2bd5..8dfe6f9 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -86,10 +86,8 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 	.dmm_lisa_map_3 = 0x80640300
 };
 
-void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
-			const struct emif_regs **emif2_regs)
-
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 	.max_freq	= 400000000,
@@ -245,7 +243,8 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static void emif_get_device_details_sdp(
 			const struct emif_device_details **emif1_details,
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index d5f98dc..13e7623 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -251,6 +251,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Aneesh V]

Embed the u-boot flash image size at a known offset from the
start of u-boot so that SPL can use it while loading u-boot
from a non-XIP media.

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
* Removed the linker script label '__flash_image_end' and its usage.
  Instead '_end' is used now
---
 arch/arm/cpu/armv7/start.S |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f92c6d9..f676d7d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -64,8 +64,12 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
 
 .global _end_vect
 _end_vect:
+.global	_u_boot_size
+_u_boot_size:
+	.word	0xDEADBEEF
+	.word	_end - _start
 
-	.balignl 16,0xdeadbeef
+.balignl 16,0xdeadbeef
 /*************************************************************************
  *
  * Startup Code (reset vector)
-- 
1.7.0.4

[U-Boot] [PATCH v2 19/22] omap: add MMC support to SPL

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Changes for make file changes
---
 arch/arm/cpu/armv7/start.S         |    1 +
 arch/arm/include/asm/omap_common.h |    4 +
 include/configs/omap4_sdp4430.h    |    7 ++-
 spl/board/ti/omap4.mk              |   35 +++++++++++
 spl/board/ti/spl-omap.c            |  112 +++++++++++++++++++++++++++++++++++-
 5 files changed, 156 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f676d7d..351276a 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -64,6 +64,7 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
 
 .global _end_vect
 _end_vect:
+/* This label should be at the same location for SPL and U-Boot */
 .global	_u_boot_size
 _u_boot_size:
 	.word	0xDEADBEEF
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 10fc9c8..efd3b3c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -55,4 +55,8 @@ u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 void preloader_console_init(void);
 
+/* symbols from start.S */
+extern u32 _u_boot_size;
+extern u32 _start;
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 13e7623..0b67345 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -261,7 +261,10 @@
 #define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
 #define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
-#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index a0e2142..ecf605e 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -72,6 +72,41 @@ $(obj)ctype.c:
 COBJS	+= serial.o ns16550.o string.o vsprintf.o console.o stdio.o
 COBJS	+= ctype.o eabi_compat.o div64.o
 
+# mmc
+$(obj)mmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/mmc.c $@
+
+$(obj)omap_hsmmc.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/mmc/omap_hsmmc.c $@
+
+$(obj)omap24xx_i2c.c: $(obj)omap24xx_i2c.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.c $@
+
+$(obj)omap24xx_i2c.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/drivers/i2c/omap24xx_i2c.h $@
+
+$(obj)time.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/lib/time.c $@
+
+$(obj)part.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part.c $@
+
+$(obj)part_dos.c: $(obj)part_dos.h
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.c $@
+
+$(obj)part_dos.h:
+	@rm -f $@
+	@ln -s $(TOPDIR)/disk/part_dos.h $@
+
+COBJS	+= omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o
+
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 855572f..2174c55 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -28,25 +28,135 @@
 #include <common.h>
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
+#include <mmc.h>
 #include <timestamp_autogenerated.h>
 #include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
 
 /* Define global data structure pointer to it*/
 gd_t gdata __attribute__ ((section(".data")));
 bd_t bdata __attribute__ ((section(".data")));
 gd_t *gd = &gdata;
 
+typedef void (*u_boot_entry_t)(void)__attribute__ ((noreturn));
+
 void board_init_f(ulong dummy)
 {
 	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
 }
 
-void board_init_r(gd_t *id, ulong dummy)
+inline void hang(void)
 {
+	puts("### ERROR ### Please RESET the board ###\n");
 	for (;;)
 		;
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
+
+static void mmc_load_uboot_raw(struct mmc *mmc, u32 mmc_dev)
+{
+	u32 u_boot_size, u_boot_size_sectors, err;
+	u32 *magic_loc = (u32 *)(CONFIG_SYS_TEXT_BASE +
+				(u32) &_u_boot_size - (u32) &_start);
+
+	/* read one sector first to find u-boot size */
+	err = mmc->block_dev.block_read(mmc_dev,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)CONFIG_SYS_TEXT_BASE);
+	if (err <= 0)
+		goto end;
+
+	if (*magic_loc++ == 0xDEADBEEF) {
+		/* Signature found - get the size saved in the next word */
+		u_boot_size = *magic_loc;
+	} else {
+		/* Signature not found - however continue to load U-Boot */
+		debug("U-Boot signature not found!\n");
+		/* Let's assume U-Boot will not be more than 200 KB */
+		u_boot_size = 200 * 1024;
+	}
+
+	/*
+	 * convert size to sectors - round down is fine because we have
+	 * already read 1 sector
+	 */
+	u_boot_size_sectors = u_boot_size/MMCSD_SECTOR_SIZE;
+	debug("spl: u-boot raw sectors - %d\n", u_boot_size_sectors + 1);
+	/* read the remaining sectors */
+	err = mmc->block_dev.block_read(mmc_dev,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + 1,
+			u_boot_size_sectors,
+			(void *)(CONFIG_SYS_TEXT_BASE + MMCSD_SECTOR_SIZE));
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_uboot(u32 mmc_dev)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	mmc = find_mmc_device(mmc_dev);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: mmc_dev - %d err - %d\n",
+			mmc_dev, err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW)
+		mmc_load_uboot_raw(mmc, mmc_dev);
+	else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	u32 boot_device;
+	u_boot_entry_t u_boot_entry = (u_boot_entry_t) CONFIG_SYS_TEXT_BASE;
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	boot_device = omap_boot_device();
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1);
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	/* Jump to u-boot */
+	debug("Jumping to U-Boot\n");
+	u_boot_entry();
+}
+
 void preloader_console_init(void)
 {
 	const char *u_boot_rev = U_BOOT_VERSION;
-- 
1.7.0.4

[U-Boot] [PATCH v2 20/22] omap: spl: add FAT support over MMC

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
 * Changes for make file changes
---
 include/configs/omap4_sdp4430.h |    1 +
 spl/board/ti/omap4.mk           |    7 +++++++
 spl/board/ti/spl-omap.c         |   22 ++++++++++++++++++++++
 3 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 0b67345..cc64671 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -263,6 +263,7 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 
 #define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
 #define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
diff --git a/spl/board/ti/omap4.mk b/spl/board/ti/omap4.mk
index ecf605e..e66a532 100644
--- a/spl/board/ti/omap4.mk
+++ b/spl/board/ti/omap4.mk
@@ -107,6 +107,13 @@ $(obj)part_dos.h:
 
 COBJS	+= omap_hsmmc.o omap24xx_i2c.o mmc.o time.o part.o part_dos.o
 
+# fat
+$(obj)fat.c:
+	@rm -f $@
+	@ln -s $(TOPDIR)/fs/fat/fat.c $@
+
+COBJS	+=  fat.o
+
 # armv7
 $(obj)start.S:
 	@rm -f $@
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 2174c55..81ca0d3 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -29,6 +29,7 @@
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <version_autogenerated.h>
 #include <asm/omap_common.h>
@@ -104,6 +105,25 @@ end:
 	}
 }
 
+static void mmc_load_uboot_fat(struct mmc *mmc)
+{
+	s32 err;
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read("u-boot.bin", (u8 *)CONFIG_SYS_TEXT_BASE, 0);
+
+	if (err <= 0) {
+		printf("spl: error reading u-boot.bin - %d\n", err);
+		hang();
+	}
+}
+
 static void mmc_load_uboot(u32 mmc_dev)
 {
 	struct mmc *mmc;
@@ -127,6 +147,8 @@ static void mmc_load_uboot(u32 mmc_dev)
 	boot_mode = omap_boot_mode();
 	if (boot_mode == MMCSD_MODE_RAW)
 		mmc_load_uboot_raw(mmc, mmc_dev);
+	else if (boot_mode == MMCSD_MODE_FAT)
+		mmc_load_uboot_fat(mmc);
 	else {
 		puts("spl: wrong MMC boot mode\n");
 		hang();
-- 
1.7.0.4

[U-Boot] [PATCH v2 21/22] omap4: add spl support for OMAP4 Panda

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
 * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 for Panda
   This is required for EMU devices
 * Changes due to make file changes
---
 arch/arm/cpu/armv7/omap4/emif.c        |    5 +++--
 arch/arm/include/asm/arch-omap4/emif.h |   10 +++++-----
 include/configs/omap4_panda.h          |   24 ++++++++++++++++++++++++
 spl/board/ti/panda/Makefile            |   32 ++++++++++++++++++++++++++++++++
 4 files changed, 64 insertions(+), 7 deletions(-)
 create mode 100644 spl/board/ti/panda/Makefile

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index b09aa8f..699a545 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -1178,9 +1178,9 @@ static void dmm_init(u32 base)
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
 #else
-	u32 emif1_size, emif2_size, mapped_size, section_map;
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
 	u32 section_cnt, sys_addr;
-	struct dmm_lisa_map_regs lis_map_regs_calculated;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
 
 	mapped_size = 0;
 	section_cnt = 3;
@@ -1253,6 +1253,7 @@ static void dmm_init(u32 base)
 		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
 		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
 	}
+
 	/* TRAP for invalid TILER mappings in section 0 */
 	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 8cc3230..b95e545 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -520,11 +520,11 @@
 
 /* Trap for invalid TILER PAT entries */
 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
-		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
-		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
-		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
-		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
-		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
 
 
 /* Reg mapping structure */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 9acd340..e28b916 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -116,7 +116,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */
@@ -238,4 +240,26 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */
diff --git a/spl/board/ti/panda/Makefile b/spl/board/ti/panda/Makefile
new file mode 100644
index 0000000..81bf51c
--- /dev/null
+++ b/spl/board/ti/panda/Makefile
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+# Aneesh V <aneesh@ti.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(SRCTREE)/spl/board/$(VENDOR)/omap4.mk
+include $(SRCTREE)/spl/board/$(VENDOR)/rules-omap.mk
-- 
1.7.0.4

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Aneesh V]

In SPL console is enabled very early where as in U-Boot
it's not. So, SPL can have traces in early init code
while U-Boot can not have it in the same shared code.

Adding a debug print macro that will be defined in SPL
but compiled out in U-Boot.

Also add some useful debug traces throughout SPL

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/omap4/clocks.c |   10 ++++++++--
 arch/arm/cpu/armv7/omap4/emif.c   |   35 +++++++++++++++++++++++++++--------
 arch/arm/include/asm/utils.h      |    6 ++++++
 spl/board/ti/spl-omap.c           |   13 ++++++++++---
 4 files changed, 51 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index c405b5c..720e60f 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -379,7 +379,7 @@ u32 omap4_ddr_clk(void)
 
 	core_dpll_params = get_core_dpll_params();
 
-	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+	spl_debug("sys_clk %d\n ", sys_clk_khz * 1000);
 
 	/* Find Core DPLL locked frequency first */
 	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
@@ -391,7 +391,7 @@ u32 omap4_ddr_clk(void)
 	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
 
 	ddr_clk *= 1000;	/* convert to Hz */
-	debug("ddr_clk %d\n ", ddr_clk);
+	spl_debug("ddr_clk %d\n ", ddr_clk);
 
 	return ddr_clk;
 }
@@ -400,6 +400,7 @@ static void setup_dplls(void)
 {
 	u32 sysclk_ind, temp;
 	const struct dpll_params *params;
+	spl_debug("setup_dplls\n");
 
 	sysclk_ind = get_sys_clk_index();
 
@@ -416,10 +417,12 @@ static void setup_dplls(void)
 	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
 	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
 	writel(temp, CM_CLKSEL_CORE);
+	spl_debug("Core DPLL configured\n");
 
 	/* lock PER dpll */
 	do_setup_dpll(CM_CLKMODE_DPLL_PER,
 			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+	spl_debug("PER DPLL locked\n");
 
 	/* MPU dpll */
 	if (omap4_revision() == OMAP4430_ES1_0)
@@ -427,6 +430,7 @@ static void setup_dplls(void)
 	else
 		params = &mpu_dpll_params_1ghz[sysclk_ind];
 	do_setup_dpll(CM_CLKMODE_DPLL_MPU, params, DPLL_LOCK);
+	spl_debug("MPU DPLL locked\n");
 }
 
 static void setup_non_essential_dplls(void)
@@ -551,6 +555,7 @@ static void scale_vcores(void)
 
 static void enable_clock_domain(u32 clkctrl_reg, u32 enable_mode)
 {
+	spl_debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
 	modify_reg_32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_SHIFT,
 		      CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode);
 }
@@ -570,6 +575,7 @@ static inline void wait_for_clk_enable(u32 clkctrl_addr)
 static void enable_clock_module(u32 clkctrl_addr, u32 enable_mode,
 				u32 wait_for_enable)
 {
+	spl_debug("Enable clock module - 0x%08x\n", clkctrl_addr);
 	modify_reg_32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_SHIFT,
 			MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode);
 	if (wait_for_enable)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 699a545..fcb6d47 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+#define print_timing_reg(reg) spl_debug(#reg" - 0x%08x\n", (reg))
 
 static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
 static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
@@ -237,7 +237,7 @@ s8 addressing_table_index(u8 type, u8 density, u8 width)
 	else
 		index = density;
 
-	debug("emif: addressing table index %d\n", index);
+	spl_debug("emif: addressing table index %d\n", index);
 
 	return index;
 }
@@ -272,7 +272,7 @@ static const struct lpddr2_ac_timings *get_timings_table(const struct
 			timings = device_timings[i];
 		}
 	}
-	debug("emif: timings table: %d\n", freq_nearest);
+	spl_debug("emif: timings table: %d\n", freq_nearest);
 	return timings;
 }
 
@@ -637,7 +637,7 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
 	else
 		mr = readl(&emif->emif_lpddr2_mode_reg_data);
-	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	spl_debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
 	      cs, mr_addr, mr);
 	return mr;
 }
@@ -790,10 +790,10 @@ static void display_sdram_details(u32 emif_nr, u32 cs,
 	char density_str[10];
 	u32 density;
 
-	debug("EMIF%d CS%d\t", emif_nr, cs);
+	spl_debug("EMIF%d CS%d\t", emif_nr, cs);
 
 	if (!device) {
-		debug("None\n");
+		spl_debug("None\n");
 		return;
 	}
 
@@ -807,7 +807,7 @@ static void display_sdram_details(u32 emif_nr, u32 cs,
 	} else
 		sprintf(density_str, "%d MB", density);
 	if (mfg_str && type_str)
-		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+		spl_debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 }
 
 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
@@ -948,6 +948,8 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
+	spl_debug(">>lpddr2_init() %x\n", base);
+
 	/* Not NVM */
 	modify_reg_32(&emif->emif_lpddr2_nvm_config,
 		OMAP44XX_REG_CS1NVMEN_SHIFT, OMAP44XX_REG_CS1NVMEN_MASK, 0);
@@ -978,6 +980,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 		OMAP44XX_REG_INITREF_DIS_SHIFT,
 		OMAP44XX_REG_INITREF_DIS_MASK, 0);
 
+	spl_debug("<<lpddr2_init()\n");
 }
 
 static void emif_update_timings(u32 base, const struct emif_regs *regs)
@@ -1023,6 +1026,8 @@ static void do_sdram_init(u32 base)
 	const struct emif_regs *regs;
 	u32 in_sdram, emif_nr;
 
+	spl_debug(">>do_sdram_init() %x\n", base);
+
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
@@ -1115,6 +1120,8 @@ static void do_sdram_init(u32 base)
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);
+
+	spl_debug("<<do_sdram_init() %x\n", base);
 }
 
 void sdram_init_pads(void)
@@ -1187,7 +1194,7 @@ static void dmm_init(u32 base)
 	sys_addr = CONFIG_SYS_SDRAM_BASE;
 	emif1_size = emif_sizes[0];
 	emif2_size = emif_sizes[1];
-	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+	spl_debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
 
 	if (!emif1_size && !emif2_size)
 		return;
@@ -1296,11 +1303,14 @@ static void dmm_init(u32 base)
  */
 void sdram_init(void)
 {
+	spl_debug(">>sdram_init()\n");
+
 	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL)
 		return;
 
 	u32 in_sdram;
 	in_sdram = running_from_sdram();
+	spl_debug("in_sdram = %d\n", in_sdram);
 
 	if (!in_sdram) {
 		sdram_init_pads();
@@ -1318,4 +1328,13 @@ void sdram_init(void)
 
 	/* for the shadow registers to take effect */
 	freq_update_core();
+
+	/* Do some basic testing */
+	writel(0xDEADBEEF, CONFIG_SYS_SDRAM_BASE);
+	if (readl(CONFIG_SYS_SDRAM_BASE) == 0xDEADBEEF)
+		spl_debug("SDRAM Init success!\n");
+	else
+		printf("SDRAM Init failed!!\n");
+
+	spl_debug("<<sdram_init()\n");
 }
diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h
index d581539..3e847c1 100644
--- a/arch/arm/include/asm/utils.h
+++ b/arch/arm/include/asm/utils.h
@@ -25,6 +25,12 @@
 #ifndef	_UTILS_H_
 #define	_UTILS_H_
 
+#if defined(DEBUG) && defined(CONFIG_PRELOADER)
+#define spl_debug(fmt, args...)	printf(fmt, ##args)
+#else
+#define spl_debug(fmt, args...)
+#endif
+
 /* extract a bit field from a bit vector */
 #define get_bit_field(nr, start, mask)\
 	(((nr) & (mask)) >> (start))
diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
index 81ca0d3..6db3675 100644
--- a/spl/board/ti/spl-omap.c
+++ b/spl/board/ti/spl-omap.c
@@ -27,6 +27,7 @@
  */
 #include <common.h>
 #include <asm/u-boot.h>
+#include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
 #include <fat.h>
@@ -45,7 +46,9 @@ typedef void (*u_boot_entry_t)(void)__attribute__ ((noreturn));
 
 void board_init_f(ulong dummy)
 {
+	debug(">>board_init_f()\n");
 	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
+	debug("<<board_init_f()\n");
 }
 
 inline void hang(void)
@@ -145,11 +148,13 @@ static void mmc_load_uboot(u32 mmc_dev)
 	}
 
 	boot_mode = omap_boot_mode();
-	if (boot_mode == MMCSD_MODE_RAW)
+	if (boot_mode == MMCSD_MODE_RAW) {
+		spl_debug("boot mode - RAW\n");
 		mmc_load_uboot_raw(mmc, mmc_dev);
-	else if (boot_mode == MMCSD_MODE_FAT)
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		spl_debug("boot mode - FAT\n");
 		mmc_load_uboot_fat(mmc);
-	else {
+	} else {
 		puts("spl: wrong MMC boot mode\n");
 		hang();
 	}
@@ -159,6 +164,7 @@ void board_init_r(gd_t *id, ulong dummy)
 {
 	u32 boot_device;
 	u_boot_entry_t u_boot_entry = (u_boot_entry_t) CONFIG_SYS_TEXT_BASE;
+	spl_debug(">>spl:board_init_r()\n");
 
 	timer_init();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
@@ -166,6 +172,7 @@ void board_init_r(gd_t *id, ulong dummy)
 	switch (boot_device) {
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
+		spl_debug("boot device - MMC2\n");
 		mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1);
 		break;
 	default:
-- 
1.7.0.4

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-10-git-send-email-aneesh@ti.com> you wrote:
> Adapted from: nand_spl/board/samsung/smdk6400/Makefile
> 
> - Add the SPL makefile for OMAP4430 SDP
> - Add the necessary CONFIG flags in the board config file
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
>  * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 from
>    0x40304360. This exact address is needed for EMU
>    devices.
>  * Removed un-necessary compiler options from CFLAGS and AFLAGS.
>    These are already set by .mk files in U-Boot
>  * Reorganize the make files to re-use common rules between
>    boards
> ---
>  board/ti/sdp4430/config.mk                         |    3 +-
>  include/configs/omap4_sdp4430.h                    |   19 +++++
>  spl/board/ti/omap4.mk                              |   77 ++++++++++++++++++++
>  spl/board/ti/rules-omap.mk                         |   74 +++++++++++++++++++
>  .../config.mk => spl/board/ti/sdp4430/Makefile     |   21 +++---
>  5 files changed, 183 insertions(+), 11 deletions(-)
>  create mode 100644 spl/board/ti/omap4.mk
>  create mode 100644 spl/board/ti/rules-omap.mk

We do you introduce these files?  Please omit them, and use a plain
Makefile instead.

> diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
> index 33901a7..c62965d 100644
> --- a/board/ti/sdp4430/config.mk
> +++ b/board/ti/sdp4430/config.mk
> @@ -28,4 +28,5 @@
>  # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
>  # (mem base + reserved)
>  
> -CONFIG_SYS_TEXT_BASE = 0x80e80000
> +# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> +CONFIG_SYS_TEXT_BASE = 0x80100000

NAK.  Please define in board config header, and get rid of the
config.mk file.


> +++ b/spl/board/ti/sdp4430/Makefile
...
> +include $(SRCTREE)/spl/board/$(VENDOR)/omap4.mk
> +include $(SRCTREE)/spl/board/$(VENDOR)/rules-omap.mk

NAK.  Move the code into the Makefile, and dump these two files.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"We don't have to protect the environment -- the Second Coming is  at
hand."                                                   - James Watt

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-14-git-send-email-aneesh@ti.com> you wrote:
> Add support for:
> 1. DPLL locking
> 2. Initialization of clock domains and clock modules
> 
> This work draws upon previous work done for x-loader mainly by:
> 	Santosh Shilimkar <santosh.shilimkar@ti.com>
> 	Rajendra Nayak <rnayak@ti.com>
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
> * Use pre-calculated M & N values instead of calculated ones
> * Changes due to make file changes
> * Some corrections
> * Do all clock initialization in SPL itself instead of differing some
>   work to u-boot
> ---
>  arch/arm/cpu/armv7/omap4/Makefile           |    1 +
>  arch/arm/cpu/armv7/omap4/board.c            |    1 +
>  arch/arm/cpu/armv7/omap4/clocks.c           |  731 +++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/omap4/clocks_get_m_n.c   |  154 ++++++
>  arch/arm/include/asm/arch-omap4/clocks.h    |  506 ++++++++++++++++++
>  arch/arm/include/asm/arch-omap4/sys_proto.h |    6 +
>  arch/arm/include/asm/omap_common.h          |    3 +
>  spl/board/ti/omap4.mk                       |    7 +-
>  8 files changed, 1408 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
>  create mode 100644 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
>  create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h

It appears this might be part of or taken from some bigger scope
clocks framework.  Otherwise it's diffcult for me to understand why
OMAP4 needs 1400+ lines of code, when other SoCs appear to do with
considerably less. Please comment.

> diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
> index 987dc9d..6154e86 100644
> --- a/arch/arm/cpu/armv7/omap4/Makefile
> +++ b/arch/arm/cpu/armv7/omap4/Makefile
> @@ -30,6 +30,7 @@ SOBJS	+= lowlevel_init.o
>  COBJS	+= board.o
>  COBJS	+= mem.o
>  COBJS	+= sys_info.o
> +COBJS	+= clocks.o

Please keep lists sorted.

...
> +static inline void do_bypass_dpll(u32 base)
> +{
> +	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
> +
> +	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
> +		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
> +		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS);

NAK, please use standard macros (see previous messages).

> +static void do_setup_dpll(u32 base, const struct dpll_params *params, u8 lock)
> +{
> +	u32 temp;
> +	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
> +
> +	bypass_dpll(base);
> +
> +	/* Set M & N */
> +	temp = readl(&dpll_regs->cm_clksel_dpll);
> +	set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK,
> +			params->m);
> +	set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK,
> +			params->n);
> +	writel(temp, &dpll_regs->cm_clksel_dpll);

NAK, please use standard macros (see previous messages).


...
> diff --git a/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
> new file mode 100644
> index 0000000..777ec11
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
> @@ -0,0 +1,154 @@
...
> +void main(void)

It appears this is a host program, not part of U-Boot.  I don't think
that arch/arm/cpu/armv7/omap4/ is the right place for this program.

...
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-omap4/clocks.h
> @@ -0,0 +1,506 @@
...
> +#define CM_WKUP_CLKSTCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7800)
> +#define CM_WKUP_L4WKUP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7820)
> +#define CM_WKUP_WDTIMER1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7828)
> +#define CM_WKUP_WDTIMER2_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7830)
> +#define CM_WKUP_GPIO1_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7838)
> +#define CM_WKUP_GPTIMER1_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7840)
> +#define CM_WKUP_GPTIMER12_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7848)
> +#define CM_WKUP_SYNCTIMER_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7850)
> +#define CM_WKUP_USIM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7858)
> +#define CM_WKUP_SARRAM_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7860)
> +#define CM_WKUP_KEYBOARD_CLKCTRL	(OMAP44XX_L4_WKUP_BASE + 0x7878)
> +#define CM_WKUP_RTC_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7880)
> +#define CM_WKUP_BANDGAP_CLKCTRL		(OMAP44XX_L4_WKUP_BASE + 0x7888)
> +
> +/* DEVICE_PRM Registers */
> +#define PRM_VC_VAL_BYPASS		(OMAP44XX_L4_WKUP_BASE + 0x7BA0)
> +#define PRM_VC_CFG_CHANNEL		(OMAP44XX_L4_WKUP_BASE + 0x7BA4)
> +#define PRM_VC_CFG_I2C_MODE		(OMAP44XX_L4_WKUP_BASE + 0x7BA8)
> +#define PRM_VC_CFG_I2C_CLK		(OMAP44XX_L4_WKUP_BASE + 0x7BAC)
> +
> +/* CM1.CKGEN module registers */
> +#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
> +#define CM_CLKSEL_ABE			(OMAP44XX_L4_CORE_BASE + 0x4108)
> +#define CM_DLL_CTRL			(OMAP44XX_L4_CORE_BASE + 0x4110)
> +#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
> +#define CM_IDLEST_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4124)
> +#define CM_AUTOIDLE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4128)
> +#define CM_CLKSEL_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x412c)
> +#define CM_DIV_M2_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4130)
> +#define CM_DIV_M3_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4134)
> +#define CM_DIV_M4_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4138)
> +#define CM_DIV_M5_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x413c)
> +#define CM_DIV_M6_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4140)
> +#define CM_DIV_M7_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4144)
> +#define CM_SSC_DELTAMSTEP_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4148)
> +#define CM_SSC_MODFREQDIV_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x414c)
> +#define CM_EMU_OVERRIDE_DPLL_CORE	(OMAP44XX_L4_CORE_BASE + 0x4150)
> +#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
> +#define CM_IDLEST_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4164)
> +#define CM_AUTOIDLE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4168)
> +#define CM_CLKSEL_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x416c)
> +#define CM_DIV_M2_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4170)
> +#define CM_SSC_DELTAMSTEP_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x4188)
> +#define CM_SSC_MODFREQDIV_DPLL_MPU	(OMAP44XX_L4_CORE_BASE + 0x418c)
> +#define CM_BYPCLK_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x419c)
> +#define CM_CLKMODE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a0)
> +#define CM_IDLEST_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a4)
> +#define CM_AUTOIDLE_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41a8)
> +#define CM_CLKSEL_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41ac)
> +#define CM_DIV_M4_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41b8)
> +#define CM_DIV_M5_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41bc)
> +#define CM_SSC_DELTAMSTEP_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41c8)
> +#define CM_SSC_MODFREQDIV_DPLL_IVA	(OMAP44XX_L4_CORE_BASE + 0x41cc)
> +#define CM_BYPCLK_DPLL_IVA		(OMAP44XX_L4_CORE_BASE + 0x41dc)
> +#define CM_CLKMODE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e0)
> +#define CM_IDLEST_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e4)
> +#define CM_AUTOIDLE_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41e8)
> +#define CM_CLKSEL_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41ec)
> +#define CM_DIV_M2_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f0)
> +#define CM_DIV_M3_DPLL_ABE		(OMAP44XX_L4_CORE_BASE + 0x41f4)
> +#define CM_SSC_DELTAMSTEP_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x4208)
> +#define CM_SSC_MODFREQDIV_DPLL_ABE	(OMAP44XX_L4_CORE_BASE + 0x420c)
> +#define CM_CLKMODE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4220)
> +#define CM_IDLEST_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4224)
> +#define CM_AUTOIDLE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4228)
> +#define CM_CLKSEL_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x422c)
> +#define CM_DIV_M2_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4230)
> +#define CM_DIV_M4_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4238)
> +#define CM_DIV_M5_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x423c)
> +#define CM_DIV_M6_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4240)
> +#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY	(OMAP44XX_L4_CORE_BASE + 0x4248)
> +#define CM_SHADOW_FREQ_CONFIG1		(OMAP44XX_L4_CORE_BASE + 0x4260)

NAK.  We do not accept base address plus offset notation.  Please
declare C structs instead.



Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I think animal testing is a terrible idea; they get all  nervous  and
give the wrong answers.

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-2-git-send-email-aneesh@ti.com> you wrote:
> From: John Rigby <john.rigby@linaro.org>
> 
> Signed-off-by: John Rigby <john.rigby@linaro.org>
> ---
>  common/image.c    |    1 +
>  include/image.h   |    1 +
>  tools/Makefile    |    2 +
>  tools/mkimage.c   |    2 +
>  tools/mkimage.h   |    1 +
>  tools/omapimage.c |  229 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>  tools/omapimage.h |   50 ++++++++++++
>  7 files changed, 286 insertions(+), 0 deletions(-)
>  create mode 100644 tools/omapimage.c
>  create mode 100644 tools/omapimage.h
> 
> diff --git a/common/image.c b/common/image.c
> index e542a57..7f6fe1c 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
>  	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
>  	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
>  	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
> +	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
>  	{	-1,		    "",		  "",			},

Please keep list sorted / sort list.

> diff --git a/tools/Makefile b/tools/Makefile
> index 623f908..a1c4ed7 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
>  OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
>  NOPED_OBJ_FILES-y += kwbimage.o
>  NOPED_OBJ_FILES-y += imximage.o
> +NOPED_OBJ_FILES-y += omapimage.o
>  NOPED_OBJ_FILES-y += mkimage.o
>  OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
>  NOPED_OBJ_FILES-y += os_support.o
> @@ -180,6 +181,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
>  			$(obj)fit_image.o \
>  			$(obj)image.o \
>  			$(obj)imximage.o \
> +			$(obj)omapimage.o \
>  			$(obj)kwbimage.o \
>  			$(obj)md5.o \
>  			$(obj)mkimage.o \

Please keep lists sorted.

> --- /dev/null
> +++ b/tools/omapimage.c
> @@ -0,0 +1,229 @@
> +/*
> + * (C) Copyright 2010
> + * Linaro LTD, www.linaro.org
> + * Author: John Rigby <john.rigby@linaro.org>
> + * Based on TI's signGP.c
> + *
> + * (C) Copyright 2009
> + * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
> + *
> + * (C) Copyright 2008
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/* Required to obtain the getline prototype from stdio.h */
> +#define _GNU_SOURCE
> +
> +#include "mkimage.h"
> +#include <image.h>
> +#include "omapimage.h"
> +
> +/* Header size is CH header rounded up to 512 bytes plus GP header */
> +#define OMAP_CH_HDR_SIZE 512
> +#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
> +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
> +
> +static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
> +
> +static int omapimage_check_image_types(uint8_t type)
> +{
> +	if (type == IH_TYPE_OMAPIMAGE)
> +		return EXIT_SUCCESS;
> +	else
> +		return EXIT_FAILURE;

Maybe an error message would be helpful?


> +static void omapimage_print_section(struct ch_settings *chs)
> +{
> +	switch (chs->section_key) {
> +	case KEY_CHSETTINGS:
> +		printf("CHSETTINGS (%x) "
> +			"valid:%x "
> +			"version:%x "
> +			"reserved:%x "
> +			"flags:%x\n",
> +			chs->section_key,
> +			chs->valid,
> +			chs->version,
> +			chs->reserved,
> +			chs->flags);
> +		break;
> +	default:
> +		printf("UNKNOWNKEY (%x) "
> +			"valid:%x "
> +			"version:%x "
> +			"reserved:%x "
> +			"flags:%x\n",
> +			chs->section_key,
> +			chs->valid,
> +			chs->version,
> +			chs->reserved,
> +			chs->flags);
> +		break;

How about unifying these cases, and passing "CHSETTINGS" resp.
"UNKNOWNKEY" as argument?

...
> +struct ch_toc {
> +	uint32_t section_offset;
> +	uint32_t section_size;
> +	uint8_t unused[12];
> +	uint8_t section_name[12];
> +} __attribute__ ((__packed__));
> +
> +struct ch_settings {
> +	uint32_t section_key;
> +	uint8_t valid;
> +	uint8_t version;
> +	uint16_t reserved;
> +	uint32_t flags;
> +} __attribute__ ((__packed__));
> +
> +struct gp_header {
> +	uint32_t size;
> +	uint32_t load_addr;
> +} __attribute__ ((__packed__));

Is there any good reason to have these "__attribute__ ((__packed__))"
here?  In general, these are only known to cause trouble and pain, and
I cannot see a need here.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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some of their equipment."                            - Harv Masterson

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-3-git-send-email-aneesh@ti.com> you wrote:
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
> * Added a revision string in addition to the revision number
>   Helps in printing out the OMAP revision at bootup
...
> +const char *omap4_rev_string(void)
> +{
> +	const char *omap4_rev = NULL;
> +	switch (omap4_revision()) {
> +	case OMAP4430_ES1_0:
> +		omap4_rev = "OMAP4430 ES1.0";
> +		break;
> +	case OMAP4430_ES2_0:
> +		omap4_rev = "OMAP4430 ES2.0";
> +		break;
> +	case OMAP4430_ES2_1:
> +		omap4_rev = "OMAP4430 ES2.1";
> +		break;
> +	case OMAP4430_ES2_2:
> +		omap4_rev = "OMAP4430 ES2.2";
> +		break;

Such code does not really scale well.  Can this not be improved?  I
think we just had similar discussions for i.MX5x - please check what
the result of these was.

> +	default:
> +		omap4_rev = "OMAP4 - Unknown Rev";
> +		break;

Please also output what the unknown revision was - this saves at least
one debug round if you ever run into this case.

> +}
> diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
> index a30bb33..1f88732 100644
> --- a/arch/arm/include/asm/arch-omap4/omap4.h
> +++ b/arch/arm/include/asm/arch-omap4/omap4.h
> @@ -51,6 +51,11 @@
>  #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
>  #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
>  
> +/* CONTROL_ID_CODE */
> +#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)

C struct?


Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Change is the essential process of all existence.
	-- Spock, "Let That Be Your Last Battlefield",
	   stardate 5730.2

[U-Boot] [PATCH v2 03/22] armv7: start.S: provide a hook for saving boot params

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-4-git-send-email-aneesh@ti.com> you wrote:
> Provide a means by which u-boot/SPL can save parameters passed
> to it by ROM code or the pre-loader.
> 
> A new function 'save_boot_params' has been defined and a default
> implentation provided. Please note that we do not have a stack yet.
> So, any implementation of this function should not use stack.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>

As is, this is dead code.  Please squash with next patch that uses
this.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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You don't have to stay up nights to succeed; you have to  stay  awake
days.

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-5-git-send-email-aneesh@ti.com> you wrote:
> Save boot device information passed by OMAP4 rom code
> 
> ROM code in OMAP4 passes information such as the media from
> which it picked up the first boot image(SPL in our case),
> the mode(raw mode/FAT mode) etc.
> 
> Save this information in SPL so that we can use the same media
> and mode to bootload u-boot.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
...
> +	/* Store the boot device in omap4_boot_device */
> +	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
> +	and	r2, #BOOT_DEVICE_MASK
> +	ldr	r3, =omap4_boot_device
> +	str     r2, [r3]			@ omap4_boot_device <- r1

Why don't you use stadard global data here?


Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I object to intellect without discipline;  I object to power without
constructive purpose.
	-- Spock, "The Squire of Gothos", stardate 2124.5

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-7-git-send-email-aneesh@ti.com> you wrote:
> Define a new type of SPL that is not tied to any particular media.
> - Create a top level directory 'spl' that has a structure similar
>   to the existing 'nand_spl'
> - Make necessary changes to top-level Makefile to build such an spl
> 
> Rationale for this approach:
> - There may be SPLs(like the OMAP x-loader) that support booting from
>   multiple media.
> - Also, there is no harm in keeping SPLs specific to a particular media
>   also under this directory. In fact it makes sense to merge all the
>   different spl directories into this one.

Thanks a lot for addressing this. This is an area that has long been
on my mind, and I'm really happy to see someone starting to work on
this.

In addition to booting from different types of media, I see at least
two more topics that scould and should addressed by this work:

- Get rid of xloader. I cannot see any good reasons why we need it,
  i. e. which functions if performs that cannot be as well (and
  eventually even more efficiently) be performed in the U-Boot SPL
  code.

- Become more flexible regarding the kind of second stage payload.
  It is definitely very powerful and convenient during development to
  be able to load U-Boot with all it's capabilities as payload of the
  SPL, but then, except for image size and parameter passing, there is
  little or no difference to loading a Linux kernel directly instead
  (and actually this is what most of the super-fast booting approaches
  do).  If done right, we may even have the flexibility to do both,
  just by providing different images as payload.


> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> This patch generates 1 checkpatch warning due to declaration
> of DECLARE_GLOBAL_DATA_PTR. This is un-avoidable
> ---
>  Makefile                           |   24 ++++++++++++++++++++++++
>  arch/arm/include/asm/global_data.h |    5 +++++
>  2 files changed, 29 insertions(+), 0 deletions(-)

Here the commit message and the implementation do not agree.  You
wrote "Create a top level directory 'spl'" - but I don't see any of
that here?

I think this should be split into a separate patch series, and care
should be taken that commit messages and implementaiton match.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Our business is run on trust.  We trust you will pay in advance.

[U-Boot] [PATCH v2 07/22] armv7: start.S: add SPL support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-8-git-send-email-aneesh@ti.com> you wrote:
> Changes for supporting SPL

As is, this is dead code.  I think this patch should be much later in
this patch series.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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point is ... the point is ... the point is we've been not experienced
for a lot longer than you. We've got  a  lot  of  experience  of  not
having any experience."           - Terry Pratchett, _Witches Abroad_

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-9-git-send-email-aneesh@ti.com> you wrote:
> Add the basic spl framework and linker script common for OMAP3/4
> platforms.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  spl/board/ti/spl-omap.c   |   47 ++++++++++++++++++++++++++++++++++
>  spl/board/ti/spl-omap.lds |   62 +++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 109 insertions(+), 0 deletions(-)
>  create mode 100644 spl/board/ti/spl-omap.c
>  create mode 100644 spl/board/ti/spl-omap.lds

Again, this appears to be not the right order.

I think, in the first step of this series, we should move the existing
code from nand_spl and onenand_ipl into something like spl/nand and
spl/onenand, respectivly, and make sure all teh existing systems still
build.  The we can add more such support.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When choosing between two evils, I always like to take the  one  I've
never tried before.                     -- Mae West, "Klondike Annie"

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-9-git-send-email-aneesh@ti.com> you wrote:
> Add the basic spl framework and linker script common for OMAP3/4
> platforms.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
...
> +void board_init_r(gd_t *id, ulong dummy)
> +{
> +	for (;;)
> +		;
> +}

Also, this cannot be right.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Committee, n.:  A group of men who individually can do nothing but as
a group decide that nothing can be done.                 - Fred Allen

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-10-git-send-email-aneesh@ti.com> you wrote:
> Adapted from: nand_spl/board/samsung/smdk6400/Makefile
> 
> - Add the SPL makefile for OMAP4430 SDP
> - Add the necessary CONFIG flags in the board config file
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
>  * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 from
>    0x40304360. This exact address is needed for EMU
>    devices.
>  * Removed un-necessary compiler options from CFLAGS and AFLAGS.
>    These are already set by .mk files in U-Boot
>  * Reorganize the make files to re-use common rules between
>    boards
> ---
>  board/ti/sdp4430/config.mk                         |    3 +-
>  include/configs/omap4_sdp4430.h                    |   19 +++++
>  spl/board/ti/omap4.mk                              |   77 ++++++++++++++++++++
>  spl/board/ti/rules-omap.mk                         |   74 +++++++++++++++++++
>  .../config.mk => spl/board/ti/sdp4430/Makefile     |   21 +++---
>  5 files changed, 183 insertions(+), 11 deletions(-)
>  create mode 100644 spl/board/ti/omap4.mk
>  create mode 100644 spl/board/ti/rules-omap.mk

See previous comments.  Please comine into plain Makefile.

> diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
> index 33901a7..c62965d 100644
> --- a/board/ti/sdp4430/config.mk
> +++ b/board/ti/sdp4430/config.mk
> @@ -28,4 +28,5 @@
>  # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
>  # (mem base + reserved)
>  
> -CONFIG_SYS_TEXT_BASE = 0x80e80000
> +# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> +CONFIG_SYS_TEXT_BASE = 0x80100000

Please move #define into board header and get rid of the config.mk


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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nug zu wollen, man mu? auch tun.   -- Goethe, Maximen und Reflexionen

[U-Boot] [PATCH v2 10/22] omap4: utility function to identify the context of hw init

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-11-git-send-email-aneesh@ti.com> you wrote:
> The basic hardware init of OMAP4(s_init()) can happen in 4
> different contexts:
>  1. SPL running from SRAM
>  2. U-Boot running from FLASH
>  3. Non-XIP U-Boot loaded to SDRAM by SPL
>  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
>     Configuration Header feature
...
> +	if (uboot_loaded_by_spl())
> +		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL;
> +	else if (running_from_sdram())
> +		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH;

For reasons of consistency, should this not better be
OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_ROM ?

> +		return OMAP_INIT_CONTEXT_XIP_UBOOT;

What exactly is OMAP_INIT_CONTEXT_XIP_UBOOT?

Do you mean the situation when booting from NOR flash, before
relocation?

Eventually the "loaded by" definition is not so good, as it does not
really cover the NOR boot case.


> +/* HW Init Context */
> +#define OMAP_INIT_CONTEXT_SPL			0
> +#define OMAP_INIT_CONTEXT_XIP_UBOOT		1
> +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL	2
> +#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH	3

Boot from NOR?

Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH v2 15/22] omap4: add sdram init support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-16-git-send-email-aneesh@ti.com> you wrote:
> Add support for the SDRAM controller (EMIF).
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> V2:
> * Changes for makefile changes
> * Minor corrections in do_lpddr2_init()
> * Minor corrections to read_idle interval calculation
> * Sanity test of memory after doing the initialization
> * Fixed warnings reported with with latest GCC compilers
> ---
>  arch/arm/cpu/armv7/omap4/Makefile           |    3 +
>  arch/arm/cpu/armv7/omap4/board.c            |    2 +-
>  arch/arm/cpu/armv7/omap4/emif.c             |  298 +++++++++++
>  arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  118 +++++
>  arch/arm/include/asm/arch-omap4/emif.h      |  719 +++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-omap4/omap4.h     |   11 +
>  arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
>  include/configs/omap4_sdp4430.h             |    5 -
>  spl/board/ti/omap4.mk                       |    9 +-
>  9 files changed, 1159 insertions(+), 7 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
>  create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
>  create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

I'm really surprised to see this patch at this position in the middle
of this patch series.

Can you please explain why you think this is the right place for it?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
2000 pounds of chinese soup                               = 1 Won Ton

[U-Boot] [PATCH v2 15/22] omap4: add sdram init support

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-16-git-send-email-aneesh@ti.com> you wrote:
> Add support for the SDRAM controller (EMIF).
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> V2:
> * Changes for makefile changes
> * Minor corrections in do_lpddr2_init()
> * Minor corrections to read_idle interval calculation
> * Sanity test of memory after doing the initialization
> * Fixed warnings reported with with latest GCC compilers
> ---
>  arch/arm/cpu/armv7/omap4/Makefile           |    3 +
>  arch/arm/cpu/armv7/omap4/board.c            |    2 +-
>  arch/arm/cpu/armv7/omap4/emif.c             |  298 +++++++++++
>  arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  118 +++++
>  arch/arm/include/asm/arch-omap4/emif.h      |  719 +++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-omap4/omap4.h     |   11 +
>  arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
>  include/configs/omap4_sdp4430.h             |    5 -
>  spl/board/ti/omap4.mk                       |    9 +-
>  9 files changed, 1159 insertions(+), 7 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
>  create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
>  create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

Note that this needs to be fixed anyway to use standard macros (get
rid of modify_reg_32() etc.)

Best regards,

Wolfgang Denk

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[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-17-git-send-email-aneesh@ti.com> you wrote:
> Calculate EMIF register values based on AC timing parameters
> from the SDRAM datasheet and the DDR frequency rather than
> using the hard-coded values.
> 
> For a new board the user doen't have to go through the tedious
> process of calculating the register values. Instead, just
> provide the AC timings from the device data sheet as input
> and the driver will automatically calculate the register values.

Does it make sense to do this in the driver code?  These parameters
will never change, so why can we not rather perform the computation
only once, at build time, and feed in the respective parameters to the
driver?

Reasons why I am concerned about such an approach are code size and
boot time.  Both suffer ...

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Never underestimate the power of human stupidity  when  it  comes  to
using technology they don't understand.

[U-Boot] [PATCH v2 17/22] omap4: automatic sdram detection

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-18-git-send-email-aneesh@ti.com> you wrote:
> Identify SDRAM devices connected to EMIF automatically:
> LPDDR2 devices have some Mode Registers that provide details
> about the device such as the type, density, bus width
> etc. EMIF has the capability to read these registers. If there
> are not devices connected to a given chip-select reading mode
> registers will return junk values. After reading as many such
> registers as possible and matching with expected ranges of
> values the driver can identify if there is a device connected
> to the respective CS. If we identify that a device is connected
> the values read give us complete details about the device.
> 
> This along with the base AC timings specified by JESD209-2
> allows us to do a complete automatic initialization of
> SDRAM that works on all boards.
> 
> Please note that the default AC timings specified by JESD209-2
> will be safe for all devices but not necessarily optimal. However,
> for the Elpida devices used on Panda and SDP the default timings
> are both safe and optimal.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  arch/arm/cpu/armv7/omap4/emif.c         |  177 +++++++++++++++++++++++++++++-
>  arch/arm/cpu/armv7/omap4/sdram_elpida.c |    9 +-
>  include/configs/omap4_sdp4430.h         |    1 +
>  3 files changed, 176 insertions(+), 11 deletions(-)

How much of this is OMAP4 specific, and how much can be reused onother
SoCs as well?

Best regards,

Wolfgang Denk

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DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is easier to write an incorrect program than understand a  correct
one.

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-19-git-send-email-aneesh@ti.com> you wrote:
> Embed the u-boot flash image size at a known offset from the
> start of u-boot so that SPL can use it while loading u-boot
> from a non-XIP media.

I don't think this is a good idea.

What you are doing here is defining an image format. Such an image
format must be good enough not only for OMAP4 and for loading U-Boot
as second stage, but for all other architectures and use cases as
well.

We therefore should be very careful not to oversimplify things here.
I suggest NOT to pot this information into the image itself, but
rather to prepend it (for example, using the mkimage tool), so the
actual payload image needs not to be modified.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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[U-Boot] [PATCH v2 20/22] omap: spl: add FAT support over MMC

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-21-git-send-email-aneesh@ti.com> you wrote:
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
>  * Changes for make file changes
> ---
>  include/configs/omap4_sdp4430.h |    1 +
>  spl/board/ti/omap4.mk           |    7 +++++++
>  spl/board/ti/spl-omap.c         |   22 ++++++++++++++++++++++
>  3 files changed, 30 insertions(+), 0 deletions(-)
...
> +	err = file_fat_read("u-boot.bin", (u8 *)CONFIG_SYS_TEXT_BASE, 0);

Please do not hard code the file name here.   Keep the code flexible
and allow for other possibilities, too.  At the very least, make this
compile-time selectable.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A quarrel is quickly settled when deserted by one party; there is  no
battle unless there be two.                                  - Seneca

[U-Boot] [PATCH v2 21/22] omap4: add spl support for OMAP4 Panda

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-22-git-send-email-aneesh@ti.com> you wrote:
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V2:
>  * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 for Panda
>    This is required for EMU devices
>  * Changes due to make file changes
> ---
>  arch/arm/cpu/armv7/omap4/emif.c        |    5 +++--
>  arch/arm/include/asm/arch-omap4/emif.h |   10 +++++-----
>  include/configs/omap4_panda.h          |   24 ++++++++++++++++++++++++
>  spl/board/ti/panda/Makefile            |   32 ++++++++++++++++++++++++++++++++
>  4 files changed, 64 insertions(+), 7 deletions(-)
>  create mode 100644 spl/board/ti/panda/Makefile
> 
> diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
> index b09aa8f..699a545 100644
> --- a/arch/arm/cpu/armv7/omap4/emif.c
> +++ b/arch/arm/cpu/armv7/omap4/emif.c
> @@ -1178,9 +1178,9 @@ static void dmm_init(u32 base)
>  #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
>  	emif_get_dmm_regs(&lisa_map_regs);
>  #else
> -	u32 emif1_size, emif2_size, mapped_size, section_map;
> +	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
>  	u32 section_cnt, sys_addr;
> -	struct dmm_lisa_map_regs lis_map_regs_calculated;
> +	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};

This iseems to be an unrelated change.  Please split into separate
patch.

>  	mapped_size = 0;
>  	section_cnt = 3;
> @@ -1253,6 +1253,7 @@ static void dmm_init(u32 base)
>  		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
>  		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
>  	}
> +

Ditto.

>  	/* TRAP for invalid TILER mappings in section 0 */
>  	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
>  
> diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
> index 8cc3230..b95e545 100644
> --- a/arch/arm/include/asm/arch-omap4/emif.h
> +++ b/arch/arm/include/asm/arch-omap4/emif.h
> @@ -520,11 +520,11 @@
>  
>  /* Trap for invalid TILER PAT entries */
>  #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
> -		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
> -		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
> -		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
> -		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
> -		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
> +	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
> +	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
> +	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
> +	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
> +	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))

Ditto.

...
> +++ b/spl/board/ti/panda/Makefile
> @@ -0,0 +1,32 @@
...
> +include $(SRCTREE)/spl/board/$(VENDOR)/omap4.mk
> +include $(SRCTREE)/spl/board/$(VENDOR)/rules-omap.mk

NAK, see previous messages.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If a train station is a place where a train stops,
                                           then what's a workstation?

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Wolfgang Denk]

Dear Aneesh V,

In message <1305472900-4004-23-git-send-email-aneesh@ti.com> you wrote:
> In SPL console is enabled very early where as in U-Boot
> it's not. So, SPL can have traces in early init code

Console should _always_ be enabled as early as possible,

> while U-Boot can not have it in the same shared code.
> 
> Adding a debug print macro that will be defined in SPL
> but compiled out in U-Boot.

Can we not rather change the code so both configurations behave the
same?

> --- a/arch/arm/cpu/armv7/omap4/clocks.c
> +++ b/arch/arm/cpu/armv7/omap4/clocks.c
> @@ -379,7 +379,7 @@ u32 omap4_ddr_clk(void)
>  
>  	core_dpll_params = get_core_dpll_params();
>  
> -	debug("sys_clk %d\n ", sys_clk_khz * 1000);
> +	spl_debug("sys_clk %d\n ", sys_clk_khz * 1000);

Do we really need a new macro name?  Can this not be the same debug()
macro, just generating different code (if really needed) when building
the SPL code?

> @@ -1318,4 +1328,13 @@ void sdram_init(void)
>  
>  	/* for the shadow registers to take effect */
>  	freq_update_core();
> +
> +	/* Do some basic testing */
> +	writel(0xDEADBEEF, CONFIG_SYS_SDRAM_BASE);
> +	if (readl(CONFIG_SYS_SDRAM_BASE) == 0xDEADBEEF)
> +		spl_debug("SDRAM Init success!\n");
> +	else
> +		printf("SDRAM Init failed!!\n");
> +
> +	spl_debug("<<sdram_init()\n");

This is beyond the scope of "adding debug traces".  it must be split
into separate patch.

Also, please do not mess witrhout need with the RAM content - at the
very least, restore the previous values.

But then - I wonder why this is needed@all. Are you not using
get_ram_size()?  Maybe you should fix your code to using it!

> diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h
> index d581539..3e847c1 100644
> --- a/arch/arm/include/asm/utils.h
> +++ b/arch/arm/include/asm/utils.h
> @@ -25,6 +25,12 @@
>  #ifndef	_UTILS_H_
>  #define	_UTILS_H_
>  
> +#if defined(DEBUG) && defined(CONFIG_PRELOADER)
> +#define spl_debug(fmt, args...)	printf(fmt, ##args)
> +#else
> +#define spl_debug(fmt, args...)
> +#endif

NAK.  This is neither the right place for such a definition, nor do I
want to see this addressed like that.

I recommend to unify the code, so both SPL and non-SPL configurations
can use teh same early console behaviour.

>  void board_init_f(ulong dummy)
>  {
> +	debug(">>board_init_f()\n");
>  	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
> +	debug("<<board_init_f()\n");

This is overkill, isn't it?

> @@ -166,6 +172,7 @@ void board_init_r(gd_t *id, ulong dummy)
>  	switch (boot_device) {
>  	case BOOT_DEVICE_MMC1:
>  	case BOOT_DEVICE_MMC2:
> +		spl_debug("boot device - MMC2\n");
>  		mmc_load_uboot(boot_device - BOOT_DEVICE_MMC1);

This is wrong in the BOOT_DEVICE_MMC1 case.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Marriage is like a cage; one sees the birds outside desperate to get
in, and those inside desperate to get out."               - Montaigne

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Måns Rullgård]

Wolfgang Denk <wd@denx.de> writes:

> Dear Aneesh V,
>
> In message <1305472900-4004-17-git-send-email-aneesh@ti.com> you wrote:
>> Calculate EMIF register values based on AC timing parameters
>> from the SDRAM datasheet and the DDR frequency rather than
>> using the hard-coded values.
>> 
>> For a new board the user doen't have to go through the tedious
>> process of calculating the register values. Instead, just
>> provide the AC timings from the device data sheet as input
>> and the driver will automatically calculate the register values.
>
> Does it make sense to do this in the driver code?  These parameters
> will never change, so why can we not rather perform the computation
> only once, at build time, and feed in the respective parameters to the
> driver?

I agree, there should be no reason for doing this at runtime.  I would
think it possible to do with some C macros.

-- 
M?ns Rullg?rd
mans at mansr.com

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Mike Frysinger]

On Sunday, May 15, 2011 11:21:19 Aneesh V wrote:
> +static void omapimage_print_header(const void *ptr)
> +{
> +	struct ch_toc *toc = (struct ch_toc *)ptr;

you're casting away the void.  something is fundamentally broken here.
-mike
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[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Mike Frysinger]

On Sunday, May 15, 2011 21:52:53 Mike Frysinger wrote:
> On Sunday, May 15, 2011 11:21:19 Aneesh V wrote:
> > +static void omapimage_print_header(const void *ptr)
> > +{
> > +	struct ch_toc *toc = (struct ch_toc *)ptr;
> 
> you're casting away the void.  something is fundamentally broken here.

err, obviously i meant "const" instead of "void" ...
-mike
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[U-Boot] [PATCH v2 08/22] omap: add spl support

[Simon Schwarz]

Hi Aneesh,

I recently started to work on a similar topic:  omap3 (devkit8000) nand_spl
support. So I'am really interested in your OMAP4/common work here ;)

In this patch comment you say its common for OMAP3/4 but in
preloader_console_init() is a call to omap4_rev_string()):
> printf("Texas Instruments %s\n", omap4_rev_string());

Regards
Simon

2011/5/15 Aneesh V <aneesh@ti.com>

> Add the basic spl framework and linker script common for OMAP3/4
> platforms.
>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  spl/board/ti/spl-omap.c   |   47 ++++++++++++++++++++++++++++++++++
>  spl/board/ti/spl-omap.lds |   62
> +++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 109 insertions(+), 0 deletions(-)
>  create mode 100644 spl/board/ti/spl-omap.c
>  create mode 100644 spl/board/ti/spl-omap.lds
>
> diff --git a/spl/board/ti/spl-omap.c b/spl/board/ti/spl-omap.c
> new file mode 100644
> index 0000000..0e08f4f
> --- /dev/null
> +++ b/spl/board/ti/spl-omap.c
> @@ -0,0 +1,47 @@
> +/*
> + *
> + * Clock initialization for OMAP4
> + *
> + * (C) Copyright 2010
> + * Texas Instruments, <www.ti.com>
> + *
> + * Aneesh V <aneesh@ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/u-boot.h>
> +#include <asm/arch/sys_proto.h>
> +#include <timestamp_autogenerated.h>
> +
> +/* Define global data structure pointer to it*/
> +gd_t gdata __attribute__ ((section(".data")));
> +bd_t bdata __attribute__ ((section(".data")));
> +gd_t *gd = &gdata;
> +
> +void board_init_f(ulong dummy)
> +{
> +       relocate_code(CONFIG_SYS_SPL_STACK, &gdata,
> CONFIG_SYS_SPL_TEXT_BASE);
> +}
> +
> +void board_init_r(gd_t *id, ulong dummy)
> +{
> +       for (;;)
> +               ;
> +}
> diff --git a/spl/board/ti/spl-omap.lds b/spl/board/ti/spl-omap.lds
> new file mode 100644
> index 0000000..674ef05
> --- /dev/null
> +++ b/spl/board/ti/spl-omap.lds
> @@ -0,0 +1,62 @@
> +/*
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> + *
> + * (C) Copyright 2010
> + * Texas Instruments, <www.ti.com>
> + *     Aneesh V <aneesh@ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
> +                LENGTH = CONFIG_SYS_SPL_MAX_SIZE }
> +MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \
> +                 LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE }
> +
> +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> +OUTPUT_ARCH(arm)
> +ENTRY(_start)
> +SECTIONS
> +{
> +       .text      :
> +       {
> +       __start = .;
> +         start.o       (.text)
> +         *(.text*)
> +       } >.sram
> +
> +       . = ALIGN(4);
> +       .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
> +
> +       . = ALIGN(4);
> +       .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
> +       . = ALIGN(4);
> +       __image_copy_end = .;
> +       _end = .;
> +
> +       .bss :
> +       {
> +               . = ALIGN(4);
> +               __bss_start = .;
> +               *(.bss*)
> +               . = ALIGN(4);
> +               __bss_end__ = .;
> +       } >.sdram
> +}
> --
> 1.7.0.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 12:36 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-2-git-send-email-aneesh@ti.com>  you wrote:
>> From: John Rigby<john.rigby@linaro.org>
>>
>> Signed-off-by: John Rigby<john.rigby@linaro.org>
>> ---
>>   common/image.c    |    1 +
>>   include/image.h   |    1 +
>>   tools/Makefile    |    2 +
>>   tools/mkimage.c   |    2 +
>>   tools/mkimage.h   |    1 +
>>   tools/omapimage.c |  229 +++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   tools/omapimage.h |   50 ++++++++++++
>>   7 files changed, 286 insertions(+), 0 deletions(-)
>>   create mode 100644 tools/omapimage.c
>>   create mode 100644 tools/omapimage.h
>>
>> diff --git a/common/image.c b/common/image.c
>> index e542a57..7f6fe1c 100644
>> --- a/common/image.c
>> +++ b/common/image.c
>> @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
>>   	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
>>   	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
>>   	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
>> +	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
>>   	{	-1,		    "",		  "",			},
>
> Please keep list sorted / sort list.

Sort by the second field(kwbimage, omapimage etc), right?

>
>> diff --git a/tools/Makefile b/tools/Makefile
>> index 623f908..a1c4ed7 100644
>> --- a/tools/Makefile
>> +++ b/tools/Makefile
>> @@ -84,6 +84,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
>>   OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
>>   NOPED_OBJ_FILES-y += kwbimage.o
>>   NOPED_OBJ_FILES-y += imximage.o
>> +NOPED_OBJ_FILES-y += omapimage.o
>>   NOPED_OBJ_FILES-y += mkimage.o
>>   OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
>>   NOPED_OBJ_FILES-y += os_support.o
>> @@ -180,6 +181,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
>>   			$(obj)fit_image.o \
>>   			$(obj)image.o \
>>   			$(obj)imximage.o \
>> +			$(obj)omapimage.o \
>>   			$(obj)kwbimage.o \
>>   			$(obj)md5.o \
>>   			$(obj)mkimage.o \
>
> Please keep lists sorted.

Ok.

>
>> --- /dev/null
>> +++ b/tools/omapimage.c
>> @@ -0,0 +1,229 @@
...

>> +struct ch_toc {
>> +	uint32_t section_offset;
>> +	uint32_t section_size;
>> +	uint8_t unused[12];
>> +	uint8_t section_name[12];
>> +} __attribute__ ((__packed__));
>> +
>> +struct ch_settings {
>> +	uint32_t section_key;
>> +	uint8_t valid;
>> +	uint8_t version;
>> +	uint16_t reserved;
>> +	uint32_t flags;
>> +} __attribute__ ((__packed__));
>> +
>> +struct gp_header {
>> +	uint32_t size;
>> +	uint32_t load_addr;
>> +} __attribute__ ((__packed__));
>
> Is there any good reason to have these "__attribute__ ((__packed__))"
> here?  In general, these are only known to cause trouble and pain, and
> I cannot see a need here.

ROM code expects the header in a precise format. I think it will not be
safe to leave it to the compiler to decide the field layout. For
instance, the compiler may align the uint8_t or uint16_t to 32 bit
boundary and that will break the Configuration Header.

Just curious, what are the issues caused by "__packed__"?

>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Mike,

On Monday 16 May 2011 08:25 AM, Mike Frysinger wrote:
> On Sunday, May 15, 2011 21:52:53 Mike Frysinger wrote:
>> On Sunday, May 15, 2011 11:21:19 Aneesh V wrote:
>>> +static void omapimage_print_header(const void *ptr)
>>> +{
>>> +	struct ch_toc *toc = (struct ch_toc *)ptr;
>>
>> you're casting away the void.  something is fundamentally broken here.
>
> err, obviously i meant "const" instead of "void" ...
> -mike

This is not my code. But I don't think it was intentional. The
following didn't seem to cause any trouble. I shall add this fix in the
next revision if this looks ok.

  static void omapimage_print_header(const void *ptr)
  {
-	struct ch_toc *toc = (struct ch_toc *)ptr;
+	const struct ch_toc *toc =  (const struct ch_toc *)ptr;

>
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD0F98A.2040302@ti.com> you wrote:
> 
> >> @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
> >>   	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
> >>   	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
> >>   	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
> >> +	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
> >>   	{	-1,		    "",		  "",			},
> >
> > Please keep list sorted / sort list.
> 
> Sort by the second field(kwbimage, omapimage etc), right?

First field, but the result is the same.

> >> +struct ch_toc {
> >> +	uint32_t section_offset;
> >> +	uint32_t section_size;
> >> +	uint8_t unused[12];
> >> +	uint8_t section_name[12];
> >> +} __attribute__ ((__packed__));
> >> +
> >> +struct ch_settings {
> >> +	uint32_t section_key;
> >> +	uint8_t valid;
> >> +	uint8_t version;
> >> +	uint16_t reserved;
> >> +	uint32_t flags;
> >> +} __attribute__ ((__packed__));
> >> +
> >> +struct gp_header {
> >> +	uint32_t size;
> >> +	uint32_t load_addr;
> >> +} __attribute__ ((__packed__));
> >
> > Is there any good reason to have these "__attribute__ ((__packed__))"
> > here?  In general, these are only known to cause trouble and pain, and
> > I cannot see a need here.
> 
> ROM code expects the header in a precise format. I think it will not be
> safe to leave it to the compiler to decide the field layout. For
> instance, the compiler may align the uint8_t or uint16_t to 32 bit
> boundary and that will break the Configuration Header.

No. Not in the structs listed above.


> Just curious, what are the issues caused by "__packed__"?

For example, 32 bit data may be accessed in 4 8-bit operations which
may be fatal when accessing device registers.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
God may be subtle, but He isn't plain mean.         - Albert Einstein

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 12:39 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-3-git-send-email-aneesh@ti.com>  you wrote:
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>> V2:
>> * Added a revision string in addition to the revision number
>>    Helps in printing out the OMAP revision at bootup
> ...
>> +const char *omap4_rev_string(void)
>> +{
>> +	const char *omap4_rev = NULL;
>> +	switch (omap4_revision()) {
>> +	case OMAP4430_ES1_0:
>> +		omap4_rev = "OMAP4430 ES1.0";
>> +		break;
>> +	case OMAP4430_ES2_0:
>> +		omap4_rev = "OMAP4430 ES2.0";
>> +		break;
>> +	case OMAP4430_ES2_1:
>> +		omap4_rev = "OMAP4430 ES2.1";
>> +		break;
>> +	case OMAP4430_ES2_2:
>> +		omap4_rev = "OMAP4430 ES2.2";
>> +		break;
>
> Such code does not really scale well.  Can this not be improved?  I
> think we just had similar discussions for i.MX5x - please check what
> the result of these was.

Are you referring to this one?
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/98522

If so, it may not work for us:

1. Please note that the above function is just for getting the string
not for the revision itself. To get the revision we have
omap4_revision().

2. In our case we do not have a 1:1 mapping between the
revisions(monotonically increasing numbers) we need in the U-Boot and
the value obtained from the ID_CODE register. So, a translation is
inevitable.

3. We need increasing numbers for subsequent revisions so that we can
have something like:

if (omap4_revision() >= OMAP4430_ES2_0)
	do_something();
>
>> +	default:
>> +		omap4_rev = "OMAP4 - Unknown Rev";
>> +		break;
>
> Please also output what the unknown revision was - this saves at least
> one debug round if you ever run into this case.

This function should be in sync with omap4_revision() function(unless
there is a bug). So, the rev will be OMAP4430_SILICON_ID_INVALID in
that case.

I shall print out the ARM revision and OMAP revision registers when I
get into OMAP4430_SILICON_ID_INVALID situation in omap4_revision()

>
>> +}
>> diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
>> index a30bb33..1f88732 100644
>> --- a/arch/arm/include/asm/arch-omap4/omap4.h
>> +++ b/arch/arm/include/asm/arch-omap4/omap4.h
>> @@ -51,6 +51,11 @@
>>   #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
>>   #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
>>
>> +/* CONTROL_ID_CODE */
>> +#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
>
> C struct?

Ok. I shall convert defines to C structs globally for register
addressing.

>
>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 12:44 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-5-git-send-email-aneesh@ti.com>  you wrote:
>> Save boot device information passed by OMAP4 rom code
>>
>> ROM code in OMAP4 passes information such as the media from
>> which it picked up the first boot image(SPL in our case),
>> the mode(raw mode/FAT mode) etc.
>>
>> Save this information in SPL so that we can use the same media
>> and mode to bootload u-boot.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
> ...
>> +	/* Store the boot device in omap4_boot_device */
>> +	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1<- value of boot device
>> +	and	r2, #BOOT_DEVICE_MASK
>> +	ldr	r3, =omap4_boot_device
>> +	str     r2, [r3]			@ omap4_boot_device<- r1
>
> Why don't you use stadard global data here?

SPL has access to .data right from the beginning. Besides this is too
early. global data is not initialized yet.

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:18 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-7-git-send-email-aneesh@ti.com>  you wrote:
>> Define a new type of SPL that is not tied to any particular media.
>> - Create a top level directory 'spl' that has a structure similar
>>    to the existing 'nand_spl'
>> - Make necessary changes to top-level Makefile to build such an spl
>>
>> Rationale for this approach:
>> - There may be SPLs(like the OMAP x-loader) that support booting from
>>    multiple media.
>> - Also, there is no harm in keeping SPLs specific to a particular media
>>    also under this directory. In fact it makes sense to merge all the
>>    different spl directories into this one.
>
> Thanks a lot for addressing this. This is an area that has long been
> on my mind, and I'm really happy to see someone starting to work on
> this.

>
> In addition to booting from different types of media, I see at least
> two more topics that scould and should addressed by this work:
>
> - Get rid of xloader. I cannot see any good reasons why we need it,
>    i. e. which functions if performs that cannot be as well (and
>    eventually even more efficiently) be performed in the U-Boot SPL
>    code.

Indeed, SPL is seen as a replacement for x-loader.

>
> - Become more flexible regarding the kind of second stage payload.
>    It is definitely very powerful and convenient during development to
>    be able to load U-Boot with all it's capabilities as payload of the
>    SPL, but then, except for image size and parameter passing, there is
>    little or no difference to loading a Linux kernel directly instead
>    (and actually this is what most of the super-fast booting approaches
>    do).  If done right, we may even have the flexibility to do both,
>    just by providing different images as payload.
>

How do we handle the differences you just mentioned, namely the size,
parameter passing etc. Maybe, we should have special handling for each
and define config flags like CONFIG_SPL_PAYLOAD_UBOOT,
CONFIG_SPL_PAYLOAD_LINUX_KERNEL etc?

>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>> This patch generates 1 checkpatch warning due to declaration
>> of DECLARE_GLOBAL_DATA_PTR. This is un-avoidable
>> ---
>>   Makefile                           |   24 ++++++++++++++++++++++++
>>   arch/arm/include/asm/global_data.h |    5 +++++
>>   2 files changed, 29 insertions(+), 0 deletions(-)
>
> Here the commit message and the implementation do not agree.  You
> wrote "Create a top level directory 'spl'" - but I don't see any of
> that here?

In this patch, I just created the makefile infrastructure that expects
this directory structure. The files are created later in an OMAP
specific patch.

I think I should have used something like "define a directory
structure" instead of "create".

>
> I think this should be split into a separate patch series, and care
> should be taken that commit messages and implementaiton match.

Ok.

>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:22 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-9-git-send-email-aneesh@ti.com>  you wrote:
>> Add the basic spl framework and linker script common for OMAP3/4
>> platforms.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>>   spl/board/ti/spl-omap.c   |   47 ++++++++++++++++++++++++++++++++++
>>   spl/board/ti/spl-omap.lds |   62 +++++++++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 109 insertions(+), 0 deletions(-)
>>   create mode 100644 spl/board/ti/spl-omap.c
>>   create mode 100644 spl/board/ti/spl-omap.lds
>
> Again, this appears to be not the right order.
>
> I think, in the first step of this series, we should move the existing
> code from nand_spl and onenand_ipl into something like spl/nand and
> spl/onenand, respectivly, and make sure all teh existing systems still
> build.  The we can add more such support.

IMHO, we should just have spl/board/<vendor>/<board>/ .

Let spl/board/<vendor>/<board>/Makefile decide what it wants to
build.

I mean something like this(similar changes for ONENAND):

+.PHONEY : SPL
+SPL	:$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
+	$(MAKE) -C spl/board/$(BOARDDIR) all
+
+ifeq ($(CONFIG_SPL),y)
+ALL += SPL
+endif
+
  __OBJS := $(subst $(obj),,$(OBJS))
  __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))

@@ -401,11 +409,8 @@ $(LDSCRIPT):	depend
  $(obj)u-boot.lds: $(LDSCRIPT)
  		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@

-nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
-		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
-
-$(obj)u-boot-nand.bin:	nand_spl $(obj)u-boot.bin
-		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > 
$(obj)u-boot-nand.bin
+$(obj)u-boot-nand.bin:	SPL $(obj)u-boot.bin
+		cat $(obj)spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin


>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:23 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-9-git-send-email-aneesh@ti.com>  you wrote:
>> Add the basic spl framework and linker script common for OMAP3/4
>> platforms.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
> ...
>> +void board_init_r(gd_t *id, ulong dummy)
>> +{
>> +	for (;;)
>> +		;
>> +}
>
> Also, this cannot be right.

I added the features one by one in the subsequent patches and removed
that loop. Maybe I should squash some patches here too.

>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Simon,

On Monday 16 May 2011 03:18 PM, Simon Schwarz wrote:
> Hi Aneesh,
>
> I recently started to work on a similar topic:  omap3 (devkit8000)
> nand_spl support. So I'am really interested in your OMAP4/common work
> here ;)
>
> In this patch comment you say its common for OMAP3/4 but in
> preloader_console_init() is a call to omap4_rev_string()):
>  > printf("Texas Instruments %s\n", omap4_rev_string());

Thank you for pointing it out. I will change it to omap_rev_string()

best regards,
Aneesh

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi wolfgang,

On Monday 16 May 2011 12:03 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-10-git-send-email-aneesh@ti.com>  you wrote:
>> Adapted from: nand_spl/board/samsung/smdk6400/Makefile
>>
>> - Add the SPL makefile for OMAP4430 SDP
>> - Add the necessary CONFIG flags in the board config file
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>> V2:
>>   * Changed CONFIG_SYS_SPL_TEXT_BASE to 0x40304350 from
>>     0x40304360. This exact address is needed for EMU
>>     devices.
>>   * Removed un-necessary compiler options from CFLAGS and AFLAGS.
>>     These are already set by .mk files in U-Boot
>>   * Reorganize the make files to re-use common rules between
>>     boards
>> ---
>>   board/ti/sdp4430/config.mk                         |    3 +-
>>   include/configs/omap4_sdp4430.h                    |   19 +++++
>>   spl/board/ti/omap4.mk                              |   77 ++++++++++++++++++++
>>   spl/board/ti/rules-omap.mk                         |   74 +++++++++++++++++++
>>   .../config.mk =>  spl/board/ti/sdp4430/Makefile     |   21 +++---
>>   5 files changed, 183 insertions(+), 11 deletions(-)
>>   create mode 100644 spl/board/ti/omap4.mk
>>   create mode 100644 spl/board/ti/rules-omap.mk
>
> We do you introduce these files?  Please omit them, and use a plain
> Makefile instead.

I introduced them because 'spl/board/ti/sdp4430/Makefile' and 'spl/board
/ti/panda/Makefile' were exactly same and wanted to re-use the make
rules.

I indeed wanted to abstract it out even further in future so that the
make rules can be shared between OMAP3 and OMAP4 too. This way the
changes needed to support a new board will be lesser and maintenance
will be easier while adding new features.

For instance, if I have to add NAND support today I just need to update
omap4.mk instead of updating the Makefile of both panda and SDP.

This re-use will be evident when you see a later patch that
replicates the same Makefile for panda.

>
>> diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
>> index 33901a7..c62965d 100644
>> --- a/board/ti/sdp4430/config.mk
>> +++ b/board/ti/sdp4430/config.mk
>> @@ -28,4 +28,5 @@
>>   # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
>>   # (mem base + reserved)
>>
>> -CONFIG_SYS_TEXT_BASE = 0x80e80000
>> +# 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
>> +CONFIG_SYS_TEXT_BASE = 0x80100000
>
> NAK.  Please define in board config header, and get rid of the
> config.mk file.

ok.

best regards,
Aneesh

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD11511.1060208@ti.com> you wrote:
>
> >> +	const char *omap4_rev = NULL;
> >> +	switch (omap4_revision()) {
> >> +	case OMAP4430_ES1_0:
> >> +		omap4_rev = "OMAP4430 ES1.0";
> >> +		break;
> >> +	case OMAP4430_ES2_0:
> >> +		omap4_rev = "OMAP4430 ES2.0";
> >> +		break;
> >> +	case OMAP4430_ES2_1:
> >> +		omap4_rev = "OMAP4430 ES2.1";
> >> +		break;
> >> +	case OMAP4430_ES2_2:
> >> +		omap4_rev = "OMAP4430 ES2.2";
> >> +		break;
> >
> > Such code does not really scale well.  Can this not be improved?  I
> > think we just had similar discussions for i.MX5x - please check what
> > the result of these was.
> 
> Are you referring to this one?
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/98522
> 
> If so, it may not work for us:
> 
> 1. Please note that the above function is just for getting the string
> not for the revision itself. To get the revision we have
> omap4_revision().

Well, when you already have such a funxction, then why cannot it be
made to return useful values that are well-suited for formatting?

Instead of 

	#define OMAP4430_ES1_0 1
	#define OMAP4430_ES2_0 2
	#define OMAP4430_ES2_1 3
	#define OMAP4430_ES2_2 4

you could use

	#define OMAP4430_ES1_0 10
	#define OMAP4430_ES2_0 20
	#define OMAP4430_ES2_1 21
	#define OMAP4430_ES2_2 22

And then use a plain

	sprintf(omap4_rev, "OMAP4430 ES%d.%d", rev/10, rev%10);

or similar.

> 2. In our case we do not have a 1:1 mapping between the
> revisions(monotonically increasing numbers) we need in the U-Boot and
> the value obtained from the ID_CODE register. So, a translation is
> inevitable.

This is not needed. See above.  Any form of table driven approach
would be suitable, too.

> 3. We need increasing numbers for subsequent revisions so that we can
> have something like:

Should be no problem, see above.  Just define your number scheme.
Instead of decimal packing you could also adapt something like the
major/minor numbers for devices, and use the existing macros to
extract the parts.

There are tons of existing solutions for this type of problem, just
pick one that fits.

> >> +	default:
> >> +		omap4_rev = "OMAP4 - Unknown Rev";
> >> +		break;
> >
> > Please also output what the unknown revision was - this saves at least
> > one debug round if you ever run into this case.
> 
> This function should be in sync with omap4_revision() function(unless
> there is a bug). So, the rev will be OMAP4430_SILICON_ID_INVALID in
> that case.

In this case omap4_revision() should print the value it is reading.
Whenever you are reading "unexpected? numbers the first thing you will
do during debugging is to check _what_ exactly you are reawding - so
you can help and safe one step by just printing thei information which
you have ready in your hands.

> I shall print out the ARM revision and OMAP revision registers when I
> get into OMAP4430_SILICON_ID_INVALID situation in omap4_revision()

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"We have the right to survive!"
"Not be killing others."
	-- Deela and Kirk, "Wink of An Eye", stardate 5710.5

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD1189D.4050603@ti.com> you wrote:
> 
> >> Save this information in SPL so that we can use the same media
> >> and mode to bootload u-boot.
> >>
> >> Signed-off-by: Aneesh V<aneesh@ti.com>
> > ...
> >> +	/* Store the boot device in omap4_boot_device */
> >> +	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1<- value of boot device
> >> +	and	r2, #BOOT_DEVICE_MASK
> >> +	ldr	r3, =omap4_boot_device
> >> +	str     r2, [r3]			@ omap4_boot_device<- r1
> >
> > Why don't you use stadard global data here?
> 
> SPL has access to .data right from the beginning. Besides this is too
> early. global data is not initialized yet.

Please keep in mind that this is a special situation then. The code
will not work as intended for example when running form NOR flash.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Good manners are the settled  medium  of  social,  as  specie  is  of
commercial, life; returns are equally expected for both.
           - Lord Chesterfield _Letters to his Son_, 25 December 1753

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD11D1F.8020006@ti.com> you wrote:
> 
> > - Get rid of xloader. I cannot see any good reasons why we need it,
> >    i. e. which functions if performs that cannot be as well (and
> >    eventually even more efficiently) be performed in the U-Boot SPL
> >    code.
> 
> Indeed, SPL is seen as a replacement for x-loader.

Excellent.

> How do we handle the differences you just mentioned, namely the size,
> parameter passing etc. Maybe, we should have special handling for each
> and define config flags like CONFIG_SPL_PAYLOAD_UBOOT,
> CONFIG_SPL_PAYLOAD_LINUX_KERNEL etc?

None of this.  Ideally, the code should not even see such a difference.
U-Boot does not need any special arguments for booting, so we calways
pass Linux-compatible args.  And things like image size should be read
from the image itself, or form other available meta information (like
file size when reading from a FAT file system, etc.).

> >>   Makefile                           |   24 ++++++++++++++++++++++++
> >>   arch/arm/include/asm/global_data.h |    5 +++++
> >>   2 files changed, 29 insertions(+), 0 deletions(-)
> >
> > Here the commit message and the implementation do not agree.  You
> > wrote "Create a top level directory 'spl'" - but I don't see any of
> > that here?
> 
> In this patch, I just created the makefile infrastructure that expects
> this directory structure. The files are created later in an OMAP
> specific patch.

Such a definition should include the rename / moving of the other,
already existing code.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Computers are not intelligent. They only think they are.

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD13056.3000509@ti.com> you wrote:
> 
> > Again, this appears to be not the right order.
> >
> > I think, in the first step of this series, we should move the existing
> > code from nand_spl and onenand_ipl into something like spl/nand and
> > spl/onenand, respectivly, and make sure all teh existing systems still
> > build.  The we can add more such support.
> 
> IMHO, we should just have spl/board/<vendor>/<board>/ .
> 
> Let spl/board/<vendor>/<board>/Makefile decide what it wants to
> build.

There are common, board independent parts both in spl/nand and
spl/onenand.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
[Doctors and Bartenders], We both get the same two kinds of customers
-- the living and the dying.
	-- Dr. Boyce, "The Menagerie" ("The Cage"), stardate unknown

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD134DD.6040802@ti.com> you wrote:
> 
> >>   create mode 100644 spl/board/ti/omap4.mk
> >>   create mode 100644 spl/board/ti/rules-omap.mk
> >
> > We do you introduce these files?  Please omit them, and use a plain
> > Makefile instead.
> 
> I introduced them because 'spl/board/ti/sdp4430/Makefile' and 'spl/board
> /ti/panda/Makefile' were exactly same and wanted to re-use the make
> rules.

But in the result, the Makefiles are still the same, aren't they?

> I indeed wanted to abstract it out even further in future so that the
> make rules can be shared between OMAP3 and OMAP4 too. This way the
> changes needed to support a new board will be lesser and maintenance
> will be easier while adding new features.
> 
> For instance, if I have to add NAND support today I just need to update
> omap4.mk instead of updating the Makefile of both panda and SDP.
> 
> This re-use will be evident when you see a later patch that
> replicates the same Makefile for panda.

Can you please rather try and move this to a common directory level,
then?

I have a bad feeling about this.  If the Makefiles are the same, then
the code is probably more or less the same, also.  Eventually larger
parts of the code should be moved to a common directory, too?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A man either lives life as it happens to him, meets  it  head-on  and
licks it, or he turns his back on it and starts to wither away.
	-- Dr. Boyce, "The Menagerie" ("The Cage"), stardate unknown

[U-Boot] [PATCH v2 10/22] omap4: utility function to identify the context of hw init

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD135D0.8070805@ti.com> you wrote:
> 
> >> +		return OMAP_INIT_CONTEXT_XIP_UBOOT;
> >
> > What exactly is OMAP_INIT_CONTEXT_XIP_UBOOT?
> >
> > Do you mean the situation when booting from NOR flash, before
> > relocation?
> 
> Yes, this is for the NOR case.

Then please call it like that.  XIP has a special emaning, that may or
may not be related to running from ROM.

> > Eventually the "loaded by" definition is not so good, as it does not
> > really cover the NOR boot case.
> 
> Please note that "loaded by" definition is not there for all the
> options. The definition is the 'context' in which the init code is
> executing.

So please get rid of the "LOADED_BY" names.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Today's robots are very primitive, capable of understanding  only  a
few  simple  instructions  such  as 'go left', 'go right', and 'build
car'."                                                  - John Sladek

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Scott Wood]

On Sun, 15 May 2011 20:51:24 +0530
Aneesh V <aneesh@ti.com> wrote:

> diff --git a/Makefile b/Makefile
> index 384a59e..d3f4bef 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -289,6 +289,22 @@ LDPPFLAGS += \
>  	$(shell $(LD) --version | \
>  	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
>  
> +ifeq ($(CONFIG_NAND_U_BOOT),y)
> +NAND_SPL = nand_spl
> +U_BOOT_NAND = $(obj)u-boot-nand.bin
> +endif
> +
> +ifeq ($(CONFIG_SPL),y)
> +.PHONEY : SPL
> +ALL += SPL
> +endif
> +
> +ifeq ($(CONFIG_ONENAND_U_BOOT),y)
> +ONENAND_IPL = onenand_ipl
> +U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
> +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
> +endif
> +
>  __OBJS := $(subst $(obj),,$(OBJS))
>  __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
>  
> @@ -402,8 +418,13 @@ $(obj)u-boot.lds: $(LDSCRIPT)
>  		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
>  
>  nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
> +
> +$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) depend

You are reverting part of e935a374dbe5c745fdde05b2b07ced0bbe70887f.  Merge
accident?

> @@ -1141,12 +1163,14 @@ clobber:	clean
>  	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
>  	@rm -f $(obj)u-boot.kwb
>  	@rm -f $(obj)u-boot.imx
> +	@rm -f $(obj)MLO

What is MLO?

> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
> index 2a84d27..2ce020e 100644
> --- a/arch/arm/include/asm/global_data.h
> +++ b/arch/arm/include/asm/global_data.h
> @@ -89,6 +89,11 @@ typedef	struct	global_data {
>  #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
>  #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
>  
> +#ifdef CONFIG_PRELOADER
> +/* SPL works from internal RAM. gd pointer can be in .data section */
> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
> +#else
>  #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
> +#endif

Is this appropriate for all ARM boards (e.g. those currently using
nand_spl)?

-Scott

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Scott Wood]

On Mon, 16 May 2011 19:40:30 +0530
Aneesh V <aneesh@ti.com> wrote:

> Hi Wolfgang,
> 
> On Monday 16 May 2011 01:22 AM, Wolfgang Denk wrote:
> > I think, in the first step of this series, we should move the existing
> > code from nand_spl and onenand_ipl into something like spl/nand and
> > spl/onenand, respectivly, and make sure all teh existing systems still
> > build.  The we can add more such support.
> 
> IMHO, we should just have spl/board/<vendor>/<board>/ .
> 
> Let spl/board/<vendor>/<board>/Makefile decide what it wants to
> build.

That's what we do in nand_spl/onenand_spl -- the common files are more like
libraries that the board makefile may or may not pull in (e.g. many
Freescale boards use nand_boot_fsl_elbc.c or nand_boot_fsl_nfc.c instead of
nand_boot.c).

Renaming nand_spl seems like it should be the first step.

> I mean something like this(similar changes for ONENAND):
> 
> +.PHONEY : SPL

.PHONY

-Scott

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Mike Frysinger]

On Monday, May 16, 2011 06:28:40 Aneesh V wrote:
> On Monday 16 May 2011 08:25 AM, Mike Frysinger wrote:
> > On Sunday, May 15, 2011 21:52:53 Mike Frysinger wrote:
> >> On Sunday, May 15, 2011 11:21:19 Aneesh V wrote:
> >>> +static void omapimage_print_header(const void *ptr)
> >>> +{
> >>> +	struct ch_toc *toc = (struct ch_toc *)ptr;
> >> 
> >> you're casting away the void.  something is fundamentally broken here.
> > 
> > err, obviously i meant "const" instead of "void" ...
> 
> This is not my code.

you're submitting the patch with only your s-o-b on it.  that means you're 
responsible for it all.

>   static void omapimage_print_header(const void *ptr)
>   {
> -	struct ch_toc *toc = (struct ch_toc *)ptr;
> +	const struct ch_toc *toc =  (const struct ch_toc *)ptr;

drop the cast entirely ... this isnt C++ after all:
	const struct ch_toc *toc =  ptr;
-mike
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[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Scott Wood]

On Sun, 15 May 2011 20:51:36 +0530
Aneesh V <aneesh@ti.com> wrote:

> Embed the u-boot flash image size at a known offset from the
> start of u-boot so that SPL can use it while loading u-boot
> from a non-XIP media.
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> V2:
> * Removed the linker script label '__flash_image_end' and its usage.
>   Instead '_end' is used now
> ---
>  arch/arm/cpu/armv7/start.S |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index f92c6d9..f676d7d 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -64,8 +64,12 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
>  
>  .global _end_vect
>  _end_vect:
> +.global	_u_boot_size
> +_u_boot_size:
> +	.word	0xDEADBEEF
> +	.word	_end - _start

0xdeadbeef does not seem like a good magic value to identify this header
format -- especially since it looks like that may have been the value
present in the older images that don't have this header (depending on
whether the .balignl needed to pad).

-Scott

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Mike,

On Tuesday 17 May 2011 12:12 AM, Mike Frysinger wrote:
> On Monday, May 16, 2011 06:28:40 Aneesh V wrote:
>> On Monday 16 May 2011 08:25 AM, Mike Frysinger wrote:
>>> On Sunday, May 15, 2011 21:52:53 Mike Frysinger wrote:
>>>> On Sunday, May 15, 2011 11:21:19 Aneesh V wrote:
>>>>> +static void omapimage_print_header(const void *ptr)
>>>>> +{
>>>>> +	struct ch_toc *toc = (struct ch_toc *)ptr;
>>>>
>>>> you're casting away the void.  something is fundamentally broken here.
>>>
>>> err, obviously i meant "const" instead of "void" ...
>>
>> This is not my code.
>
> you're submitting the patch with only your s-o-b on it.  that means you're
> responsible for it all.

No. both From and s-o-b are John's on this patch.

>
>>    static void omapimage_print_header(const void *ptr)
>>    {
>> -	struct ch_toc *toc = (struct ch_toc *)ptr;
>> +	const struct ch_toc *toc =  (const struct ch_toc *)ptr;
>
> drop the cast entirely ... this isnt C++ after all:
> 	const struct ch_toc *toc =  ptr;

ok.

best regards,
Aneesh

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 09:05 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
...
>>
>> 1. Please note that the above function is just for getting the string
>> not for the revision itself. To get the revision we have
>> omap4_revision().
>
> Well, when you already have such a funxction, then why cannot it be
> made to return useful values that are well-suited for formatting?
>
> Instead of
>
> 	#define OMAP4430_ES1_0 1
> 	#define OMAP4430_ES2_0 2
> 	#define OMAP4430_ES2_1 3
> 	#define OMAP4430_ES2_2 4
>
> you could use
>
> 	#define OMAP4430_ES1_0 10
> 	#define OMAP4430_ES2_0 20
> 	#define OMAP4430_ES2_1 21
> 	#define OMAP4430_ES2_2 22
>
> And then use a plain
>
> 	sprintf(omap4_rev, "OMAP4430 ES%d.%d", rev/10, rev%10);
>
> or similar.

This is a good idea. The only minor hitch is that OMAP4460 will come
into picture in near future, again having at least ES1_0. But I think
that can be worked out.

best regards,
Aneesh

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 09:07 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD1189D.4050603@ti.com>  you wrote:
>>
>>>> Save this information in SPL so that we can use the same media
>>>> and mode to bootload u-boot.
>>>>
>>>> Signed-off-by: Aneesh V<aneesh@ti.com>
>>> ...
>>>> +	/* Store the boot device in omap4_boot_device */
>>>> +	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1<- value of boot device
>>>> +	and	r2, #BOOT_DEVICE_MASK
>>>> +	ldr	r3, =omap4_boot_device
>>>> +	str     r2, [r3]			@ omap4_boot_device<- r1
>>>
>>> Why don't you use stadard global data here?
>>
>> SPL has access to .data right from the beginning. Besides this is too
>> early. global data is not initialized yet.
>
> Please keep in mind that this is a special situation then. The code
> will not work as intended for example when running form NOR flash.

Yes, I realize that. The values passed in the ARM registers need to be
saved before they are lost. At the moment only SPL needs them. We do
not have a board with NOR flash yet. If there is a need in the future
we may have to save it in some predefined special purpose memory such
as the scratchpad memory of OMAP or some location in the internal RAM
that is not used. But there is no such need at the moment.

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Scott,

On Tuesday 17 May 2011 12:02 AM, Scott Wood wrote:
> On Sun, 15 May 2011 20:51:24 +0530
> Aneesh V<aneesh@ti.com>  wrote:
>
>> diff --git a/Makefile b/Makefile
>> index 384a59e..d3f4bef 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -289,6 +289,22 @@ LDPPFLAGS += \
>>   	$(shell $(LD) --version | \
>>   	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
>>
>> +ifeq ($(CONFIG_NAND_U_BOOT),y)
>> +NAND_SPL = nand_spl
>> +U_BOOT_NAND = $(obj)u-boot-nand.bin
>> +endif
>> +
>> +ifeq ($(CONFIG_SPL),y)
>> +.PHONEY : SPL
>> +ALL += SPL
>> +endif
>> +
>> +ifeq ($(CONFIG_ONENAND_U_BOOT),y)
>> +ONENAND_IPL = onenand_ipl
>> +U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
>> +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
>> +endif
>> +
>>   __OBJS := $(subst $(obj),,$(OBJS))
>>   __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
>>
>> @@ -402,8 +418,13 @@ $(obj)u-boot.lds: $(LDSCRIPT)
>>   		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P -<$^>$@
>>
>>   nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
>> +
>> +$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
>
> You are reverting part of e935a374dbe5c745fdde05b2b07ced0bbe70887f.  Merge
> accident?
>

Oops! That indeed seems like a merge accident. I will correct it in the
next version.

>> @@ -1141,12 +1163,14 @@ clobber:	clean
>>   	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
>>   	@rm -f $(obj)u-boot.kwb
>>   	@rm -f $(obj)u-boot.imx
>> +	@rm -f $(obj)MLO
>
> What is MLO?

MLO is the name of SPL created for OMAP. ROM code expects a file with
this name as the first image when it boots from FAT.

>
>> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
>> index 2a84d27..2ce020e 100644
>> --- a/arch/arm/include/asm/global_data.h
>> +++ b/arch/arm/include/asm/global_data.h
>> @@ -89,6 +89,11 @@ typedef	struct	global_data {
>>   #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in&  out)		*/
>>   #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
>>
>> +#ifdef CONFIG_PRELOADER
>> +/* SPL works from internal RAM. gd pointer can be in .data section */
>> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
>> +#else
>>   #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
>> +#endif
>
> Is this appropriate for all ARM boards (e.g. those currently using
> nand_spl)?

None of the SPL's other than this one seems to be using global data
today. If anybody wants to use it this seems to be the logical option
for me because by definition SPL runs from some kind of RAM so global
data can be placed in the .data section of SPL.

best regards,
Aneesh

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 09:13 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD13056.3000509@ti.com>  you wrote:
>>
>>> Again, this appears to be not the right order.
>>>
>>> I think, in the first step of this series, we should move the existing
>>> code from nand_spl and onenand_ipl into something like spl/nand and
>>> spl/onenand, respectivly, and make sure all teh existing systems still
>>> build.  The we can add more such support.
>>
>> IMHO, we should just have spl/board/<vendor>/<board>/ .
>>
>> Let spl/board/<vendor>/<board>/Makefile decide what it wants to
>> build.
>
> There are common, board independent parts both in spl/nand and
> spl/onenand.
>

How about having them at the root level in 'spl/' ?

best regards,
Aneesh

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 09:18 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD134DD.6040802@ti.com>  you wrote:
>>
>>>>    create mode 100644 spl/board/ti/omap4.mk
>>>>    create mode 100644 spl/board/ti/rules-omap.mk
>>>
>>> We do you introduce these files?  Please omit them, and use a plain
>>> Makefile instead.
>>
>> I introduced them because 'spl/board/ti/sdp4430/Makefile' and 'spl/board
>> /ti/panda/Makefile' were exactly same and wanted to re-use the make
>> rules.
>
> But in the result, the Makefiles are still the same, aren't they?

Yes, but the contents are not duplicated in two files. Easier for
maintenance.

>
>> I indeed wanted to abstract it out even further in future so that the
>> make rules can be shared between OMAP3 and OMAP4 too. This way the
>> changes needed to support a new board will be lesser and maintenance
>> will be easier while adding new features.
>>
>> For instance, if I have to add NAND support today I just need to update
>> omap4.mk instead of updating the Makefile of both panda and SDP.
>>
>> This re-use will be evident when you see a later patch that
>> replicates the same Makefile for panda.
>
> Can you please rather try and move this to a common directory level,
> then?

The top-level make rule being the following, we will need a Makefile in
the board directory, right?

+SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
+    $(MAKE) -C spl/board/$(BOARDDIR) all

>
> I have a bad feeling about this.  If the Makefiles are the same, then
> the code is probably more or less the same, also.  Eventually larger
> parts of the code should be moved to a common directory, too?
>

In fact, code is already common. All OMAP code specific to SPL comes
from spl/board/ti/spl-omap.c . All OMAP code shared with OMAP U-Boot
comes from the respective directory within arch/arm/cpu/armv7/*

In the interest of simplicity I deferred all board specific
initialization of OMAP4(mainly mux) to U-Boot. So, SPL is board
independent today for OMAP4.

best regards,
Aneesh

[U-Boot] [PATCH v2 02/22] omap4: add OMAP4430 revision check

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD21843.4060000@ti.com> you wrote:
> 
> > you could use
> >
> > 	#define OMAP4430_ES1_0 10
> > 	#define OMAP4430_ES2_0 20
> > 	#define OMAP4430_ES2_1 21
> > 	#define OMAP4430_ES2_2 22
> >
> > And then use a plain
> >
> > 	sprintf(omap4_rev, "OMAP4430 ES%d.%d", rev/10, rev%10);
> >
> > or similar.
> 
> This is a good idea. The only minor hitch is that OMAP4460 will come
> into picture in near future, again having at least ES1_0. But I think
> that can be worked out.

Then go for something like

	#define OMAP4430_ES1_0 0x44300100
	#define OMAP4430_ES2_0 0x44300200
	#define OMAP4430_ES2_1 0x44300201
	#define OMAP4430_ES2_2 0x44300202

	sprintf(omap4_rev, "OMAP%x ES%x.%x",
		(rev >> 16) & 0xFFFF,
		(rev >> 8) & 0xFF,
		rev & 0xFF);

or so.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The optimum committee has no members.
                                                   - Norman Augustine

[U-Boot] [PATCH v2 04/22] omap4: save parameters passed by ROM code to SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD21961.7070408@ti.com> you wrote:
> 
> >> SPL has access to .data right from the beginning. Besides this is too
> >> early. global data is not initialized yet.
> >
> > Please keep in mind that this is a special situation then. The code
> > will not work as intended for example when running form NOR flash.
> 
> Yes, I realize that. The values passed in the ARM registers need to be
> saved before they are lost. At the moment only SPL needs them. We do
> not have a board with NOR flash yet. If there is a need in the future
> we may have to save it in some predefined special purpose memory such
> as the scratchpad memory of OMAP or some location in the internal RAM
> that is not used. But there is no such need at the moment.

OK. Maybe you can add a comment that explains this situation.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It may be that our role on this planet is not to worship God but  to
create him."                                       - Arthur C. Clarke

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD21BAA.6000601@ti.com> you wrote:
> 
> > What is MLO?
> 
> MLO is the name of SPL created for OMAP. ROM code expects a file with
> this name as the first image when it boots from FAT.

What does MLO mean?


> >> +#ifdef CONFIG_PRELOADER
> >> +/* SPL works from internal RAM. gd pointer can be in .data section */
> >> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
> >> +#else
> >>   #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
> >> +#endif
> >
> > Is this appropriate for all ARM boards (e.g. those currently using
> > nand_spl)?
> 
> None of the SPL's other than this one seems to be using global data
> today. If anybody wants to use it this seems to be the logical option
> for me because by definition SPL runs from some kind of RAM so global
> data can be placed in the .data section of SPL.

But that's not what you are doing.  You are not changing the storage
of the global data itself, you are changing the storage of the POINTER
TO the global data - and this makes no sense to me.  The pointer can
certainly remain in a register even if the data itself is somewhere
else.

This will save us this #ifdef here.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Witch!  Witch!  They'll burn ya!
	-- Hag, "Tomorrow is Yesterday", stardate unknown

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD21CD8.2080409@ti.com> you wrote:
> 
> > There are common, board independent parts both in spl/nand and
> > spl/onenand.
> 
> How about having them at the root level in 'spl/' ?

Why? It seems more logical to me to group nand and onenand related
files in their own subdirectories.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Quantum Mechanics is God's version of "Trust me."

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD21FB9.6070901@ti.com> you wrote:
> 
> The top-level make rule being the following, we will need a Makefile in
> the board directory, right?
> 
> +SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
> +    $(MAKE) -C spl/board/$(BOARDDIR) all

Maybe this needs to be tweaked to allow for boards that don;t require
board specific code.

> In fact, code is already common. All OMAP code specific to SPL comes
> from spl/board/ti/spl-omap.c . All OMAP code shared with OMAP U-Boot
> comes from the respective directory within arch/arm/cpu/armv7/*
> 
> In the interest of simplicity I deferred all board specific
> initialization of OMAP4(mainly mux) to U-Boot. So, SPL is board
> independent today for OMAP4.

Then we should adapt the directory and Makefile structure and allow
for such common code without need for separate spl/board/
directories.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A mouse is an elephant built by the Japanese.

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 05:18 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
...
>
>>>> +struct ch_toc {
>>>> +	uint32_t section_offset;
>>>> +	uint32_t section_size;
>>>> +	uint8_t unused[12];
>>>> +	uint8_t section_name[12];
>>>> +} __attribute__ ((__packed__));
>>>> +
>>>> +struct ch_settings {
>>>> +	uint32_t section_key;
>>>> +	uint8_t valid;
>>>> +	uint8_t version;
>>>> +	uint16_t reserved;
>>>> +	uint32_t flags;
>>>> +} __attribute__ ((__packed__));
>>>> +
>>>> +struct gp_header {
>>>> +	uint32_t size;
>>>> +	uint32_t load_addr;
>>>> +} __attribute__ ((__packed__));
>>>
>>> Is there any good reason to have these "__attribute__ ((__packed__))"
>>> here?  In general, these are only known to cause trouble and pain, and
>>> I cannot see a need here.
>>
>> ROM code expects the header in a precise format. I think it will not be
>> safe to leave it to the compiler to decide the field layout. For
>> instance, the compiler may align the uint8_t or uint16_t to 32 bit
>> boundary and that will break the Configuration Header.
>
> No. Not in the structs listed above.

You mean "__packed__" should be removed from "struct gp_header" alone,
not from the other structs?

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Aneesh,

On Tuesday 17 May 2011 01:45 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD21BAA.6000601@ti.com>  you wrote:
>>
>>> What is MLO?
>>
>> MLO is the name of SPL created for OMAP. ROM code expects a file with
>> this name as the first image when it boots from FAT.
>
> What does MLO mean?

On looking up ROM code spec, this seems to stand for "MMC/SD Loader"

>
>
>>>> +#ifdef CONFIG_PRELOADER
>>>> +/* SPL works from internal RAM. gd pointer can be in .data section */
>>>> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
>>>> +#else
>>>>    #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
>>>> +#endif
>>>
>>> Is this appropriate for all ARM boards (e.g. those currently using
>>> nand_spl)?
>>
>> None of the SPL's other than this one seems to be using global data
>> today. If anybody wants to use it this seems to be the logical option
>> for me because by definition SPL runs from some kind of RAM so global
>> data can be placed in the .data section of SPL.
>
> But that's not what you are doing.  You are not changing the storage
> of the global data itself, you are changing the storage of the POINTER
> TO the global data - and this makes no sense to me.  The pointer can
> certainly remain in a register even if the data itself is somewhere
> else.

Why do we want to waste a register in the entire SPL when global data
can be accessed directly from .data section?

best regards,
Aneesh

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD24CC2.9040302@ti.com> you wrote:
> 
> You mean "__packed__" should be removed from "struct gp_header" alone,
> not from the other structs?

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD24E63.3020006@ti.com> you wrote:
> 
> > But that's not what you are doing.  You are not changing the storage
> > of the global data itself, you are changing the storage of the POINTER
> > TO the global data - and this makes no sense to me.  The pointer can
> > certainly remain in a register even if the data itself is somewhere
> > else.
> 
> Why do we want to waste a register in the entire SPL when global data
> can be accessed directly from .data section?

Because the resulting code is smaller?

I did not measure it on your hardware with your compiler, but IIRC
this was the result on some other processors.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It may be that your whole purpose in life is simply  to  serve  as  a
warning to others.

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 05:18 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD0F98A.2040302@ti.com>  you wrote:
>>
>>>> @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
>>>>    	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
>>>>    	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
>>>>    	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
>>>> +	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
>>>>    	{	-1,		    "",		  "",			},
>>>
>>> Please keep list sorted / sort list.
>>
>> Sort by the second field(kwbimage, omapimage etc), right?
>
> First field, but the result is the same.
>
>>>> +struct ch_toc {
>>>> +	uint32_t section_offset;
>>>> +	uint32_t section_size;
>>>> +	uint8_t unused[12];
>>>> +	uint8_t section_name[12];
>>>> +} __attribute__ ((__packed__));
>>>> +
>>>> +struct ch_settings {
>>>> +	uint32_t section_key;
>>>> +	uint8_t valid;
>>>> +	uint8_t version;
>>>> +	uint16_t reserved;
>>>> +	uint32_t flags;
>>>> +} __attribute__ ((__packed__));
>>>> +
>>>> +struct gp_header {
>>>> +	uint32_t size;
>>>> +	uint32_t load_addr;
>>>> +} __attribute__ ((__packed__));
>>>
>>> Is there any good reason to have these "__attribute__ ((__packed__))"
>>> here?  In general, these are only known to cause trouble and pain, and
>>> I cannot see a need here.
>>
>> ROM code expects the header in a precise format. I think it will not be
>> safe to leave it to the compiler to decide the field layout. For
>> instance, the compiler may align the uint8_t or uint16_t to 32 bit
>> boundary and that will break the Configuration Header.
>
> No. Not in the structs listed above.

Why do you think it will not create any problems. For instance, what if
the field "uint8_t version" in "struct ch_settings" is aligned to a 32
bit boundary by the compiler for faster access? That is not the
intended layout.

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Wolfgang,

On Tuesday 17 May 2011 04:47 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD24E63.3020006@ti.com>  you wrote:
>>
>>> But that's not what you are doing.  You are not changing the storage
>>> of the global data itself, you are changing the storage of the POINTER
>>> TO the global data - and this makes no sense to me.  The pointer can
>>> certainly remain in a register even if the data itself is somewhere
>>> else.
>>
>> Why do we want to waste a register in the entire SPL when global data
>> can be accessed directly from .data section?
>
> Because the resulting code is smaller?
>

I was thinking that it may be faster. More number of registers at
disposal may mean less number of pushes to the stack, right? I am not
sure if this will make a significant difference.

best regards,
Aneesh

[U-Boot] [PATCH v2 01/22] mkimage: Add OMAP boot image support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD2657F.3020708@ti.com> you wrote:
> 
> >>>> +struct ch_toc {
> >>>> +	uint32_t section_offset;
> >>>> +	uint32_t section_size;
> >>>> +	uint8_t unused[12];
> >>>> +	uint8_t section_name[12];
> >>>> +} __attribute__ ((__packed__));
> >>>> +
> >>>> +struct ch_settings {
> >>>> +	uint32_t section_key;
> >>>> +	uint8_t valid;
> >>>> +	uint8_t version;
> >>>> +	uint16_t reserved;
> >>>> +	uint32_t flags;
> >>>> +} __attribute__ ((__packed__));
> >>>> +
> >>>> +struct gp_header {
> >>>> +	uint32_t size;
> >>>> +	uint32_t load_addr;
> >>>> +} __attribute__ ((__packed__));
...
> > No. Not in the structs listed above.
> 
> Why do you think it will not create any problems. For instance, what if
> the field "uint8_t version" in "struct ch_settings" is aligned to a 32
> bit boundary by the compiler for faster access? That is not the
> intended layout.

If the compiler did such a thing, this would indeed be bad.  But I
have never seen a compiler doing this, nor is there a reason to do so.
The naturla alignment requirement for a uint8_t is a byte; ther eis no
need to align it on 4 byte boundary.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Man is the best computer we can put aboard a spacecraft ...  and  the
only one that can be mass produced with unskilled labor.
                                                  - Wernher von Braun

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD26719.5090003@ti.com> you wrote:
> 
> I was thinking that it may be faster. More number of registers at
> disposal may mean less number of pushes to the stack, right? I am not
> sure if this will make a significant difference.

It does not make a significant difference. Which is the reason I vote
for avoiding the #ifdef.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Never put off until tomorrow what you can put off indefinitely.

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi Wolfgang,

On Tuesday 17 May 2011 01:49 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD21FB9.6070901@ti.com>  you wrote:
>>
>> The top-level make rule being the following, we will need a Makefile in
>> the board directory, right?
>>
>> +SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
>> +    $(MAKE) -C spl/board/$(BOARDDIR) all
>
> Maybe this needs to be tweaked to allow for boards that don;t require
> board specific code.
>

And how do you distinguish between the two cases at the top level
Makefile? Using a CONFIG flag or on a per platform basis?

Why not just invoke the board level Makefile from the top-level
Makefile and let it decide about the code-reuse by doing something like
I did?

>> In fact, code is already common. All OMAP code specific to SPL comes
>> from spl/board/ti/spl-omap.c . All OMAP code shared with OMAP U-Boot
>> comes from the respective directory within arch/arm/cpu/armv7/*
>>
>> In the interest of simplicity I deferred all board specific
>> initialization of OMAP4(mainly mux) to U-Boot. So, SPL is board
>> independent today for OMAP4.
>
> Then we should adapt the directory and Makefile structure and allow
> for such common code without need for separate spl/board/
> directories.

Do you have any specific proposals? I have a feeling that this may get 
un-necessarily complicated.

Best regards,
Aneesh

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD26B36.4050102@ti.com> you wrote:
> 
> And how do you distinguish between the two cases at the top level
> Makefile? Using a CONFIG flag or on a per platform basis?

The decision should not be make in the top level makefile, but in
spl/Makefile.  And this can simply check if a board directory exists
in the first place.

> Why not just invoke the board level Makefile from the top-level
> Makefile and let it decide about the code-reuse by doing something like
> I did?

Because then we need board specific directories and board specific
Makefiles even for those boards where no board specific code exists,
and all these Makefiles will be semi-identical copies of each other.

> > Then we should adapt the directory and Makefile structure and allow
> > for such common code without need for separate spl/board/
> > directories.
> 
> Do you have any specific proposals? I have a feeling that this may get 
> un-necessarily complicated.

Having to maintain multiple copies of identical Makefiles is more
complicated and error prone in the long run. Let's rather spoend a few
thoughts initially and solve this problem before it spreads.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It ain't so much the things we don't know that get  us  in  trouble.
It's  the  things  we know that ain't so." - Artemus Ward aka Charles
Farrar Brown

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 12:30 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-14-git-send-email-aneesh@ti.com>  you wrote:
>> Add support for:
>> 1. DPLL locking
>> 2. Initialization of clock domains and clock modules
>>
>> This work draws upon previous work done for x-loader mainly by:
>> 	Santosh Shilimkar<santosh.shilimkar@ti.com>
>> 	Rajendra Nayak<rnayak@ti.com>
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>> V2:
>> * Use pre-calculated M&  N values instead of calculated ones
>> * Changes due to make file changes
>> * Some corrections
>> * Do all clock initialization in SPL itself instead of differing some
>>    work to u-boot
>> ---
>>   arch/arm/cpu/armv7/omap4/Makefile           |    1 +
>>   arch/arm/cpu/armv7/omap4/board.c            |    1 +
>>   arch/arm/cpu/armv7/omap4/clocks.c           |  731 +++++++++++++++++++++++++++
>>   arch/arm/cpu/armv7/omap4/clocks_get_m_n.c   |  154 ++++++
>>   arch/arm/include/asm/arch-omap4/clocks.h    |  506 ++++++++++++++++++
>>   arch/arm/include/asm/arch-omap4/sys_proto.h |    6 +
>>   arch/arm/include/asm/omap_common.h          |    3 +
>>   spl/board/ti/omap4.mk                       |    7 +-
>>   8 files changed, 1408 insertions(+), 1 deletions(-)
>>   create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
>>   create mode 100644 arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
>>   create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
>
> It appears this might be part of or taken from some bigger scope
> clocks framework.  Otherwise it's diffcult for me to understand why
> OMAP4 needs 1400+ lines of code, when other SoCs appear to do with
> considerably less. Please comment.
>

No. This code was written for SPL. Please note that a lot of it is
tables used for PLL locking, clock enabling etc. OMAP4 supports
different crystal frequencies. So, more entries in each table. Also,
there are some special handling based on the OMAP4 revisions because of
some frequency limitations. So, more number of tables.

>> diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
>> index 987dc9d..6154e86 100644
>> --- a/arch/arm/cpu/armv7/omap4/Makefile
>> +++ b/arch/arm/cpu/armv7/omap4/Makefile
>> @@ -30,6 +30,7 @@ SOBJS	+= lowlevel_init.o
>>   COBJS	+= board.o
>>   COBJS	+= mem.o
>>   COBJS	+= sys_info.o
>> +COBJS	+= clocks.o
>
> Please keep lists sorted.

ok.

>
> ...
>> +static inline void do_bypass_dpll(u32 base)
>> +{
>> +	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
>> +
>> +	modify_reg_32(&dpll_regs->cm_clkmode_dpll,
>> +		      CM_CLKMODE_DPLL_DPLL_EN_SHIFT,
>> +		      CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_FAST_RELOCK_BYPASS);
>
> NAK, please use standard macros (see previous messages).
>
>> +static void do_setup_dpll(u32 base, const struct dpll_params *params, u8 lock)
>> +{
>> +	u32 temp;
>> +	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
>> +
>> +	bypass_dpll(base);
>> +
>> +	/* Set M&  N */
>> +	temp = readl(&dpll_regs->cm_clksel_dpll);
>> +	set_bit_field(temp, CM_CLKSEL_DPLL_M_SHIFT, CM_CLKSEL_DPLL_M_MASK,
>> +			params->m);
>> +	set_bit_field(temp, CM_CLKSEL_DPLL_N_SHIFT, CM_CLKSEL_DPLL_N_MASK,
>> +			params->n);
>> +	writel(temp,&dpll_regs->cm_clksel_dpll);
>
> NAK, please use standard macros (see previous messages).
>
>
> ...
>> diff --git a/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
>> new file mode 100644
>> index 0000000..777ec11
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/omap4/clocks_get_m_n.c
>> @@ -0,0 +1,154 @@
> ...
>> +void main(void)
>
> It appears this is a host program, not part of U-Boot.  I don't think
> that arch/arm/cpu/armv7/omap4/ is the right place for this program.
>
> ...
...
>> +#define CM_CLKMODE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4220)
>> +#define CM_IDLEST_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4224)
>> +#define CM_AUTOIDLE_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4228)
>> +#define CM_CLKSEL_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x422c)
>> +#define CM_DIV_M2_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4230)
>> +#define CM_DIV_M4_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4238)
>> +#define CM_DIV_M5_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x423c)
>> +#define CM_DIV_M6_DPLL_DDRPHY		(OMAP44XX_L4_CORE_BASE + 0x4240)
>> +#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY	(OMAP44XX_L4_CORE_BASE + 0x4248)
>> +#define CM_SHADOW_FREQ_CONFIG1		(OMAP44XX_L4_CORE_BASE + 0x4260)
>
> NAK.  We do not accept base address plus offset notation.  Please
> declare C structs instead.
>

Ok. will do.

Again just curious, what's the reasoning behind this policy? Is it just
aesthetics or something more?

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Wolfgang,

On Tuesday 17 May 2011 06:03 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD26719.5090003@ti.com>  you wrote:
>>
>> I was thinking that it may be faster. More number of registers at
>> disposal may mean less number of pushes to the stack, right? I am not
>> sure if this will make a significant difference.
>
> It does not make a significant difference. Which is the reason I vote
> for avoiding the #ifdef.
>

Ok. I shall change it.

best regards,
Aneesh

[U-Boot] [PATCH v2 15/22] omap4: add sdram init support

[Aneesh V]

On Monday 16 May 2011 01:31 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-16-git-send-email-aneesh@ti.com>  you wrote:
>> Add support for the SDRAM controller (EMIF).
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> V2:
>> * Changes for makefile changes
>> * Minor corrections in do_lpddr2_init()
>> * Minor corrections to read_idle interval calculation
>> * Sanity test of memory after doing the initialization
>> * Fixed warnings reported with with latest GCC compilers
>> ---
>>   arch/arm/cpu/armv7/omap4/Makefile           |    3 +
>>   arch/arm/cpu/armv7/omap4/board.c            |    2 +-
>>   arch/arm/cpu/armv7/omap4/emif.c             |  298 +++++++++++
>>   arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  118 +++++
>>   arch/arm/include/asm/arch-omap4/emif.h      |  719 +++++++++++++++++++++++++++
>>   arch/arm/include/asm/arch-omap4/omap4.h     |   11 +
>>   arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
>>   include/configs/omap4_sdp4430.h             |    5 -
>>   spl/board/ti/omap4.mk                       |    9 +-
>>   9 files changed, 1159 insertions(+), 7 deletions(-)
>>   create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
>>   create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
>>   create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
>
> I'm really surprised to see this patch at this position in the middle
> of this patch series.
>
> Can you please explain why you think this is the right place for it?

This is roughly the sequence I followed.
1. Make the basic infrastructure.
2. Have a working skeleton of SPL(Just boots but doesn't do the loading
part yet)
3. Add mux support.
4. Add clock initialization
5. Add SDRAM initialization(clock patch is a pre-requisite for this)
6. Add support for MMC initialization and loading of U-Boot
7. Add FAT mode boot support.
8. Add support for Panda

I think this will change a bit when I do some squashing as you
suggested.

best regards,
Aneesh

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:35 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-17-git-send-email-aneesh@ti.com>  you wrote:
>> Calculate EMIF register values based on AC timing parameters
>> from the SDRAM datasheet and the DDR frequency rather than
>> using the hard-coded values.
>>
>> For a new board the user doen't have to go through the tedious
>> process of calculating the register values. Instead, just
>> provide the AC timings from the device data sheet as input
>> and the driver will automatically calculate the register values.
>
> Does it make sense to do this in the driver code?  These parameters
> will never change, so why can we not rather perform the computation
> only once, at build time, and feed in the respective parameters to the
> driver?

Some of the parameters do change. For instance on one of the OMAP4
revisions the DDR runs at 200MHz, on another one at 380MHz and for the
rest at 400MHz. Also, on ES1 we have 512 MB of memory where as on
others we have 1GB. This driver is also doing discovery of SDRAM
geometry, type, etc.

>
> Reasons why I am concerned about such an approach are code size and
> boot time.  Both suffer ...
>

I had the same concerns too. So, I have provided a CONFIG option -
CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - by which the user can
provide the register values, so no computation will be done.

So, if somebody is concerned about the performance they can just
compute the values using this driver and print them out by enabling the
debug traces, fill it up in the structs provided for it and enable
CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS. That should work.

Also, please note that I had measured the time taken for the entire
SDRAM initialization and it was not at all significant(IIRC, it was
less than 1ms).

best regards,
Aneesh

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Aneesh V]

Hi Mans,

On Monday 16 May 2011 02:12 AM, M?ns Rullg?rd wrote:
> Wolfgang Denk<wd@denx.de>  writes:
>
>> Dear Aneesh V,
>>
>> In message<1305472900-4004-17-git-send-email-aneesh@ti.com>  you wrote:
>>> Calculate EMIF register values based on AC timing parameters
>>> from the SDRAM datasheet and the DDR frequency rather than
>>> using the hard-coded values.
>>>
>>> For a new board the user doen't have to go through the tedious
>>> process of calculating the register values. Instead, just
>>> provide the AC timings from the device data sheet as input
>>> and the driver will automatically calculate the register values.
>>
>> Does it make sense to do this in the driver code?  These parameters
>> will never change, so why can we not rather perform the computation
>> only once, at build time, and feed in the respective parameters to the
>> driver?
>
> I agree, there should be no reason for doing this at runtime.  I would
> think it possible to do with some C macros.
>

I had a C macro version earlier. But as I have mentioned in my reply to
Wolfgang some of the inputs vary between different revisions of our
silicon. I am doing a run-time identification of the revision and doing
the settings accordingly.

Besides, the forest of MACROs was really ugly.

best regards,
Aneesh

[U-Boot] [PATCH v2 17/22] omap4: automatic sdram detection

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:36 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-18-git-send-email-aneesh@ti.com>  you wrote:
>> Identify SDRAM devices connected to EMIF automatically:
>> LPDDR2 devices have some Mode Registers that provide details
>> about the device such as the type, density, bus width
>> etc. EMIF has the capability to read these registers. If there
>> are not devices connected to a given chip-select reading mode
>> registers will return junk values. After reading as many such
>> registers as possible and matching with expected ranges of
>> values the driver can identify if there is a device connected
>> to the respective CS. If we identify that a device is connected
>> the values read give us complete details about the device.
>>
>> This along with the base AC timings specified by JESD209-2
>> allows us to do a complete automatic initialization of
>> SDRAM that works on all boards.
>>
>> Please note that the default AC timings specified by JESD209-2
>> will be safe for all devices but not necessarily optimal. However,
>> for the Elpida devices used on Panda and SDP the default timings
>> are both safe and optimal.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> ---
>>   arch/arm/cpu/armv7/omap4/emif.c         |  177 +++++++++++++++++++++++++++++-
>>   arch/arm/cpu/armv7/omap4/sdram_elpida.c |    9 +-
>>   include/configs/omap4_sdp4430.h         |    1 +
>>   3 files changed, 176 insertions(+), 11 deletions(-)
>
> How much of this is OMAP4 specific, and how much can be reused onother
> SoCs as well?

LPDDR2 provides registers. But OMAP4 EMIF controller provides the means
to read them. In that sense it is closely tied to EMIF.

best regards,
Aneesh

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Scott Wood]

On Tue, 17 May 2011 12:24:34 +0530
Aneesh V <aneesh@ti.com> wrote:

> On Tuesday 17 May 2011 12:02 AM, Scott Wood wrote:
> > On Sun, 15 May 2011 20:51:24 +0530
> > Aneesh V<aneesh@ti.com>  wrote:
> >> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
> >> index 2a84d27..2ce020e 100644
> >> --- a/arch/arm/include/asm/global_data.h
> >> +++ b/arch/arm/include/asm/global_data.h
> >> @@ -89,6 +89,11 @@ typedef	struct	global_data {
> >>   #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in&  out)		*/
> >>   #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
> >>
> >> +#ifdef CONFIG_PRELOADER
> >> +/* SPL works from internal RAM. gd pointer can be in .data section */
> >> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
> >> +#else
> >>   #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
> >> +#endif
> >
> > Is this appropriate for all ARM boards (e.g. those currently using
> > nand_spl)?
> 
> None of the SPL's other than this one seems to be using global data
> today. If anybody wants to use it this seems to be the logical option
> for me because by definition SPL runs from some kind of RAM so global
> data can be placed in the .data section of SPL.

There is nand_spl code, including ARM, that uses gd.  E.g. putc() in
board/davinci/da8xxevm/hawkboard_nand_spl.c.

This comment also applies to the other uses of CONFIG_PRELOADER -- are all
of those changes appropriate for the existing nand_spl users?

-Scott

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD27893.5000606@ti.com> you wrote:
> 
> > It appears this might be part of or taken from some bigger scope
> > clocks framework.  Otherwise it's diffcult for me to understand why
> > OMAP4 needs 1400+ lines of code, when other SoCs appear to do with
> > considerably less. Please comment.
> 
> No. This code was written for SPL. Please note that a lot of it is
> tables used for PLL locking, clock enabling etc. OMAP4 supports
> different crystal frequencies. So, more entries in each table. Also,
> there are some special handling based on the OMAP4 revisions because of
> some frequency limitations. So, more number of tables.

hm... is this really a type of selection that has to be done at
runtime?  In the real system, the frequencies will probably pretty
much fixed, and not dynamically adjusted in U-Boot.  So maybe we can
compile at least poarts of this at build time?

> > NAK.  We do not accept base address plus offset notation.  Please
> > declare C structs instead.
> >
> 
> Ok. will do.
> 
> Again just curious, what's the reasoning behind this policy? Is it just
> aesthetics or something more?

It's more.  When using base+offset, the compiler will know nothing
about the data type, so it canot warn you if you use a 32 bit accessor
on a 8 bit register, or vice versa.  When you pass a struct element,
it can check type information.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
How many seconds are there in a year? If I tell you there are 3.155 x
10^7, you won't even try to remember it. On the other hand, who could
forget that, to within half a percent, pi seconds is  a  nanocentury.
                                               -- Tom Duff, Bell Labs

[U-Boot] [PATCH v2 15/22] omap4: add sdram init support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD28296.2060608@ti.com> you wrote:
> 
> > Can you please explain why you think this is the right place for it?
> 
> This is roughly the sequence I followed.
> 1. Make the basic infrastructure.
> 2. Have a working skeleton of SPL(Just boots but doesn't do the loading part yet)
> 3. Add mux support.
> 4. Add clock initialization
> 5. Add SDRAM initialization(clock patch is a pre-requisite for this)
> 6. Add support for MMC initialization and loading of U-Boot
> 7. Add FAT mode boot support.
> 8. Add support for Panda
> 
> I think this will change a bit when I do some squashing as you
> suggested.

Thanks for the explanation. It was really helpful.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Backed up the system lately?

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD2858E.2000703@ti.com> you wrote:
> 
> I had the same concerns too. So, I have provided a CONFIG option -
> CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - by which the user can
> provide the register values, so no computation will be done.

Ah, great. Sorry, I have missed this.

> So, if somebody is concerned about the performance they can just
> compute the values using this driver and print them out by enabling the
> debug traces, fill it up in the structs provided for it and enable
> CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS. That should work.

Will this also comment out the respective code, so we don't waste the
memory for it?

> Also, please note that I had measured the time taken for the entire
> SDRAM initialization and it was not at all significant(IIRC, it was
> less than 1ms).

Thanks!

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Mr. Cole's Axiom:
        The sum of the intelligence on the planet is a constant;
        the population is growing.

[U-Boot] [PATCH v2 06/22] Add generic spl infrastructure

[Aneesh V]

Hi Scott,

On Tuesday 17 May 2011 10:20 PM, Scott Wood wrote:
> On Tue, 17 May 2011 12:24:34 +0530
> Aneesh V<aneesh@ti.com>  wrote:
>
>> On Tuesday 17 May 2011 12:02 AM, Scott Wood wrote:
>>> On Sun, 15 May 2011 20:51:24 +0530
>>> Aneesh V<aneesh@ti.com>   wrote:
>>>> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
>>>> index 2a84d27..2ce020e 100644
>>>> --- a/arch/arm/include/asm/global_data.h
>>>> +++ b/arch/arm/include/asm/global_data.h
>>>> @@ -89,6 +89,11 @@ typedef	struct	global_data {
>>>>    #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in&   out)		*/
>>>>    #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
>>>>
>>>> +#ifdef CONFIG_PRELOADER
>>>> +/* SPL works from internal RAM. gd pointer can be in .data section */
>>>> +#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
>>>> +#else
>>>>    #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
>>>> +#endif
>>>
>>> Is this appropriate for all ARM boards (e.g. those currently using
>>> nand_spl)?
>>
>> None of the SPL's other than this one seems to be using global data
>> today. If anybody wants to use it this seems to be the logical option
>> for me because by definition SPL runs from some kind of RAM so global
>> data can be placed in the .data section of SPL.
>
> There is nand_spl code, including ARM, that uses gd.  E.g. putc() in
> board/davinci/da8xxevm/hawkboard_nand_spl.c.
>
> This comment also applies to the other uses of CONFIG_PRELOADER -- are all
> of those changes appropriate for the existing nand_spl users?

I would probably revert the change as advised by Wolfgang.

best regards,
Aneesh

[U-Boot] [PATCH v2 16/22] omap4: calculate EMIF register values

[Aneesh V]

Hi Wolfgang,

On Wednesday 18 May 2011 03:24 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD2858E.2000703@ti.com>  you wrote:
>>
>> I had the same concerns too. So, I have provided a CONFIG option -
>> CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - by which the user can
>> provide the register values, so no computation will be done.
>
> Ah, great. Sorry, I have missed this.
>
>> So, if somebody is concerned about the performance they can just
>> compute the values using this driver and print them out by enabling the
>> debug traces, fill it up in the structs provided for it and enable
>> CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS. That should work.
>
> Will this also comment out the respective code, so we don't waste the
> memory for it?

In SPL yes, because I am using -ffunction-sections -fdata-sections
along with --gc-sections, but not in U-Boot. I shall take care
of this in the next revision.

BTW, I was thinking that I should enable -ffunction-sections
-fdata-sections in OMAP U-Boot too. What do you think?

best regards,
Aneesh

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Aneesh V]

Hi Scott,

On Tuesday 17 May 2011 12:26 AM, Scott Wood wrote:
> On Sun, 15 May 2011 20:51:36 +0530
> Aneesh V<aneesh@ti.com>  wrote:
>
>> Embed the u-boot flash image size at a known offset from the
>> start of u-boot so that SPL can use it while loading u-boot
>> from a non-XIP media.
>>
>> Signed-off-by: Aneesh V<aneesh@ti.com>
>> V2:
>> * Removed the linker script label '__flash_image_end' and its usage.
>>    Instead '_end' is used now
>> ---
>>   arch/arm/cpu/armv7/start.S |    6 +++++-
>>   1 files changed, 5 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
>> index f92c6d9..f676d7d 100644
>> --- a/arch/arm/cpu/armv7/start.S
>> +++ b/arch/arm/cpu/armv7/start.S
>> @@ -64,8 +64,12 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
>>
>>   .global _end_vect
>>   _end_vect:
>> +.global	_u_boot_size
>> +_u_boot_size:
>> +	.word	0xDEADBEEF
>> +	.word	_end - _start
>
> 0xdeadbeef does not seem like a good magic value to identify this header
> format -- especially since it looks like that may have been the value
> present in the older images that don't have this header (depending on
> whether the .balignl needed to pad).

Thanks for pointing this out. I will change it to something different.

best regards,
Aneesh

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Aneesh V]

Hi Wolfgang,

On Monday 16 May 2011 01:39 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-19-git-send-email-aneesh@ti.com>  you wrote:
>> Embed the u-boot flash image size at a known offset from the
>> start of u-boot so that SPL can use it while loading u-boot
>> from a non-XIP media.
>
> I don't think this is a good idea.
>
> What you are doing here is defining an image format. Such an image
> format must be good enough not only for OMAP4 and for loading U-Boot
> as second stage, but for all other architectures and use cases as
> well.

I am not defining and publishing a format for the external world. It's
just an internal information much like any other info embedded in
start.S such as  _bss_end_ofs, _end_ofs etc. It's just that SPL, being
an insider, can take advantage of it.

I feel creating a new mkimage target just for this will be an overkill.
I will be happy loading the maximum image size always.

best regards,
Aneesh

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Scott,

On Tuesday 17 May 2011 12:09 AM, Scott Wood wrote:
> On Mon, 16 May 2011 19:40:30 +0530
> Aneesh V<aneesh@ti.com>  wrote:
>
>> Hi Wolfgang,
>>
>> On Monday 16 May 2011 01:22 AM, Wolfgang Denk wrote:
>>> I think, in the first step of this series, we should move the existing
>>> code from nand_spl and onenand_ipl into something like spl/nand and
>>> spl/onenand, respectivly, and make sure all teh existing systems still
>>> build.  The we can add more such support.
>>
>> IMHO, we should just have spl/board/<vendor>/<board>/ .
>>
>> Let spl/board/<vendor>/<board>/Makefile decide what it wants to
>> build.
>
> That's what we do in nand_spl/onenand_spl -- the common files are more like
> libraries that the board makefile may or may not pull in (e.g. many
> Freescale boards use nand_boot_fsl_elbc.c or nand_boot_fsl_nfc.c instead of
> nand_boot.c).
>
> Renaming nand_spl seems like it should be the first step.
>
>> I mean something like this(similar changes for ONENAND):
>>
>> +.PHONEY : SPL
>
> .PHONY

Oops! I wonder how it was working then. My real patch too had the same
mistake!

best regards,
Aneesh

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <4DD352EA.3090007@ti.com> you wrote:
> 
> > What you are doing here is defining an image format. Such an image
> > format must be good enough not only for OMAP4 and for loading U-Boot
> > as second stage, but for all other architectures and use cases as
> > well.
> 
> I am not defining and publishing a format for the external world. It's

In the essence this is what you are doing: you are defining an
interface how the payload has to look like.  Anything not meeting this
"specification" or "image format" or "ABI" or whatever you call it
will not be directly loadable by the SPL.

But I want to make sure that we can load arbitrary payloads as second
stage, not only U-Boot images.  Because we cannot guarantee that we
can embed such information into other payloads we may want to load, we
must prepend or append such information, but not embed it somewhere
within the image itself.

> just an internal information much like any other info embedded in
> start.S such as  _bss_end_ofs, _end_ofs etc. It's just that SPL, being
> an insider, can take advantage of it.

This is not quite correct. SPL needs this information.  We are defining
an API here, and we should make sure it fits the use cases we can see
now (and ideally is flexible enough so we can adjust/extend it for
future use).

> I feel creating a new mkimage target just for this will be an overkill.

We don't have to create a new format. We can, for example, use the
existing format with a prepended 64 byte header. The only thing that
needs changes is that we now have to consider the header when loading
the image, but the same problem will always exist when we accept that
we cannot embed the information within the payload. We don't need any
new code to implement this solution. We can easily create the images
using "mkimage -T firmware -O u-boot".

> I will be happy loading the maximum image size always.

This makes no sense.  What is "the maximum image size always"? 4 MB,
so we can also load a Linux kernel as payload? 8 MB, so we can stil do
this in a year from now?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A metaphor is like a simile.

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Scott Wood]

On Wed, 18 May 2011 10:35:56 +0530
Aneesh V <aneesh@ti.com> wrote:

> On Tuesday 17 May 2011 12:09 AM, Scott Wood wrote:
> >> +.PHONEY : SPL
> >
> > .PHONY
> 
> Oops! I wonder how it was working then. My real patch too had the same
> mistake!

Well, .PHONY is mainly a performance hint if there's no actual file or
rule with that name.

-Scott

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Aneesh V]

Hi Wolfgang,

On Wednesday 18 May 2011 11:36 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD352EA.3090007@ti.com>  you wrote:
>>
>>> What you are doing here is defining an image format. Such an image
>>> format must be good enough not only for OMAP4 and for loading U-Boot
>>> as second stage, but for all other architectures and use cases as
>>> well.
>>
>> I am not defining and publishing a format for the external world. It's
>
> In the essence this is what you are doing: you are defining an
> interface how the payload has to look like.  Anything not meeting this
> "specification" or "image format" or "ABI" or whatever you call it
> will not be directly loadable by the SPL.

This is not exactly true. I had implemented a fall-back option albeit
with a maximum size assumed for U-Boot.

>
> But I want to make sure that we can load arbitrary payloads as second
> stage, not only U-Boot images.  Because we cannot guarantee that we
> can embed such information into other payloads we may want to load, we
> must prepend or append such information, but not embed it somewhere
> within the image itself.
>
>> just an internal information much like any other info embedded in
>> start.S such as  _bss_end_ofs, _end_ofs etc. It's just that SPL, being
>> an insider, can take advantage of it.
>
> This is not quite correct. SPL needs this information.  We are defining
> an API here, and we should make sure it fits the use cases we can see
> now (and ideally is flexible enough so we can adjust/extend it for
> future use).

Agree that mkimage approach works better for different types of
payloads.

>
>> I feel creating a new mkimage target just for this will be an overkill.
>
> We don't have to create a new format. We can, for example, use the
> existing format with a prepended 64 byte header. The only thing that
> needs changes is that we now have to consider the header when loading
> the image, but the same problem will always exist when we accept that
> we cannot embed the information within the payload. We don't need any
> new code to implement this solution. We can easily create the images
> using "mkimage -T firmware -O u-boot".

The existing target u-boot.img works for me. Just a couple of questions:

1. I see that size is at offset 0xC in this header. Is this a standard?
2. I see that the header is 64 bytes. Is that again a standard for
mkimage.
3. Is it ok to add u-boot.img to the target "ALL"?
4. If not, is it ok to add it to "ALL" when CONFIG_SPL is defined? 
Something like this:

  ifeq ($(CONFIG_SPL),y)
  .PHONEY : SPL
-ALL += SPL
+ALL += SPL u-boot.img
  endif

Is it ok to add support for kernel payload as a subsequent incremental
step. That's, right now I intend to parse the mkimage header, find the
size and load address and load the image and pass control to it, but
*without* passing any parameters. Is that ok?

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi Wolfgang,

On Tuesday 17 May 2011 06:23 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD26B36.4050102@ti.com>  you wrote:
>>
>> And how do you distinguish between the two cases at the top level
>> Makefile? Using a CONFIG flag or on a per platform basis?
>
> The decision should not be make in the top level makefile, but in
> spl/Makefile.  And this can simply check if a board directory exists
> in the first place.

1. How about the case where there is some board dependent code but also
code shared by the boards(SoC based code). Will we have different
'Makefile's then - one for board and one for SoC. Will we then build
different libraries at each leavel and link them together etc?

2. I think one key thing that you are perhaps missing is that in SPL
the board level Makefile is not just meant for board level files.
Instead it is used to pull together files from all the layers and make
a custom image. IMHO, we will get into un-necessary complexities if we
lose this property of SPL. We may rather spend efforts on making the
regular U-Boot more configurable.

>
>> Why not just invoke the board level Makefile from the top-level
>> Makefile and let it decide about the code-reuse by doing something like
>> I did?
>
> Because then we need board specific directories and board specific
> Makefiles even for those boards where no board specific code exists,
> and all these Makefiles will be semi-identical copies of each other.
>

Considering point 2 above I think this is logical.

The board level Makefile needs to have all the files. For the SoC level
selection of files and the SoC level rules, include the respective *.mk
files. Because in this case there are no board specific files there is
nothing more in the Makefile. Please note that this may not be the case
in general. Most boards, I suspect, may have some board specific files
too.

I wouldn't really consider the include statements as duplication of
code. Instead, that was a way of avoiding duplication of code "given
the constraints of the SPL model".

best regards,
Aneesh

>>> Then we should adapt the directory and Makefile structure and allow
>>> for such common code without need for separate spl/board/
>>> directories.
>>
>> Do you have any specific proposals? I have a feeling that this may get
>> un-necessarily complicated.
>
> Having to maintain multiple copies of identical Makefiles is more
> complicated and error prone in the long run. Let's rather spoend a few
> thoughts initially and solve this problem before it spreads.
>
> Best regards,
>
> Wolfgang Denk
>

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,
On Tuesday 17 May 2011 01:46 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DD21CD8.2080409@ti.com>  you wrote:
>>
>>> There are common, board independent parts both in spl/nand and
>>> spl/onenand.
>>
>> How about having them at the root level in 'spl/' ?
>
> Why? It seems more logical to me to group nand and onenand related
> files in their own subdirectories.

I do not have any issue in having media specific files in their 
respective directories. However, I would like to see the 'Makefile's 
coming from the same directory tree irrespective of the media. So, how 
about something like this:

spl/
     mmc/
     nand/
     one-nand/
     board/<vendor>/<board>/Makefile

The idea is to have the board level Makefile in 'spl/board/<vendor>
/<board>/' no matter what the SPL type is. This will help in better
consolidation of SPLs.

I see 3 SPL use-cases in general:
1. A single SPL that supports multiple media(suitable for SoCs with
large internal RAM)
2. A single SPL supporting a single media(the board supports only one
media)
3. Multiple SPLs for the same board each supporting a different
memory device(maybe preferred over 1 to keep the foot-print of each
small).

Supporting (1) and (2) is straight forward with the above directory
structure.

To support (3) the board level Makefile should conditionally
include the respective image file in the target 'all' based on CONFIG
options. For instance 'all' may include 'onenand-ipl-2k.bin' if
CONFIG_ONENAND_U_BOOT is defined and so on.

Please let me know if any of you have better ideas. I would like to
finalize on this before re-working on my patch-set.

best regards,
Aneesh

[U-Boot] [PATCH v2 18/22] armv7: embed u-boot size within u-boot for use from SPL

[Wolfgang Denk]

Dear Aneesh V,

In message <4DDE34C5.1050407@ti.com> you wrote:
> 
> 1. I see that size is at offset 0xC in this header. Is this a standard?
> 2. I see that the header is 64 bytes. Is that again a standard for
> mkimage.

Both are not really "standards" in the sense that any standardization
group like ANSI or IEEE has approved this, but these are standard
within U-Boot context. The header (struct image_header) is defined in
"include/image.h"

> 3. Is it ok to add u-boot.img to the target "ALL"?

No, because in the general case this is not needed, so it's just a
waste of build time and disk space.

> 4. If not, is it ok to add it to "ALL" when CONFIG_SPL is defined? 
> Something like this:
> 
>   ifeq ($(CONFIG_SPL),y)
>   .PHONEY : SPL
> -ALL += SPL
> +ALL += SPL u-boot.img
>   endif

IN principle this should be OK, but please pay attention not to break
out-of-tree builds (You have to prefext target names with "$(obj)").

> Is it ok to add support for kernel payload as a subsequent incremental
> step. That's, right now I intend to parse the mkimage header, find the
> size and load address and load the image and pass control to it, but
> *without* passing any parameters. Is that ok?

That's perfectly fine.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Due to lack of disk space, this fortune database has been discontinued.

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi Wolfgang,

What's your final view on the Makefile structure of SPL.

best regards,
Aneesh

On Thursday 26 May 2011 06:55 PM, Aneesh V wrote:
> Hi Wolfgang,
>
> On Tuesday 17 May 2011 06:23 PM, Wolfgang Denk wrote:
>> Dear Aneesh V,
>>
>> In message<4DD26B36.4050102@ti.com> you wrote:
>>>
>>> And how do you distinguish between the two cases at the top level
>>> Makefile? Using a CONFIG flag or on a per platform basis?
>>
>> The decision should not be make in the top level makefile, but in
>> spl/Makefile. And this can simply check if a board directory exists
>> in the first place.
>
> 1. How about the case where there is some board dependent code but also
> code shared by the boards(SoC based code). Will we have different
> 'Makefile's then - one for board and one for SoC. Will we then build
> different libraries at each leavel and link them together etc?
>
> 2. I think one key thing that you are perhaps missing is that in SPL
> the board level Makefile is not just meant for board level files.
> Instead it is used to pull together files from all the layers and make
> a custom image. IMHO, we will get into un-necessary complexities if we
> lose this property of SPL. We may rather spend efforts on making the
> regular U-Boot more configurable.
>
>>
>>> Why not just invoke the board level Makefile from the top-level
>>> Makefile and let it decide about the code-reuse by doing something like
>>> I did?
>>
>> Because then we need board specific directories and board specific
>> Makefiles even for those boards where no board specific code exists,
>> and all these Makefiles will be semi-identical copies of each other.
>>
>
> Considering point 2 above I think this is logical.
>
> The board level Makefile needs to have all the files. For the SoC level
> selection of files and the SoC level rules, include the respective *.mk
> files. Because in this case there are no board specific files there is
> nothing more in the Makefile. Please note that this may not be the case
> in general. Most boards, I suspect, may have some board specific files
> too.
>
> I wouldn't really consider the include statements as duplication of
> code. Instead, that was a way of avoiding duplication of code "given
> the constraints of the SPL model".
>
> best regards,
> Aneesh
>
>>>> Then we should adapt the directory and Makefile structure and allow
>>>> for such common code without need for separate spl/board/
>>>> directories.
>>>
>>> Do you have any specific proposals? I have a feeling that this may get
>>> un-necessarily complicated.
>>
>> Having to maintain multiple copies of identical Makefiles is more
>> complicated and error prone in the long run. Let's rather spoend a few
>> thoughts initially and solve this problem before it spreads.
>>
>> Best regards,
>>
>> Wolfgang Denk
>>

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,

On Thursday 26 May 2011 07:21 PM, Aneesh V wrote:
> Hi Wolfgang,
> On Tuesday 17 May 2011 01:46 PM, Wolfgang Denk wrote:
>> Dear Aneesh V,
>>
>> In message<4DD21CD8.2080409@ti.com> you wrote:
>>>
>>>> There are common, board independent parts both in spl/nand and
>>>> spl/onenand.
>>>
>>> How about having them at the root level in 'spl/' ?
>>
>> Why? It seems more logical to me to group nand and onenand related
>> files in their own subdirectories.
>
> I do not have any issue in having media specific files in their
> respective directories. However, I would like to see the 'Makefile's
> coming from the same directory tree irrespective of the media. So, how
> about something like this:
>
> spl/
> mmc/
> nand/
> one-nand/
> board/<vendor>/<board>/Makefile
>
> The idea is to have the board level Makefile in 'spl/board/<vendor>
> /<board>/' no matter what the SPL type is. This will help in better
> consolidation of SPLs.
>
> I see 3 SPL use-cases in general:
> 1. A single SPL that supports multiple media(suitable for SoCs with
> large internal RAM)
> 2. A single SPL supporting a single media(the board supports only one
> media)
> 3. Multiple SPLs for the same board each supporting a different
> memory device(maybe preferred over 1 to keep the foot-print of each
> small).
>
> Supporting (1) and (2) is straight forward with the above directory
> structure.
>
> To support (3) the board level Makefile should conditionally
> include the respective image file in the target 'all' based on CONFIG
> options. For instance 'all' may include 'onenand-ipl-2k.bin' if
> CONFIG_ONENAND_U_BOOT is defined and so on.
>
> Please let me know if any of you have better ideas. I would like to
> finalize on this before re-working on my patch-set.

What's your views on the above scheme.

best regards,
Aneesh

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Aneesh V]

Hi Wolfgang,

On Thursday 26 May 2011 06:55 PM, Aneesh V wrote:
> Hi Wolfgang,
>
> On Tuesday 17 May 2011 06:23 PM, Wolfgang Denk wrote:
>> Dear Aneesh V,
>>
>> In message<4DD26B36.4050102@ti.com> you wrote:
>>>
>>> And how do you distinguish between the two cases at the top level
>>> Makefile? Using a CONFIG flag or on a per platform basis?
>>
>> The decision should not be make in the top level makefile, but in
>> spl/Makefile. And this can simply check if a board directory exists
>> in the first place.
>
> 1. How about the case where there is some board dependent code but also
> code shared by the boards(SoC based code). Will we have different
> 'Makefile's then - one for board and one for SoC. Will we then build
> different libraries at each leavel and link them together etc?
>
> 2. I think one key thing that you are perhaps missing is that in SPL
> the board level Makefile is not just meant for board level files.
> Instead it is used to pull together files from all the layers and make
> a custom image. IMHO, we will get into un-necessary complexities if we
> lose this property of SPL. We may rather spend efforts on making the
> regular U-Boot more configurable.

Do you have any thoughts on this yet.

Is it ok if I continue to use the current SPL Makefile structure and
abstract out common content from board level 'Makefile's to something
like omap4.mk

>
>>
>>> Why not just invoke the board level Makefile from the top-level
>>> Makefile and let it decide about the code-reuse by doing something like
>>> I did?
>>
>> Because then we need board specific directories and board specific
>> Makefiles even for those boards where no board specific code exists,
>> and all these Makefiles will be semi-identical copies of each other.
>>
>
> Considering point 2 above I think this is logical.
>
> The board level Makefile needs to have all the files. For the SoC level
> selection of files and the SoC level rules, include the respective *.mk
> files. Because in this case there are no board specific files there is
> nothing more in the Makefile. Please note that this may not be the case
> in general. Most boards, I suspect, may have some board specific files
> too.
>
> I wouldn't really consider the include statements as duplication of
> code. Instead, that was a way of avoiding duplication of code "given
> the constraints of the SPL model".

best regards,
Aneesh

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Hi Wolfgang,

On Thursday 26 May 2011 07:21 PM, Aneesh V wrote:
> Hi Wolfgang,
> On Tuesday 17 May 2011 01:46 PM, Wolfgang Denk wrote:
>> Dear Aneesh V,
>>
>> In message<4DD21CD8.2080409@ti.com> you wrote:
>>>
>>>> There are common, board independent parts both in spl/nand and
>>>> spl/onenand.
>>>
>>> How about having them at the root level in 'spl/' ?
>>
>> Why? It seems more logical to me to group nand and onenand related
>> files in their own subdirectories.
>
> I do not have any issue in having media specific files in their
> respective directories. However, I would like to see the 'Makefile's
> coming from the same directory tree irrespective of the media. So, how
> about something like this:
>
> spl/
> mmc/
> nand/
> one-nand/
> board/<vendor>/<board>/Makefile
>
> The idea is to have the board level Makefile in 'spl/board/<vendor>
> /<board>/' no matter what the SPL type is. This will help in better
> consolidation of SPLs.
>
> I see 3 SPL use-cases in general:
> 1. A single SPL that supports multiple media(suitable for SoCs with
> large internal RAM)
> 2. A single SPL supporting a single media(the board supports only one
> media)
> 3. Multiple SPLs for the same board each supporting a different
> memory device(maybe preferred over 1 to keep the foot-print of each
> small).
>
> Supporting (1) and (2) is straight forward with the above directory
> structure.
>
> To support (3) the board level Makefile should conditionally
> include the respective image file in the target 'all' based on CONFIG
> options. For instance 'all' may include 'onenand-ipl-2k.bin' if
> CONFIG_ONENAND_U_BOOT is defined and so on.
>
> Please let me know if any of you have better ideas. I would like to
> finalize on this before re-working on my patch-set.

Are you fine with this scheme. Appreciate if you could let me know your
thoughts on this. I am waiting for your inputs to start the re-work.

best regards,
Aneesh

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Aneesh V]

Dear Wolfgang,

I just realized that I had not responded to this message.

On Monday 16 May 2011 01:51 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1305472900-4004-23-git-send-email-aneesh@ti.com>  you wrote:
>> In SPL console is enabled very early where as in U-Boot
>> it's not. So, SPL can have traces in early init code
>
> Console should _always_ be enabled as early as possible,

Unfortunately this is not the case with U-Boot today. Console
initialization happens in board_init_f(). Before board_init_f()
typically a lot of(in fact most of) low level initialization happens
through the lowlevel_init() function called from start.S and the
initial part of init_sequence()

>
>> while U-Boot can not have it in the same shared code.
>>
>> Adding a debug print macro that will be defined in SPL
>> but compiled out in U-Boot.
>
> Can we not rather change the code so both configurations behave the
> same?

In SPL I had more flexibility, so I do a simplified init of console
right at the beginning of lowlevel_init(), so I can use debug prints in
lowlevel_init(). Some part of our lowlevel_init() that is executed in
SPL path may also be executed by U-Boot if it runs from NOR flash, but
in this case console wouldn't be ready. That's why I made the macro.

>
>> --- a/arch/arm/cpu/armv7/omap4/clocks.c
>> +++ b/arch/arm/cpu/armv7/omap4/clocks.c
>> @@ -379,7 +379,7 @@ u32 omap4_ddr_clk(void)
>>
>>   	core_dpll_params = get_core_dpll_params();
>>
>> -	debug("sys_clk %d\n ", sys_clk_khz * 1000);
>> +	spl_debug("sys_clk %d\n ", sys_clk_khz * 1000);
>
> Do we really need a new macro name?  Can this not be the same debug()
> macro, just generating different code (if really needed) when building
> the SPL code?

No. That wouldn't serve the purpose. I need two macros to distinguish
between the two cases.
1. 'debug()' - can be used in all places at which console is guaranteed
to be initialized whether executed as part of U-Boot or SPL.
2. 'spl_debug()' to be used at places where console is initialized for
SPL but not for U-Boot (eg. lowlevel_init()) - so emit no code for
U-Boot.

>
>> @@ -1318,4 +1328,13 @@ void sdram_init(void)
>>
>>   	/* for the shadow registers to take effect */
>>   	freq_update_core();
>> +
>> +	/* Do some basic testing */
>> +	writel(0xDEADBEEF, CONFIG_SYS_SDRAM_BASE);
>> +	if (readl(CONFIG_SYS_SDRAM_BASE) == 0xDEADBEEF)
>> +		spl_debug("SDRAM Init success!\n");
>> +	else
>> +		printf("SDRAM Init failed!!\n");
>> +
>> +	spl_debug("<<sdram_init()\n");
>
> This is beyond the scope of "adding debug traces".  it must be split
> into separate patch.

will do.

>
> Also, please do not mess witrhout need with the RAM content - at the
> very least, restore the previous values.

Will do.

>
> But then - I wonder why this is needed at all. Are you not using
> get_ram_size()?  Maybe you should fix your code to using it!

It may make sense for us to do this as a memory test. For discovering
the amount of memory installed we are using a technique based on
reading of LPDDR2 mode registers.

The above was intended as a simple sanity testing.

>
>> diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h
>> index d581539..3e847c1 100644
>> --- a/arch/arm/include/asm/utils.h
>> +++ b/arch/arm/include/asm/utils.h
>> @@ -25,6 +25,12 @@
>>   #ifndef	_UTILS_H_
>>   #define	_UTILS_H_
>>
>> +#if defined(DEBUG)&&  defined(CONFIG_PRELOADER)
>> +#define spl_debug(fmt, args...)	printf(fmt, ##args)
>> +#else
>> +#define spl_debug(fmt, args...)
>> +#endif
>
> NAK.  This is neither the right place for such a definition, nor do I
> want to see this addressed like that.
>
> I recommend to unify the code, so both SPL and non-SPL configurations
> can use teh same early console behaviour.

I always thought this is a serious issue with U-Boot. I gave it a quick
shot like below:

---
diff --git a/arch/arm/cpu/armv7/omap4/board.c 
b/arch/arm/cpu/armv7/omap4/board.c
index fcd29a7..56902e3 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -41,6 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
   */
  void s_init(void)
  {
+	printf("Hello World!!\n");
  	watchdog_init();
  }

diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa4..42264b2 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -31,17 +31,6 @@
  .globl lowlevel_init
  lowlevel_init:
  	/*
-	 * Setup a temporary stack
-	 */
-	ldr	sp, =LOW_LEVEL_SRAM_STACK
-
-	/*
-	 * Save the old lr(passed in ip) and the current lr to stack
-	 */
-	push	{ip, lr}
-
-	/*
  	 * go setup pll, mux, memory
  	 */
-	bl	s_init
-	pop	{ip, pc}
+	b	s_init
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index d91ae12..4a9251f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -307,10 +307,11 @@ cpu_init_crit:
  	 * basic memory. Go here to bump up clock rate and handle
  	 * wake up conditions.
  	 */
-	mov	ip, lr			@ persevere link reg across call
+	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
+	push	{lr}
+	bl	early_console_init
  	bl	lowlevel_init		@ go setup pll,mux,memory
-	mov	lr, ip			@ restore link
-	mov	pc, lr			@ back to my caller
+	pop	{pc}
  /*
   *************************************************************************
   *
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 1a784a1..0c696c2 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -248,9 +248,6 @@ init_fnc_t *init_sequence[] = {
  	get_clocks,
  #endif
  	env_init,		/* initialize environment */
-	init_baudrate,		/* initialze baudrate settings */
-	serial_init,		/* serial communications setup */
-	console_init_f,		/* stage 1 init of console */
  	display_banner,		/* say that we are here */
  #if defined(CONFIG_DISPLAY_CPUINFO)
  	print_cpuinfo,		/* display cpu info (and speed) */
@@ -268,6 +265,13 @@ init_fnc_t *init_sequence[] = {
  	NULL,
  };

+void early_console_init(void)
+{
+	init_baudrate();	/* initialze baudrate settings */
+	serial_init();		/* serial communications setup */
+	console_init_f();	/* stage 1 init of console */
+}
+
  void board_init_f (ulong bootflag)
  {
  	bd_t *bd;
---


But this didn't work. It crashes at the first printf(). The reason is
init_baudrate() needs global data and global data is initialized in
board_init_f(). Further, we can not move global data initialization
earlier because for global data we reuse low level stack used by
lowlevel_init().

	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);

So, we have an egg-and-chicken problem unless we find different spaces
for low-level stack and global data(that should not be a problem for
our board, but I am not sure of other boards).

Also, perhaps this needs to be done for all CPUs/archs.

IMHO, this will need a major overhaul and is not in the scope of my
current activity. Please suggest how to go about this.

Do you think re-naming spl_debug to omap_spl_debug() and putting it in
an OMAP header will help?:-) I am not sure if everybody has the same
situation as we have(that is, U-Boot and SPL sharing low-level init
code and console being initialized in one case while not in the other)

best regards,
Aneesh

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Aneesh V]

Dear Wolfgang, Heiko,

On Monday 13 June 2011 07:29 PM, Aneesh V wrote:
> Dear Wolfgang,
[snip ...]
> But this didn't work. It crashes at the first printf(). The reason is
> init_baudrate() needs global data and global data is initialized in
> board_init_f(). Further, we can not move global data initialization
> earlier because for global data we reuse low level stack used by
> lowlevel_init().
>
> gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);

On second thoughts I realize that the stack in internal RAM is still in
use in board_init_f(). So, how does this work at all? The global data
and the stack seems to be overlapping!

Please note the register dump after the above instruction. Note that
R8(gd) and R13(sp) are very close.

N _  R0          0  R8   4030DF80  SP> 12345678
Z Z  R1         0A  R9   12345678  -04 80E80078
C C  R2   4030DED4  R10  40304350  FP> D78772CA
V _  R3       5555  R11  0002FE40  +04 4049A39E
I I  R4          0  R12  80E80068  +08 F5A73CF4
F F  R5         10  R13  4030DF78  +0C 7B317D39
T _  R6   12345678  R14  80E80078  +10 ED3CFCF0
J _  R7   12345678  PC   80E80880  +14 FEECEC6A
svc  SPSR        0  CPSR 600001D3  +18 6DB22EB2

Am I missing something?

best regards,
Aneesh

[U-Boot] [PATCH v2 09/22] omap4: add spl support for OMAP4 SDP

[Wolfgang Denk]

Dear Aneesh V,

In message <4DDE54E5.7080404@ti.com> you wrote:
>
> >> And how do you distinguish between the two cases at the top level
> >> Makefile? Using a CONFIG flag or on a per platform basis?
> >
> > The decision should not be make in the top level makefile, but in
> > spl/Makefile.  And this can simply check if a board directory exists
> > in the first place.
> 
> 1. How about the case where there is some board dependent code but also
> code shared by the boards(SoC based code). Will we have different
> 'Makefile's then - one for board and one for SoC. Will we then build
> different libraries at each leavel and link them together etc?

Yes.  If a  board directory exists the code there gets built and then
linked.

> 2. I think one key thing that you are perhaps missing is that in SPL
> the board level Makefile is not just meant for board level files.

This probably should be reworked.  We should have a Makefile in
nand_spl/ which covers the general code and then runs the respective
SoC and/or board specific sub-makes.

> Instead it is used to pull together files from all the layers and make
> a custom image. IMHO, we will get into un-necessary complexities if we

Yes, but most of thisis actually not board specific, but more SoC
specific, if not general at all.

> lose this property of SPL. We may rather spend efforts on making the
> regular U-Boot more configurable.

Indeed we should allow for more fine granular selection.


> The board level Makefile needs to have all the files. For the SoC level

No.  It needs only those files that are actually board specific.

> selection of files and the SoC level rules, include the respective *.mk
> files. Because in this case there are no board specific files there is

I don;t think that this is actually board specific - if we follow that
route, we will duplicate the same stuff for all boards that use the
same SoC.

> nothing more in the Makefile. Please note that this may not be the case
> in general. Most boards, I suspect, may have some board specific files
> too.

That's why I suggest to separate common, SoC specific and board
specific stuff .


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de

There were meetings. There were always meetings. And they were  dull,
which is part of the reason they were meetings. Dull likes company.
                                    - Terry Pratchett, _Making_Money_

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DDE5AFE.9000404@ti.com> you wrote:
>
> I do not have any issue in having media specific files in their 
> respective directories. However, I would like to see the 'Makefile's 
> coming from the same directory tree irrespective of the media. So, how 
> about something like this:
> 
> spl/
>      mmc/
>      nand/
>      one-nand/
>      board/<vendor>/<board>/Makefile

Actually that would be

	 board/[<vendor>/]<board>/

> The idea is to have the board level Makefile in 'spl/board/<vendor>
> /<board>/' no matter what the SPL type is. This will help in better
> consolidation of SPLs.

OK.

> I see 3 SPL use-cases in general:
> 1. A single SPL that supports multiple media(suitable for SoCs with
> large internal RAM)
> 2. A single SPL supporting a single media(the board supports only one
> media)

1. and 2. are actually the same (2. being the special case of N=1)

> 3. Multiple SPLs for the same board each supporting a different
> memory device(maybe preferred over 1 to keep the foot-print of each
> small).
> 
> Supporting (1) and (2) is straight forward with the above directory
> structure.
> 
> To support (3) the board level Makefile should conditionally
> include the respective image file in the target 'all' based on CONFIG
> options. For instance 'all' may include 'onenand-ipl-2k.bin' if
> CONFIG_ONENAND_U_BOOT is defined and so on.

I don't get this.  Why don't we just pass the required make target
from the top level Makefile?  If we want to build "onenand-ipl-2k.bin"
then this would result in running "make onenand-ipl-2k.bin" in the
respective directory - this is then also independent of whether this
image contains support for one specific boot device or for any set of
different devices.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I object to intellect without discipline;  I object to power without
constructive purpose.
	-- Spock, "The Squire of Gothos", stardate 2124.5

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Wolfgang Denk]

Dear Aneesh V,

In message <4DF617C2.6070100@ti.com> you wrote:
> 
> > Console should _always_ be enabled as early as possible,
> 
> Unfortunately this is not the case with U-Boot today. Console
> initialization happens in board_init_f(). Before board_init_f()
> typically a lot of(in fact most of) low level initialization happens
> through the lowlevel_init() function called from start.S and the
> initial part of init_sequence()

As the name LOWLEVEL_init() suggests, this is suppoed to contain
always only the bare minimum of initialization that is necessary to
get the CPU running.  All more complex initializations should be
delayed and only be run when we have a proper environment, including
debug output on the console.

> > Can we not rather change the code so both configurations behave the
> > same?
> 
> In SPL I had more flexibility, so I do a simplified init of console
> right at the beginning of lowlevel_init(), so I can use debug prints in
> lowlevel_init(). Some part of our lowlevel_init() that is executed in
> SPL path may also be executed by U-Boot if it runs from NOR flash, but
> in this case console wouldn't be ready. That's why I made the macro.

I do not understand this.  How can you have more flexibility in the
more restricted environment?

We definitely should unify this.

> No. That wouldn't serve the purpose. I need two macros to distinguish
> between the two cases.
> 1. 'debug()' - can be used in all places at which console is guaranteed
> to be initialized whether executed as part of U-Boot or SPL.
> 2. 'spl_debug()' to be used at places where console is initialized for
> SPL but not for U-Boot (eg. lowlevel_init()) - so emit no code for
> U-Boot.

You see - this distinction is becoming a mess.  Let's get rid of this
and use common code for both cases.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Very ugly or very beautiful women should be flattered on their
understanding, and mediocre ones on their beauty.
                                       -- Philip Earl of Chesterfield

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Dear Wolfgang,

On Wednesday 15 June 2011 03:43 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4DDE5AFE.9000404@ti.com>  you wrote:
>>
>> I do not have any issue in having media specific files in their
>> respective directories. However, I would like to see the 'Makefile's
>> coming from the same directory tree irrespective of the media. So, how
>> about something like this:
>>
>> spl/
>>       mmc/
>>       nand/
>>       one-nand/
>>       board/<vendor>/<board>/Makefile
>
> Actually that would be
>
> 	 board/[<vendor>/]<board>/
>
>> The idea is to have the board level Makefile in 'spl/board/<vendor>
>> /<board>/' no matter what the SPL type is. This will help in better
>> consolidation of SPLs.
>
> OK.
>
>> I see 3 SPL use-cases in general:
>> 1. A single SPL that supports multiple media(suitable for SoCs with
>> large internal RAM)
>> 2. A single SPL supporting a single media(the board supports only one
>> media)
>
> 1. and 2. are actually the same (2. being the special case of N=1)
>
>> 3. Multiple SPLs for the same board each supporting a different
>> memory device(maybe preferred over 1 to keep the foot-print of each
>> small).
>>
>> Supporting (1) and (2) is straight forward with the above directory
>> structure.
>>
>> To support (3) the board level Makefile should conditionally
>> include the respective image file in the target 'all' based on CONFIG
>> options. For instance 'all' may include 'onenand-ipl-2k.bin' if
>> CONFIG_ONENAND_U_BOOT is defined and so on.
>
> I don't get this.  Why don't we just pass the required make target
> from the top level Makefile?  If we want to build "onenand-ipl-2k.bin"
> then this would result in running "make onenand-ipl-2k.bin" in the
> respective directory - this is then also independent of whether this
> image contains support for one specific boot device or for any set of
> different devices.

Then you will have to deal with many such images in the top-level
Makefile(u-boot/Makefile). Instead why not have just one rule like the
below in the top-level Makefile for all the different spl's:


SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
     $(MAKE) -C spl/board/$(BOARDDIR) all

And leave the rest to the board level Makefiles

Of course, this is assuming the existing Makefile structure. With the
new Makefile structure you are suggesting this may not hold good.

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh,

In message <4DF88F45.9090905@ti.com> you wrote:
>
> > I don't get this.  Why don't we just pass the required make target
> > from the top level Makefile?  If we want to build "onenand-ipl-2k.bin"
> > then this would result in running "make onenand-ipl-2k.bin" in the
> > respective directory - this is then also independent of whether this
> > image contains support for one specific boot device or for any set of
> > different devices.
> 
> Then you will have to deal with many such images in the top-level
> Makefile(u-boot/Makefile). Instead why not have just one rule like the
> below in the top-level Makefile for all the different spl's:
> 
> 
> SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
>      $(MAKE) -C spl/board/$(BOARDDIR) all
> 
> And leave the rest to the board level Makefiles

We just discussed that there are cases where there may be no board
level Makefile be needed at all, because there is no board specific
code to handle.

Also, why would there be many such images? We might just want to use
more reasonable names.  We have "u-boot.bin", and this works fine for
all boards, so why cannot we make it that "u-boot-nand.bin" works for
all boards booting from NAND, and in general "u-boot-<DEV>.bin" works
for all boards booting from a <DEV> boot device?

Instead of "onenand-ipl-2k.bin", we would just have a generic
"u-boot-onenand.bin"

> Of course, this is assuming the existing Makefile structure. With the
> new Makefile structure you are suggesting this may not hold good.

Why not?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Wenn das dann in die Hose geht, nehme ich es auf meine Kappe.
                                         -- Rudi V?ller, 15. Nov 2003

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Aneesh V]

Dear Wolfgang,

On Wednesday 15 June 2011 05:34 PM, Wolfgang Denk wrote:
> Dear Aneesh,
>
> In message<4DF88F45.9090905@ti.com>  you wrote:
>>
>>> I don't get this.  Why don't we just pass the required make target
>>> from the top level Makefile?  If we want to build "onenand-ipl-2k.bin"
>>> then this would result in running "make onenand-ipl-2k.bin" in the
>>> respective directory - this is then also independent of whether this
>>> image contains support for one specific boot device or for any set of
>>> different devices.
>>
>> Then you will have to deal with many such images in the top-level
>> Makefile(u-boot/Makefile). Instead why not have just one rule like the
>> below in the top-level Makefile for all the different spl's:
>>
>>
>> SPL    :$(TIMESTAMP_FILE) $(VERSION_FILE) depend tools
>>       $(MAKE) -C spl/board/$(BOARDDIR) all
>>
>> And leave the rest to the board level Makefiles
>
> We just discussed that there are cases where there may be no board
> level Makefile be needed at all, because there is no board specific
> code to handle.
>
> Also, why would there be many such images? We might just want to use
> more reasonable names.  We have "u-boot.bin", and this works fine for
> all boards, so why cannot we make it that "u-boot-nand.bin" works for
> all boards booting from NAND, and in general "u-boot-<DEV>.bin" works
> for all boards booting from a<DEV>  boot device?
>
> Instead of "onenand-ipl-2k.bin", we would just have a generic
> "u-boot-onenand.bin"
>
>> Of course, this is assuming the existing Makefile structure. With the
>> new Makefile structure you are suggesting this may not hold good.
>
> Why not?

I was saying that my suggestion of delegating everything to board level
Makefile will not work with the new top-down approach you are
suggesting in the other mail-chain.

best regards,
Aneesh

[U-Boot] [PATCH v2 08/22] omap: add spl support

[Wolfgang Denk]

Dear Aneesh V,

In message <4DF8A0C0.2040900@ti.com> you wrote:
> 
> >> Of course, this is assuming the existing Makefile structure. With the
> >> new Makefile structure you are suggesting this may not hold good.
> >
> > Why not?
> 
> I was saying that my suggestion of delegating everything to board level
> Makefile will not work with the new top-down approach you are
> suggesting in the other mail-chain.

I did not suggest this.  On contrary, I think I pointed out that we
might have cases where no board directory (and thus no board specific
Makefile) will be needed at all.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Many Myths are based on truth
	-- Spock, "The Way to Eden",  stardate 5832.3

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

Dear Wolfgang,

On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
[snip ..]
> +static const u32 clk_modules_hw_auto_essential[] = {
> +	CM_WKUP_GPIO1_CLKCTRL,
> +	CM_L4PER_GPIO2_CLKCTRL,
> +	CM_L4PER_GPIO3_CLKCTRL,
> +	CM_L4PER_GPIO4_CLKCTRL,
> +	CM_L4PER_GPIO5_CLKCTRL,
> +	CM_L4PER_GPIO6_CLKCTRL,
> +	CM_MEMIF_EMIF_1_CLKCTRL,
> +	CM_MEMIF_EMIF_2_CLKCTRL,
> +	CM_L3INIT_HSUSBOTG_CLKCTRL,
> +	CM_L3INIT_USBPHY_CLKCTRL,
> +	CM_L4CFG_L4_CFG_CLKCTRL,
> +	0
> +};

In this series you asked me to convert the base + offset mode of
register address definition to struct based register address
definition. While doing this I am facing a problem. Please note the
above array that contain register addresses. This is a group of
registers that control our clock modules. All these registers have
similar bit fields and they can be programmed in same manner. So, I
keep them in an array and pass the array to a function that iterates
through array and does similar processing on all the registers(see
below).

I am finding it difficult to implement this using the struct based
approach. I tried the sample code below:

struct my_regs_struct {
	const unsigned int reg1;
	const unsigned int reg2;
	const unsigned int reg3;
};

static struct my_regs_struct *const my_regs = (struct my_regs_struct 
*)0x1000;

static unsigned int *const reg_arr[] = {
	&my_regs->reg1,
	&my_regs->reg3
};

void main(void)
{
	printf("regs %x %x \n", reg_arr[0], reg_arr[1]);
}

I am getting the following errors on compiling this:
main.c:10: error: initializer element is not constant
main.c:10: error: (near initialization for ?reg_arr[0]?)
main.c:12: error: initializer element is not constant
main.c:12: error: (near initialization for ?reg_arr[1]?)

I can't make it work unless I make my_regs a statically defined
structure itself and not a pointer - like this:

static struct my_regs_struct my_regs;

This seems quite strange(behavior is the same with gcc and Microsoft
compiler). Am I missing something?

Any ideas to make it work? If not, can I go back to defines for the
addresses. All the registers we have are 32 bit long and we always use
u32 for them and use readl/writel for accessor functions. Using the
wrong accessor function is highly unlikely.

[snip ...]

> +	/* Clock modules that need to be put in HW_AUTO */
> +	for (i = 0; (i<  max)&&  clock_modules_hw_auto[i]; i++) {
> +		enable_clock_module(clock_modules_hw_auto[i],
> +				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
> +				    wait_for_enable);
> +	};

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

Dear Wolfgang,

On Tuesday 21 June 2011 11:19 AM, Aneesh V wrote:
> Dear Wolfgang,
>
> On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
> [snip ..]
>> +static const u32 clk_modules_hw_auto_essential[] = {
>> + CM_WKUP_GPIO1_CLKCTRL,
>> + CM_L4PER_GPIO2_CLKCTRL,
>> + CM_L4PER_GPIO3_CLKCTRL,
>> + CM_L4PER_GPIO4_CLKCTRL,
>> + CM_L4PER_GPIO5_CLKCTRL,
>> + CM_L4PER_GPIO6_CLKCTRL,
>> + CM_MEMIF_EMIF_1_CLKCTRL,
>> + CM_MEMIF_EMIF_2_CLKCTRL,
>> + CM_L3INIT_HSUSBOTG_CLKCTRL,
>> + CM_L3INIT_USBPHY_CLKCTRL,
>> + CM_L4CFG_L4_CFG_CLKCTRL,
>> + 0
>> +};
>
> In this series you asked me to convert the base + offset mode of
> register address definition to struct based register address
> definition. While doing this I am facing a problem. Please note the
> above array that contain register addresses. This is a group of
> registers that control our clock modules. All these registers have
> similar bit fields and they can be programmed in same manner. So, I
> keep them in an array and pass the array to a function that iterates
> through array and does similar processing on all the registers(see
> below).
>
> I am finding it difficult to implement this using the struct based
> approach. I tried the sample code below:
>
> struct my_regs_struct {
> const unsigned int reg1;
> const unsigned int reg2;
> const unsigned int reg3;
> };
>
> static struct my_regs_struct *const my_regs = (struct my_regs_struct
> *)0x1000;
>
> static unsigned int *const reg_arr[] = {
> &my_regs->reg1,
> &my_regs->reg3
> };

Apologies for the hasty mail. Looks like I can solve it by doing 
something like:

static unsigned int *const reg_arr[] = {
	&(((struct my_regs_struct *)0x1000)->reg1),
	&(((struct my_regs_struct *)0x1000)->reg3),
};

Analyzing this further right now. Hopefully, the issue can be solved
cleanly.

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh V,

In message <4E0030F8.6030104@ti.com> you wrote:
> 
> I am finding it difficult to implement this using the struct based
> approach. I tried the sample code below:
> 
> struct my_regs_struct {
> 	const unsigned int reg1;
> 	const unsigned int reg2;
> 	const unsigned int reg3;
> };
> 
> static struct my_regs_struct *const my_regs = (struct my_regs_struct 
> *)0x1000;
> 
> static unsigned int *const reg_arr[] = {
> 	&my_regs->reg1,
> 	&my_regs->reg3
> };
> 
> void main(void)
> {
> 	printf("regs %x %x \n", reg_arr[0], reg_arr[1]);
> }

Sorry, but I fail to understand the problem.  Why is reg_arr[] needed?
Why don't you use

	struct my_regs_struct {
		const unsigned int reg[3];
	};
?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
But it's real. And if it's real it can be affected ... we may not  be
able  to break it, but, I'll bet you credits to Navy Beans we can put
a dent in it.
	-- deSalle, "Catspaw", stardate 3018.2

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

On Tuesday 21 June 2011 12:35 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4E0030F8.6030104@ti.com>  you wrote:
>>
>> I am finding it difficult to implement this using the struct based
>> approach. I tried the sample code below:
>>
>> struct my_regs_struct {
>> 	const unsigned int reg1;
>> 	const unsigned int reg2;
>> 	const unsigned int reg3;
>> };
>>

The const for structure fields above were not intended. I put them
while debugging this issue and forgot to remove later.

>> static struct my_regs_struct *const my_regs = (struct my_regs_struct
>> *)0x1000;
>>
>> static unsigned int *const reg_arr[] = {
>> 	&my_regs->reg1,
>> 	&my_regs->reg3
>> };
>>
>> void main(void)
>> {
>> 	printf("regs %x %x \n", reg_arr[0], reg_arr[1]);
>> }
>
> Sorry, but I fail to understand the problem.  Why is reg_arr[] needed?
> Why don't you use
>
> 	struct my_regs_struct {
> 		const unsigned int reg[3];
> 	};
> ?

I want a number of register addresses in an array - an array of
constant pointers. The array is populated at compile time with the
addresses of all the modules that need to be initialized. At run-time I
do a specific operation on all the registers given in this array.

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

On Tuesday 21 June 2011 11:55 AM, Aneesh V wrote:
> Dear Wolfgang,
>
> On Tuesday 21 June 2011 11:19 AM, Aneesh V wrote:
>> Dear Wolfgang,
>>
>> On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
>> [snip ..]
>>> +static const u32 clk_modules_hw_auto_essential[] = {
>>> + CM_WKUP_GPIO1_CLKCTRL,
>>> + CM_L4PER_GPIO2_CLKCTRL,
>>> + CM_L4PER_GPIO3_CLKCTRL,
>>> + CM_L4PER_GPIO4_CLKCTRL,
>>> + CM_L4PER_GPIO5_CLKCTRL,
>>> + CM_L4PER_GPIO6_CLKCTRL,
>>> + CM_MEMIF_EMIF_1_CLKCTRL,
>>> + CM_MEMIF_EMIF_2_CLKCTRL,
>>> + CM_L3INIT_HSUSBOTG_CLKCTRL,
>>> + CM_L3INIT_USBPHY_CLKCTRL,
>>> + CM_L4CFG_L4_CFG_CLKCTRL,
>>> + 0
>>> +};
>>
>> In this series you asked me to convert the base + offset mode of
>> register address definition to struct based register address
>> definition. While doing this I am facing a problem. Please note the
>> above array that contain register addresses. This is a group of
>> registers that control our clock modules. All these registers have
>> similar bit fields and they can be programmed in same manner. So, I
>> keep them in an array and pass the array to a function that iterates
>> through array and does similar processing on all the registers(see
>> below).
>>
>> I am finding it difficult to implement this using the struct based
>> approach. I tried the sample code below:
>>
>> struct my_regs_struct {
>> const unsigned int reg1;
>> const unsigned int reg2;
>> const unsigned int reg3;
>> };
>>
>> static struct my_regs_struct *const my_regs = (struct my_regs_struct
>> *)0x1000;
>>
>> static unsigned int *const reg_arr[] = {
>> &my_regs->reg1,
>> &my_regs->reg3
>> };
>
> Apologies for the hasty mail. Looks like I can solve it by doing
> something like:
>
> static unsigned int *const reg_arr[] = {
> &(((struct my_regs_struct *)0x1000)->reg1),
> &(((struct my_regs_struct *)0x1000)->reg3),
> };
>
> Analyzing this further right now. Hopefully, the issue can be solved
> cleanly.
>

Some more interesting information:

I can reproduce the problem with something as simple as this:

main.c:
const int const1 = 10;
const int const2 = 11;

int arr[] = {
	const1,
	const2
};

$ gcc main.c
main.c:5: error: initializer element is not constant
main.c:5: error: (near initialization for ?arr[0]?)
main.c:7: error: initializer element is not constant
main.c:7: error: (near initialization for ?arr[1]?)


The ARM compiler RVCT happily compiles this without an issue. GCC and
Visual C++ compilers fail!

As a result, I will have to do something like this to populate my
array:

static unsigned int *const reg_arr[] = {
	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->uart_clkctrl),
	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->i2c_clkctrl),
};

Is this acceptable?

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh,

In message <4E00447B.9070804@ti.com> you wrote:
> 
> $ gcc main.c
> main.c:5: error: initializer element is not constant
> main.c:5: error: (near initialization for ?arr[0]?)
> main.c:7: error: initializer element is not constant
> main.c:7: error: (near initialization for ?arr[1]?)

I have to admit that I don't understand either why this error is
raised here; after all, from our understanding of the code these _are_
constant addresses.

You may want to ask this in a compiler group...

> As a result, I will have to do something like this to populate my
> array:
> 
> static unsigned int *const reg_arr[] = {
> 	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->uart_clkctrl),
> 	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->i2c_clkctrl),
> };
> 
> Is this acceptable?

No, please don't.

Note that the following code compiles fine:

----------------------------- snip -----------------------------
#include <stdio.h>

struct my_regs_struct {
	unsigned int reg1;
	unsigned int reg2;
	unsigned int reg3;
};

static struct my_regs_struct *const my_regs = (struct my_regs_struct *) 0x1000;

static void print_regs(void)
{
	unsigned int *const reg_arr[] = {
		&my_regs->reg1,
		&my_regs->reg3,
	};
	printf("regs %p %p \n", (void *)reg_arr[0], (void *)reg_arr[1]);
}

int main(void)
{
	print_regs();
	return 0;
}
----------------------------- snip -----------------------------

With "gcc -Wall -pedantic" you will get warnings "initializer element
is not computable at load time [enabled by default]", but this can be
avoided by adding "--std=c99" to the compiler options.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Wish not to seem, but to be, the best."                  - Aeschylus

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

On Tuesday 21 June 2011 01:50 PM, Wolfgang Denk wrote:
> Dear Aneesh,
>
> In message<4E00447B.9070804@ti.com>  you wrote:
>>
>> $ gcc main.c
>> main.c:5: error: initializer element is not constant
>> main.c:5: error: (near initialization for ?arr[0]?)
>> main.c:7: error: initializer element is not constant
>> main.c:7: error: (near initialization for ?arr[1]?)
>
> I have to admit that I don't understand either why this error is
> raised here; after all, from our understanding of the code these _are_
> constant addresses.
>
> You may want to ask this in a compiler group...

Yes. I will.

>
>> As a result, I will have to do something like this to populate my
>> array:
>>
>> static unsigned int *const reg_arr[] = {
>> 	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->uart_clkctrl),
>> 	&(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)->i2c_clkctrl),
>> };
>>
>> Is this acceptable?
>
> No, please don't.
>
> Note that the following code compiles fine:
>
> ----------------------------- snip -----------------------------
> #include<stdio.h>
>
> struct my_regs_struct {
> 	unsigned int reg1;
> 	unsigned int reg2;
> 	unsigned int reg3;
> };
>
> static struct my_regs_struct *const my_regs = (struct my_regs_struct *) 0x1000;
>
> static void print_regs(void)
> {
> 	unsigned int *const reg_arr[] = {
> 		&my_regs->reg1,
> 		&my_regs->reg3,
> 	};
> 	printf("regs %p %p \n", (void *)reg_arr[0], (void *)reg_arr[1]);
> }

In my function I am using 3 such arrays with quite a few entries in
them. Won't it look ugly besides increasing the stack footprint.

Of course, I can try to break them down to different functions, if need
be.

Or, how about using a utility macro and make it look better like this:

#define OMAP4_PRCM_REG_ADDR(reg)\
	(&(((struct my_regs_struct *)OMAP4_PRCM_BASE)->reg))

static unsigned int *const reg_arr[] = {
     OMAP4_PRCM_REG_ADDR(uart_clkctrl),
     OMAP4_PRCM_REG_ADDR(i2c_clkctrl)
};

This one doesn't generate any warning even with 'gcc -Wall -pedantic'.

Are you not comfortable with getting the address in this manner at all?

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh V,

In message <4E005F9E.8050003@ti.com> you wrote:
>
> In my function I am using 3 such arrays with quite a few entries in
> them. Won't it look ugly besides increasing the stack footprint.

I don;t see a significant difference whether you declare these arrays
inside a function or with file scope.

Regarding the stack footprint: this would actually even be preferrable
(assuming this code is run after relocation to RAM), and from what
I've seen in the example, the compiler actually optimizes the code and
does not really allocate such an array if you don't use it otherwise
(like passing it to other functions).

> Or, how about using a utility macro and make it look better like this:
> 
> #define OMAP4_PRCM_REG_ADDR(reg)\
> 	(&(((struct my_regs_struct *)OMAP4_PRCM_BASE)->reg))

I consider this code too ugly.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Plan to throw one away. You will anyway."
                              - Fred Brooks, "The Mythical Man Month"

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

On Tuesday 21 June 2011 03:52 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4E005F9E.8050003@ti.com>  you wrote:
>>
>> In my function I am using 3 such arrays with quite a few entries in
>> them. Won't it look ugly besides increasing the stack footprint.
>
> I don;t see a significant difference whether you declare these arrays
> inside a function or with file scope.
>
> Regarding the stack footprint: this would actually even be preferrable
> (assuming this code is run after relocation to RAM), and from what

Indeed this runs before relocation. But I think I can keep the array
size to a reasonable level by splitting the function. Also, as you said
if the array is optimized out there should not be any problem.

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

On Tuesday 21 June 2011 02:38 PM, Aneesh V wrote:
> On Tuesday 21 June 2011 01:50 PM, Wolfgang Denk wrote:
>> Dear Aneesh,
>>
>> In message<4E00447B.9070804@ti.com> you wrote:
>>>
>>> $ gcc main.c
>>> main.c:5: error: initializer element is not constant
>>> main.c:5: error: (near initialization for ?arr[0]?)
>>> main.c:7: error: initializer element is not constant
>>> main.c:7: error: (near initialization for ?arr[1]?)
>>
>> I have to admit that I don't understand either why this error is
>> raised here; after all, from our understanding of the code these _are_
>> constant addresses.
>>
>> You may want to ask this in a compiler group...
>
> Yes. I will.

I asked in the GCC mailing list and got this reply. That also seems to
explain why the array as a local variable worked.

http://gcc.gnu.org/ml/gcc/2011-06/msg00291.html

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Aneesh V]

Dear Wolfgang,

On Wednesday 18 May 2011 03:14 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
[snip ...]
>>> NAK.  We do not accept base address plus offset notation.  Please
>>> declare C structs instead.
>>>
>>
>> Ok. will do.
>>
>> Again just curious, what's the reasoning behind this policy? Is it just
>> aesthetics or something more?
>
> It's more.  When using base+offset, the compiler will know nothing
> about the data type, so it canot warn you if you use a 32 bit accessor
> on a 8 bit register, or vice versa.  When you pass a struct element,
> it can check type information.

Is this really valid in our context? readl()/writel() and friends just
cast the address to the target type pointer. I tried writeb() on my 32
bit register represented using the struct approach and the compiler
didn't give any warning (as expected)!

best regards,
Aneesh

[U-Boot] [PATCH v2 13/22] omap4: add clock support

[Wolfgang Denk]

Dear Aneesh V,

In message <4E05CF18.4020800@ti.com> you wrote:
> 
> > It's more.  When using base+offset, the compiler will know nothing
> > about the data type, so it canot warn you if you use a 32 bit accessor
> > on a 8 bit register, or vice versa.  When you pass a struct element,
> > it can check type information.
> 
> Is this really valid in our context? readl()/writel() and friends just
> cast the address to the target type pointer. I tried writeb() on my 32
> bit register represented using the struct approach and the compiler
> didn't give any warning (as expected)!

Yes, we should fix the I/O accessors definitons on ARM to provide
strict type checking.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
 The software required `Windows 95 or better', so I installed Linux.

[U-Boot] [PATCH v2 00/22] U-Boot MMC SPL for OMAP4

[Aneesh V]

Dear Wolfgang,

On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
> This series adds mmc SPL support for OMAP4. This is essentially
> an up-streaming effort for TI's x-loader for OMAP4 using the SPL
> framework
>
> This work partly draws upon previous work done for x-loader by:
> 	Santosh Shilimkar<santosh.shilimkar@ti.com>
> 	Rajendra Nayak<rnayak@ti.com>
> and many others
>
> This series is depedent on the following series:
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/95550
>
> Features supported:
> * Clock init - DPLL locking, clock domains/modules enabling
> * SDRAM/DMM initialization
> * Mux initialization
> * MMC raw read support
> * MMC FAT read support
>
> Improvments over x-loader:
> * Code completely revamped
> * DPLL programming that works for all SYS_CLK frequencies
> * Automatic SDRAM identification and initialization
> * Board dependent parts(especially mux) deferred to u-boot. So, same
>    SPL will work for Panda and SDP and most likely on any other board
>    that comes along
> * Determination of u-boot size to avoid reading extra content while
>    loading U-Boot
> * Modular apporach to enable future addition of support for all OMAP3/4
>    platforms
>
> V2:
> * Some fixes in SDRAM init, clock init
> * Use of pre-calculated M&  N values for DPLL locking instead
>    run-time calculation
> * Change in make files to allow reuse of common rules
>    between boards
> * Console initialization moved further earlier in the boot
>    allowing traces from even clock initialization code
> * Reuse utility macros from a previous series
>
> Aneesh V (21):
>    omap4: add OMAP4430 revision check
>    armv7: start.S: provide a hook for saving boot params
>    omap4: save parameters passed by ROM code to SPL
>    arm: new labels in the linker script file
>    Add generic spl infrastructure
>    armv7: start.S: add SPL support
>    omap: add spl support
>    omap4: add spl support for OMAP4 SDP
>    omap4: utility function to identify the context of hw init
>    omap4: separate mux settings into essential and non essential parts
>    omap4: correct mux data for sdp4430
>    omap4: add clock support
>    omap4: add serial console support to SPL
>    omap4: add sdram init support
>    omap4: calculate EMIF register values
>    omap4: automatic sdram detection
>    armv7: embed u-boot size within u-boot for use from SPL
>    omap: add MMC support to SPL
>    omap: spl: add FAT support over MMC
>    omap4: add spl support for OMAP4 Panda
>    omap: spl: add more debug traces
>
> John Rigby (1):
>    mkimage: Add OMAP boot image support
>

This work has mainly two parts:
1. Add the missing hardware support for OMAP4 such as clock init, sdram
init etc (OMAP4 u-boot worked without these because it was always
prececeded by x-loader)
2. Addd SPL support.

Now that SPL framework design is taking time, I was wondering whether I
should split the series into two based on the two main tasks above.

That is, I can send out the hw initialization part immediately without
waiting for the SPL design to be finalized and send out the SPL support
once we concluded the SPL design discussions.

The patches themselves will not change much. Just that they will be
separated into two different series. The reviews done so far will not
be wasted.

Are you Ok with this approach?

best regards,
Aneesh

[U-Boot] [PATCH v2 22/22] omap: spl: add more debug traces

[Aneesh V]

Dear Wolfgang,

On Wednesday 15 June 2011 03:48 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>

[snip ..]

>> No. That wouldn't serve the purpose. I need two macros to distinguish
>> between the two cases.
>> 1. 'debug()' - can be used in all places at which console is guaranteed
>> to be initialized whether executed as part of U-Boot or SPL.
>> 2. 'spl_debug()' to be used at places where console is initialized for
>> SPL but not for U-Boot (eg. lowlevel_init()) - so emit no code for
>> U-Boot.
>
> You see - this distinction is becoming a mess.  Let's get rid of this
> and use common code for both cases.

I replaced spl_debug() with debug() now. I moved sdram_init() out of
lowlevel_init() for u-boot so that console is available by the time
sdram_init() runs.

However, clock init needs to remain in lowlevel_init() and I still feel
that some debug traces from this module will be a good debugging tool
for SPL, so I retained the traces and added something like this in
arch/arm/cpu/armv7/omap4/clocks.c:


/*
  * printing to console doesn't work unless
  * this code is executed from SPL
  */
#ifndef CONFIG_PRELOADER
#define printf(fmt, args...)
#define puts(s)
#endif

Is that fine?

best regards,
Aneesh

[U-Boot] [PATCH v3 00/12] U-Boot MMC SPL for OMAP4

[Aneesh V]

This series adds mmc SPL support for OMAP4. This is essentially
an up-streaming effort for TI's x-loader for OMAP4 using the SPL
framework

This work partly draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>
and many others

This series depends on the following series for the new SPL framework:
http://marc.info/?l=u-boot&m=131056990001719&w=2

Features supported:
* Clock init - DPLL locking, clock domains/modules enabling
* SDRAM/DMM initialization
* Mux initialization
* MMC raw read support
* MMC FAT read support

Improvments over x-loader:
* Code completely revamped
* DPLL programming that works for all SYS_CLK frequencies
* Automatic SDRAM identification and initialization
* Board dependent parts(especially mux) deferred to u-boot. So, same
  SPL will work for Panda and SDP and most likely on any other board
  that comes along
* Flexible about the payload. Any image with a mkimage header can be
  loaded.
* The core SPL logic is generic and available for OMAP3/4. So, OMAP3
  platforms can easily extend this work to add SPL support for the
  respective boards.

V2:
* Some fixes in SDRAM init, clock init
* Use of pre-calculated M & N values for DPLL locking instead
  run-time calculation
* Change in make files to allow reuse of common rules
  between boards
* Console initialization moved further earlier in the boot
  allowing traces from even clock initialization code
* Reuse utility macros from a previous series

V3:
* Moved to the new SPL framework
* struct based register access for clock init
* Squashed together related patches as per Wolfgang's suggestions
* Re-organization of code in sdram init for better readability
* SPL loading the payload using mkimage header
* Avoided using custom bit-field accessor macros
* Several other minor changes(documented in respective patches)

Aneesh V (11):
  omap4: utility function to identify the context of hw init
  omap4: cleanup pin mux data
  omap4: add OMAP4430 revision check
  omap4: add clock support
  omap4: add sdram init support
  omap4: calculate EMIF register values
  omap4: automatic sdram detection
  armv7: start.S: fixes and enhancements for SPL
  omap: add basic SPL support
  Correct ih_os for u-boot.img
  omap: add MMC and FAT support to SPL

John Rigby (1):
  mkimage: Add OMAP boot image support

 Makefile                                           |    2 +-
 arch/arm/cpu/armv7/Makefile                        |    7 +-
 arch/arm/cpu/armv7/cpu.c                           |    7 +
 arch/arm/cpu/armv7/omap-common/Makefile            |    5 +
 arch/arm/cpu/armv7/omap-common/spl.c               |  272 ++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds      |   62 +
 arch/arm/cpu/armv7/omap-common/utils.c             |   57 +
 arch/arm/cpu/armv7/omap4/Makefile                  |    6 +
 arch/arm/cpu/armv7/omap4/board.c                   |  161 +++-
 arch/arm/cpu/armv7/omap4/clocks.c                  |  842 +++++++++++++
 .../panda => arch/arm/cpu/armv7/omap4}/config.mk   |   25 +-
 arch/arm/cpu/armv7/omap4/emif.c                    | 1305 ++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  282 +++++
 arch/arm/cpu/armv7/start.S                         |   51 +-
 arch/arm/cpu/armv7/u-boot.lds                      |    2 +
 arch/arm/include/asm/arch-omap4/clocks.h           |  664 ++++++++++
 arch/arm/include/asm/arch-omap4/emif.h             | 1034 ++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |   52 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |   72 ++-
 arch/arm/include/asm/armv7.h                       |    5 +
 arch/arm/include/asm/omap_common.h                 |   56 +
 board/ti/panda/Makefile                            |    2 +
 board/ti/panda/panda.c                             |   25 +-
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +-
 board/ti/sdp4430/Makefile                          |    2 +
 board/ti/sdp4430/config.mk                         |   31 -
 board/ti/sdp4430/sdp.c                             |   25 +-
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +--
 common/image.c                                     |    9 +-
 include/configs/omap4_panda.h                      |   37 +
 include/configs/omap4_sdp4430.h                    |   37 +
 include/image.h                                    |    1 +
 spl/Makefile                                       |    6 +
 tools/Makefile                                     |    2 +
 tools/mkimage.c                                    |    2 +
 tools/mkimage.h                                    |    1 +
 tools/omap/clocks_get_m_n.c                        |  197 +++
 tools/omapimage.c                                  |  224 ++++
 tools/omapimage.h                                  |   50 +
 41 files changed, 5668 insertions(+), 263 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 rename {board/ti/panda => arch/arm/cpu/armv7/omap4}/config.mk (64%)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
 create mode 100644 arch/arm/include/asm/omap_common.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 delete mode 100644 board/ti/sdp4430/config.mk
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)
 create mode 100644 tools/omap/clocks_get_m_n.c
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

[U-Boot] [PATCH v3 01/12] omap4: utility function to identify the context of hw init

[Aneesh V]

The basic hardware init of OMAP4(s_init()) can happen in 4
different contexts:
 1. SPL running from SRAM
 2. U-Boot running from FLASH
 3. Non-XIP U-Boot loaded to SDRAM by SPL
 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
    Configuration Header feature

What level of hw initialization gets done depends on this
context. Add a utility function to find this context.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Changed the context names to more meaningful names as
  suggested by WD
---
 arch/arm/include/asm/arch-omap4/sys_proto.h |   49 ++++++++++++++++++++++++++-
 arch/arm/include/asm/omap_common.h          |   34 ++++++++++++++++++
 2 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/omap_common.h

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4fa4f4b..6b596b4 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -23,10 +23,12 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;
 };
+extern const struct omap_sysinfo sysinfo;
 
 void gpmc_init(void);
 void watchdog_init(void);
@@ -37,6 +39,51 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 
-extern const struct omap_sysinfo sysinfo;
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
 
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..d80f665
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+#endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v3 02/12] omap4: cleanup pin mux data

[Aneesh V]

- separate mux settings into essential and non essential parts
- essential part is board independent as of now(so move it
  to SoC directory). Will help in having single SPL for all
  boards.
- Non-essential part(the pins not essential for u-boot to function)
  need to be phased out eventually.
- Correct mux data by aligning to the latest settings in x-loader

Signed-off-by: Aneesh V <aneesh@ti.com>
---
This patch add 33 warnings for lines over 80 characters.
However, this for the mux table and improves readability.

V3:
* Squashed two mux related patches into one
---
 arch/arm/cpu/armv7/omap4/board.c                   |   53 ++++++++-
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    4 +-
 board/ti/panda/panda.c                             |   25 +---
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +++---------
 board/ti/sdp4430/sdp.c                             |   25 +---
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +++++++------------
 7 files changed, 209 insertions(+), 178 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index de4cc2a..3fd6f84 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -31,17 +31,65 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing,  andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ *	Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 }
 
 /*
@@ -124,7 +172,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 6b596b4..3624378 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
@@ -33,7 +34,8 @@ extern const struct omap_sysinfo sysinfo;
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/panda/panda_mux_data.h
similarity index 76%
rename from board/ti/sdp4430/sdp.h
rename to board/ti/panda/panda_mux_data.h
index bf41067..16cc0ad 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -207,11 +173,11 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,13 +216,15 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/sdp4430/sdp4430_mux_data.h
similarity index 67%
rename from board/ti/panda/panda.h
rename to board/ti/sdp4430/sdp4430_mux_data.h
index e3d090e..16cc0ad 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v3 03/12] omap4: add OMAP4430 revision check

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Added a revision string in addition to the revision number
  Helps in printing out the OMAP revision at bootup

V3:
 * Improved the revision check function by saving the
   value instead of finding it every time.
 * Improved revision string function by generating it
   from the revision rather than hard-coding the string
   per revision
---
 arch/arm/cpu/armv7/omap4/board.c            |   64 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |   29 +++++++++---
 arch/arm/include/asm/arch-omap4/sys_proto.h |    7 +++
 arch/arm/include/asm/armv7.h                |    5 ++
 4 files changed, 97 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 3fd6f84..09861a9 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
@@ -35,6 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
@@ -72,6 +75,66 @@ static void set_mux_conf_regs(void)
 	}
 }
 
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+static void init_omap4_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int arm_rev = cortex_a9_rev();
+
+	switch (arm_rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		*omap4_revision = OMAP4430_ES1_0;
+		break;
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
+			*omap4_revision = OMAP4430_ES2_1;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
+			*omap4_revision = OMAP4430_ES2_2;
+			break;
+		default:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		*omap4_revision = OMAP4430_ES2_3;
+		break;
+	default:
+		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
+		break;
+	}
+}
+
+void omap_rev_string(char *omap4_rev_string)
+{
+	u32 omap4_rev = omap_revision();
+	u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
+	u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
+	u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
+
+	sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+		minor_rev);
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -88,6 +151,7 @@ static void set_mux_conf_regs(void)
  */
 void s_init(void)
 {
+	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
 }
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..76b06c2 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,15 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -119,13 +128,17 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+#define LOW_LEVEL_SRAM_STACK		NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3624378..c10fa18 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -40,6 +40,7 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap4_rev_string);
 
 static inline u32 running_from_sdram(void)
 {
@@ -88,4 +89,10 @@ static inline u32 omap4_hw_init_context(void)
 #endif
 }
 
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap4_revision;
+	return *omap4_revision;
+}
+
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 88b9c62..b5784d8 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -25,6 +25,11 @@
 #define ARMV7_H
 #include <linux/types.h>
 
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
 #define CCSIDR_LINE_SIZE_MASK		0x7
-- 
1.7.0.4

[U-Boot] [PATCH v3 04/12] omap4: add clock support

[Aneesh V]

Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Use pre-calculated M & N values instead of calculated ones
* Changes due to make file changes
* Some corrections
* Do all clock initialization in SPL itself instead of differing some
  work to u-boot

V3:
* Use struct for register addressing
* Support only Turbo OPP for MPU. OPP's above this need Smart Reflex
  enabled
* Cleaned up the scale_vcore(). Now takes into account the differing
  voltage offsets for different revisions of Phoenix.
* Removed references to deprecated utility functions - modify_reg_32() etc.
* Changed all spl_debug() to debug()
* Moved the host-program for calculating DPLL multiplier/divider to
  tools/omap/ directory. Added more documentation
* Replaced calls to omap4_revision() with omap_revision()
* Some changes to IVA and ABE dpll locking code
---
 arch/arm/cpu/armv7/omap4/Makefile           |    1 +
 arch/arm/cpu/armv7/omap4/board.c            |    1 +
 arch/arm/cpu/armv7/omap4/clocks.c           |  809 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/clocks.h    |  664 ++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    8 +
 arch/arm/include/asm/omap_common.h          |    3 +
 tools/omap/clocks_get_m_n.c                 |  197 +++++++
 7 files changed, 1683 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 tools/omap/clocks_get_m_n.c

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..ac4b2a6 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,6 +28,7 @@ LIB	=  $(obj)lib$(SOC).o
 SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
+COBJS	+= clocks.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 09861a9..1c26a66 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -154,6 +154,7 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..e8d3a52
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,809 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
+
+static const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */
+static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
+	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{330, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{165, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{396, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{88, 2, 1, -1, -1, -1, -1, -1},		/* 27 MHz   */
+	{165, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* dpll locked at 1200 MHz - MPU clk@600 MHz */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
+	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1
+};
+
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	u32 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl(&prcm->cm_sys_clksel) &
+			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_FAST_RELOCK_BYPASS <<
+			CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+				LDELAY)) {
+		printf("Bypassing DPLL failed %p\n", base);
+	}
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
+		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+		&dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for %p\n", base);
+		hang();
+	}
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+				u8 lock)
+{
+	u32 temp;
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	switch (omap_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_1524mhz[sysclk_ind];
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		 /* safest */
+		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+	default:
+		return &core_dpll_params_1600mhz[sysclk_ind];
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz;
+	const struct dpll_params *core_dpll_params;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params();
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+static void setup_dplls(void)
+{
+	u32 sysclk_ind, temp;
+	const struct dpll_params *params;
+	debug("setup_dplls\n");
+
+	sysclk_ind = get_sys_clk_index();
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, &prcm->cm_clksel_core);
+	debug("Core DPLL configured\n");
+
+	/* lock PER dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+	debug("PER DPLL locked\n");
+
+	/* MPU dpll */
+	if (omap_revision() == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, abe_ref_clk;
+	u32 sysclk_ind, sd_div, num, den;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/* IVA */
+	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
+			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
+
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = &usb_dpll_params_1920mhz[sysclk_ind];
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
+
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+	params = &abe_dpll_params_32k_196608khz;
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+	/*
+	 * We need to enable some additional options to achieve
+	 * 196.608MHz from 32768 Hz
+	 */
+	setbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
+			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
+			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
+			CM_CLKMODE_DPLL_REGM4XEN_MASK);
+	/* Spend 4 REFCLK cycles at each stage */
+	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
+			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+#endif
+
+	/* Select the right reference clk */
+	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
+	/* Lock the dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+{
+	u32 temp, offset_code;
+	u32 step = 12660; /* 12.66 mV represented in uV */
+	u32 offset = volt_mv;
+
+	/* convert to uV for better accuracy in the calculations */
+	offset *= 1000;
+
+	if (omap_revision() == OMAP4430_ES1_0)
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+	else
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+	offset_code = (offset + step - 1) / step;
+	/* The code starts at 1 not 0 */
+	offset_code++;
+
+	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+		offset_code);
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, &prcm->prm_vc_val_bypass);
+	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				&prcm->prm_vc_val_bypass, LDELAY)) {
+		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+	}
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+
+	/*
+	 * VCORE 1 - 4430 : supplies vdd_mpu
+	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+	 * We use the maximum possible value in the AVS range because the next
+	 * higher voltage in the discrete range (code >= 0b111010) is way too
+	 * high
+	 */
+	volt = 1417;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+	/* VCORE 2 - supplies vdd_iva */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/* VCORE 3 - supplies vdd_core */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+				clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 1;
+	u32 *const clk_domains_essential[] = {
+		&prcm->cm_l4per_clkstctrl,
+		&prcm->cm_l3init_clkstctrl,
+		&prcm->cm_memif_clkstctrl,
+		&prcm->cm_l4cfg_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_wkup_gpio1_clkctrl,
+		&prcm->cm_l4per_gpio2_clkctrl,
+		&prcm->cm_l4per_gpio3_clkctrl,
+		&prcm->cm_l4per_gpio4_clkctrl,
+		&prcm->cm_l4per_gpio5_clkctrl,
+		&prcm->cm_l4per_gpio6_clkctrl,
+		&prcm->cm_memif_emif_1_clkctrl,
+		&prcm->cm_memif_emif_2_clkctrl,
+		&prcm->cm_l3init_hsusbotg_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_l4cfg_l4_cfg_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_essential[] = {
+		&prcm->cm_l4per_gptimer2_clkctrl,
+		&prcm->cm_l3init_hsmmc1_clkctrl,
+		&prcm->cm_l3init_hsmmc2_clkctrl,
+		&prcm->cm_l4per_mcspi1_clkctrl,
+		&prcm->cm_wkup_gptimer1_clkctrl,
+		&prcm->cm_l4per_i2c1_clkctrl,
+		&prcm->cm_l4per_i2c2_clkctrl,
+		&prcm->cm_l4per_i2c3_clkctrl,
+		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_l4per_uart3_clkctrl,
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 0;
+	u32 *const clk_domains_non_essential[] = {
+		&prcm->cm_mpu_m3_clkstctrl,
+		&prcm->cm_ivahd_clkstctrl,
+		&prcm->cm_dsp_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sgx_clkstctrl,
+		&prcm->cm1_abe_clkstctrl,
+		&prcm->cm_c2c_clkstctrl,
+		&prcm->cm_cam_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sdma_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_non_essential[] = {
+		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
+		&prcm->cm_ivahd_ivahd_clkctrl,
+		&prcm->cm_ivahd_sl2_clkctrl,
+		&prcm->cm_dsp_dsp_clkctrl,
+		&prcm->cm_l3_2_gpmc_clkctrl,
+		&prcm->cm_l3instr_l3_3_clkctrl,
+		&prcm->cm_l3instr_l3_instr_clkctrl,
+		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
+		&prcm->cm_l3init_hsi_clkctrl,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_non_essential[] = {
+		&prcm->cm1_abe_aess_clkctrl,
+		&prcm->cm1_abe_pdm_clkctrl,
+		&prcm->cm1_abe_dmic_clkctrl,
+		&prcm->cm1_abe_mcasp_clkctrl,
+		&prcm->cm1_abe_mcbsp1_clkctrl,
+		&prcm->cm1_abe_mcbsp2_clkctrl,
+		&prcm->cm1_abe_mcbsp3_clkctrl,
+		&prcm->cm1_abe_slimbus_clkctrl,
+		&prcm->cm1_abe_timer5_clkctrl,
+		&prcm->cm1_abe_timer6_clkctrl,
+		&prcm->cm1_abe_timer7_clkctrl,
+		&prcm->cm1_abe_timer8_clkctrl,
+		&prcm->cm1_abe_wdt3_clkctrl,
+		&prcm->cm_l4per_gptimer9_clkctrl,
+		&prcm->cm_l4per_gptimer10_clkctrl,
+		&prcm->cm_l4per_gptimer11_clkctrl,
+		&prcm->cm_l4per_gptimer3_clkctrl,
+		&prcm->cm_l4per_gptimer4_clkctrl,
+		&prcm->cm_l4per_hdq1w_clkctrl,
+		&prcm->cm_l4per_mcbsp4_clkctrl,
+		&prcm->cm_l4per_mcspi2_clkctrl,
+		&prcm->cm_l4per_mcspi3_clkctrl,
+		&prcm->cm_l4per_mcspi4_clkctrl,
+		&prcm->cm_l4per_mmcsd3_clkctrl,
+		&prcm->cm_l4per_mmcsd4_clkctrl,
+		&prcm->cm_l4per_mmcsd5_clkctrl,
+		&prcm->cm_l4per_uart1_clkctrl,
+		&prcm->cm_l4per_uart2_clkctrl,
+		&prcm->cm_l4per_uart4_clkctrl,
+		&prcm->cm_wkup_keyboard_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_cam_iss_clkctrl,
+		&prcm->cm_cam_fdif_clkctrl,
+		&prcm->cm_dss_dss_clkctrl,
+		&prcm->cm_sgx_sgx_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
+		0
+	};
+
+	/* Enable optional functional clock for ISS */
+	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable all optional functional clocks of DSS */
+	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
+	     i++) {
+		enable_clock_module(clk_modules_explicit_en_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+
+	/* Put camera module in no sleep mode */
+	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+	freq_config1 |= (core_dpll_params->m2 <<
+			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+	writel(freq_config1, &prcm->cm_shadow_freq_config1);
+	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+				&prcm->cm_shadow_freq_config1, LDELAY)) {
+		puts("FREQ UPDATE procedure failed!!");
+		hang();
+	}
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+}
+
+void bypass_dpll(u32 *const base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 *const base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..71db39c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,664 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+
+struct omap4_prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 pad001[1];
+	u32 cm_clksel_abe;
+	u32 pad002[1];
+	u32 cm_dll_ctrl;
+	u32 pad003[3];
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 pad004[3];
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 pad005[5];
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 pad006[3];
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 pad007[2];
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 pad008[2];
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 pad009[3];
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 pad010[4];
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 pad011[4];
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 pad012[1];
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 pad013[1];
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 pad014[5];
+	u32 cm_shadow_freq_config1;
+
+	/* cm1.dsp */
+	u32 pad015[103];
+	u32 cm_dsp_clkstctrl;
+	u32 pad016[7];
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 pad017[55];
+	u32 cm1_abe_clkstctrl;
+	u32 pad018[7];
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 pad019[1];
+	u32 cm1_abe_aess_clkctrl;
+	u32 pad020[1];
+	u32 cm1_abe_pdm_clkctrl;
+	u32 pad021[1];
+	u32 cm1_abe_dmic_clkctrl;
+	u32 pad022[1];
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 pad023[1];
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 pad024[1];
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 pad025[1];
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 pad026[1];
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 pad027[1];
+	u32 cm1_abe_timer5_clkctrl;
+	u32 pad028[1];
+	u32 cm1_abe_timer6_clkctrl;
+	u32 pad029[1];
+	u32 cm1_abe_timer7_clkctrl;
+	u32 pad030[1];
+	u32 cm1_abe_timer8_clkctrl;
+	u32 pad031[1];
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 pad032[3805];
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 pad033[1];
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 pad034[1];
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 pad035[1];
+	u32 cm_iva_dvfs_current;
+	u32 pad036[1];
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 pad037[3];
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 pad038[5];
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 pad039[1];
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 pad040[2];
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 pad041[5];
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+	/* cm2.core */
+	u32 pad0411[324];
+	u32 cm_l3_1_clkstctrl;
+	u32 pad042[1];
+	u32 cm_l3_1_dynamicdep;
+	u32 pad043[5];
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 pad044[55];
+	u32 cm_l3_2_clkstctrl;
+	u32 pad045[1];
+	u32 cm_l3_2_dynamicdep;
+	u32 pad046[5];
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 pad047[1];
+	u32 cm_l3_2_gpmc_clkctrl;
+	u32 pad048[1];
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 pad049[51];
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 pad050[5];
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 pad051[55];
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 pad052[5];
+	u32 cm_sdma_sdma_clkctrl;
+	u32 pad053[55];
+	u32 cm_memif_clkstctrl;
+	u32 pad054[7];
+	u32 cm_memif_dmm_clkctrl;
+	u32 pad055[1];
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 pad056[1];
+	u32 cm_memif_emif_1_clkctrl;
+	u32 pad057[1];
+	u32 cm_memif_emif_2_clkctrl;
+	u32 pad058[1];
+	u32 cm_memif_dll_clkctrl;
+	u32 pad059[3];
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 pad060[1];
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 pad061[1];
+	u32 cm_memif_dll_h_clkctrl;
+	u32 pad062[39];
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 pad063[5];
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 pad064[1];
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 pad065[1];
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 pad066[51];
+	u32 cm_l4cfg_clkstctrl;
+	u32 pad067[1];
+	u32 cm_l4cfg_dynamicdep;
+	u32 pad068[5];
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 pad069[1];
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 pad070[1];
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 pad071[1];
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 pad072[49];
+	u32 cm_l3instr_clkstctrl;
+	u32 pad073[7];
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 pad074[1];
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 pad075[5];
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+
+	/* cm2.ivahd */
+	u32 pad076[47];
+	u32 cm_ivahd_clkstctrl;
+	u32 pad077[7];
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 pad078[1];
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 pad079[53];
+	u32 cm_cam_clkstctrl;
+	u32 pad080[7];
+	u32 cm_cam_iss_clkctrl;
+	u32 pad081[1];
+	u32 cm_cam_fdif_clkctrl;
+
+	/* cm2.dss */
+	u32 pad082[53];
+	u32 cm_dss_clkstctrl;
+	u32 pad083[7];
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 pad084[55];
+	u32 cm_sgx_clkstctrl;
+	u32 pad085[7];
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 pad086[55];
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 pad087[9];
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 pad088[1];
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 pad089[1];
+	u32 cm_l3init_hsi_clkctrl;
+	u32 pad090[7];
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 pad091[1];
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 pad092[1];
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 pad093[3];
+	u32 cm_l3init_p1500_clkctrl;
+	u32 pad094[21];
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 pad095[3];
+	u32 cm_l3init_usbphy_clkctrl;
+
+	/* cm2.l4per */
+	u32 pad096[7];
+	u32 cm_l4per_clkstctrl;
+	u32 pad097[1];
+	u32 cm_l4per_dynamicdep;
+	u32 pad098[5];
+	u32 cm_l4per_adc_clkctrl;
+	u32 pad100[1];
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 pad101[1];
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 pad102[1];
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 pad103[1];
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 pad104[1];
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 pad105[1];
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 pad106[1];
+	u32 cm_l4per_elm_clkctrl;
+	u32 pad107[1];
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 pad108[1];
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 pad109[1];
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 pad110[1];
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 pad111[1];
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 pad112[1];
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 pad113[1];
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 pad114[1];
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 pad115[1];
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 pad116[1];
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 pad117[1];
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 pad118[1];
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 pad119[1];
+	u32 cm_l4per_l4per_clkctrl;
+	u32 pad1191[3];
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 pad120[1];
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 pad121[1];
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 pad122[1];
+	u32 cm_l4per_mgate_clkctrl;
+	u32 pad123[1];
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 pad124[1];
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 pad125[1];
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 pad126[1];
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 pad127[5];
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 pad128[1];
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 pad129[1];
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 pad130[1];
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 pad131[1];
+	u32 cm_l4per_uart1_clkctrl;
+	u32 pad132[1];
+	u32 cm_l4per_uart2_clkctrl;
+	u32 pad133[1];
+	u32 cm_l4per_uart3_clkctrl;
+	u32 pad134[1];
+	u32 cm_l4per_uart4_clkctrl;
+	u32 pad135[1];
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 pad136[1];
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 pad137[5];
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 pad138[5];
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 pad139[1];
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 pad140[1];
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 pad141[1];
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 pad142[1];
+	u32 cm_l4sec_rng_clkctrl;
+	u32 pad143[1];
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 pad144[3];
+	u32 cm_l4sec_cryptodma_clkctrl;
+	u32 pad145[776841];
+
+	/* l4 wkup regs */
+	u32 pad201[6211];
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 pad202[1467];
+	u32 cm_wkup_clkstctrl;
+	u32 pad203[7];
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 pad204;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 pad205;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 pad206;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 pad207;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 pad208;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 pad209;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 pad210;
+	u32 cm_wkup_usim_clkctrl;
+	u32 pad211;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 pad212[5];
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 pad213;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 pad214;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 pad215[197];
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_channel;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#define NUM_SYS_CLKS	7
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	u32 m;
+	u32 n;
+	u8 m2;
+	u8 m3;
+	u8 m4;
+	u8 m5;
+	u8 m6;
+	u8 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index c10fa18..f871921 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,6 +22,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/arch/omap4.h>
+#include <asm/arch/clocks.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mux_omap4.h>
@@ -31,6 +32,8 @@ struct omap_sysinfo {
 };
 extern const struct omap_sysinfo sysinfo;
 
+extern struct omap4_prcm_regs *const prcm;
+
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
@@ -41,6 +44,11 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d80f665..33caa4e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL			0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c
new file mode 100644
index 0000000..cfc1760
--- /dev/null
+++ b/tools/omap/clocks_get_m_n.c
@@ -0,0 +1,197 @@
+/*
+ * Program for finding M & N values for DPLLs
+ * To be run on Host PC
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <stdlib.h>
+#include <stdio.h>
+typedef unsigned int u32;
+#define MAX_N	127
+
+/*
+ * get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N)
+ * values based on the reference frequency, required output frequency,
+ * maximum tolerance for output frequency etc.
+ *
+ * target_freq_khz - output frequency required in KHz
+ * ref_freq_khz - reference(input) frequency in KHz
+ * m - pointer to computed M value
+ * n - pointer to computed N value
+ * tolerance_khz - tolerance for the output frequency. When the algorithm
+ * succeeds in finding vialble M and N values the corresponding output
+ * frequency will be in the range:
+ *	[target_freq_khz - tolerance_khz, target_freq_khz]
+ *
+ * Formula:
+ *	Fdpll = (2 * M * Fref) / (N + 1)
+ *
+ * Considerations for lock-time:
+ *	- Smaller the N, better lock-time, especially lock-time will be
+ *	- For acceptable lock-times:
+ *		Fref / (M + 1) >= 1 MHz
+ *
+ * Considerations for power:
+ *	- The difference in power for different N values giving the same
+ *	  output is negligible. So, we optimize for lock-time
+ *
+ * Hard-constraints:
+ *	- N can not be greater than 127(7 bit field for representing N)
+ *
+ * Usage:
+ *	$ gcc clocks_get_m_n.c
+ *	$ ./a.out
+ */
+int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n,
+			u32 tolerance_khz)
+{
+	u32 min_freq = target_freq_khz - tolerance_khz;
+	u32 max_freq = target_freq_khz;
+	u32 freq, freq_old;
+	*n = 1;
+	while (1) {
+		*m = min_freq / ref_freq_khz / 2 * (*n) ;
+		freq_old = 0;
+		while (1) {
+			freq = ref_freq_khz * 2 * (*m) / (*n);
+			if (abs(target_freq_khz - freq_old) <=
+				abs(target_freq_khz - freq)) {
+				freq = freq_old;
+				(*m)--;
+				break;
+			}
+			(*m)++;
+			freq_old = freq;
+		}
+		if (freq >= min_freq && freq <= max_freq)
+			break;
+		(*n)++;
+		if ((*n) > MAX_N + 1) {
+			printf("ref %d m %d n %d target %d : ",
+				ref_freq_khz, *m, *n, target_freq_khz);
+			printf("can not find m & n - please consider"
+				" increasing tolerance\n");
+			return -1;
+		}
+	}
+	(*n)--;
+	printf("ref %d m %d n %d target %d locked %d\n",
+		ref_freq_khz, *m, *n, target_freq_khz, freq);
+	if ((ref_freq_khz / (*n + 1)) < 1000) {
+		printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than"
+			" ideal, locking time will be high!\n");
+	}
+	return 0;
+}
+
+void main(void)
+{
+	u32 m, n;
+	printf("\nMPU - 2000000\n");
+	get_m_n_optimized(2000000, 12000, &m, &n, 0);
+	get_m_n_optimized(2000000, 13000, &m, &n, 0);
+	get_m_n_optimized(2000000, 16800, &m, &n, 800);
+	get_m_n_optimized(2000000, 19200, &m, &n, 0);
+	get_m_n_optimized(2000000, 26000, &m, &n, 0);
+	get_m_n_optimized(2000000, 27000, &m, &n, 0);
+	get_m_n_optimized(2000000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1200000\n");
+	get_m_n_optimized(1200000, 12000, &m, &n, 0);
+	get_m_n_optimized(1200000, 13000, &m, &n, 0);
+	get_m_n_optimized(1200000, 16800, &m, &n, 800);
+	get_m_n_optimized(1200000, 19200, &m, &n, 0);
+	get_m_n_optimized(1200000, 26000, &m, &n, 0);
+	get_m_n_optimized(1200000, 27000, &m, &n, 0);
+	get_m_n_optimized(1200000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1584000\n");
+	get_m_n_optimized(1584000, 12000, &m, &n, 0);
+	get_m_n_optimized(1584000, 13000, &m, &n, 0);
+	get_m_n_optimized(1584000, 16800, &m, &n, 400);
+	get_m_n_optimized(1584000, 19200, &m, &n, 0);
+	get_m_n_optimized(1584000, 26000, &m, &n, 0);
+	get_m_n_optimized(1584000, 27000, &m, &n, 0);
+	get_m_n_optimized(1584000, 38400, &m, &n, 0);
+
+	printf("\nCore 1600000\n");
+	get_m_n_optimized(1600000, 12000, &m, &n, 0);
+	get_m_n_optimized(1600000, 13000, &m, &n, 0);
+	get_m_n_optimized(1600000, 16800, &m, &n, 200);
+	get_m_n_optimized(1600000, 19200, &m, &n, 0);
+	get_m_n_optimized(1600000, 26000, &m, &n, 0);
+	get_m_n_optimized(1600000, 27000, &m, &n, 0);
+	get_m_n_optimized(1600000, 38400, &m, &n, 0);
+
+	printf("\nPER 1536000\n");
+	get_m_n_optimized(1536000, 12000, &m, &n, 0);
+	get_m_n_optimized(1536000, 13000, &m, &n, 0);
+	get_m_n_optimized(1536000, 16800, &m, &n, 0);
+	get_m_n_optimized(1536000, 19200, &m, &n, 0);
+	get_m_n_optimized(1536000, 26000, &m, &n, 0);
+	get_m_n_optimized(1536000, 27000, &m, &n, 0);
+	get_m_n_optimized(1536000, 38400, &m, &n, 0);
+
+	printf("\nIVA 1862000\n");
+	get_m_n_optimized(1862000, 12000, &m, &n, 0);
+	get_m_n_optimized(1862000, 13000, &m, &n, 0);
+	get_m_n_optimized(1862000, 16800, &m, &n, 0);
+	get_m_n_optimized(1862000, 19200, &m, &n, 900);
+	get_m_n_optimized(1862000, 26000, &m, &n, 0);
+	get_m_n_optimized(1862000, 27000, &m, &n, 0);
+	get_m_n_optimized(1862000, 38400, &m, &n, 800);
+
+	printf("\nABE 196608 sys clk\n");
+	get_m_n_optimized(196608, 12000, &m, &n, 700);
+	get_m_n_optimized(196608, 13000, &m, &n, 200);
+	get_m_n_optimized(196608, 16800, &m, &n, 700);
+	get_m_n_optimized(196608, 19200, &m, &n, 400);
+	get_m_n_optimized(196608, 26000, &m, &n, 200);
+	get_m_n_optimized(196608, 27000, &m, &n, 900);
+	get_m_n_optimized(196608, 38400, &m, &n, 0);
+
+	printf("\nABE 196608 32K\n");
+	get_m_n_optimized(196608000/4, 32768, &m, &n, 0);
+
+	printf("\nUSB 1920000\n");
+	get_m_n_optimized(1920000, 12000, &m, &n, 0);
+	get_m_n_optimized(1920000, 13000, &m, &n, 0);
+	get_m_n_optimized(1920000, 16800, &m, &n, 0);
+	get_m_n_optimized(1920000, 19200, &m, &n, 0);
+	get_m_n_optimized(1920000, 26000, &m, &n, 0);
+	get_m_n_optimized(1920000, 27000, &m, &n, 0);
+	get_m_n_optimized(1920000, 38400, &m, &n, 0);
+
+	printf("\nCore ES1 1523712\n");
+	get_m_n_optimized(1524000, 12000, &m, &n, 100);
+	get_m_n_optimized(1524000, 13000, &m, &n, 0);
+	get_m_n_optimized(1524000, 16800, &m, &n, 0);
+	get_m_n_optimized(1524000, 19200, &m, &n, 0);
+	get_m_n_optimized(1524000, 26000, &m, &n, 0);
+	get_m_n_optimized(1524000, 27000, &m, &n, 0);
+
+	/* exact recommendation for SDPs */
+	get_m_n_optimized(1523712, 38400, &m, &n, 0);
+
+}
-- 
1.7.0.4

[U-Boot] [PATCH v3 05/12] omap4: add sdram init support

[Aneesh V]

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Minor corrections in do_lpddr2_init()
* Minor corrections to read_idle interval calculation
* Sanity test of memory after doing the initialization
* Fixed warnings reported with with latest GCC compilers
V3:
* Removed references to modify_reg_32()
* Updated references to OMAP_INIT_CONTEXT_* flags
* Replaced calls to omap4_revision() with omap_revision()
* Replaced sanity test with get_ram_size()
---
 arch/arm/cpu/armv7/omap4/Makefile           |    2 +
 arch/arm/cpu/armv7/omap4/board.c            |    6 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  328 +++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  131 ++++
 arch/arm/include/asm/arch-omap4/clocks.h    |    8 +-
 arch/arm/include/asm/arch-omap4/emif.h      | 1025 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |    5 +
 arch/arm/include/asm/arch-omap4/sys_proto.h |    2 +
 8 files changed, 1500 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index ac4b2a6..e1ccd68 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -29,7 +29,9 @@ SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clocks.o
+COBJS	+= emif.o
 COBJS	+= mem.o
+COBJS	+= sdram_elpida.o
 COBJS	+= sys_info.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 1c26a66..ca107f7 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -189,7 +189,7 @@ void watchdog_init(void)
  * This is needed because the size of memory installed may be
  * different on different versions of the board
  */
-u32 sdram_size(void)
+u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
@@ -215,8 +215,8 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
-	gd->ram_size = sdram_size();
+	sdram_init();
+	gd->ram_size = omap4_sdram_size();
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..b25c1ee
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,328 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+	sdelay(2000);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
+
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/*
+	 * Workaround:
+	 * In a specific situation, the OCP interface between the DMM and
+	 * EMIF may hang.
+	 * 1. A TILER port is used to perform 2D burst writes of
+	 *       width 1 and height 8
+	 * 2. ELLAn port is used to perform reads
+	 * 3. All accesses are routed to the same EMIF controller
+	 *
+	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
+	 * be kept higher than default 0x7. As per recommondation 0x0A will
+	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
+	 */
+	if (omap_revision() == OMAP4430_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
+		       &emif->emif_l3_config);
+	}
+}
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs;
+	u32 in_sdram, emif_nr;
+
+	debug(">>do_sdram_init() %x\n", base);
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+	emif_get_reg_dump(emif_nr, &regs);
+	if (!regs) {
+		debug("EMIF: reg dump not provided\n");
+		return;
+	}
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+
+	debug("<<do_sdram_init() %x\n", base);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	struct control_lpddr2io_regs *lpddr2io_regs =
+		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+	emif_get_dmm_regs(&lisa_map_regs);
+
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram, size_prog, size_detect;
+
+	debug(">>sdram_init()\n");
+
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	in_sdram = running_from_sdram();
+	debug("in_sdram = %d\n", in_sdram);
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(&prcm->cm_clkmode_dpll_core);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+
+	/* Do some testing after the init */
+	if (!in_sdram) {
+		size_prog = omap4_sdram_size();
+		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+						size_prog);
+		/* Compare with the size programmed */
+		if (size_detect != size_prog) {
+			printf("SDRAM: identified size not same as expected"
+				" size identified: %x expected: %x\n",
+				size_detect,
+				size_prog);
+		} else
+			debug("get_ram_size() successful");
+	}
+
+	debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..c950c87
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,131 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
+ * SDP and Panda. Since the parts used and geometry are identical for
+ * SDP and Panda for a given OMAP4 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP4 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_2cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 71db39c..37bdcee 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -33,10 +33,10 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+#define CM_CLKMODE_DPLL_CORE		0x4A004120
+#define CM_CLKMODE_DPLL_PER		0x4A008140
+#define CM_CLKMODE_DPLL_MPU		0x4A004160
+#define CM_CLKSEL_CORE			0x4A004100
 
 struct omap4_prcm_regs {
 	/* cm1.ckgen */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..09e9baa
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,1025 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+struct control_lpddr2io_regs {
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value for ES1*/
+#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen@lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 76b06c2..c9c86e1 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define LPDDR2_IO_REGS_BASE	0x4A100638
+
+#define CONTROL_EFUSE_2		0x4A100704
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index f871921..7183a90 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,8 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
+u32 omap4_sdram_size(void);
 
 static inline u32 running_from_sdram(void)
 {
-- 
1.7.0.4

[U-Boot] [PATCH v3 06/12] omap4: calculate EMIF register values

[Aneesh V]

Calculate EMIF register values based on AC timing parameters
from the SDRAM datasheet and the DDR frequency rather than
using the hard-coded values.

For a new board the user doen't have to go through the tedious
process of calculating the register values. Instead, just
provide the AC timings from the device data sheet as input
and the driver will automatically calculate the register values.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Added SDRAM init related CONFIG flags for Panda too.
  Earlier Panda support for everything was added in a
  single patch at the end
* Replaced calls to omap4_revision() with omap_revision()
* Reorganization of code for better readability
* Some code re-organization to reduce #ifdef complexities -
  cleanly separated out functions for getting device details
  (geometry) vs timings
* Ensured un-necessary code is compiled out if
  CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REG is defined
---
 arch/arm/cpu/armv7/omap-common/Makefile     |    1 +
 arch/arm/cpu/armv7/omap-common/utils.c      |   57 ++
 arch/arm/cpu/armv7/omap4/board.c            |    9 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  739 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  151 ++++++
 arch/arm/include/asm/arch-omap4/emif.h      |    9 +
 arch/arm/include/asm/arch-omap4/omap4.h     |   10 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_panda.h               |    5 +
 include/configs/omap4_sdp4430.h             |    5 +
 10 files changed, 977 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..8f698f8 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..ea935da
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2011 Linaro Limited
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index ca107f7..786c239 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -193,13 +194,13 @@ u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index b25c1ee..ceead9e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -170,6 +170,628 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	config_reg |=  (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
+	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+			OMAP44XX_REG_IBANK_POS_SHIFT;
+
+	config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
+
+	config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
+
+	config_reg |= addressing->row_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_ROWSIZE_SHIFT;
+
+	config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
+
+	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+			OMAP44XX_REG_EBANK_SHIFT;
+
+	config_reg |= addressing->col_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_PAGESIZE_SHIFT;
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
+
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
+	tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
+
+	zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
+
+	zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
+
+	zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
+
+	zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
+
+	alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
+
+	idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+	/* Other fields are constant magic values. Hardcode them together */
+	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+		OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+	return phy;
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = &jedec_default_timings;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
@@ -180,11 +802,54 @@ static void do_sdram_init(u32 base)
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_reg_dump(emif_nr, &regs);
 	if (!regs) {
 		debug("EMIF: reg dump not provided\n");
 		return;
 	}
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+	struct emif_device_details dev_details;
+	struct emif_regs calculated_regs;
+
+	/*
+	 * Get device details:
+	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+	 * - Obtained from user otherwise
+	 */
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	emif_get_device_details(emif_nr, &cs0_dev_details,
+				&cs1_dev_details);
+	dev_details.cs0_device_details = &cs0_dev_details;
+	dev_details.cs1_device_details = &cs1_dev_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+	/*
+	 * Get device timings:
+	 * - Default timings specified by JESD209-2 if
+	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+	 * - Obtained from user otherwise
+	 */
+	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+				&dev_details.cs1_device_timings);
+
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
 	 * Initializing the LPDDR2 device can not happen from SDRAM.
@@ -242,8 +907,82 @@ static void dmm_init(u32 base)
 {
 	const struct dmm_lisa_map_regs *lisa_map_regs;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) <<
+				OMAP44XX_SYS_ADDR_SHIFT;
+		section_map |= get_dmm_section_size_map(mapped_size * 2)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif1_size)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= (mapped_size >> 24) <<
+				OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif2_size) <<
+				OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
 	    (struct dmm_lisa_map_regs *)base;
 
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index c950c87..7757aad 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -46,6 +46,8 @@
  * - emif_get_device_timings()
  */
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
@@ -129,3 +131,152 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 omap_rev = omap_revision();
+
+	/* EMIF1 & EMIF2 have identical configuration */
+	*cs0_device_details = elpida_2G_S4_details;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		cs1_device_details = NULL;
+	else
+		*cs1_device_details = elpida_2G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	u32 omap_rev = omap_revision();
+
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*cs1_device_timings = NULL;
+	else
+		*cs1_device_timings = &elpida_2G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 09e9baa..a167508 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1019,7 +1019,16 @@ struct emif_regs {
 #define emif_assert(c)	({ if (0) hang(); })
 #endif
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index c9c86e1..a8dbedb 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -84,12 +84,6 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
 /*
  * Hardware Register Details
  */
@@ -137,6 +131,10 @@ struct s32ktimer {
 #define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
 /* SRAM scratch space entries */
 #define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
 
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 7183a90..1e62878 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,7 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_sdram_size(void);
 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 1daffb7..9f82ef4 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -237,4 +237,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 68ffa87..6df1c3d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -243,4 +243,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v3 07/12] omap4: automatic sdram detection

[Aneesh V]

Identify SDRAM devices connected to EMIF automatically:
LPDDR2 devices have some Mode Registers that provide details
about the device such as the type, density, bus width
etc. EMIF has the capability to read these registers. If there
are no devices connected to a given chip-select reading mode
registers will return junk values. After reading as many such
registers as possible and matching with expected ranges of
values the driver can identify if there is a device connected
to the respective CS. If we identify that a device is connected
the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2
allows us to do a complete automatic initialization of
SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2
will be safe for all devices but not necessarily optimal. However,
for the Elpida devices used on Panda and SDP the default timings
are both safe and optimal.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Code re-organization for better readability
* Ensured that un-necessary code is compiled out when
  CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is not defined
---
 arch/arm/cpu/armv7/omap4/emif.c |  238 +++++++++++++++++++++++++++++++++++++++
 include/configs/omap4_panda.h   |    1 +
 include/configs/omap4_sdp4430.h |    1 +
 3 files changed, 240 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index ceead9e..1234a7e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -792,6 +792,244 @@ void emif_get_device_timings(u32 emif_nr,
 }
 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
+
+	if (running_from_sdram()) {
+		/*
+		 * We can not do automatic discovery running from SDRAM
+		 * Most likely we came here by mistake. Indicate error
+		 * by returning NULL
+		 */
+		cs0_device_details = NULL;
+		cs1_device_details = NULL;
+	} else {
+		/*
+		 * Automatically find the device details:
+		 *
+		 * Reset the PHY after each call to get_lpddr2_details().
+		 * If there is nothing connected to a given chip select
+		 * (typically CS1) mode register reads will mess up with
+		 * the PHY state and subsequent initialization won't work.
+		 * PHY reset brings back PHY to a good state.
+		 */
+		cs0_device_details =
+		    get_lpddr2_details(base, CS0, cs0_device_details);
+		emif_reset_phy(base);
+
+		cs1_device_details =
+		    get_lpddr2_details(base, CS1, cs1_device_details);
+		emif_reset_phy(base);
+	}
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 9f82ef4..a8dd861 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -239,6 +239,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 6df1c3d..534f89a 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -245,6 +245,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH v3 08/12] armv7: start.S: fixes and enhancements for SPL

[Aneesh V]

- Allow SPL to have .bss disjoint from rest of the image
- Allow for .bss setup in CONFIG_SPL_BUILD case too.
- Take care of the special case where relocation offset = 0.
- Compile out exception handling code and install a simpler
  vector

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Taken care of the case where .bss is at a lower address
  comapred to  _start
---
 arch/arm/cpu/armv7/start.S    |   50 ++++++++++++++++++++++++++++++----------
 arch/arm/cpu/armv7/u-boot.lds |    2 +
 2 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index d2a6207..5be436f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
 .global _end_vect
 _end_vect:
 
@@ -89,6 +100,10 @@ _armboot_start:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -182,12 +197,11 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_SPL_BUILD
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
@@ -235,20 +249,34 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 clear_bss:
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -276,13 +304,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -327,6 +348,8 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+
+#ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
@@ -514,4 +537,5 @@ fiq:
 	bad_save_user_regs
 	bl	do_fiq
 
-#endif
+#endif /* CONFIG_USE_IRQ */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index dbae54d..40ecf78 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
-- 
1.7.0.4

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Aneesh V]

- Provide alternate implementations of board_init_f()
  board_init_r() for OMAP spl.
- Provide linker script
- Initialize global data
- Add serial console support
- Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move
  it to board config header from config.mk

Signed-off-by: Aneesh V <aneesh@ti.com>
---

This patch adds two checkpatch warnings that look like false
positives. Reported these to checkpatch maintainer.

V2:
* Removed the label __flash_image_end because _end serves the
  same purpose after rebasing to latest mainline

V3:
* Moved CONFIG_SYS_TEXT_BASE to board config header and
  deleted config.mk
* Changes for the struct based register accesses
* Removed usage of modify_reg_32() macro
* omap4_rev_string() reference changed to omap_rev_string()
* Folded the patches for linker script changes and console
  support into this patch
* Improved commit message
---
 arch/arm/cpu/armv7/Makefile                   |    7 ++-
 arch/arm/cpu/armv7/omap-common/Makefile       |    4 +
 arch/arm/cpu/armv7/omap-common/spl.c          |   82 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds |   62 +++++++++++++++++++
 arch/arm/cpu/armv7/omap4/Makefile             |    5 +-
 arch/arm/cpu/armv7/omap4/board.c              |    7 ++
 arch/arm/cpu/armv7/omap4/clocks.c             |   33 ++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h   |    1 +
 arch/arm/include/asm/omap_common.h            |    2 +
 board/ti/panda/Makefile                       |    2 +
 board/ti/panda/config.mk                      |   31 ---------
 board/ti/sdp4430/Makefile                     |    2 +
 board/ti/sdp4430/config.mk                    |   31 ---------
 include/configs/omap4_panda.h                 |   26 ++++++++
 include/configs/omap4_sdp4430.h               |   26 ++++++++
 15 files changed, 257 insertions(+), 64 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 delete mode 100644 board/ti/panda/config.mk
 delete mode 100644 board/ti/sdp4430/config.mk

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 299792a..92a5a96 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	:= start.o
-COBJS	:= cpu.o cache_v7.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= cache_v7.o
+COBJS	+= cpu.o
+endif
+
 COBJS  += syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 8f698f8..0708796 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -30,6 +30,10 @@ SOBJS	:= reset.o
 COBJS	:= timer.o
 COBJS	+= utils.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS	+= spl.o
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
new file mode 100644
index 0000000..166d7eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * We call relocate_code() with relocation target same as the
+	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+	 * skipped. Instead, only .bss initialization will happen. That's
+	 * all we need
+	 */
+	debug(">>board_init_f()\n");
+	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}
+
+void preloader_console_init(void)
+{
+	const char *u_boot_rev = U_BOOT_VERSION;
+	char omap4_rev_string[50];
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	setup_clocks_for_console();
+	serial_init();		/* serial communications setup */
+
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+
+	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+		U_BOOT_TIME);
+	omap_rev_string(omap4_rev_string);
+	printf("Texas Instruments %s\n", omap4_rev_string);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
new file mode 100644
index 0000000..1f944a7
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
+		 LENGTH = CONFIG_SYS_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SYS_SPL_BSS_START_ADDR, \
+		  LENGTH = CONFIG_SYS_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/armv7/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index e1ccd68..e7ee0b8 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -30,9 +30,12 @@ SOBJS	+= lowlevel_init.o
 COBJS	+= board.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
-COBJS	+= mem.o
 COBJS	+= sdram_elpida.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= mem.o
 COBJS	+= sys_info.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 786c239..54dd509 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -155,7 +155,14 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+#endif
 	prcm_init();
+#ifdef CONFIG_SPL_BUILD
+	/* For regular u-boot sdram_init() is called from dram_init() */
+	sdram_init();
+#endif
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index e8d3a52..f1e233a 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -791,6 +791,39 @@ void lock_dpll(u32 *const base)
 	wait_for_lock(base);
 }
 
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable all UARTs - console will be on one of them */
+	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
 void prcm_init(void)
 {
 	switch (omap4_hw_init_context()) {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 1e62878..a81f8e5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);
 void freq_update_core(void);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 33caa4e..69d53d2 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -34,4 +34,6 @@
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
+void preloader_console_init(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index 2186403..09f88ee 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/panda/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index f1ee544..12f2743 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= sdp.o cmd_bat.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/sdp4430/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index a8dd861..3244fc1 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -243,4 +243,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
+#define CONFIG_SYS_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SYS_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 534f89a..5c486c3 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -249,4 +249,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
+#define CONFIG_SYS_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SYS_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v3 10/12] Correct ih_os for u-boot.img

[Aneesh V]

Provide appropriate '-O u-boot' while doing mkimage
for u-boot.img

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 Makefile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 0707036..f8ae883 100644
--- a/Makefile
+++ b/Makefile
@@ -375,7 +375,7 @@ $(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
 
 $(obj)u-boot.img:	$(obj)u-boot.bin
 		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-		-a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+		-O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
 		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
-- 
1.7.0.4

[U-Boot] [PATCH v3 11/12] omap: add MMC and FAT support to SPL

[Aneesh V]

- Add MMC raw and FAT mode boot support for OMAP
- Provide a means by which parameters passed by ROM-code
  can be saved in u-boot.
- Save boot mode related information passed by OMAP4 ROM-code
  and use it to determine where to load the u-boot from
- Assumes that the image has a mkimage header. Gets the
  payload size and load address from this header. If the
  header is not detected assume u-boot.bin as payload

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Squashed the patches that provided MMC support, FAT support,
  start.S hook for saving parameters, and OMAP4 patch for saving
  the parameters all into this patch.
* Removed the assumption that payload is u-boot.bin. Payload
  size and address
---
 arch/arm/cpu/armv7/cpu.c                 |    7 +
 arch/arm/cpu/armv7/omap-common/spl.c     |  194 +++++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/board.c         |   21 ++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S |   31 +++++
 arch/arm/cpu/armv7/start.S               |    1 +
 arch/arm/include/asm/arch-omap4/omap4.h  |    8 ++
 arch/arm/include/asm/omap_common.h       |   17 +++
 include/configs/omap4_panda.h            |    5 +
 include/configs/omap4_sdp4430.h          |    5 +
 9 files changed, 287 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index def9ced..091e3e0 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -37,6 +37,13 @@
 #include <asm/cache.h>
 #include <asm/armv7.h>
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index 166d7eb..f326f9a 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -24,15 +24,27 @@
  */
 #include <common.h>
 #include <asm/u-boot.h>
+#include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
+#include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <image.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Define global data structure pointer to it*/
 static gd_t gdata __attribute__ ((section(".data")));
 static bd_t bdata __attribute__ ((section(".data")));
+static const char *image_name;
+static u8 image_os;
+static u32 image_load_addr;
+static u32 image_entry_point;
+static u32 image_size;
 
 inline void hang(void)
 {
@@ -53,10 +65,188 @@ void board_init_f(ulong dummy)
 	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0);
+		break;
+	case BOOT_DEVICE_MMC2:
+		omap_mmc_init(1);
+		break;
+	}
+	return 0;
+}
+#endif
+
+static void parse_image_header(const struct image_header *header)
+{
+	u32 header_size = sizeof(struct image_header);
+
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		image_size = __be32_to_cpu(header->ih_size) + header_size;
+		image_entry_point = __be32_to_cpu(header->ih_load);
+		/* Load including the header */
+		image_load_addr = image_entry_point - header_size;
+		image_os = header->ih_os;
+		image_name = (const char *)&header->ih_name;
+		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
+			image_name, image_load_addr, image_size);
+	} else {
+		/* Signature not found - assume u-boot.bin */
+		printf("mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		puts("Assuming u-boot.bin ..\n");
+		/* Let's assume U-Boot will not be more than 200 KB */
+		image_size = 200 * 1024;
+		image_entry_point = CONFIG_SYS_TEXT_BASE;
+		image_load_addr = CONFIG_SYS_TEXT_BASE;
+		image_os = IH_OS_U_BOOT;
+		image_name = "U-Boot";
+	}
+}
+
+static void mmc_load_image_raw(struct mmc *mmc)
+{
+	u32 image_size_sectors, err;
+	const struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	/* read image header to find the image size & load address */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)header);
+
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	/* convert size to sectors - round up */
+	image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) /
+				MMCSD_SECTOR_SIZE;
+
+	/* Read the header too to avoid extra memcpy */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+			image_size_sectors, (void *)image_load_addr);
+
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_image_fat(struct mmc *mmc)
+{
+	s32 err;
+	struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)image_load_addr, 0);
+
+end:
+	if (err <= 0) {
+		printf("spl: error reading image %s, err - %d\n",
+			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
+		hang();
+	}
+}
+
+static void mmc_load_image(void)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: err - %d\n", err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW) {
+		debug("boot mode - RAW\n");
+		mmc_load_image_raw(mmc);
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		debug("boot mode - FAT\n");
+		mmc_load_image_fat(mmc);
+	} else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) image_entry_point;
+
+	image_entry();
+}
+
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
 void board_init_r(gd_t *id, ulong dummy)
 {
-	for (;;)
-		;
+	u32 boot_device;
+	debug(">>spl:board_init_r()\n");
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	boot_device = omap_boot_device();
+	debug("boot device - %d\n", boot_device);
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_image();
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	switch (image_os) {
+	case IH_OS_U_BOOT:
+		debug("Jumping to U-Boot\n");
+		jump_to_image_no_args();
+		break;
+	default:
+		puts("Unsupported OS image.. Jumping nevertheless..\n");
+		jump_to_image_no_args();
+	}
 }
 
 void preloader_console_init(void)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 54dd509..2e5739a 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -39,6 +39,27 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 6abfbba..91525ec 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_SPL_BUILD
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5be436f..89ea01f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -134,6 +134,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a8dbedb..563544f 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -144,4 +144,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_2	0x44300220
 #define OMAP4430_ES2_3	0x44300230
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 69d53d2..d3cb857 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -36,4 +36,21 @@
 
 void preloader_console_init(void);
 
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 3244fc1..310c353 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -252,6 +252,11 @@
 #define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
 #define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 5c486c3..57ffb3c 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -258,6 +258,11 @@
 #define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
 #define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-- 
1.7.0.4

[U-Boot] [PATCH v3 12/12] mkimage: Add OMAP boot image support

[Aneesh V]

From: John Rigby <john.rigby@linaro.org>

- Add mkimage support for OMAP boot image
- Add support for OMAP boot image(MLO) generation in the new
  SPL framework

Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
 * Fixed minor issue with casting away 'const'ness of
   pointers
 * Ensure lists are sorted alphabetically
 * Added an error message
 * Removed 'packed' attribute from structs
 * Fixed some other minor comments on V2
---
 arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
 common/image.c                     |    9 +-
 include/image.h                    |    1 +
 spl/Makefile                       |    6 +
 tools/Makefile                     |    2 +
 tools/mkimage.c                    |    2 +
 tools/mkimage.h                    |    1 +
 tools/omapimage.c                  |  224 ++++++++++++++++++++++++++++++++++++
 tools/omapimage.h                  |   50 ++++++++
 9 files changed, 321 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/config.mk
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
new file mode 100644
index 0000000..b34fa64
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/common/image.c b/common/image.c
index e542a57..a141904 100644
--- a/common/image.c
+++ b/common/image.c
@@ -130,17 +130,18 @@ static const table_entry_t uimage_os[] = {
 };
 
 static const table_entry_t uimage_type[] = {
-	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
 	{	IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image",	},
 	{	IH_TYPE_FIRMWARE,   "firmware",	  "Firmware",		},
+	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
+	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	IH_TYPE_KERNEL,	    "kernel",	  "Kernel Image",	},
+	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
 	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
 	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
 	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
-	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
-	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
-	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index c31e862..c606644 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types
diff --git a/spl/Makefile b/spl/Makefile
index fda4049..b9f4232 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -85,6 +85,12 @@ LDPPFLAGS += \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
+ifdef CONFIG_OMAP
+$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SYS_SPL_TEXT_BASE) -d $< $@
+endif
+
 ALL-y	+= $(obj)u-boot-spl.bin
 
 all:	$(ALL-y)
diff --git a/tools/Makefile b/tools/Makefile
index 97f83f8..cb7f92d 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -88,6 +88,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
 OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
@@ -188,6 +189,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
 			$(obj)md5.o \
 			$(obj)mkimage.o \
 			$(obj)os_support.o \
+			$(obj)omapimage.o \
 			$(obj)sha1.o \
 			$(LIBFDT_OBJS)
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 60f7263..b6a7cb7 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -156,6 +156,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 9033a7d..3b49645 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/omapimage.c b/tools/omapimage.c
new file mode 100644
index 0000000..29d91cc
--- /dev/null
+++ b/tools/omapimage.c
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "omapimage.h"
+
+/* Header size is CH header rounded up to 512 bytes plus GP header */
+#define OMAP_CH_HDR_SIZE 512
+#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+
+static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
+
+static int omapimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_OMAPIMAGE)
+		return EXIT_SUCCESS;
+	else {
+		fprintf(stderr, "Unknown OMAP image type - %x", type);
+		return EXIT_FAILURE;
+	}
+}
+
+/*
+ * Only the simplest image type is currently supported:
+ * TOC pointing to CHSETTINGS
+ * TOC terminator
+ * CHSETTINGS
+ *
+ * padding to OMAP_CH_HDR_SIZE bytes
+ *
+ * gp header
+ *   size
+ *   load_addr
+ */
+static int valid_gph_size(uint32_t size)
+{
+	return size;
+}
+
+static int valid_gph_load_addr(uint32_t load_addr)
+{
+	return load_addr;
+}
+
+static int omapimage_verify_header(unsigned char *ptr, int image_size,
+			struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+		if (!offset || !size)
+			return -1;
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			return -1;
+		toc++;
+	}
+	if (!valid_gph_size(gph->size))
+		return -1;
+	if (!valid_gph_load_addr(gph->load_addr))
+		return -1;
+
+	return 0;
+}
+
+static void omapimage_print_section(struct ch_settings *chs)
+{
+	const char *section_name;
+
+	if (chs->section_key)
+		section_name = "CHSETTINGS";
+	else
+		section_name = "UNKNOWNKEY";
+
+	printf("%s (%x) "
+		"valid:%x "
+		"version:%x "
+		"reserved:%x "
+		"flags:%x\n",
+		section_name,
+		chs->section_key,
+		chs->valid,
+		chs->version,
+		chs->reserved,
+		chs->flags);
+}
+
+static void omapimage_print_header(const void *ptr)
+{
+	const struct ch_toc *toc = (struct ch_toc *)ptr;
+	const struct gp_header *gph =
+			(struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			exit(EXIT_FAILURE);
+
+		printf("Section %s offset %x length %x\n",
+			toc->section_name,
+			toc->section_offset,
+			toc->section_size);
+
+		omapimage_print_section((struct ch_settings *)(ptr+offset));
+		toc++;
+	}
+
+	if (!valid_gph_size(gph->size)) {
+		fprintf(stderr,
+			"Error: invalid image size %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!valid_gph_load_addr(gph->load_addr)) {
+		fprintf(stderr,
+			"Error: invalid image load address %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	printf("GP Header: Size %x LoadAddr %x\n",
+		gph->size, gph->load_addr);
+}
+
+static int toc_offset(void *hdr, void *member)
+{
+	return member - hdr;
+}
+
+static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct ch_settings *chs = (struct ch_settings *)
+					(ptr + 2 * sizeof(*toc));
+	struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE);
+
+	toc->section_offset = toc_offset(ptr, chs);
+	toc->section_size = sizeof(struct ch_settings);
+	strcpy((char *)toc->section_name, "CHSETTINGS");
+
+	chs->section_key = KEY_CHSETTINGS;
+	chs->valid = 0;
+	chs->version = 1;
+	chs->reserved = 0;
+	chs->flags = 0;
+
+	toc++;
+	memset(toc, 0xff, sizeof(*toc));
+
+	gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
+	gph->load_addr = params->addr;
+}
+
+int omapimage_check_params(struct mkimage_params *params)
+{
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+/*
+ * omapimage parameters
+ */
+static struct image_type_params omapimage_params = {
+	.name		= "TI OMAP CH/GP Boot Image support",
+	.header_size	= OMAP_FILE_HDR_SIZE,
+	.hdr		= (void *)&omapimage_header,
+	.check_image_type = omapimage_check_image_types,
+	.verify_header	= omapimage_verify_header,
+	.print_header	= omapimage_print_header,
+	.set_header	= omapimage_set_header,
+	.check_params	= omapimage_check_params,
+};
+
+void init_omap_image_type(void)
+{
+	mkimage_register(&omapimage_params);
+}
diff --git a/tools/omapimage.h b/tools/omapimage.h
new file mode 100644
index 0000000..719db00
--- /dev/null
+++ b/tools/omapimage.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAPIMAGE_H_
+#define _OMAPIMAGE_H_
+
+struct ch_toc {
+	uint32_t section_offset;
+	uint32_t section_size;
+	uint8_t unused[12];
+	uint8_t section_name[12];
+};
+
+struct ch_settings {
+	uint32_t section_key;
+	uint8_t valid;
+	uint8_t version;
+	uint16_t reserved;
+	uint32_t flags;
+};
+
+struct gp_header {
+	uint32_t size;
+	uint32_t load_addr;
+};
+
+#define KEY_CHSETTINGS 0xC0C0C0C1
+#endif /* _OMAPIMAGE_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Daniel Schwierzeck]

Hi Aneesh,

On 07/16/2011 02:53 PM, Aneesh V wrote:

> diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
> index a8dd861..3244fc1 100644
> --- a/include/configs/omap4_panda.h
> +++ b/include/configs/omap4_panda.h
> @@ -243,4 +243,30 @@
>   #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
>   #endif
>
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350

Does this work? The SPL framework patches currently use

ifneq ($(CONFIG_SPL_TEXT_BASE),)
CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
endif

But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.
Shall I fix it in the SPL framework patches?

> +#define CONFIG_SYS_SPL_MAX_SIZE		0x8000	/* 32 K */
> +#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
> +#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SYS_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
> +
> +/*
> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> + * 64 bytes before this address should be set aside for u-boot.img's
> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
> + * other needs.
> + */
> +#define CONFIG_SYS_TEXT_BASE		0x80100000
> +
>   #endif /* __CONFIG_H */
> diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
> index 534f89a..5c486c3 100644
> --- a/include/configs/omap4_sdp4430.h
> +++ b/include/configs/omap4_sdp4430.h
> @@ -249,4 +249,30 @@
>   #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
>   #endif
>
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SYS_SPL_TEXT_BASE	0x40304350
> +#define CONFIG_SYS_SPL_MAX_SIZE		0x8000	/* 32 K */
> +#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
> +#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
> +
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SYS_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
> +
> +/*
> + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
> + * 64 bytes before this address should be set aside for u-boot.img's
> + * header. That is 0x800FFFC0--0x80100000 should not be used for any
> + * other needs.
> + */
> +#define CONFIG_SYS_TEXT_BASE		0x80100000
> +
>   #endif /* __CONFIG_H */

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Aneesh V]

On Saturday 16 July 2011 07:06 PM, Daniel Schwierzeck wrote:
> Hi Aneesh,
>
> On 07/16/2011 02:53 PM, Aneesh V wrote:
>
>> diff --git a/include/configs/omap4_panda.h
>> b/include/configs/omap4_panda.h
>> index a8dd861..3244fc1 100644
>> --- a/include/configs/omap4_panda.h
>> +++ b/include/configs/omap4_panda.h
>> @@ -243,4 +243,30 @@
>> #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
>> #endif
>>
>> +/* Defines for SPL */
>> +#define CONFIG_SPL
>> +#define CONFIG_SYS_SPL_TEXT_BASE 0x40304350
>
> Does this work? The SPL framework patches currently use

Hmm.. Good catch. I think it was still working for me because I had
this in my linker script:

MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
		 LENGTH = CONFIG_SYS_SPL_MAX_SIZE }

And then I was using the .sram region for rest of the script.

I think this over-rides the -Ttext on the linker command line.

>
> ifneq ($(CONFIG_SPL_TEXT_BASE),)
> CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
> endif
>
> But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.

Yes, looks like CONFIG_SYS_SPL_TEXT_BASE is the right name. For u-boot
we have CONFIG_SYS_TEXT_BASE

> Shall I fix it in the SPL framework patches?

I don't know if Daniel wants to do this himself.
As long as you are working on omap and use my linker script, you may
still be able to work without any compilation error.

If the framework is going to retain CONFIG_SPL_TEXT_BASE I shall
re-submit my patch.

best regards,
Aneesh

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Aneesh V]

On Saturday 16 July 2011 07:54 PM, Aneesh V wrote:
> On Saturday 16 July 2011 07:06 PM, Daniel Schwierzeck wrote:
>> Hi Aneesh,
>>
>> On 07/16/2011 02:53 PM, Aneesh V wrote:
>>
>>> diff --git a/include/configs/omap4_panda.h
>>> b/include/configs/omap4_panda.h
>>> index a8dd861..3244fc1 100644
>>> --- a/include/configs/omap4_panda.h
>>> +++ b/include/configs/omap4_panda.h
>>> @@ -243,4 +243,30 @@
>>> #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
>>> #endif
>>>
>>> +/* Defines for SPL */
>>> +#define CONFIG_SPL
>>> +#define CONFIG_SYS_SPL_TEXT_BASE 0x40304350
>>
>> Does this work? The SPL framework patches currently use
>
> Hmm.. Good catch. I think it was still working for me because I had
> this in my linker script:
>
> MEMORY { .sram : ORIGIN = CONFIG_SYS_SPL_TEXT_BASE,\
> LENGTH = CONFIG_SYS_SPL_MAX_SIZE }
>
> And then I was using the .sram region for rest of the script.
>
> I think this over-rides the -Ttext on the linker command line.
>
>>
>> ifneq ($(CONFIG_SPL_TEXT_BASE),)
>> CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
>> endif
>>
>> But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.
>
> Yes, looks like CONFIG_SYS_SPL_TEXT_BASE is the right name. For u-boot
> we have CONFIG_SYS_TEXT_BASE
>
>> Shall I fix it in the SPL framework patches?
>
> I don't know if Daniel wants to do this himself.
> As long as you are working on omap and use my linker script, you may
> still be able to work without any compilation error.

Oops! Terrible mix-up!! I took your mail to be from Simon and hence the
above confusion:-)

Yes, fixing this in the framework series seems to be the right thing.
Thanks.

best regards,
Aneesh

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Wolfgang Denk]

Dear Daniel Schwierzeck,

In message <4E2193DC.8040207@googlemail.com> you wrote:
>
> But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.
> Shall I fix it in the SPL framework patches?

This is getting a very long name - and if we do this, we probably have
to rename a few other CONFIG_SPL_* into CONFIG_SYS_SPL_* as well.

If you are not really, really convinced this must be renamed I suggest
we stick with the shorter CONFIG_SPL_TEXT_BASE instead...

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Nobody trips over mountains. It is the small pebble that  causes  you
to  stumble.  Pass all the pebbles in your path and you will find you
have crossed the mountain.

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Daniel Schwierzeck]

Dear Wolfgang,

On Sat, Jul 16, 2011 at 5:02 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Daniel Schwierzeck,
>
> In message <4E2193DC.8040207@googlemail.com> you wrote:
>>
>> But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.
>> Shall I fix it in the SPL framework patches?
>
> This is getting a very long name - and if we do this, we probably have
> to rename a few other CONFIG_SPL_* into CONFIG_SYS_SPL_* as well.
>
> If you are not really, really convinced this must be renamed I suggest
> we stick with the shorter CONFIG_SPL_TEXT_BASE instead...

ok I won't change the SPL patches. So CONFIG_SPL_* is the new prefix
for all SPL specific config options?

Best regards,
Daniel

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Aneesh V]

On Monday 18 July 2011 03:12 PM, Daniel Schwierzeck wrote:
> Dear Wolfgang,
>
> On Sat, Jul 16, 2011 at 5:02 PM, Wolfgang Denk<wd@denx.de>  wrote:
>> Dear Daniel Schwierzeck,
>>
>> In message<4E2193DC.8040207@googlemail.com>  you wrote:
>>>
>>> But CONFIG_SYS_SPL_TEXT_BASE seems to be the right name for this option.
>>> Shall I fix it in the SPL framework patches?
>>
>> This is getting a very long name - and if we do this, we probably have
>> to rename a few other CONFIG_SPL_* into CONFIG_SYS_SPL_* as well.
>>
>> If you are not really, really convinced this must be renamed I suggest
>> we stick with the shorter CONFIG_SPL_TEXT_BASE instead...
>
> ok I won't change the SPL patches. So CONFIG_SPL_* is the new prefix
> for all SPL specific config options?

Ok. I will change my patch to use CONFIG_SPL_TEXT_BASE then.

br,
Aneesh

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Wolfgang Denk]

Dear Daniel Schwierzeck,

In message <CACUy__WZKkYGB9PWu7hTBqBSFV5FD43+E78nD1JQA9pdqoFbPA@mail.gmail.com> you wrote:
> 
> ok I won't change the SPL patches. So CONFIG_SPL_* is the new prefix
> for all SPL specific config options?

I'm fine with that.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Man is the best computer we can put aboard a spacecraft ...  and  the
only one that can be mass produced with unskilled labor.
                                                  - Wernher von Braun

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Simon Schwarz]

Hi Aneesh,

On Sat, 16 Jul 2011 18:23:19 +0530
Aneesh V <aneesh@ti.com> wrote:

> * omap4_rev_string() reference changed to omap_rev_string()

>+	char omap4_rev_string[50];
[snip]
> +	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev,
> U_BOOT_DATE,
> +		U_BOOT_TIME);
> +	omap_rev_string(omap4_rev_string);
> +	printf("Texas Instruments %s\n", omap4_rev_string);

Shouldn't also the omap4_rev_string be renamed to omap_rev_string?

Regards
Simon

[U-Boot] [PATCH v3 09/12] omap: add basic SPL support

[Aneesh V]

Hi Simon,

On Monday 18 July 2011 06:51 PM, Simon Schwarz wrote:
> Hi Aneesh,
>
> On Sat, 16 Jul 2011 18:23:19 +0530
> Aneesh V<aneesh@ti.com>  wrote:
>
>> * omap4_rev_string() reference changed to omap_rev_string()
>
>> +	char omap4_rev_string[50];
> [snip]
>> +	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev,
>> U_BOOT_DATE,
>> +		U_BOOT_TIME);
>> +	omap_rev_string(omap4_rev_string);
>> +	printf("Texas Instruments %s\n", omap4_rev_string);
>
> Shouldn't also the omap4_rev_string be renamed to omap_rev_string?

Just the name of the local variable. But will fix it anyway in the next
revision.

br,
Aneesh

[U-Boot] [PATCH v3 00/12] U-Boot MMC SPL for OMAP4

[Aneesh V]

Dear Wolfgang,

On Saturday 16 July 2011 06:23 PM, Aneesh V wrote:
> This series adds mmc SPL support for OMAP4. This is essentially
> an up-streaming effort for TI's x-loader for OMAP4 using the SPL
> framework
>
> This work partly draws upon previous work done for x-loader by:
> 	Santosh Shilimkar<santosh.shilimkar@ti.com>
> 	Rajendra Nayak<rnayak@ti.com>
> and many others
>
> This series depends on the following series for the new SPL framework:
> http://marc.info/?l=u-boot&m=131056990001719&w=2
>
> Features supported:
> * Clock init - DPLL locking, clock domains/modules enabling
> * SDRAM/DMM initialization
> * Mux initialization
> * MMC raw read support
> * MMC FAT read support
>
> Improvments over x-loader:
> * Code completely revamped
> * DPLL programming that works for all SYS_CLK frequencies
> * Automatic SDRAM identification and initialization
> * Board dependent parts(especially mux) deferred to u-boot. So, same
>    SPL will work for Panda and SDP and most likely on any other board
>    that comes along
> * Flexible about the payload. Any image with a mkimage header can be
>    loaded.
> * The core SPL logic is generic and available for OMAP3/4. So, OMAP3
>    platforms can easily extend this work to add SPL support for the
>    respective boards.
>
> V2:
> * Some fixes in SDRAM init, clock init
> * Use of pre-calculated M&  N values for DPLL locking instead
>    run-time calculation
> * Change in make files to allow reuse of common rules
>    between boards
> * Console initialization moved further earlier in the boot
>    allowing traces from even clock initialization code
> * Reuse utility macros from a previous series
>
> V3:
> * Moved to the new SPL framework
> * struct based register access for clock init
> * Squashed together related patches as per Wolfgang's suggestions
> * Re-organization of code in sdram init for better readability
> * SPL loading the payload using mkimage header
> * Avoided using custom bit-field accessor macros
> * Several other minor changes(documented in respective patches)

I think I have addressed all the comments you and others had on the
previous series and adapted it to the new SPL framework.

There are just two comments for this series so far. I have to omit the
'SYS' from CONFIG_SYS_SPL_TEXT_BASE and a minor comment by Simon.

If I fix these two, is it ready to go. Do you have any other comments.
If not, shall I re-spin the next revision?

br,
Aneesh

[U-Boot] [PATCH v3 00/12] U-Boot MMC SPL for OMAP4

[Wolfgang Denk]

Dear Aneesh V,

In message <4E24375D.1000800@ti.com> you wrote:
>
> I think I have addressed all the comments you and others had on the
> previous series and adapted it to the new SPL framework.

Yes, I agree.

> There are just two comments for this series so far. I have to omit the
> 'SYS' from CONFIG_SYS_SPL_TEXT_BASE and a minor comment by Simon.

That's my understanding, too.

> If I fix these two, is it ready to go. Do you have any other comments.
> If not, shall I re-spin the next revision?

Please feel free to send the next version, without the RFC part in the
subject now.  If no complaints come in, I want to pull this in soon.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
######## This message was made from 100% recycled electrons. ########

[U-Boot] [PATCH v3 00/12] U-Boot MMC SPL for OMAP4

[Aneesh V]

Dear Wolfgang,

On Monday 18 July 2011 07:20 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4E24375D.1000800@ti.com>  you wrote:
>>
>> I think I have addressed all the comments you and others had on the
>> previous series and adapted it to the new SPL framework.
>
> Yes, I agree.
>
>> There are just two comments for this series so far. I have to omit the
>> 'SYS' from CONFIG_SYS_SPL_TEXT_BASE and a minor comment by Simon.
>
> That's my understanding, too.

One minor question. For the OMAP spl I have some cofig flags like

CONFIG_SYS_SPL_STACK, CONFIG_SYS_SPL_BSS_START_ADDR etc.

Is it ok to omit the 'SYS' part of these too?

>
>> If I fix these two, is it ready to go. Do you have any other comments.
>> If not, shall I re-spin the next revision?
>
> Please feel free to send the next version, without the RFC part in the
> subject now.  If no complaints come in, I want to pull this in soon.

Thanks. Will send in the next revision soon.

best regards,
Aneesh

[U-Boot] [PATCH v3 00/12] U-Boot MMC SPL for OMAP4

[Wolfgang Denk]

Dear Aneesh V,

In message <4E243DA5.4080802@ti.com> you wrote:
> 
> One minor question. For the OMAP spl I have some cofig flags like
> 
> CONFIG_SYS_SPL_STACK, CONFIG_SYS_SPL_BSS_START_ADDR etc.
> 
> Is it ok to omit the 'SYS' part of these too?

Yes, please. I think we should make this consistently.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When a program is being  tested,  it  is  too  late  to  make  design
changes.                  -- Geoffrey James, "The Tao of Programming"

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[Aneesh V]

This series adds mmc SPL support for OMAP4. This is essentially
an up-streaming effort for TI's x-loader for OMAP4 using the SPL
framework

This work partly draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>
and many others

This series depends on the following series for the new SPL framework:
http://marc.info/?l=u-boot&m=131056990001719&w=2

Features supported:
* Clock init - DPLL locking, clock domains/modules enabling
* SDRAM/DMM initialization
* Mux initialization
* MMC raw read support
* MMC FAT read support

Improvments over x-loader:
* Code completely revamped
* DPLL programming that works for all SYS_CLK frequencies
* Automatic SDRAM identification and initialization
* Board dependent parts(especially mux) deferred to u-boot. So, same
  SPL will work for Panda and SDP and most likely on any other board
  that comes along
* Flexible about the payload. Any image with a mkimage header can be
  loaded.
* The core SPL logic is generic and available for OMAP3/4. So, OMAP3
  platforms can easily extend this work to add SPL support for the
  respective boards.

V2:
* Some fixes in SDRAM init, clock init
* Use of pre-calculated M & N values for DPLL locking instead
  run-time calculation
* Change in make files to allow reuse of common rules
  between boards
* Console initialization moved further earlier in the boot
  allowing traces from even clock initialization code
* Reuse utility macros from a previous series

V3:
* Moved to the new SPL framework
* struct based register access for clock init
* Squashed together related patches as per Wolfgang's suggestions
* Re-organization of code in sdram init for better readability
* SPL loading the payload using mkimage header
* Avoided using custom bit-field accessor macros
* Several other minor changes(documented in respective patches)

V4:
* Changed the CONFIG_SYS_SPL_* config flags to CONFIG_SPL_*
* Changed the name omap4_rev_string used in spl.c as this
  file is common for OMAP3/4

Aneesh V (11):
  omap4: utility function to identify the context of hw init
  omap4: cleanup pin mux data
  omap4: add OMAP4430 revision check
  omap4: add clock support
  omap4: add sdram init support
  omap4: calculate EMIF register values
  omap4: automatic sdram detection
  armv7: start.S: fixes and enhancements for SPL
  omap: add basic SPL support
  Correct ih_os for u-boot.img
  omap: add MMC and FAT support to SPL

John Rigby (1):
  mkimage: Add OMAP boot image support

 Makefile                                           |    2 +-
 arch/arm/cpu/armv7/Makefile                        |    7 +-
 arch/arm/cpu/armv7/cpu.c                           |    7 +
 arch/arm/cpu/armv7/omap-common/Makefile            |    5 +
 arch/arm/cpu/armv7/omap-common/spl.c               |  272 ++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds      |   62 +
 arch/arm/cpu/armv7/omap-common/utils.c             |   57 +
 arch/arm/cpu/armv7/omap4/Makefile                  |    6 +
 arch/arm/cpu/armv7/omap4/board.c                   |  161 +++-
 arch/arm/cpu/armv7/omap4/clocks.c                  |  842 +++++++++++++
 .../panda => arch/arm/cpu/armv7/omap4}/config.mk   |   25 +-
 arch/arm/cpu/armv7/omap4/emif.c                    | 1305 ++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  282 +++++
 arch/arm/cpu/armv7/start.S                         |   51 +-
 arch/arm/cpu/armv7/u-boot.lds                      |    2 +
 arch/arm/include/asm/arch-omap4/clocks.h           |  664 ++++++++++
 arch/arm/include/asm/arch-omap4/emif.h             | 1034 ++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |   52 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |   72 ++-
 arch/arm/include/asm/armv7.h                       |    5 +
 arch/arm/include/asm/omap_common.h                 |   56 +
 board/ti/panda/Makefile                            |    2 +
 board/ti/panda/panda.c                             |   25 +-
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +-
 board/ti/sdp4430/Makefile                          |    2 +
 board/ti/sdp4430/config.mk                         |   31 -
 board/ti/sdp4430/sdp.c                             |   25 +-
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +--
 common/image.c                                     |    9 +-
 include/configs/omap4_panda.h                      |   37 +
 include/configs/omap4_sdp4430.h                    |   37 +
 include/image.h                                    |    1 +
 spl/Makefile                                       |    6 +
 tools/Makefile                                     |    2 +
 tools/mkimage.c                                    |    2 +
 tools/mkimage.h                                    |    1 +
 tools/omap/clocks_get_m_n.c                        |  197 +++
 tools/omapimage.c                                  |  224 ++++
 tools/omapimage.h                                  |   50 +
 41 files changed, 5668 insertions(+), 263 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 rename {board/ti/panda => arch/arm/cpu/armv7/omap4}/config.mk (64%)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
 create mode 100644 arch/arm/include/asm/omap_common.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 delete mode 100644 board/ti/sdp4430/config.mk
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)
 create mode 100644 tools/omap/clocks_get_m_n.c
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

[U-Boot] [PATCH v4 01/12] omap4: utility function to identify the context of hw init

[Aneesh V]

The basic hardware init of OMAP4(s_init()) can happen in 4
different contexts:
 1. SPL running from SRAM
 2. U-Boot running from FLASH
 3. Non-XIP U-Boot loaded to SDRAM by SPL
 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
    Configuration Header feature

What level of hw initialization gets done depends on this
context. Add a utility function to find this context.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Changed the context names to more meaningful names as
  suggested by WD
---
 arch/arm/include/asm/arch-omap4/sys_proto.h |   49 ++++++++++++++++++++++++++-
 arch/arm/include/asm/omap_common.h          |   34 ++++++++++++++++++
 2 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/omap_common.h

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4fa4f4b..6b596b4 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -23,10 +23,12 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;
 };
+extern const struct omap_sysinfo sysinfo;
 
 void gpmc_init(void);
 void watchdog_init(void);
@@ -37,6 +39,51 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 
-extern const struct omap_sysinfo sysinfo;
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
 
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..d80f665
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+#endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Aneesh V]

- separate mux settings into essential and non essential parts
- essential part is board independent as of now(so move it
  to SoC directory). Will help in having single SPL for all
  boards.
- Non-essential part(the pins not essential for u-boot to function)
  need to be phased out eventually.
- Correct mux data by aligning to the latest settings in x-loader

Signed-off-by: Aneesh V <aneesh@ti.com>
---
This patch add 33 warnings for lines over 80 characters.
However, this for the mux table and improves readability.

V3:
* Squashed two mux related patches into one
---
 arch/arm/cpu/armv7/omap4/board.c                   |   53 ++++++++-
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    4 +-
 board/ti/panda/panda.c                             |   25 +---
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +++---------
 board/ti/sdp4430/sdp.c                             |   25 +---
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +++++++------------
 7 files changed, 209 insertions(+), 178 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index de4cc2a..3fd6f84 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -31,17 +31,65 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing,  andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ *	Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 }
 
 /*
@@ -124,7 +172,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 6b596b4..3624378 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
@@ -33,7 +34,8 @@ extern const struct omap_sysinfo sysinfo;
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/panda/panda_mux_data.h
similarity index 76%
rename from board/ti/sdp4430/sdp.h
rename to board/ti/panda/panda_mux_data.h
index bf41067..16cc0ad 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -207,11 +173,11 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,13 +216,15 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/sdp4430/sdp4430_mux_data.h
similarity index 67%
rename from board/ti/panda/panda.h
rename to board/ti/sdp4430/sdp4430_mux_data.h
index e3d090e..16cc0ad 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 03/12] omap4: add OMAP4430 revision check

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Added a revision string in addition to the revision number
  Helps in printing out the OMAP revision at bootup

V3:
 * Improved the revision check function by saving the
   value instead of finding it every time.
 * Improved revision string function by generating it
   from the revision rather than hard-coding the string
   per revision
---
 arch/arm/cpu/armv7/omap4/board.c            |   64 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |   29 +++++++++---
 arch/arm/include/asm/arch-omap4/sys_proto.h |    7 +++
 arch/arm/include/asm/armv7.h                |    5 ++
 4 files changed, 97 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 3fd6f84..09861a9 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
@@ -35,6 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
@@ -72,6 +75,66 @@ static void set_mux_conf_regs(void)
 	}
 }
 
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+static void init_omap4_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int arm_rev = cortex_a9_rev();
+
+	switch (arm_rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		*omap4_revision = OMAP4430_ES1_0;
+		break;
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
+			*omap4_revision = OMAP4430_ES2_1;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
+			*omap4_revision = OMAP4430_ES2_2;
+			break;
+		default:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		*omap4_revision = OMAP4430_ES2_3;
+		break;
+	default:
+		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
+		break;
+	}
+}
+
+void omap_rev_string(char *omap4_rev_string)
+{
+	u32 omap4_rev = omap_revision();
+	u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
+	u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
+	u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
+
+	sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+		minor_rev);
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -88,6 +151,7 @@ static void set_mux_conf_regs(void)
  */
 void s_init(void)
 {
+	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
 }
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..76b06c2 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,15 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -119,13 +128,17 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+#define LOW_LEVEL_SRAM_STACK		NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3624378..c10fa18 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -40,6 +40,7 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap4_rev_string);
 
 static inline u32 running_from_sdram(void)
 {
@@ -88,4 +89,10 @@ static inline u32 omap4_hw_init_context(void)
 #endif
 }
 
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap4_revision;
+	return *omap4_revision;
+}
+
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 88b9c62..b5784d8 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -25,6 +25,11 @@
 #define ARMV7_H
 #include <linux/types.h>
 
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
 #define CCSIDR_LINE_SIZE_MASK		0x7
-- 
1.7.0.4

[U-Boot] [PATCH v4 04/12] omap4: add clock support

[Aneesh V]

Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Use pre-calculated M & N values instead of calculated ones
* Changes due to make file changes
* Some corrections
* Do all clock initialization in SPL itself instead of differing some
  work to u-boot

V3:
* Use struct for register addressing
* Support only Turbo OPP for MPU. OPP's above this need Smart Reflex
  enabled
* Cleaned up the scale_vcore(). Now takes into account the differing
  voltage offsets for different revisions of Phoenix.
* Removed references to deprecated utility functions - modify_reg_32() etc.
* Changed all spl_debug() to debug()
* Moved the host-program for calculating DPLL multiplier/divider to
  tools/omap/ directory. Added more documentation
* Replaced calls to omap4_revision() with omap_revision()
* Some changes to IVA and ABE dpll locking code
---
 arch/arm/cpu/armv7/omap4/Makefile           |    1 +
 arch/arm/cpu/armv7/omap4/board.c            |    1 +
 arch/arm/cpu/armv7/omap4/clocks.c           |  809 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/clocks.h    |  664 ++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    8 +
 arch/arm/include/asm/omap_common.h          |    3 +
 tools/omap/clocks_get_m_n.c                 |  197 +++++++
 7 files changed, 1683 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 tools/omap/clocks_get_m_n.c

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..ac4b2a6 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,6 +28,7 @@ LIB	=  $(obj)lib$(SOC).o
 SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
+COBJS	+= clocks.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 09861a9..1c26a66 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -154,6 +154,7 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..e8d3a52
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,809 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
+
+static const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */
+static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
+	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{330, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{165, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{396, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{88, 2, 1, -1, -1, -1, -1, -1},		/* 27 MHz   */
+	{165, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* dpll locked at 1200 MHz - MPU clk@600 MHz */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
+	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1
+};
+
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	u32 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl(&prcm->cm_sys_clksel) &
+			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_FAST_RELOCK_BYPASS <<
+			CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+				LDELAY)) {
+		printf("Bypassing DPLL failed %p\n", base);
+	}
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
+		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+		&dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for %p\n", base);
+		hang();
+	}
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+				u8 lock)
+{
+	u32 temp;
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	switch (omap_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_1524mhz[sysclk_ind];
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		 /* safest */
+		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+	default:
+		return &core_dpll_params_1600mhz[sysclk_ind];
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz;
+	const struct dpll_params *core_dpll_params;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params();
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+static void setup_dplls(void)
+{
+	u32 sysclk_ind, temp;
+	const struct dpll_params *params;
+	debug("setup_dplls\n");
+
+	sysclk_ind = get_sys_clk_index();
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, &prcm->cm_clksel_core);
+	debug("Core DPLL configured\n");
+
+	/* lock PER dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+	debug("PER DPLL locked\n");
+
+	/* MPU dpll */
+	if (omap_revision() == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, abe_ref_clk;
+	u32 sysclk_ind, sd_div, num, den;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/* IVA */
+	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
+			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
+
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = &usb_dpll_params_1920mhz[sysclk_ind];
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
+
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+	params = &abe_dpll_params_32k_196608khz;
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+	/*
+	 * We need to enable some additional options to achieve
+	 * 196.608MHz from 32768 Hz
+	 */
+	setbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
+			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
+			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
+			CM_CLKMODE_DPLL_REGM4XEN_MASK);
+	/* Spend 4 REFCLK cycles at each stage */
+	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
+			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+#endif
+
+	/* Select the right reference clk */
+	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
+	/* Lock the dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+{
+	u32 temp, offset_code;
+	u32 step = 12660; /* 12.66 mV represented in uV */
+	u32 offset = volt_mv;
+
+	/* convert to uV for better accuracy in the calculations */
+	offset *= 1000;
+
+	if (omap_revision() == OMAP4430_ES1_0)
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+	else
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+	offset_code = (offset + step - 1) / step;
+	/* The code starts at 1 not 0 */
+	offset_code++;
+
+	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+		offset_code);
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, &prcm->prm_vc_val_bypass);
+	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				&prcm->prm_vc_val_bypass, LDELAY)) {
+		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+	}
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+
+	/*
+	 * VCORE 1 - 4430 : supplies vdd_mpu
+	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+	 * We use the maximum possible value in the AVS range because the next
+	 * higher voltage in the discrete range (code >= 0b111010) is way too
+	 * high
+	 */
+	volt = 1417;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+	/* VCORE 2 - supplies vdd_iva */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/* VCORE 3 - supplies vdd_core */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+				clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 1;
+	u32 *const clk_domains_essential[] = {
+		&prcm->cm_l4per_clkstctrl,
+		&prcm->cm_l3init_clkstctrl,
+		&prcm->cm_memif_clkstctrl,
+		&prcm->cm_l4cfg_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_wkup_gpio1_clkctrl,
+		&prcm->cm_l4per_gpio2_clkctrl,
+		&prcm->cm_l4per_gpio3_clkctrl,
+		&prcm->cm_l4per_gpio4_clkctrl,
+		&prcm->cm_l4per_gpio5_clkctrl,
+		&prcm->cm_l4per_gpio6_clkctrl,
+		&prcm->cm_memif_emif_1_clkctrl,
+		&prcm->cm_memif_emif_2_clkctrl,
+		&prcm->cm_l3init_hsusbotg_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_l4cfg_l4_cfg_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_essential[] = {
+		&prcm->cm_l4per_gptimer2_clkctrl,
+		&prcm->cm_l3init_hsmmc1_clkctrl,
+		&prcm->cm_l3init_hsmmc2_clkctrl,
+		&prcm->cm_l4per_mcspi1_clkctrl,
+		&prcm->cm_wkup_gptimer1_clkctrl,
+		&prcm->cm_l4per_i2c1_clkctrl,
+		&prcm->cm_l4per_i2c2_clkctrl,
+		&prcm->cm_l4per_i2c3_clkctrl,
+		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_l4per_uart3_clkctrl,
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 0;
+	u32 *const clk_domains_non_essential[] = {
+		&prcm->cm_mpu_m3_clkstctrl,
+		&prcm->cm_ivahd_clkstctrl,
+		&prcm->cm_dsp_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sgx_clkstctrl,
+		&prcm->cm1_abe_clkstctrl,
+		&prcm->cm_c2c_clkstctrl,
+		&prcm->cm_cam_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sdma_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_non_essential[] = {
+		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
+		&prcm->cm_ivahd_ivahd_clkctrl,
+		&prcm->cm_ivahd_sl2_clkctrl,
+		&prcm->cm_dsp_dsp_clkctrl,
+		&prcm->cm_l3_2_gpmc_clkctrl,
+		&prcm->cm_l3instr_l3_3_clkctrl,
+		&prcm->cm_l3instr_l3_instr_clkctrl,
+		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
+		&prcm->cm_l3init_hsi_clkctrl,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_non_essential[] = {
+		&prcm->cm1_abe_aess_clkctrl,
+		&prcm->cm1_abe_pdm_clkctrl,
+		&prcm->cm1_abe_dmic_clkctrl,
+		&prcm->cm1_abe_mcasp_clkctrl,
+		&prcm->cm1_abe_mcbsp1_clkctrl,
+		&prcm->cm1_abe_mcbsp2_clkctrl,
+		&prcm->cm1_abe_mcbsp3_clkctrl,
+		&prcm->cm1_abe_slimbus_clkctrl,
+		&prcm->cm1_abe_timer5_clkctrl,
+		&prcm->cm1_abe_timer6_clkctrl,
+		&prcm->cm1_abe_timer7_clkctrl,
+		&prcm->cm1_abe_timer8_clkctrl,
+		&prcm->cm1_abe_wdt3_clkctrl,
+		&prcm->cm_l4per_gptimer9_clkctrl,
+		&prcm->cm_l4per_gptimer10_clkctrl,
+		&prcm->cm_l4per_gptimer11_clkctrl,
+		&prcm->cm_l4per_gptimer3_clkctrl,
+		&prcm->cm_l4per_gptimer4_clkctrl,
+		&prcm->cm_l4per_hdq1w_clkctrl,
+		&prcm->cm_l4per_mcbsp4_clkctrl,
+		&prcm->cm_l4per_mcspi2_clkctrl,
+		&prcm->cm_l4per_mcspi3_clkctrl,
+		&prcm->cm_l4per_mcspi4_clkctrl,
+		&prcm->cm_l4per_mmcsd3_clkctrl,
+		&prcm->cm_l4per_mmcsd4_clkctrl,
+		&prcm->cm_l4per_mmcsd5_clkctrl,
+		&prcm->cm_l4per_uart1_clkctrl,
+		&prcm->cm_l4per_uart2_clkctrl,
+		&prcm->cm_l4per_uart4_clkctrl,
+		&prcm->cm_wkup_keyboard_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_cam_iss_clkctrl,
+		&prcm->cm_cam_fdif_clkctrl,
+		&prcm->cm_dss_dss_clkctrl,
+		&prcm->cm_sgx_sgx_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
+		0
+	};
+
+	/* Enable optional functional clock for ISS */
+	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable all optional functional clocks of DSS */
+	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
+	     i++) {
+		enable_clock_module(clk_modules_explicit_en_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+
+	/* Put camera module in no sleep mode */
+	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+	freq_config1 |= (core_dpll_params->m2 <<
+			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+	writel(freq_config1, &prcm->cm_shadow_freq_config1);
+	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+				&prcm->cm_shadow_freq_config1, LDELAY)) {
+		puts("FREQ UPDATE procedure failed!!");
+		hang();
+	}
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+}
+
+void bypass_dpll(u32 *const base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 *const base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..71db39c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,664 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+
+struct omap4_prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 pad001[1];
+	u32 cm_clksel_abe;
+	u32 pad002[1];
+	u32 cm_dll_ctrl;
+	u32 pad003[3];
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 pad004[3];
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 pad005[5];
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 pad006[3];
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 pad007[2];
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 pad008[2];
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 pad009[3];
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 pad010[4];
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 pad011[4];
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 pad012[1];
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 pad013[1];
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 pad014[5];
+	u32 cm_shadow_freq_config1;
+
+	/* cm1.dsp */
+	u32 pad015[103];
+	u32 cm_dsp_clkstctrl;
+	u32 pad016[7];
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 pad017[55];
+	u32 cm1_abe_clkstctrl;
+	u32 pad018[7];
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 pad019[1];
+	u32 cm1_abe_aess_clkctrl;
+	u32 pad020[1];
+	u32 cm1_abe_pdm_clkctrl;
+	u32 pad021[1];
+	u32 cm1_abe_dmic_clkctrl;
+	u32 pad022[1];
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 pad023[1];
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 pad024[1];
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 pad025[1];
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 pad026[1];
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 pad027[1];
+	u32 cm1_abe_timer5_clkctrl;
+	u32 pad028[1];
+	u32 cm1_abe_timer6_clkctrl;
+	u32 pad029[1];
+	u32 cm1_abe_timer7_clkctrl;
+	u32 pad030[1];
+	u32 cm1_abe_timer8_clkctrl;
+	u32 pad031[1];
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 pad032[3805];
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 pad033[1];
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 pad034[1];
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 pad035[1];
+	u32 cm_iva_dvfs_current;
+	u32 pad036[1];
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 pad037[3];
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 pad038[5];
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 pad039[1];
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 pad040[2];
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 pad041[5];
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+	/* cm2.core */
+	u32 pad0411[324];
+	u32 cm_l3_1_clkstctrl;
+	u32 pad042[1];
+	u32 cm_l3_1_dynamicdep;
+	u32 pad043[5];
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 pad044[55];
+	u32 cm_l3_2_clkstctrl;
+	u32 pad045[1];
+	u32 cm_l3_2_dynamicdep;
+	u32 pad046[5];
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 pad047[1];
+	u32 cm_l3_2_gpmc_clkctrl;
+	u32 pad048[1];
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 pad049[51];
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 pad050[5];
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 pad051[55];
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 pad052[5];
+	u32 cm_sdma_sdma_clkctrl;
+	u32 pad053[55];
+	u32 cm_memif_clkstctrl;
+	u32 pad054[7];
+	u32 cm_memif_dmm_clkctrl;
+	u32 pad055[1];
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 pad056[1];
+	u32 cm_memif_emif_1_clkctrl;
+	u32 pad057[1];
+	u32 cm_memif_emif_2_clkctrl;
+	u32 pad058[1];
+	u32 cm_memif_dll_clkctrl;
+	u32 pad059[3];
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 pad060[1];
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 pad061[1];
+	u32 cm_memif_dll_h_clkctrl;
+	u32 pad062[39];
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 pad063[5];
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 pad064[1];
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 pad065[1];
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 pad066[51];
+	u32 cm_l4cfg_clkstctrl;
+	u32 pad067[1];
+	u32 cm_l4cfg_dynamicdep;
+	u32 pad068[5];
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 pad069[1];
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 pad070[1];
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 pad071[1];
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 pad072[49];
+	u32 cm_l3instr_clkstctrl;
+	u32 pad073[7];
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 pad074[1];
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 pad075[5];
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+
+	/* cm2.ivahd */
+	u32 pad076[47];
+	u32 cm_ivahd_clkstctrl;
+	u32 pad077[7];
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 pad078[1];
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 pad079[53];
+	u32 cm_cam_clkstctrl;
+	u32 pad080[7];
+	u32 cm_cam_iss_clkctrl;
+	u32 pad081[1];
+	u32 cm_cam_fdif_clkctrl;
+
+	/* cm2.dss */
+	u32 pad082[53];
+	u32 cm_dss_clkstctrl;
+	u32 pad083[7];
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 pad084[55];
+	u32 cm_sgx_clkstctrl;
+	u32 pad085[7];
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 pad086[55];
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 pad087[9];
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 pad088[1];
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 pad089[1];
+	u32 cm_l3init_hsi_clkctrl;
+	u32 pad090[7];
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 pad091[1];
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 pad092[1];
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 pad093[3];
+	u32 cm_l3init_p1500_clkctrl;
+	u32 pad094[21];
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 pad095[3];
+	u32 cm_l3init_usbphy_clkctrl;
+
+	/* cm2.l4per */
+	u32 pad096[7];
+	u32 cm_l4per_clkstctrl;
+	u32 pad097[1];
+	u32 cm_l4per_dynamicdep;
+	u32 pad098[5];
+	u32 cm_l4per_adc_clkctrl;
+	u32 pad100[1];
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 pad101[1];
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 pad102[1];
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 pad103[1];
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 pad104[1];
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 pad105[1];
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 pad106[1];
+	u32 cm_l4per_elm_clkctrl;
+	u32 pad107[1];
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 pad108[1];
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 pad109[1];
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 pad110[1];
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 pad111[1];
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 pad112[1];
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 pad113[1];
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 pad114[1];
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 pad115[1];
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 pad116[1];
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 pad117[1];
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 pad118[1];
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 pad119[1];
+	u32 cm_l4per_l4per_clkctrl;
+	u32 pad1191[3];
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 pad120[1];
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 pad121[1];
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 pad122[1];
+	u32 cm_l4per_mgate_clkctrl;
+	u32 pad123[1];
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 pad124[1];
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 pad125[1];
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 pad126[1];
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 pad127[5];
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 pad128[1];
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 pad129[1];
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 pad130[1];
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 pad131[1];
+	u32 cm_l4per_uart1_clkctrl;
+	u32 pad132[1];
+	u32 cm_l4per_uart2_clkctrl;
+	u32 pad133[1];
+	u32 cm_l4per_uart3_clkctrl;
+	u32 pad134[1];
+	u32 cm_l4per_uart4_clkctrl;
+	u32 pad135[1];
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 pad136[1];
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 pad137[5];
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 pad138[5];
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 pad139[1];
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 pad140[1];
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 pad141[1];
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 pad142[1];
+	u32 cm_l4sec_rng_clkctrl;
+	u32 pad143[1];
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 pad144[3];
+	u32 cm_l4sec_cryptodma_clkctrl;
+	u32 pad145[776841];
+
+	/* l4 wkup regs */
+	u32 pad201[6211];
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 pad202[1467];
+	u32 cm_wkup_clkstctrl;
+	u32 pad203[7];
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 pad204;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 pad205;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 pad206;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 pad207;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 pad208;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 pad209;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 pad210;
+	u32 cm_wkup_usim_clkctrl;
+	u32 pad211;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 pad212[5];
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 pad213;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 pad214;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 pad215[197];
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_channel;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#define NUM_SYS_CLKS	7
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	u32 m;
+	u32 n;
+	u8 m2;
+	u8 m3;
+	u8 m4;
+	u8 m5;
+	u8 m6;
+	u8 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index c10fa18..f871921 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,6 +22,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/arch/omap4.h>
+#include <asm/arch/clocks.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mux_omap4.h>
@@ -31,6 +32,8 @@ struct omap_sysinfo {
 };
 extern const struct omap_sysinfo sysinfo;
 
+extern struct omap4_prcm_regs *const prcm;
+
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
@@ -41,6 +44,11 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d80f665..33caa4e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL			0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c
new file mode 100644
index 0000000..cfc1760
--- /dev/null
+++ b/tools/omap/clocks_get_m_n.c
@@ -0,0 +1,197 @@
+/*
+ * Program for finding M & N values for DPLLs
+ * To be run on Host PC
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <stdlib.h>
+#include <stdio.h>
+typedef unsigned int u32;
+#define MAX_N	127
+
+/*
+ * get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N)
+ * values based on the reference frequency, required output frequency,
+ * maximum tolerance for output frequency etc.
+ *
+ * target_freq_khz - output frequency required in KHz
+ * ref_freq_khz - reference(input) frequency in KHz
+ * m - pointer to computed M value
+ * n - pointer to computed N value
+ * tolerance_khz - tolerance for the output frequency. When the algorithm
+ * succeeds in finding vialble M and N values the corresponding output
+ * frequency will be in the range:
+ *	[target_freq_khz - tolerance_khz, target_freq_khz]
+ *
+ * Formula:
+ *	Fdpll = (2 * M * Fref) / (N + 1)
+ *
+ * Considerations for lock-time:
+ *	- Smaller the N, better lock-time, especially lock-time will be
+ *	- For acceptable lock-times:
+ *		Fref / (M + 1) >= 1 MHz
+ *
+ * Considerations for power:
+ *	- The difference in power for different N values giving the same
+ *	  output is negligible. So, we optimize for lock-time
+ *
+ * Hard-constraints:
+ *	- N can not be greater than 127(7 bit field for representing N)
+ *
+ * Usage:
+ *	$ gcc clocks_get_m_n.c
+ *	$ ./a.out
+ */
+int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n,
+			u32 tolerance_khz)
+{
+	u32 min_freq = target_freq_khz - tolerance_khz;
+	u32 max_freq = target_freq_khz;
+	u32 freq, freq_old;
+	*n = 1;
+	while (1) {
+		*m = min_freq / ref_freq_khz / 2 * (*n) ;
+		freq_old = 0;
+		while (1) {
+			freq = ref_freq_khz * 2 * (*m) / (*n);
+			if (abs(target_freq_khz - freq_old) <=
+				abs(target_freq_khz - freq)) {
+				freq = freq_old;
+				(*m)--;
+				break;
+			}
+			(*m)++;
+			freq_old = freq;
+		}
+		if (freq >= min_freq && freq <= max_freq)
+			break;
+		(*n)++;
+		if ((*n) > MAX_N + 1) {
+			printf("ref %d m %d n %d target %d : ",
+				ref_freq_khz, *m, *n, target_freq_khz);
+			printf("can not find m & n - please consider"
+				" increasing tolerance\n");
+			return -1;
+		}
+	}
+	(*n)--;
+	printf("ref %d m %d n %d target %d locked %d\n",
+		ref_freq_khz, *m, *n, target_freq_khz, freq);
+	if ((ref_freq_khz / (*n + 1)) < 1000) {
+		printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than"
+			" ideal, locking time will be high!\n");
+	}
+	return 0;
+}
+
+void main(void)
+{
+	u32 m, n;
+	printf("\nMPU - 2000000\n");
+	get_m_n_optimized(2000000, 12000, &m, &n, 0);
+	get_m_n_optimized(2000000, 13000, &m, &n, 0);
+	get_m_n_optimized(2000000, 16800, &m, &n, 800);
+	get_m_n_optimized(2000000, 19200, &m, &n, 0);
+	get_m_n_optimized(2000000, 26000, &m, &n, 0);
+	get_m_n_optimized(2000000, 27000, &m, &n, 0);
+	get_m_n_optimized(2000000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1200000\n");
+	get_m_n_optimized(1200000, 12000, &m, &n, 0);
+	get_m_n_optimized(1200000, 13000, &m, &n, 0);
+	get_m_n_optimized(1200000, 16800, &m, &n, 800);
+	get_m_n_optimized(1200000, 19200, &m, &n, 0);
+	get_m_n_optimized(1200000, 26000, &m, &n, 0);
+	get_m_n_optimized(1200000, 27000, &m, &n, 0);
+	get_m_n_optimized(1200000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1584000\n");
+	get_m_n_optimized(1584000, 12000, &m, &n, 0);
+	get_m_n_optimized(1584000, 13000, &m, &n, 0);
+	get_m_n_optimized(1584000, 16800, &m, &n, 400);
+	get_m_n_optimized(1584000, 19200, &m, &n, 0);
+	get_m_n_optimized(1584000, 26000, &m, &n, 0);
+	get_m_n_optimized(1584000, 27000, &m, &n, 0);
+	get_m_n_optimized(1584000, 38400, &m, &n, 0);
+
+	printf("\nCore 1600000\n");
+	get_m_n_optimized(1600000, 12000, &m, &n, 0);
+	get_m_n_optimized(1600000, 13000, &m, &n, 0);
+	get_m_n_optimized(1600000, 16800, &m, &n, 200);
+	get_m_n_optimized(1600000, 19200, &m, &n, 0);
+	get_m_n_optimized(1600000, 26000, &m, &n, 0);
+	get_m_n_optimized(1600000, 27000, &m, &n, 0);
+	get_m_n_optimized(1600000, 38400, &m, &n, 0);
+
+	printf("\nPER 1536000\n");
+	get_m_n_optimized(1536000, 12000, &m, &n, 0);
+	get_m_n_optimized(1536000, 13000, &m, &n, 0);
+	get_m_n_optimized(1536000, 16800, &m, &n, 0);
+	get_m_n_optimized(1536000, 19200, &m, &n, 0);
+	get_m_n_optimized(1536000, 26000, &m, &n, 0);
+	get_m_n_optimized(1536000, 27000, &m, &n, 0);
+	get_m_n_optimized(1536000, 38400, &m, &n, 0);
+
+	printf("\nIVA 1862000\n");
+	get_m_n_optimized(1862000, 12000, &m, &n, 0);
+	get_m_n_optimized(1862000, 13000, &m, &n, 0);
+	get_m_n_optimized(1862000, 16800, &m, &n, 0);
+	get_m_n_optimized(1862000, 19200, &m, &n, 900);
+	get_m_n_optimized(1862000, 26000, &m, &n, 0);
+	get_m_n_optimized(1862000, 27000, &m, &n, 0);
+	get_m_n_optimized(1862000, 38400, &m, &n, 800);
+
+	printf("\nABE 196608 sys clk\n");
+	get_m_n_optimized(196608, 12000, &m, &n, 700);
+	get_m_n_optimized(196608, 13000, &m, &n, 200);
+	get_m_n_optimized(196608, 16800, &m, &n, 700);
+	get_m_n_optimized(196608, 19200, &m, &n, 400);
+	get_m_n_optimized(196608, 26000, &m, &n, 200);
+	get_m_n_optimized(196608, 27000, &m, &n, 900);
+	get_m_n_optimized(196608, 38400, &m, &n, 0);
+
+	printf("\nABE 196608 32K\n");
+	get_m_n_optimized(196608000/4, 32768, &m, &n, 0);
+
+	printf("\nUSB 1920000\n");
+	get_m_n_optimized(1920000, 12000, &m, &n, 0);
+	get_m_n_optimized(1920000, 13000, &m, &n, 0);
+	get_m_n_optimized(1920000, 16800, &m, &n, 0);
+	get_m_n_optimized(1920000, 19200, &m, &n, 0);
+	get_m_n_optimized(1920000, 26000, &m, &n, 0);
+	get_m_n_optimized(1920000, 27000, &m, &n, 0);
+	get_m_n_optimized(1920000, 38400, &m, &n, 0);
+
+	printf("\nCore ES1 1523712\n");
+	get_m_n_optimized(1524000, 12000, &m, &n, 100);
+	get_m_n_optimized(1524000, 13000, &m, &n, 0);
+	get_m_n_optimized(1524000, 16800, &m, &n, 0);
+	get_m_n_optimized(1524000, 19200, &m, &n, 0);
+	get_m_n_optimized(1524000, 26000, &m, &n, 0);
+	get_m_n_optimized(1524000, 27000, &m, &n, 0);
+
+	/* exact recommendation for SDPs */
+	get_m_n_optimized(1523712, 38400, &m, &n, 0);
+
+}
-- 
1.7.0.4

[U-Boot] [PATCH v4 05/12] omap4: add sdram init support

[Aneesh V]

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Minor corrections in do_lpddr2_init()
* Minor corrections to read_idle interval calculation
* Sanity test of memory after doing the initialization
* Fixed warnings reported with with latest GCC compilers
V3:
* Removed references to modify_reg_32()
* Updated references to OMAP_INIT_CONTEXT_* flags
* Replaced calls to omap4_revision() with omap_revision()
* Replaced sanity test with get_ram_size()
---
 arch/arm/cpu/armv7/omap4/Makefile           |    2 +
 arch/arm/cpu/armv7/omap4/board.c            |    6 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  328 +++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  131 ++++
 arch/arm/include/asm/arch-omap4/clocks.h    |    8 +-
 arch/arm/include/asm/arch-omap4/emif.h      | 1025 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |    5 +
 arch/arm/include/asm/arch-omap4/sys_proto.h |    2 +
 8 files changed, 1500 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index ac4b2a6..e1ccd68 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -29,7 +29,9 @@ SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clocks.o
+COBJS	+= emif.o
 COBJS	+= mem.o
+COBJS	+= sdram_elpida.o
 COBJS	+= sys_info.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 1c26a66..ca107f7 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -189,7 +189,7 @@ void watchdog_init(void)
  * This is needed because the size of memory installed may be
  * different on different versions of the board
  */
-u32 sdram_size(void)
+u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
@@ -215,8 +215,8 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
-	gd->ram_size = sdram_size();
+	sdram_init();
+	gd->ram_size = omap4_sdram_size();
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..b25c1ee
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,328 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+	sdelay(2000);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
+
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/*
+	 * Workaround:
+	 * In a specific situation, the OCP interface between the DMM and
+	 * EMIF may hang.
+	 * 1. A TILER port is used to perform 2D burst writes of
+	 *       width 1 and height 8
+	 * 2. ELLAn port is used to perform reads
+	 * 3. All accesses are routed to the same EMIF controller
+	 *
+	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
+	 * be kept higher than default 0x7. As per recommondation 0x0A will
+	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
+	 */
+	if (omap_revision() == OMAP4430_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
+		       &emif->emif_l3_config);
+	}
+}
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs;
+	u32 in_sdram, emif_nr;
+
+	debug(">>do_sdram_init() %x\n", base);
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+	emif_get_reg_dump(emif_nr, &regs);
+	if (!regs) {
+		debug("EMIF: reg dump not provided\n");
+		return;
+	}
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+
+	debug("<<do_sdram_init() %x\n", base);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	struct control_lpddr2io_regs *lpddr2io_regs =
+		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+	emif_get_dmm_regs(&lisa_map_regs);
+
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram, size_prog, size_detect;
+
+	debug(">>sdram_init()\n");
+
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	in_sdram = running_from_sdram();
+	debug("in_sdram = %d\n", in_sdram);
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(&prcm->cm_clkmode_dpll_core);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+
+	/* Do some testing after the init */
+	if (!in_sdram) {
+		size_prog = omap4_sdram_size();
+		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+						size_prog);
+		/* Compare with the size programmed */
+		if (size_detect != size_prog) {
+			printf("SDRAM: identified size not same as expected"
+				" size identified: %x expected: %x\n",
+				size_detect,
+				size_prog);
+		} else
+			debug("get_ram_size() successful");
+	}
+
+	debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..c950c87
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,131 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
+ * SDP and Panda. Since the parts used and geometry are identical for
+ * SDP and Panda for a given OMAP4 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP4 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_2cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 71db39c..37bdcee 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -33,10 +33,10 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+#define CM_CLKMODE_DPLL_CORE		0x4A004120
+#define CM_CLKMODE_DPLL_PER		0x4A008140
+#define CM_CLKMODE_DPLL_MPU		0x4A004160
+#define CM_CLKSEL_CORE			0x4A004100
 
 struct omap4_prcm_regs {
 	/* cm1.ckgen */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..09e9baa
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,1025 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+struct control_lpddr2io_regs {
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value for ES1*/
+#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen@lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 76b06c2..c9c86e1 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define LPDDR2_IO_REGS_BASE	0x4A100638
+
+#define CONTROL_EFUSE_2		0x4A100704
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index f871921..7183a90 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,8 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
+u32 omap4_sdram_size(void);
 
 static inline u32 running_from_sdram(void)
 {
-- 
1.7.0.4

[U-Boot] [PATCH v4 06/12] omap4: calculate EMIF register values

[Aneesh V]

Calculate EMIF register values based on AC timing parameters
from the SDRAM datasheet and the DDR frequency rather than
using the hard-coded values.

For a new board the user doen't have to go through the tedious
process of calculating the register values. Instead, just
provide the AC timings from the device data sheet as input
and the driver will automatically calculate the register values.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Added SDRAM init related CONFIG flags for Panda too.
  Earlier Panda support for everything was added in a
  single patch at the end
* Replaced calls to omap4_revision() with omap_revision()
* Reorganization of code for better readability
* Some code re-organization to reduce #ifdef complexities -
  cleanly separated out functions for getting device details
  (geometry) vs timings
* Ensured un-necessary code is compiled out if
  CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REG is defined
---
 arch/arm/cpu/armv7/omap-common/Makefile     |    1 +
 arch/arm/cpu/armv7/omap-common/utils.c      |   57 ++
 arch/arm/cpu/armv7/omap4/board.c            |    9 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  739 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  151 ++++++
 arch/arm/include/asm/arch-omap4/emif.h      |    9 +
 arch/arm/include/asm/arch-omap4/omap4.h     |   10 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_panda.h               |    5 +
 include/configs/omap4_sdp4430.h             |    5 +
 10 files changed, 977 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..8f698f8 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..ea935da
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2011 Linaro Limited
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index ca107f7..786c239 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -193,13 +194,13 @@ u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index b25c1ee..ceead9e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -170,6 +170,628 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	config_reg |=  (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
+	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+			OMAP44XX_REG_IBANK_POS_SHIFT;
+
+	config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
+
+	config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
+
+	config_reg |= addressing->row_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_ROWSIZE_SHIFT;
+
+	config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
+
+	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+			OMAP44XX_REG_EBANK_SHIFT;
+
+	config_reg |= addressing->col_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_PAGESIZE_SHIFT;
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
+
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
+	tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
+
+	zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
+
+	zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
+
+	zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
+
+	zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
+
+	alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
+
+	idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+	/* Other fields are constant magic values. Hardcode them together */
+	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+		OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+	return phy;
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = &jedec_default_timings;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
@@ -180,11 +802,54 @@ static void do_sdram_init(u32 base)
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_reg_dump(emif_nr, &regs);
 	if (!regs) {
 		debug("EMIF: reg dump not provided\n");
 		return;
 	}
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+	struct emif_device_details dev_details;
+	struct emif_regs calculated_regs;
+
+	/*
+	 * Get device details:
+	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+	 * - Obtained from user otherwise
+	 */
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	emif_get_device_details(emif_nr, &cs0_dev_details,
+				&cs1_dev_details);
+	dev_details.cs0_device_details = &cs0_dev_details;
+	dev_details.cs1_device_details = &cs1_dev_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+	/*
+	 * Get device timings:
+	 * - Default timings specified by JESD209-2 if
+	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+	 * - Obtained from user otherwise
+	 */
+	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+				&dev_details.cs1_device_timings);
+
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
 	 * Initializing the LPDDR2 device can not happen from SDRAM.
@@ -242,8 +907,82 @@ static void dmm_init(u32 base)
 {
 	const struct dmm_lisa_map_regs *lisa_map_regs;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) <<
+				OMAP44XX_SYS_ADDR_SHIFT;
+		section_map |= get_dmm_section_size_map(mapped_size * 2)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif1_size)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= (mapped_size >> 24) <<
+				OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif2_size) <<
+				OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
 	    (struct dmm_lisa_map_regs *)base;
 
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index c950c87..7757aad 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -46,6 +46,8 @@
  * - emif_get_device_timings()
  */
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
@@ -129,3 +131,152 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 omap_rev = omap_revision();
+
+	/* EMIF1 & EMIF2 have identical configuration */
+	*cs0_device_details = elpida_2G_S4_details;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		cs1_device_details = NULL;
+	else
+		*cs1_device_details = elpida_2G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	u32 omap_rev = omap_revision();
+
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*cs1_device_timings = NULL;
+	else
+		*cs1_device_timings = &elpida_2G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 09e9baa..a167508 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1019,7 +1019,16 @@ struct emif_regs {
 #define emif_assert(c)	({ if (0) hang(); })
 #endif
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index c9c86e1..a8dbedb 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -84,12 +84,6 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
 /*
  * Hardware Register Details
  */
@@ -137,6 +131,10 @@ struct s32ktimer {
 #define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
 /* SRAM scratch space entries */
 #define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
 
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 7183a90..1e62878 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,7 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_sdram_size(void);
 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 1daffb7..9f82ef4 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -237,4 +237,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 68ffa87..6df1c3d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -243,4 +243,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 07/12] omap4: automatic sdram detection

[Aneesh V]

Identify SDRAM devices connected to EMIF automatically:
LPDDR2 devices have some Mode Registers that provide details
about the device such as the type, density, bus width
etc. EMIF has the capability to read these registers. If there
are no devices connected to a given chip-select reading mode
registers will return junk values. After reading as many such
registers as possible and matching with expected ranges of
values the driver can identify if there is a device connected
to the respective CS. If we identify that a device is connected
the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2
allows us to do a complete automatic initialization of
SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2
will be safe for all devices but not necessarily optimal. However,
for the Elpida devices used on Panda and SDP the default timings
are both safe and optimal.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Code re-organization for better readability
* Ensured that un-necessary code is compiled out when
  CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is not defined
---
 arch/arm/cpu/armv7/omap4/emif.c |  238 +++++++++++++++++++++++++++++++++++++++
 include/configs/omap4_panda.h   |    1 +
 include/configs/omap4_sdp4430.h |    1 +
 3 files changed, 240 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index ceead9e..1234a7e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -792,6 +792,244 @@ void emif_get_device_timings(u32 emif_nr,
 }
 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
+
+	if (running_from_sdram()) {
+		/*
+		 * We can not do automatic discovery running from SDRAM
+		 * Most likely we came here by mistake. Indicate error
+		 * by returning NULL
+		 */
+		cs0_device_details = NULL;
+		cs1_device_details = NULL;
+	} else {
+		/*
+		 * Automatically find the device details:
+		 *
+		 * Reset the PHY after each call to get_lpddr2_details().
+		 * If there is nothing connected to a given chip select
+		 * (typically CS1) mode register reads will mess up with
+		 * the PHY state and subsequent initialization won't work.
+		 * PHY reset brings back PHY to a good state.
+		 */
+		cs0_device_details =
+		    get_lpddr2_details(base, CS0, cs0_device_details);
+		emif_reset_phy(base);
+
+		cs1_device_details =
+		    get_lpddr2_details(base, CS1, cs1_device_details);
+		emif_reset_phy(base);
+	}
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 9f82ef4..a8dd861 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -239,6 +239,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 6df1c3d..534f89a 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -245,6 +245,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH v4 08/12] armv7: start.S: fixes and enhancements for SPL

[Aneesh V]

- Allow SPL to have .bss disjoint from rest of the image
- Allow for .bss setup in CONFIG_SPL_BUILD case too.
- Take care of the special case where relocation offset = 0.
- Compile out exception handling code and install a simpler
  vector

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Taken care of the case where .bss is at a lower address
  comapred to  _start
---
 arch/arm/cpu/armv7/start.S    |   50 ++++++++++++++++++++++++++++++----------
 arch/arm/cpu/armv7/u-boot.lds |    2 +
 2 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index d2a6207..5be436f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
 .global _end_vect
 _end_vect:
 
@@ -89,6 +100,10 @@ _armboot_start:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -182,12 +197,11 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_SPL_BUILD
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
@@ -235,20 +249,34 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 clear_bss:
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -276,13 +304,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -327,6 +348,8 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+
+#ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
@@ -514,4 +537,5 @@ fiq:
 	bad_save_user_regs
 	bl	do_fiq
 
-#endif
+#endif /* CONFIG_USE_IRQ */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index dbae54d..40ecf78 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
-- 
1.7.0.4

[U-Boot] [PATCH v4 09/12] omap: add basic SPL support

[Aneesh V]

- Provide alternate implementations of board_init_f()
  board_init_r() for OMAP spl.
- Provide linker script
- Initialize global data
- Add serial console support
- Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move
  it to board config header from config.mk

Signed-off-by: Aneesh V <aneesh@ti.com>
---

This patch adds two checkpatch warnings that look like false
positives. Reported these to checkpatch maintainer.

V2:
* Removed the label __flash_image_end because _end serves the
  same purpose after rebasing to latest mainline

V3:
* Moved CONFIG_SYS_TEXT_BASE to board config header and
  deleted config.mk
* Changes for the struct based register accesses
* Removed usage of modify_reg_32() macro
* omap4_rev_string() reference changed to omap_rev_string()
* Folded the patches for linker script changes and console
  support into this patch
* Improved commit message

V4:
* Changed the CONFIG_SYS_SPL_* config flags to:
  CONFIG_SPL_*
* Changed the name omap4_rev_string used in spl.c as this
  file is common for OMAP3/4
---
 arch/arm/cpu/armv7/Makefile                   |    7 ++-
 arch/arm/cpu/armv7/omap-common/Makefile       |    4 +
 arch/arm/cpu/armv7/omap-common/spl.c          |   82 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds |   62 +++++++++++++++++++
 arch/arm/cpu/armv7/omap4/Makefile             |    5 +-
 arch/arm/cpu/armv7/omap4/board.c              |    7 ++
 arch/arm/cpu/armv7/omap4/clocks.c             |   33 ++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h   |    1 +
 arch/arm/include/asm/omap_common.h            |    2 +
 board/ti/panda/Makefile                       |    2 +
 board/ti/panda/config.mk                      |   31 ---------
 board/ti/sdp4430/Makefile                     |    2 +
 board/ti/sdp4430/config.mk                    |   31 ---------
 include/configs/omap4_panda.h                 |   26 ++++++++
 include/configs/omap4_sdp4430.h               |   26 ++++++++
 15 files changed, 257 insertions(+), 64 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 delete mode 100644 board/ti/panda/config.mk
 delete mode 100644 board/ti/sdp4430/config.mk

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 299792a..92a5a96 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	:= start.o
-COBJS	:= cpu.o cache_v7.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= cache_v7.o
+COBJS	+= cpu.o
+endif
+
 COBJS  += syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 8f698f8..0708796 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -30,6 +30,10 @@ SOBJS	:= reset.o
 COBJS	:= timer.o
 COBJS	+= utils.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS	+= spl.o
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
new file mode 100644
index 0000000..b201543
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * We call relocate_code() with relocation target same as the
+	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+	 * skipped. Instead, only .bss initialization will happen. That's
+	 * all we need
+	 */
+	debug(">>board_init_f()\n");
+	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}
+
+void preloader_console_init(void)
+{
+	const char *u_boot_rev = U_BOOT_VERSION;
+	char rev_string_buffer[50];
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	setup_clocks_for_console();
+	serial_init();		/* serial communications setup */
+
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+
+	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+		U_BOOT_TIME);
+	omap_rev_string(rev_string_buffer);
+	printf("Texas Instruments %s\n", rev_string_buffer);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
new file mode 100644
index 0000000..8867e06
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/armv7/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index e1ccd68..e7ee0b8 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -30,9 +30,12 @@ SOBJS	+= lowlevel_init.o
 COBJS	+= board.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
-COBJS	+= mem.o
 COBJS	+= sdram_elpida.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= mem.o
 COBJS	+= sys_info.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 786c239..54dd509 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -155,7 +155,14 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+#endif
 	prcm_init();
+#ifdef CONFIG_SPL_BUILD
+	/* For regular u-boot sdram_init() is called from dram_init() */
+	sdram_init();
+#endif
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index e8d3a52..f1e233a 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -791,6 +791,39 @@ void lock_dpll(u32 *const base)
 	wait_for_lock(base);
 }
 
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable all UARTs - console will be on one of them */
+	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
 void prcm_init(void)
 {
 	switch (omap4_hw_init_context()) {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 1e62878..a81f8e5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);
 void freq_update_core(void);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 33caa4e..69d53d2 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -34,4 +34,6 @@
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
+void preloader_console_init(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index 2186403..09f88ee 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/panda/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index f1ee544..12f2743 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= sdp.o cmd_bat.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/sdp4430/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index a8dd861..1112362 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -243,4 +243,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 534f89a..6a6be9e 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -249,4 +249,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 10/12] Correct ih_os for u-boot.img

[Aneesh V]

Provide appropriate '-O u-boot' while doing mkimage
for u-boot.img

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 Makefile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 0707036..f8ae883 100644
--- a/Makefile
+++ b/Makefile
@@ -375,7 +375,7 @@ $(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
 
 $(obj)u-boot.img:	$(obj)u-boot.bin
 		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-		-a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+		-O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
 		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
-- 
1.7.0.4

[U-Boot] [PATCH v4 11/12] omap: add MMC and FAT support to SPL

[Aneesh V]

- Add MMC raw and FAT mode boot support for OMAP
- Provide a means by which parameters passed by ROM-code
  can be saved in u-boot.
- Save boot mode related information passed by OMAP4 ROM-code
  and use it to determine where to load the u-boot from
- Assumes that the image has a mkimage header. Gets the
  payload size and load address from this header. If the
  header is not detected assume u-boot.bin as payload

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Squashed the patches that provided MMC support, FAT support,
  start.S hook for saving parameters, and OMAP4 patch for saving
  the parameters all into this patch.
* Removed the assumption that payload is u-boot.bin. Payload
  size and address
---
 arch/arm/cpu/armv7/cpu.c                 |    7 +
 arch/arm/cpu/armv7/omap-common/spl.c     |  194 +++++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/board.c         |   21 ++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S |   31 +++++
 arch/arm/cpu/armv7/start.S               |    1 +
 arch/arm/include/asm/arch-omap4/omap4.h  |    8 ++
 arch/arm/include/asm/omap_common.h       |   17 +++
 include/configs/omap4_panda.h            |    5 +
 include/configs/omap4_sdp4430.h          |    5 +
 9 files changed, 287 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index def9ced..091e3e0 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -37,6 +37,13 @@
 #include <asm/cache.h>
 #include <asm/armv7.h>
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index b201543..d177652 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -24,15 +24,27 @@
  */
 #include <common.h>
 #include <asm/u-boot.h>
+#include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
+#include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <image.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Define global data structure pointer to it*/
 static gd_t gdata __attribute__ ((section(".data")));
 static bd_t bdata __attribute__ ((section(".data")));
+static const char *image_name;
+static u8 image_os;
+static u32 image_load_addr;
+static u32 image_entry_point;
+static u32 image_size;
 
 inline void hang(void)
 {
@@ -53,10 +65,188 @@ void board_init_f(ulong dummy)
 	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0);
+		break;
+	case BOOT_DEVICE_MMC2:
+		omap_mmc_init(1);
+		break;
+	}
+	return 0;
+}
+#endif
+
+static void parse_image_header(const struct image_header *header)
+{
+	u32 header_size = sizeof(struct image_header);
+
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		image_size = __be32_to_cpu(header->ih_size) + header_size;
+		image_entry_point = __be32_to_cpu(header->ih_load);
+		/* Load including the header */
+		image_load_addr = image_entry_point - header_size;
+		image_os = header->ih_os;
+		image_name = (const char *)&header->ih_name;
+		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
+			image_name, image_load_addr, image_size);
+	} else {
+		/* Signature not found - assume u-boot.bin */
+		printf("mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		puts("Assuming u-boot.bin ..\n");
+		/* Let's assume U-Boot will not be more than 200 KB */
+		image_size = 200 * 1024;
+		image_entry_point = CONFIG_SYS_TEXT_BASE;
+		image_load_addr = CONFIG_SYS_TEXT_BASE;
+		image_os = IH_OS_U_BOOT;
+		image_name = "U-Boot";
+	}
+}
+
+static void mmc_load_image_raw(struct mmc *mmc)
+{
+	u32 image_size_sectors, err;
+	const struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	/* read image header to find the image size & load address */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)header);
+
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	/* convert size to sectors - round up */
+	image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) /
+				MMCSD_SECTOR_SIZE;
+
+	/* Read the header too to avoid extra memcpy */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+			image_size_sectors, (void *)image_load_addr);
+
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_image_fat(struct mmc *mmc)
+{
+	s32 err;
+	struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)image_load_addr, 0);
+
+end:
+	if (err <= 0) {
+		printf("spl: error reading image %s, err - %d\n",
+			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
+		hang();
+	}
+}
+
+static void mmc_load_image(void)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: err - %d\n", err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW) {
+		debug("boot mode - RAW\n");
+		mmc_load_image_raw(mmc);
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		debug("boot mode - FAT\n");
+		mmc_load_image_fat(mmc);
+	} else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) image_entry_point;
+
+	image_entry();
+}
+
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
 void board_init_r(gd_t *id, ulong dummy)
 {
-	for (;;)
-		;
+	u32 boot_device;
+	debug(">>spl:board_init_r()\n");
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	boot_device = omap_boot_device();
+	debug("boot device - %d\n", boot_device);
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_image();
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	switch (image_os) {
+	case IH_OS_U_BOOT:
+		debug("Jumping to U-Boot\n");
+		jump_to_image_no_args();
+		break;
+	default:
+		puts("Unsupported OS image.. Jumping nevertheless..\n");
+		jump_to_image_no_args();
+	}
 }
 
 void preloader_console_init(void)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 54dd509..2e5739a 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -39,6 +39,27 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 6abfbba..91525ec 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_SPL_BUILD
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5be436f..89ea01f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -134,6 +134,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a8dbedb..563544f 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -144,4 +144,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_2	0x44300220
 #define OMAP4430_ES2_3	0x44300230
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 69d53d2..d3cb857 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -36,4 +36,21 @@
 
 void preloader_console_init(void);
 
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 1112362..f6f283a 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -252,6 +252,11 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 6a6be9e..346763d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -258,6 +258,11 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-- 
1.7.0.4

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Aneesh V]

From: John Rigby <john.rigby@linaro.org>

- Add mkimage support for OMAP boot image
- Add support for OMAP boot image(MLO) generation in the new
  SPL framework

Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
 * Fixed minor issue with casting away 'const'ness of
   pointers
 * Ensure lists are sorted alphabetically
 * Added an error message
 * Removed 'packed' attribute from structs
 * Fixed some other minor comments on V2
 * Adapted for the new SPL framework
V4:
 * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
---
 arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
 common/image.c                     |    9 +-
 include/image.h                    |    1 +
 spl/Makefile                       |    6 +
 tools/Makefile                     |    2 +
 tools/mkimage.c                    |    2 +
 tools/mkimage.h                    |    1 +
 tools/omapimage.c                  |  224 ++++++++++++++++++++++++++++++++++++
 tools/omapimage.h                  |   50 ++++++++
 9 files changed, 321 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/config.mk
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
new file mode 100644
index 0000000..b34fa64
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/common/image.c b/common/image.c
index e542a57..a141904 100644
--- a/common/image.c
+++ b/common/image.c
@@ -130,17 +130,18 @@ static const table_entry_t uimage_os[] = {
 };
 
 static const table_entry_t uimage_type[] = {
-	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
 	{	IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image",	},
 	{	IH_TYPE_FIRMWARE,   "firmware",	  "Firmware",		},
+	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
+	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	IH_TYPE_KERNEL,	    "kernel",	  "Kernel Image",	},
+	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
 	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
 	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
 	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
-	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
-	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
-	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index c31e862..c606644 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types
diff --git a/spl/Makefile b/spl/Makefile
index 0c0ae2a..5cdd9e9 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -85,6 +85,12 @@ LDPPFLAGS += \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
+ifdef CONFIG_OMAP
+$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
 ALL-y	+= $(obj)u-boot-spl.bin
 
 all:	$(ALL-y)
diff --git a/tools/Makefile b/tools/Makefile
index 97f83f8..cb7f92d 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -88,6 +88,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
 OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
@@ -188,6 +189,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
 			$(obj)md5.o \
 			$(obj)mkimage.o \
 			$(obj)os_support.o \
+			$(obj)omapimage.o \
 			$(obj)sha1.o \
 			$(LIBFDT_OBJS)
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 60f7263..b6a7cb7 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -156,6 +156,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 9033a7d..3b49645 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/omapimage.c b/tools/omapimage.c
new file mode 100644
index 0000000..29d91cc
--- /dev/null
+++ b/tools/omapimage.c
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "omapimage.h"
+
+/* Header size is CH header rounded up to 512 bytes plus GP header */
+#define OMAP_CH_HDR_SIZE 512
+#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+
+static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
+
+static int omapimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_OMAPIMAGE)
+		return EXIT_SUCCESS;
+	else {
+		fprintf(stderr, "Unknown OMAP image type - %x", type);
+		return EXIT_FAILURE;
+	}
+}
+
+/*
+ * Only the simplest image type is currently supported:
+ * TOC pointing to CHSETTINGS
+ * TOC terminator
+ * CHSETTINGS
+ *
+ * padding to OMAP_CH_HDR_SIZE bytes
+ *
+ * gp header
+ *   size
+ *   load_addr
+ */
+static int valid_gph_size(uint32_t size)
+{
+	return size;
+}
+
+static int valid_gph_load_addr(uint32_t load_addr)
+{
+	return load_addr;
+}
+
+static int omapimage_verify_header(unsigned char *ptr, int image_size,
+			struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+		if (!offset || !size)
+			return -1;
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			return -1;
+		toc++;
+	}
+	if (!valid_gph_size(gph->size))
+		return -1;
+	if (!valid_gph_load_addr(gph->load_addr))
+		return -1;
+
+	return 0;
+}
+
+static void omapimage_print_section(struct ch_settings *chs)
+{
+	const char *section_name;
+
+	if (chs->section_key)
+		section_name = "CHSETTINGS";
+	else
+		section_name = "UNKNOWNKEY";
+
+	printf("%s (%x) "
+		"valid:%x "
+		"version:%x "
+		"reserved:%x "
+		"flags:%x\n",
+		section_name,
+		chs->section_key,
+		chs->valid,
+		chs->version,
+		chs->reserved,
+		chs->flags);
+}
+
+static void omapimage_print_header(const void *ptr)
+{
+	const struct ch_toc *toc = (struct ch_toc *)ptr;
+	const struct gp_header *gph =
+			(struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			exit(EXIT_FAILURE);
+
+		printf("Section %s offset %x length %x\n",
+			toc->section_name,
+			toc->section_offset,
+			toc->section_size);
+
+		omapimage_print_section((struct ch_settings *)(ptr+offset));
+		toc++;
+	}
+
+	if (!valid_gph_size(gph->size)) {
+		fprintf(stderr,
+			"Error: invalid image size %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!valid_gph_load_addr(gph->load_addr)) {
+		fprintf(stderr,
+			"Error: invalid image load address %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	printf("GP Header: Size %x LoadAddr %x\n",
+		gph->size, gph->load_addr);
+}
+
+static int toc_offset(void *hdr, void *member)
+{
+	return member - hdr;
+}
+
+static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct ch_settings *chs = (struct ch_settings *)
+					(ptr + 2 * sizeof(*toc));
+	struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE);
+
+	toc->section_offset = toc_offset(ptr, chs);
+	toc->section_size = sizeof(struct ch_settings);
+	strcpy((char *)toc->section_name, "CHSETTINGS");
+
+	chs->section_key = KEY_CHSETTINGS;
+	chs->valid = 0;
+	chs->version = 1;
+	chs->reserved = 0;
+	chs->flags = 0;
+
+	toc++;
+	memset(toc, 0xff, sizeof(*toc));
+
+	gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
+	gph->load_addr = params->addr;
+}
+
+int omapimage_check_params(struct mkimage_params *params)
+{
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+/*
+ * omapimage parameters
+ */
+static struct image_type_params omapimage_params = {
+	.name		= "TI OMAP CH/GP Boot Image support",
+	.header_size	= OMAP_FILE_HDR_SIZE,
+	.hdr		= (void *)&omapimage_header,
+	.check_image_type = omapimage_check_image_types,
+	.verify_header	= omapimage_verify_header,
+	.print_header	= omapimage_print_header,
+	.set_header	= omapimage_set_header,
+	.check_params	= omapimage_check_params,
+};
+
+void init_omap_image_type(void)
+{
+	mkimage_register(&omapimage_params);
+}
diff --git a/tools/omapimage.h b/tools/omapimage.h
new file mode 100644
index 0000000..719db00
--- /dev/null
+++ b/tools/omapimage.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAPIMAGE_H_
+#define _OMAPIMAGE_H_
+
+struct ch_toc {
+	uint32_t section_offset;
+	uint32_t section_size;
+	uint8_t unused[12];
+	uint8_t section_name[12];
+};
+
+struct ch_settings {
+	uint32_t section_key;
+	uint8_t valid;
+	uint8_t version;
+	uint16_t reserved;
+	uint32_t flags;
+};
+
+struct gp_header {
+	uint32_t size;
+	uint32_t load_addr;
+};
+
+#define KEY_CHSETTINGS 0xC0C0C0C1
+#endif /* _OMAPIMAGE_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v4 11/12] omap: add MMC and FAT support to SPL

[Simon Schwarz]

Hi Aneesh,

I'am not really sure about the save_boot_params() feature you added.

May you point me where I can find this in the OMAP reference docs?

Thanks!
Simon

[U-Boot] [PATCH v4 11/12] omap: add MMC and FAT support to SPL

[Aneesh V]

Hi Simon,

On Tuesday 19 July 2011 02:46 PM, Simon Schwarz wrote:
> Hi Aneesh,
>
> I'am not really sure about the save_boot_params() feature you added.
>
> May you point me where I can find this in the OMAP reference docs?

What I have done for OMAP4 will not work for OMAP3. For OMAP3 you will
get only the boot-device(eMMC, MMC/SD, nand etc) and *not* the bootmode(raw
vs FAT).

To get boot device you can don one of the following approaches.

1. What x-loader does

git://git.omapzoom.org/repo/x-loader.git - master branch

cpu/omap3/start.S:

reset:
	ldr	r4, scratchpad		/* r4 <- scratchpad reg address */
	ldr	r5, [r0, #0x4]		/* r5 <- value of boot device */
	str	r5, [r4]		/* store r5 in scratchpad reg */


See the usage in lib/board.c:

Here are the device numbers:
	case 0x03:
		strcpy(boot_dev_name, "ONENAND");
	case 0x02:
		strcpy(boot_dev_name, "NAND");
	case 0x05:
		strcpy(boot_dev_name, "EMMC");
	case 0x06:
		strcpy(boot_dev_name, "MMC/SD1");

This is internal ROM code information and not documented anywhere.

You may assume FAT mode for MMC/SD1 and raw mode for the rest.

2. Read the boot device from a hw register(SYS_BOOT)

See 'chapter 26 Initialization' and look@table 26-3

best regards,
Aneesh

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[Paulraj, Sandeep]

> Aneesh V (11):
>   omap4: utility function to identify the context of hw init
>   omap4: cleanup pin mux data
>   omap4: add OMAP4430 revision check
>   omap4: add clock support
>   omap4: add sdram init support
>   omap4: calculate EMIF register values
>   omap4: automatic sdram detection
>   armv7: start.S: fixes and enhancements for SPL
>   omap: add basic SPL support
>   Correct ih_os for u-boot.img
>   omap: add MMC and FAT support to SPL
> 
> John Rigby (1):
>   mkimage: Add OMAP boot image support


Patch #8 of this seires does not apply on the current u-boot-ti
U-boot-ti now has the updated SPL framework

Please rebase with u-boot-ti and send updated patch sets for both your series.

Regards,
Sandeep

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[V, Aneesh]

Hi Sandeep,

On Thu, Jul 21, 2011 at 3:01 AM, Paulraj, Sandeep <s-paulraj@ti.com> wrote:
>> Aneesh V (11):
>> ? omap4: utility function to identify the context of hw init
>> ? omap4: cleanup pin mux data
>> ? omap4: add OMAP4430 revision check
>> ? omap4: add clock support
>> ? omap4: add sdram init support
>> ? omap4: calculate EMIF register values
>> ? omap4: automatic sdram detection
>> ? armv7: start.S: fixes and enhancements for SPL
>> ? omap: add basic SPL support
>> ? Correct ih_os for u-boot.img
>> ? omap: add MMC and FAT support to SPL
>>
>> John Rigby (1):
>> ? mkimage: Add OMAP boot image support
>
>
> Patch #8 of this seires does not apply on the current u-boot-ti
> U-boot-ti now has the updated SPL framework

There was v4 for just two of the patches of the framework series: 2/9 and 5/9.

I think you missed them. Can you correct this?

>
> Please rebase with u-boot-ti and send updated patch sets for both your series.

Sure. I will do that.

Thanks,
Aneesh

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[V, Aneesh]

Hi Sandeep,

On Thu, Jul 21, 2011 at 3:01 AM, Paulraj, Sandeep <s-paulraj@ti.com> wrote:
>> Aneesh V (11):
>> ? omap4: utility function to identify the context of hw init
>> ? omap4: cleanup pin mux data
>> ? omap4: add OMAP4430 revision check
>> ? omap4: add clock support
>> ? omap4: add sdram init support
>> ? omap4: calculate EMIF register values
>> ? omap4: automatic sdram detection
>> ? armv7: start.S: fixes and enhancements for SPL
>> ? omap: add basic SPL support
>> ? Correct ih_os for u-boot.img
>> ? omap: add MMC and FAT support to SPL
>>
>> John Rigby (1):
>> ? mkimage: Add OMAP boot image support
>
>
> Patch #8 of this seires does not apply on the current u-boot-ti
> U-boot-ti now has the updated SPL framework
>
> Please rebase with u-boot-ti and send updated patch sets for both your series.

I have done my re-basing. Will send out my series shortly. However,
please note that u-boot-ti/master is not building for me. You will need this
fix:

Fix typo from 'mb_alloc' -> 'lmb_alloc
http://patchwork.ozlabs.org/patch/105364/

best regards,
Aneesh

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[Aneesh V]

This series adds mmc SPL support for OMAP4. This is essentially
an up-streaming effort for TI's x-loader for OMAP4 using the SPL
framework

This work partly draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>
and many others

This series depends on the following series for the new SPL framework:
http://marc.info/?l=u-boot&m=131056990001719&w=2

Features supported:
* Clock init - DPLL locking, clock domains/modules enabling
* SDRAM/DMM initialization
* Mux initialization
* MMC raw read support
* MMC FAT read support

Improvments over x-loader:
* Code completely revamped
* DPLL programming that works for all SYS_CLK frequencies
* Automatic SDRAM identification and initialization
* Board dependent parts(especially mux) deferred to u-boot. So, same
  SPL will work for Panda and SDP and most likely on any other board
  that comes along
* Flexible about the payload. Any image with a mkimage header can be
  loaded.
* The core SPL logic is generic and available for OMAP3/4. So, OMAP3
  platforms can easily extend this work to add SPL support for the
  respective boards.

V2:
* Some fixes in SDRAM init, clock init
* Use of pre-calculated M & N values for DPLL locking instead
  run-time calculation
* Change in make files to allow reuse of common rules
  between boards
* Console initialization moved further earlier in the boot
  allowing traces from even clock initialization code
* Reuse utility macros from a previous series

V3:
* Moved to the new SPL framework
* struct based register access for clock init
* Squashed together related patches as per Wolfgang's suggestions
* Re-organization of code in sdram init for better readability
* SPL loading the payload using mkimage header
* Avoided using custom bit-field accessor macros
* Several other minor changes(documented in respective patches)

V4:
* Rebased on u-boot-ti/master as on 21 Jul 2011

Aneesh V (11):
  omap4: utility function to identify the context of hw init
  omap4: cleanup pin mux data
  omap4: add OMAP4430 revision check
  omap4: add clock support
  omap4: add sdram init support
  omap4: calculate EMIF register values
  omap4: automatic sdram detection
  armv7: start.S: fixes and enhancements for SPL
  omap: add basic SPL support
  Correct ih_os for u-boot.img
  omap: add MMC and FAT support to SPL

John Rigby (1):
  mkimage: Add OMAP boot image support

 Makefile                                           |    2 +-
 arch/arm/cpu/armv7/Makefile                        |    7 +-
 arch/arm/cpu/armv7/cpu.c                           |    7 +
 arch/arm/cpu/armv7/omap-common/Makefile            |    5 +
 arch/arm/cpu/armv7/omap-common/spl.c               |  272 ++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds      |   62 +
 arch/arm/cpu/armv7/omap-common/utils.c             |   57 +
 arch/arm/cpu/armv7/omap4/Makefile                  |    6 +
 arch/arm/cpu/armv7/omap4/board.c                   |  161 +++-
 arch/arm/cpu/armv7/omap4/clocks.c                  |  842 +++++++++++++
 .../panda => arch/arm/cpu/armv7/omap4}/config.mk   |   25 +-
 arch/arm/cpu/armv7/omap4/emif.c                    | 1305 ++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S           |   31 +
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c            |  282 +++++
 arch/arm/cpu/armv7/start.S                         |   50 +-
 arch/arm/cpu/armv7/u-boot.lds                      |    2 +
 arch/arm/include/asm/arch-omap4/clocks.h           |  664 ++++++++++
 arch/arm/include/asm/arch-omap4/emif.h             | 1034 ++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |   52 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |   72 ++-
 arch/arm/include/asm/armv7.h                       |    5 +
 arch/arm/include/asm/omap_common.h                 |   56 +
 board/ti/panda/Makefile                            |    2 +
 board/ti/panda/panda.c                             |   25 +-
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +-
 board/ti/sdp4430/Makefile                          |    2 +
 board/ti/sdp4430/config.mk                         |   31 -
 board/ti/sdp4430/sdp.c                             |   25 +-
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +--
 common/image.c                                     |    9 +-
 include/configs/omap4_panda.h                      |   37 +
 include/configs/omap4_sdp4430.h                    |   37 +
 include/image.h                                    |    1 +
 spl/Makefile                                       |    6 +
 tools/Makefile                                     |    2 +
 tools/mkimage.c                                    |    2 +
 tools/mkimage.h                                    |    1 +
 tools/omap/clocks_get_m_n.c                        |  197 +++
 tools/omapimage.c                                  |  224 ++++
 tools/omapimage.h                                  |   50 +
 41 files changed, 5668 insertions(+), 262 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 rename {board/ti/panda => arch/arm/cpu/armv7/omap4}/config.mk (64%)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h
 create mode 100644 arch/arm/include/asm/omap_common.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 delete mode 100644 board/ti/sdp4430/config.mk
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)
 create mode 100644 tools/omap/clocks_get_m_n.c
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

[U-Boot] [PATCH v4 01/12] omap4: utility function to identify the context of hw init

[Aneesh V]

The basic hardware init of OMAP4(s_init()) can happen in 4
different contexts:
 1. SPL running from SRAM
 2. U-Boot running from FLASH
 3. Non-XIP U-Boot loaded to SDRAM by SPL
 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
    Configuration Header feature

What level of hw initialization gets done depends on this
context. Add a utility function to find this context.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Changed the context names to more meaningful names as
  suggested by WD
---
 arch/arm/include/asm/arch-omap4/sys_proto.h |   49 ++++++++++++++++++++++++++-
 arch/arm/include/asm/omap_common.h          |   34 ++++++++++++++++++
 2 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/omap_common.h

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4fa4f4b..6b596b4 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -23,10 +23,12 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;
 };
+extern const struct omap_sysinfo sysinfo;
 
 void gpmc_init(void);
 void watchdog_init(void);
@@ -37,6 +39,51 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 
-extern const struct omap_sysinfo sysinfo;
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
 
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..d80f665
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+#endif /* _OMAP_COMMON_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Aneesh V]

- separate mux settings into essential and non essential parts
- essential part is board independent as of now(so move it
  to SoC directory). Will help in having single SPL for all
  boards.
- Non-essential part(the pins not essential for u-boot to function)
  need to be phased out eventually.
- Correct mux data by aligning to the latest settings in x-loader

Signed-off-by: Aneesh V <aneesh@ti.com>
---
This patch add 33 warnings for lines over 80 characters.
However, this for the mux table and improves readability.

V3:
* Squashed two mux related patches into one
---
 arch/arm/cpu/armv7/omap4/board.c                   |   53 ++++++++-
 arch/arm/cpu/armv7/omap4/omap4_mux_data.h          |   76 ++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    4 +-
 board/ti/panda/panda.c                             |   25 +---
 board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} |   76 +++---------
 board/ti/sdp4430/sdp.c                             |   25 +---
 .../{panda/panda.h => sdp4430/sdp4430_mux_data.h}  |  128 +++++++------------
 7 files changed, 209 insertions(+), 178 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/omap4_mux_data.h
 rename board/ti/{sdp4430/sdp.h => panda/panda_mux_data.h} (76%)
 rename board/ti/{panda/panda.h => sdp4430/sdp4430_mux_data.h} (67%)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index de4cc2a..3fd6f84 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -31,17 +31,65 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing,  andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ *	Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 }
 
 /*
@@ -124,7 +172,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 6b596b4..3624378 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
@@ -33,7 +34,8 @@ extern const struct omap_sysinfo sysinfo;
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 78e1910..9afed80 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/sdp4430/sdp.h b/board/ti/panda/panda_mux_data.h
similarity index 76%
rename from board/ti/sdp4430/sdp.h
rename to board/ti/panda/panda_mux_data.h
index bf41067..16cc0ad 100644
--- a/board/ti/sdp4430/sdp.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _SDP_H_
-#define _SDP_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -207,11 +173,11 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
@@ -252,13 +216,15 @@ const struct pad_conf_entry wkup_padconf_array[] = {
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index b13c4c5..a5ea682 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 
diff --git a/board/ti/panda/panda.h b/board/ti/sdp4430/sdp4430_mux_data.h
similarity index 67%
rename from board/ti/panda/panda.h
rename to board/ti/sdp4430/sdp4430_mux_data.h
index e3d090e..16cc0ad 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -23,22 +23,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_H_
-#define _PANDA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
-const struct pad_conf_entry core_padconf_array[] = {
-	{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat0 */
-	{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, 	/* sdmmc2_dat1 */
-	{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat2 */
-	{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat3 */
-	{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat4 */
-	{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat5 */
-	{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat6 */
-	{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_dat7 */
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
@@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
@@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_NWP, (M3)},						/* gpio_54 */
 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},		/* sdmmc2_clk */
-	{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* sdmmc2_cmd */
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
@@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
@@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
-	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
-	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
-	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
-	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
-	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
-	{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat4 */
-	{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat5 */
-	{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat6 */
-	{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat7 */
 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
@@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
 	{UART2_TX, (M0)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
@@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
-	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
-	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
-	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
@@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
@@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
@@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = {
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
 };
 
-const struct pad_conf_entry wkup_padconf_array[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif
+#endif /* _SDP4430_MUX_DATA_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 03/12] omap4: add OMAP4430 revision check

[Aneesh V]

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Added a revision string in addition to the revision number
  Helps in printing out the OMAP revision at bootup

V3:
 * Improved the revision check function by saving the
   value instead of finding it every time.
 * Improved revision string function by generating it
   from the revision rather than hard-coding the string
   per revision
---
 arch/arm/cpu/armv7/omap4/board.c            |   64 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |   29 +++++++++---
 arch/arm/include/asm/arch-omap4/sys_proto.h |    7 +++
 arch/arm/include/asm/armv7.h                |    5 ++
 4 files changed, 97 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 3fd6f84..09861a9 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
@@ -35,6 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
@@ -72,6 +75,66 @@ static void set_mux_conf_regs(void)
 	}
 }
 
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+static void init_omap4_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int arm_rev = cortex_a9_rev();
+
+	switch (arm_rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		*omap4_revision = OMAP4430_ES1_0;
+		break;
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
+			*omap4_revision = OMAP4430_ES2_1;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
+			*omap4_revision = OMAP4430_ES2_2;
+			break;
+		default:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		*omap4_revision = OMAP4430_ES2_3;
+		break;
+	default:
+		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
+		break;
+	}
+}
+
+void omap_rev_string(char *omap4_rev_string)
+{
+	u32 omap4_rev = omap_revision();
+	u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
+	u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
+	u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
+
+	sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+		minor_rev);
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -88,6 +151,7 @@ static void set_mux_conf_regs(void)
  */
 void s_init(void)
 {
+	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
 }
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..76b06c2 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,15 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -119,13 +128,17 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+#define LOW_LEVEL_SRAM_STACK		NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3624378..c10fa18 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -40,6 +40,7 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap4_rev_string);
 
 static inline u32 running_from_sdram(void)
 {
@@ -88,4 +89,10 @@ static inline u32 omap4_hw_init_context(void)
 #endif
 }
 
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap4_revision;
+	return *omap4_revision;
+}
+
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 88b9c62..b5784d8 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -25,6 +25,11 @@
 #define ARMV7_H
 #include <linux/types.h>
 
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
 #define CCSIDR_LINE_SIZE_MASK		0x7
-- 
1.7.0.4

[U-Boot] [PATCH v4 04/12] omap4: add clock support

[Aneesh V]

Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Use pre-calculated M & N values instead of calculated ones
* Changes due to make file changes
* Some corrections
* Do all clock initialization in SPL itself instead of differing some
  work to u-boot

V3:
* Use struct for register addressing
* Support only Turbo OPP for MPU. OPP's above this need Smart Reflex
  enabled
* Cleaned up the scale_vcore(). Now takes into account the differing
  voltage offsets for different revisions of Phoenix.
* Removed references to deprecated utility functions - modify_reg_32() etc.
* Changed all spl_debug() to debug()
* Moved the host-program for calculating DPLL multiplier/divider to
  tools/omap/ directory. Added more documentation
* Replaced calls to omap4_revision() with omap_revision()
* Some changes to IVA and ABE dpll locking code
---
 arch/arm/cpu/armv7/omap4/Makefile           |    1 +
 arch/arm/cpu/armv7/omap4/board.c            |    1 +
 arch/arm/cpu/armv7/omap4/clocks.c           |  809 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/clocks.h    |  664 ++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h |    8 +
 arch/arm/include/asm/omap_common.h          |    3 +
 tools/omap/clocks_get_m_n.c                 |  197 +++++++
 7 files changed, 1683 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c
 create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h
 create mode 100644 tools/omap/clocks_get_m_n.c

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..ac4b2a6 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,6 +28,7 @@ LIB	=  $(obj)lib$(SOC).o
 SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
+COBJS	+= clocks.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 09861a9..1c26a66 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -154,6 +154,7 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..e8d3a52
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,809 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
+
+static const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */
+static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
+	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{330, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{165, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{396, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{88, 2, 1, -1, -1, -1, -1, -1},		/* 27 MHz   */
+	{165, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* dpll locked at 1200 MHz - MPU clk@600 MHz */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
+	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1
+};
+
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	u32 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl(&prcm->cm_sys_clksel) &
+			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_FAST_RELOCK_BYPASS <<
+			CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+				LDELAY)) {
+		printf("Bypassing DPLL failed %p\n", base);
+	}
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
+		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+		&dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for %p\n", base);
+		hang();
+	}
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+				u8 lock)
+{
+	u32 temp;
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	switch (omap_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_1524mhz[sysclk_ind];
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		 /* safest */
+		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+	default:
+		return &core_dpll_params_1600mhz[sysclk_ind];
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz;
+	const struct dpll_params *core_dpll_params;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params();
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+static void setup_dplls(void)
+{
+	u32 sysclk_ind, temp;
+	const struct dpll_params *params;
+	debug("setup_dplls\n");
+
+	sysclk_ind = get_sys_clk_index();
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, &prcm->cm_clksel_core);
+	debug("Core DPLL configured\n");
+
+	/* lock PER dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+	debug("PER DPLL locked\n");
+
+	/* MPU dpll */
+	if (omap_revision() == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, abe_ref_clk;
+	u32 sysclk_ind, sd_div, num, den;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/* IVA */
+	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
+			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
+
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = &usb_dpll_params_1920mhz[sysclk_ind];
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
+
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+	params = &abe_dpll_params_32k_196608khz;
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+	/*
+	 * We need to enable some additional options to achieve
+	 * 196.608MHz from 32768 Hz
+	 */
+	setbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
+			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
+			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
+			CM_CLKMODE_DPLL_REGM4XEN_MASK);
+	/* Spend 4 REFCLK cycles at each stage */
+	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
+			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+#endif
+
+	/* Select the right reference clk */
+	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
+	/* Lock the dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+{
+	u32 temp, offset_code;
+	u32 step = 12660; /* 12.66 mV represented in uV */
+	u32 offset = volt_mv;
+
+	/* convert to uV for better accuracy in the calculations */
+	offset *= 1000;
+
+	if (omap_revision() == OMAP4430_ES1_0)
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+	else
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+	offset_code = (offset + step - 1) / step;
+	/* The code starts at 1 not 0 */
+	offset_code++;
+
+	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+		offset_code);
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, &prcm->prm_vc_val_bypass);
+	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				&prcm->prm_vc_val_bypass, LDELAY)) {
+		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+	}
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+
+	/*
+	 * VCORE 1 - 4430 : supplies vdd_mpu
+	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+	 * We use the maximum possible value in the AVS range because the next
+	 * higher voltage in the discrete range (code >= 0b111010) is way too
+	 * high
+	 */
+	volt = 1417;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+	/* VCORE 2 - supplies vdd_iva */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/* VCORE 3 - supplies vdd_core */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+				clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 1;
+	u32 *const clk_domains_essential[] = {
+		&prcm->cm_l4per_clkstctrl,
+		&prcm->cm_l3init_clkstctrl,
+		&prcm->cm_memif_clkstctrl,
+		&prcm->cm_l4cfg_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_wkup_gpio1_clkctrl,
+		&prcm->cm_l4per_gpio2_clkctrl,
+		&prcm->cm_l4per_gpio3_clkctrl,
+		&prcm->cm_l4per_gpio4_clkctrl,
+		&prcm->cm_l4per_gpio5_clkctrl,
+		&prcm->cm_l4per_gpio6_clkctrl,
+		&prcm->cm_memif_emif_1_clkctrl,
+		&prcm->cm_memif_emif_2_clkctrl,
+		&prcm->cm_l3init_hsusbotg_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_l4cfg_l4_cfg_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_essential[] = {
+		&prcm->cm_l4per_gptimer2_clkctrl,
+		&prcm->cm_l3init_hsmmc1_clkctrl,
+		&prcm->cm_l3init_hsmmc2_clkctrl,
+		&prcm->cm_l4per_mcspi1_clkctrl,
+		&prcm->cm_wkup_gptimer1_clkctrl,
+		&prcm->cm_l4per_i2c1_clkctrl,
+		&prcm->cm_l4per_i2c2_clkctrl,
+		&prcm->cm_l4per_i2c3_clkctrl,
+		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_l4per_uart3_clkctrl,
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 0;
+	u32 *const clk_domains_non_essential[] = {
+		&prcm->cm_mpu_m3_clkstctrl,
+		&prcm->cm_ivahd_clkstctrl,
+		&prcm->cm_dsp_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sgx_clkstctrl,
+		&prcm->cm1_abe_clkstctrl,
+		&prcm->cm_c2c_clkstctrl,
+		&prcm->cm_cam_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sdma_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_non_essential[] = {
+		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
+		&prcm->cm_ivahd_ivahd_clkctrl,
+		&prcm->cm_ivahd_sl2_clkctrl,
+		&prcm->cm_dsp_dsp_clkctrl,
+		&prcm->cm_l3_2_gpmc_clkctrl,
+		&prcm->cm_l3instr_l3_3_clkctrl,
+		&prcm->cm_l3instr_l3_instr_clkctrl,
+		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
+		&prcm->cm_l3init_hsi_clkctrl,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_non_essential[] = {
+		&prcm->cm1_abe_aess_clkctrl,
+		&prcm->cm1_abe_pdm_clkctrl,
+		&prcm->cm1_abe_dmic_clkctrl,
+		&prcm->cm1_abe_mcasp_clkctrl,
+		&prcm->cm1_abe_mcbsp1_clkctrl,
+		&prcm->cm1_abe_mcbsp2_clkctrl,
+		&prcm->cm1_abe_mcbsp3_clkctrl,
+		&prcm->cm1_abe_slimbus_clkctrl,
+		&prcm->cm1_abe_timer5_clkctrl,
+		&prcm->cm1_abe_timer6_clkctrl,
+		&prcm->cm1_abe_timer7_clkctrl,
+		&prcm->cm1_abe_timer8_clkctrl,
+		&prcm->cm1_abe_wdt3_clkctrl,
+		&prcm->cm_l4per_gptimer9_clkctrl,
+		&prcm->cm_l4per_gptimer10_clkctrl,
+		&prcm->cm_l4per_gptimer11_clkctrl,
+		&prcm->cm_l4per_gptimer3_clkctrl,
+		&prcm->cm_l4per_gptimer4_clkctrl,
+		&prcm->cm_l4per_hdq1w_clkctrl,
+		&prcm->cm_l4per_mcbsp4_clkctrl,
+		&prcm->cm_l4per_mcspi2_clkctrl,
+		&prcm->cm_l4per_mcspi3_clkctrl,
+		&prcm->cm_l4per_mcspi4_clkctrl,
+		&prcm->cm_l4per_mmcsd3_clkctrl,
+		&prcm->cm_l4per_mmcsd4_clkctrl,
+		&prcm->cm_l4per_mmcsd5_clkctrl,
+		&prcm->cm_l4per_uart1_clkctrl,
+		&prcm->cm_l4per_uart2_clkctrl,
+		&prcm->cm_l4per_uart4_clkctrl,
+		&prcm->cm_wkup_keyboard_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_cam_iss_clkctrl,
+		&prcm->cm_cam_fdif_clkctrl,
+		&prcm->cm_dss_dss_clkctrl,
+		&prcm->cm_sgx_sgx_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
+		0
+	};
+
+	/* Enable optional functional clock for ISS */
+	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable all optional functional clocks of DSS */
+	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
+	     i++) {
+		enable_clock_module(clk_modules_explicit_en_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+
+	/* Put camera module in no sleep mode */
+	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+	freq_config1 |= (core_dpll_params->m2 <<
+			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+	writel(freq_config1, &prcm->cm_shadow_freq_config1);
+	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+				&prcm->cm_shadow_freq_config1, LDELAY)) {
+		puts("FREQ UPDATE procedure failed!!");
+		hang();
+	}
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+}
+
+void bypass_dpll(u32 *const base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 *const base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		scale_vcores();
+		setup_dplls();
+		enable_basic_clocks();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..71db39c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,664 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+
+struct omap4_prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 pad001[1];
+	u32 cm_clksel_abe;
+	u32 pad002[1];
+	u32 cm_dll_ctrl;
+	u32 pad003[3];
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 pad004[3];
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 pad005[5];
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 pad006[3];
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 pad007[2];
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 pad008[2];
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 pad009[3];
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 pad010[4];
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 pad011[4];
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 pad012[1];
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 pad013[1];
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 pad014[5];
+	u32 cm_shadow_freq_config1;
+
+	/* cm1.dsp */
+	u32 pad015[103];
+	u32 cm_dsp_clkstctrl;
+	u32 pad016[7];
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 pad017[55];
+	u32 cm1_abe_clkstctrl;
+	u32 pad018[7];
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 pad019[1];
+	u32 cm1_abe_aess_clkctrl;
+	u32 pad020[1];
+	u32 cm1_abe_pdm_clkctrl;
+	u32 pad021[1];
+	u32 cm1_abe_dmic_clkctrl;
+	u32 pad022[1];
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 pad023[1];
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 pad024[1];
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 pad025[1];
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 pad026[1];
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 pad027[1];
+	u32 cm1_abe_timer5_clkctrl;
+	u32 pad028[1];
+	u32 cm1_abe_timer6_clkctrl;
+	u32 pad029[1];
+	u32 cm1_abe_timer7_clkctrl;
+	u32 pad030[1];
+	u32 cm1_abe_timer8_clkctrl;
+	u32 pad031[1];
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 pad032[3805];
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 pad033[1];
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 pad034[1];
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 pad035[1];
+	u32 cm_iva_dvfs_current;
+	u32 pad036[1];
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 pad037[3];
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 pad038[5];
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 pad039[1];
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 pad040[2];
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 pad041[5];
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+	/* cm2.core */
+	u32 pad0411[324];
+	u32 cm_l3_1_clkstctrl;
+	u32 pad042[1];
+	u32 cm_l3_1_dynamicdep;
+	u32 pad043[5];
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 pad044[55];
+	u32 cm_l3_2_clkstctrl;
+	u32 pad045[1];
+	u32 cm_l3_2_dynamicdep;
+	u32 pad046[5];
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 pad047[1];
+	u32 cm_l3_2_gpmc_clkctrl;
+	u32 pad048[1];
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 pad049[51];
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 pad050[5];
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 pad051[55];
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 pad052[5];
+	u32 cm_sdma_sdma_clkctrl;
+	u32 pad053[55];
+	u32 cm_memif_clkstctrl;
+	u32 pad054[7];
+	u32 cm_memif_dmm_clkctrl;
+	u32 pad055[1];
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 pad056[1];
+	u32 cm_memif_emif_1_clkctrl;
+	u32 pad057[1];
+	u32 cm_memif_emif_2_clkctrl;
+	u32 pad058[1];
+	u32 cm_memif_dll_clkctrl;
+	u32 pad059[3];
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 pad060[1];
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 pad061[1];
+	u32 cm_memif_dll_h_clkctrl;
+	u32 pad062[39];
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 pad063[5];
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 pad064[1];
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 pad065[1];
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 pad066[51];
+	u32 cm_l4cfg_clkstctrl;
+	u32 pad067[1];
+	u32 cm_l4cfg_dynamicdep;
+	u32 pad068[5];
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 pad069[1];
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 pad070[1];
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 pad071[1];
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 pad072[49];
+	u32 cm_l3instr_clkstctrl;
+	u32 pad073[7];
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 pad074[1];
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 pad075[5];
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+
+	/* cm2.ivahd */
+	u32 pad076[47];
+	u32 cm_ivahd_clkstctrl;
+	u32 pad077[7];
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 pad078[1];
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 pad079[53];
+	u32 cm_cam_clkstctrl;
+	u32 pad080[7];
+	u32 cm_cam_iss_clkctrl;
+	u32 pad081[1];
+	u32 cm_cam_fdif_clkctrl;
+
+	/* cm2.dss */
+	u32 pad082[53];
+	u32 cm_dss_clkstctrl;
+	u32 pad083[7];
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 pad084[55];
+	u32 cm_sgx_clkstctrl;
+	u32 pad085[7];
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 pad086[55];
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 pad087[9];
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 pad088[1];
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 pad089[1];
+	u32 cm_l3init_hsi_clkctrl;
+	u32 pad090[7];
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 pad091[1];
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 pad092[1];
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 pad093[3];
+	u32 cm_l3init_p1500_clkctrl;
+	u32 pad094[21];
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 pad095[3];
+	u32 cm_l3init_usbphy_clkctrl;
+
+	/* cm2.l4per */
+	u32 pad096[7];
+	u32 cm_l4per_clkstctrl;
+	u32 pad097[1];
+	u32 cm_l4per_dynamicdep;
+	u32 pad098[5];
+	u32 cm_l4per_adc_clkctrl;
+	u32 pad100[1];
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 pad101[1];
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 pad102[1];
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 pad103[1];
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 pad104[1];
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 pad105[1];
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 pad106[1];
+	u32 cm_l4per_elm_clkctrl;
+	u32 pad107[1];
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 pad108[1];
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 pad109[1];
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 pad110[1];
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 pad111[1];
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 pad112[1];
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 pad113[1];
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 pad114[1];
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 pad115[1];
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 pad116[1];
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 pad117[1];
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 pad118[1];
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 pad119[1];
+	u32 cm_l4per_l4per_clkctrl;
+	u32 pad1191[3];
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 pad120[1];
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 pad121[1];
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 pad122[1];
+	u32 cm_l4per_mgate_clkctrl;
+	u32 pad123[1];
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 pad124[1];
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 pad125[1];
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 pad126[1];
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 pad127[5];
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 pad128[1];
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 pad129[1];
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 pad130[1];
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 pad131[1];
+	u32 cm_l4per_uart1_clkctrl;
+	u32 pad132[1];
+	u32 cm_l4per_uart2_clkctrl;
+	u32 pad133[1];
+	u32 cm_l4per_uart3_clkctrl;
+	u32 pad134[1];
+	u32 cm_l4per_uart4_clkctrl;
+	u32 pad135[1];
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 pad136[1];
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 pad137[5];
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 pad138[5];
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 pad139[1];
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 pad140[1];
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 pad141[1];
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 pad142[1];
+	u32 cm_l4sec_rng_clkctrl;
+	u32 pad143[1];
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 pad144[3];
+	u32 cm_l4sec_cryptodma_clkctrl;
+	u32 pad145[776841];
+
+	/* l4 wkup regs */
+	u32 pad201[6211];
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 pad202[1467];
+	u32 cm_wkup_clkstctrl;
+	u32 pad203[7];
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 pad204;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 pad205;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 pad206;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 pad207;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 pad208;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 pad209;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 pad210;
+	u32 cm_wkup_usim_clkctrl;
+	u32 pad211;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 pad212[5];
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 pad213;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 pad214;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 pad215[197];
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_channel;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#define NUM_SYS_CLKS	7
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	u32 m;
+	u32 n;
+	u8 m2;
+	u8 m3;
+	u8 m4;
+	u8 m5;
+	u8 m6;
+	u8 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index c10fa18..f871921 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,6 +22,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/arch/omap4.h>
+#include <asm/arch/clocks.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mux_omap4.h>
@@ -31,6 +32,8 @@ struct omap_sysinfo {
 };
 extern const struct omap_sysinfo sysinfo;
 
+extern struct omap4_prcm_regs *const prcm;
+
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
@@ -41,6 +44,11 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
 
 static inline u32 running_from_sdram(void)
 {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d80f665..33caa4e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL			0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c
new file mode 100644
index 0000000..cfc1760
--- /dev/null
+++ b/tools/omap/clocks_get_m_n.c
@@ -0,0 +1,197 @@
+/*
+ * Program for finding M & N values for DPLLs
+ * To be run on Host PC
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <stdlib.h>
+#include <stdio.h>
+typedef unsigned int u32;
+#define MAX_N	127
+
+/*
+ * get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N)
+ * values based on the reference frequency, required output frequency,
+ * maximum tolerance for output frequency etc.
+ *
+ * target_freq_khz - output frequency required in KHz
+ * ref_freq_khz - reference(input) frequency in KHz
+ * m - pointer to computed M value
+ * n - pointer to computed N value
+ * tolerance_khz - tolerance for the output frequency. When the algorithm
+ * succeeds in finding vialble M and N values the corresponding output
+ * frequency will be in the range:
+ *	[target_freq_khz - tolerance_khz, target_freq_khz]
+ *
+ * Formula:
+ *	Fdpll = (2 * M * Fref) / (N + 1)
+ *
+ * Considerations for lock-time:
+ *	- Smaller the N, better lock-time, especially lock-time will be
+ *	- For acceptable lock-times:
+ *		Fref / (M + 1) >= 1 MHz
+ *
+ * Considerations for power:
+ *	- The difference in power for different N values giving the same
+ *	  output is negligible. So, we optimize for lock-time
+ *
+ * Hard-constraints:
+ *	- N can not be greater than 127(7 bit field for representing N)
+ *
+ * Usage:
+ *	$ gcc clocks_get_m_n.c
+ *	$ ./a.out
+ */
+int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n,
+			u32 tolerance_khz)
+{
+	u32 min_freq = target_freq_khz - tolerance_khz;
+	u32 max_freq = target_freq_khz;
+	u32 freq, freq_old;
+	*n = 1;
+	while (1) {
+		*m = min_freq / ref_freq_khz / 2 * (*n) ;
+		freq_old = 0;
+		while (1) {
+			freq = ref_freq_khz * 2 * (*m) / (*n);
+			if (abs(target_freq_khz - freq_old) <=
+				abs(target_freq_khz - freq)) {
+				freq = freq_old;
+				(*m)--;
+				break;
+			}
+			(*m)++;
+			freq_old = freq;
+		}
+		if (freq >= min_freq && freq <= max_freq)
+			break;
+		(*n)++;
+		if ((*n) > MAX_N + 1) {
+			printf("ref %d m %d n %d target %d : ",
+				ref_freq_khz, *m, *n, target_freq_khz);
+			printf("can not find m & n - please consider"
+				" increasing tolerance\n");
+			return -1;
+		}
+	}
+	(*n)--;
+	printf("ref %d m %d n %d target %d locked %d\n",
+		ref_freq_khz, *m, *n, target_freq_khz, freq);
+	if ((ref_freq_khz / (*n + 1)) < 1000) {
+		printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than"
+			" ideal, locking time will be high!\n");
+	}
+	return 0;
+}
+
+void main(void)
+{
+	u32 m, n;
+	printf("\nMPU - 2000000\n");
+	get_m_n_optimized(2000000, 12000, &m, &n, 0);
+	get_m_n_optimized(2000000, 13000, &m, &n, 0);
+	get_m_n_optimized(2000000, 16800, &m, &n, 800);
+	get_m_n_optimized(2000000, 19200, &m, &n, 0);
+	get_m_n_optimized(2000000, 26000, &m, &n, 0);
+	get_m_n_optimized(2000000, 27000, &m, &n, 0);
+	get_m_n_optimized(2000000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1200000\n");
+	get_m_n_optimized(1200000, 12000, &m, &n, 0);
+	get_m_n_optimized(1200000, 13000, &m, &n, 0);
+	get_m_n_optimized(1200000, 16800, &m, &n, 800);
+	get_m_n_optimized(1200000, 19200, &m, &n, 0);
+	get_m_n_optimized(1200000, 26000, &m, &n, 0);
+	get_m_n_optimized(1200000, 27000, &m, &n, 0);
+	get_m_n_optimized(1200000, 38400, &m, &n, 0);
+
+	printf("\nMPU - 1584000\n");
+	get_m_n_optimized(1584000, 12000, &m, &n, 0);
+	get_m_n_optimized(1584000, 13000, &m, &n, 0);
+	get_m_n_optimized(1584000, 16800, &m, &n, 400);
+	get_m_n_optimized(1584000, 19200, &m, &n, 0);
+	get_m_n_optimized(1584000, 26000, &m, &n, 0);
+	get_m_n_optimized(1584000, 27000, &m, &n, 0);
+	get_m_n_optimized(1584000, 38400, &m, &n, 0);
+
+	printf("\nCore 1600000\n");
+	get_m_n_optimized(1600000, 12000, &m, &n, 0);
+	get_m_n_optimized(1600000, 13000, &m, &n, 0);
+	get_m_n_optimized(1600000, 16800, &m, &n, 200);
+	get_m_n_optimized(1600000, 19200, &m, &n, 0);
+	get_m_n_optimized(1600000, 26000, &m, &n, 0);
+	get_m_n_optimized(1600000, 27000, &m, &n, 0);
+	get_m_n_optimized(1600000, 38400, &m, &n, 0);
+
+	printf("\nPER 1536000\n");
+	get_m_n_optimized(1536000, 12000, &m, &n, 0);
+	get_m_n_optimized(1536000, 13000, &m, &n, 0);
+	get_m_n_optimized(1536000, 16800, &m, &n, 0);
+	get_m_n_optimized(1536000, 19200, &m, &n, 0);
+	get_m_n_optimized(1536000, 26000, &m, &n, 0);
+	get_m_n_optimized(1536000, 27000, &m, &n, 0);
+	get_m_n_optimized(1536000, 38400, &m, &n, 0);
+
+	printf("\nIVA 1862000\n");
+	get_m_n_optimized(1862000, 12000, &m, &n, 0);
+	get_m_n_optimized(1862000, 13000, &m, &n, 0);
+	get_m_n_optimized(1862000, 16800, &m, &n, 0);
+	get_m_n_optimized(1862000, 19200, &m, &n, 900);
+	get_m_n_optimized(1862000, 26000, &m, &n, 0);
+	get_m_n_optimized(1862000, 27000, &m, &n, 0);
+	get_m_n_optimized(1862000, 38400, &m, &n, 800);
+
+	printf("\nABE 196608 sys clk\n");
+	get_m_n_optimized(196608, 12000, &m, &n, 700);
+	get_m_n_optimized(196608, 13000, &m, &n, 200);
+	get_m_n_optimized(196608, 16800, &m, &n, 700);
+	get_m_n_optimized(196608, 19200, &m, &n, 400);
+	get_m_n_optimized(196608, 26000, &m, &n, 200);
+	get_m_n_optimized(196608, 27000, &m, &n, 900);
+	get_m_n_optimized(196608, 38400, &m, &n, 0);
+
+	printf("\nABE 196608 32K\n");
+	get_m_n_optimized(196608000/4, 32768, &m, &n, 0);
+
+	printf("\nUSB 1920000\n");
+	get_m_n_optimized(1920000, 12000, &m, &n, 0);
+	get_m_n_optimized(1920000, 13000, &m, &n, 0);
+	get_m_n_optimized(1920000, 16800, &m, &n, 0);
+	get_m_n_optimized(1920000, 19200, &m, &n, 0);
+	get_m_n_optimized(1920000, 26000, &m, &n, 0);
+	get_m_n_optimized(1920000, 27000, &m, &n, 0);
+	get_m_n_optimized(1920000, 38400, &m, &n, 0);
+
+	printf("\nCore ES1 1523712\n");
+	get_m_n_optimized(1524000, 12000, &m, &n, 100);
+	get_m_n_optimized(1524000, 13000, &m, &n, 0);
+	get_m_n_optimized(1524000, 16800, &m, &n, 0);
+	get_m_n_optimized(1524000, 19200, &m, &n, 0);
+	get_m_n_optimized(1524000, 26000, &m, &n, 0);
+	get_m_n_optimized(1524000, 27000, &m, &n, 0);
+
+	/* exact recommendation for SDPs */
+	get_m_n_optimized(1523712, 38400, &m, &n, 0);
+
+}
-- 
1.7.0.4

[U-Boot] [PATCH v4 05/12] omap4: add sdram init support

[Aneesh V]

Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Minor corrections in do_lpddr2_init()
* Minor corrections to read_idle interval calculation
* Sanity test of memory after doing the initialization
* Fixed warnings reported with with latest GCC compilers
V3:
* Removed references to modify_reg_32()
* Updated references to OMAP_INIT_CONTEXT_* flags
* Replaced calls to omap4_revision() with omap_revision()
* Replaced sanity test with get_ram_size()
---
 arch/arm/cpu/armv7/omap4/Makefile           |    2 +
 arch/arm/cpu/armv7/omap4/board.c            |    6 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  328 +++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  131 ++++
 arch/arm/include/asm/arch-omap4/clocks.h    |    8 +-
 arch/arm/include/asm/arch-omap4/emif.h      | 1025 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h     |    5 +
 arch/arm/include/asm/arch-omap4/sys_proto.h |    2 +
 8 files changed, 1500 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/emif.c
 create mode 100644 arch/arm/cpu/armv7/omap4/sdram_elpida.c
 create mode 100644 arch/arm/include/asm/arch-omap4/emif.h

diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index ac4b2a6..e1ccd68 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -29,7 +29,9 @@ SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clocks.o
+COBJS	+= emif.o
 COBJS	+= mem.o
+COBJS	+= sdram_elpida.o
 COBJS	+= sys_info.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 1c26a66..ca107f7 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -189,7 +189,7 @@ void watchdog_init(void)
  * This is needed because the size of memory installed may be
  * different on different versions of the board
  */
-u32 sdram_size(void)
+u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
@@ -215,8 +215,8 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
-	gd->ram_size = sdram_size();
+	sdram_init();
+	gd->ram_size = omap4_sdram_size();
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..b25c1ee
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,328 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+	sdelay(2000);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
+
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/*
+	 * Workaround:
+	 * In a specific situation, the OCP interface between the DMM and
+	 * EMIF may hang.
+	 * 1. A TILER port is used to perform 2D burst writes of
+	 *       width 1 and height 8
+	 * 2. ELLAn port is used to perform reads
+	 * 3. All accesses are routed to the same EMIF controller
+	 *
+	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
+	 * be kept higher than default 0x7. As per recommondation 0x0A will
+	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
+	 */
+	if (omap_revision() == OMAP4430_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
+		       &emif->emif_l3_config);
+	}
+}
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs;
+	u32 in_sdram, emif_nr;
+
+	debug(">>do_sdram_init() %x\n", base);
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+	emif_get_reg_dump(emif_nr, &regs);
+	if (!regs) {
+		debug("EMIF: reg dump not provided\n");
+		return;
+	}
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+
+	debug("<<do_sdram_init() %x\n", base);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	struct control_lpddr2io_regs *lpddr2io_regs =
+		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+	emif_get_dmm_regs(&lisa_map_regs);
+
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram, size_prog, size_detect;
+
+	debug(">>sdram_init()\n");
+
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	in_sdram = running_from_sdram();
+	debug("in_sdram = %d\n", in_sdram);
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(&prcm->cm_clkmode_dpll_core);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+
+	/* Do some testing after the init */
+	if (!in_sdram) {
+		size_prog = omap4_sdram_size();
+		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+						size_prog);
+		/* Compare with the size programmed */
+		if (size_detect != size_prog) {
+			printf("SDRAM: identified size not same as expected"
+				" size identified: %x expected: %x\n",
+				size_detect,
+				size_prog);
+		} else
+			debug("get_ram_size() successful");
+	}
+
+	debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..c950c87
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,131 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
+ * SDP and Panda. Since the parts used and geometry are identical for
+ * SDP and Panda for a given OMAP4 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP4 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_2cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 71db39c..37bdcee 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -33,10 +33,10 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		(OMAP44XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER		(OMAP44XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU		(OMAP44XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE			(OMAP44XX_L4_CORE_BASE + 0x4100)
+#define CM_CLKMODE_DPLL_CORE		0x4A004120
+#define CM_CLKMODE_DPLL_PER		0x4A008140
+#define CM_CLKMODE_DPLL_MPU		0x4A004160
+#define CM_CLKSEL_CORE			0x4A004100
 
 struct omap4_prcm_regs {
 	/* cm1.ckgen */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..09e9baa
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,1025 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+struct control_lpddr2io_regs {
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value for ES1*/
+#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen@lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index 76b06c2..c9c86e1 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define LPDDR2_IO_REGS_BASE	0x4A100638
+
+#define CONTROL_EFUSE_2		0x4A100704
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index f871921..7183a90 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,8 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
+u32 omap4_sdram_size(void);
 
 static inline u32 running_from_sdram(void)
 {
-- 
1.7.0.4

[U-Boot] [PATCH v4 06/12] omap4: calculate EMIF register values

[Aneesh V]

Calculate EMIF register values based on AC timing parameters
from the SDRAM datasheet and the DDR frequency rather than
using the hard-coded values.

For a new board the user doen't have to go through the tedious
process of calculating the register values. Instead, just
provide the AC timings from the device data sheet as input
and the driver will automatically calculate the register values.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Added SDRAM init related CONFIG flags for Panda too.
  Earlier Panda support for everything was added in a
  single patch at the end
* Replaced calls to omap4_revision() with omap_revision()
* Reorganization of code for better readability
* Some code re-organization to reduce #ifdef complexities -
  cleanly separated out functions for getting device details
  (geometry) vs timings
* Ensured un-necessary code is compiled out if
  CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REG is defined
---
 arch/arm/cpu/armv7/omap-common/Makefile     |    1 +
 arch/arm/cpu/armv7/omap-common/utils.c      |   57 ++
 arch/arm/cpu/armv7/omap4/board.c            |    9 +-
 arch/arm/cpu/armv7/omap4/emif.c             |  739 +++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap4/sdram_elpida.c     |  151 ++++++
 arch/arm/include/asm/arch-omap4/emif.h      |    9 +
 arch/arm/include/asm/arch-omap4/omap4.h     |   10 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h |    1 +
 include/configs/omap4_panda.h               |    5 +
 include/configs/omap4_sdp4430.h             |    5 +
 10 files changed, 977 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/utils.c

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..8f698f8 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..ea935da
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2011 Linaro Limited
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index ca107f7..786c239 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -193,13 +194,13 @@ u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index b25c1ee..ceead9e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -170,6 +170,628 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	config_reg |=  (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
+	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+			OMAP44XX_REG_IBANK_POS_SHIFT;
+
+	config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
+
+	config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
+
+	config_reg |= addressing->row_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_ROWSIZE_SHIFT;
+
+	config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
+
+	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+			OMAP44XX_REG_EBANK_SHIFT;
+
+	config_reg |= addressing->col_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_PAGESIZE_SHIFT;
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
+
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
+	tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
+
+	zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
+
+	zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
+
+	zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
+
+	zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
+
+	alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
+
+	idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+	/* Other fields are constant magic values. Hardcode them together */
+	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+		OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+	return phy;
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = &jedec_default_timings;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
@@ -180,11 +802,54 @@ static void do_sdram_init(u32 base)
 	in_sdram = running_from_sdram();
 	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_reg_dump(emif_nr, &regs);
 	if (!regs) {
 		debug("EMIF: reg dump not provided\n");
 		return;
 	}
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+	struct emif_device_details dev_details;
+	struct emif_regs calculated_regs;
+
+	/*
+	 * Get device details:
+	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+	 * - Obtained from user otherwise
+	 */
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	emif_get_device_details(emif_nr, &cs0_dev_details,
+				&cs1_dev_details);
+	dev_details.cs0_device_details = &cs0_dev_details;
+	dev_details.cs1_device_details = &cs1_dev_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+	/*
+	 * Get device timings:
+	 * - Default timings specified by JESD209-2 if
+	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+	 * - Obtained from user otherwise
+	 */
+	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+				&dev_details.cs1_device_timings);
+
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
 	 * Initializing the LPDDR2 device can not happen from SDRAM.
@@ -242,8 +907,82 @@ static void dmm_init(u32 base)
 {
 	const struct dmm_lisa_map_regs *lisa_map_regs;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) <<
+				OMAP44XX_SYS_ADDR_SHIFT;
+		section_map |= get_dmm_section_size_map(mapped_size * 2)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif1_size)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= (mapped_size >> 24) <<
+				OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif2_size) <<
+				OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
 
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
 	struct dmm_lisa_map_regs *hw_lisa_map_regs =
 	    (struct dmm_lisa_map_regs *)base;
 
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index c950c87..7757aad 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -46,6 +46,8 @@
  * - emif_get_device_timings()
  */
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
@@ -129,3 +131,152 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 omap_rev = omap_revision();
+
+	/* EMIF1 & EMIF2 have identical configuration */
+	*cs0_device_details = elpida_2G_S4_details;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		cs1_device_details = NULL;
+	else
+		*cs1_device_details = elpida_2G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	u32 omap_rev = omap_revision();
+
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*cs1_device_timings = NULL;
+	else
+		*cs1_device_timings = &elpida_2G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 09e9baa..a167508 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -1019,7 +1019,16 @@ struct emif_regs {
 #define emif_assert(c)	({ if (0) hang(); })
 #endif
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index c9c86e1..a8dbedb 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -84,12 +84,6 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
 /*
  * Hardware Register Details
  */
@@ -137,6 +131,10 @@ struct s32ktimer {
 #define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
 /* SRAM scratch space entries */
 #define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
 
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 7183a90..1e62878 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -49,6 +49,7 @@ void bypass_dpll(u32 *const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_sdram_size(void);
 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 1daffb7..9f82ef4 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -237,4 +237,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 68ffa87..6df1c3d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -243,4 +243,9 @@
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 07/12] omap4: automatic sdram detection

[Aneesh V]

Identify SDRAM devices connected to EMIF automatically:
LPDDR2 devices have some Mode Registers that provide details
about the device such as the type, density, bus width
etc. EMIF has the capability to read these registers. If there
are no devices connected to a given chip-select reading mode
registers will return junk values. After reading as many such
registers as possible and matching with expected ranges of
values the driver can identify if there is a device connected
to the respective CS. If we identify that a device is connected
the values read give us complete details about the device.

This along with the base AC timings specified by JESD209-2
allows us to do a complete automatic initialization of
SDRAM that works on all boards.

Please note that the default AC timings specified by JESD209-2
will be safe for all devices but not necessarily optimal. However,
for the Elpida devices used on Panda and SDP the default timings
are both safe and optimal.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Code re-organization for better readability
* Ensured that un-necessary code is compiled out when
  CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is not defined
---
 arch/arm/cpu/armv7/omap4/emif.c |  238 +++++++++++++++++++++++++++++++++++++++
 include/configs/omap4_panda.h   |    1 +
 include/configs/omap4_sdp4430.h |    1 +
 3 files changed, 240 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index ceead9e..1234a7e 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -792,6 +792,244 @@ void emif_get_device_timings(u32 emif_nr,
 }
 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
+
+	if (running_from_sdram()) {
+		/*
+		 * We can not do automatic discovery running from SDRAM
+		 * Most likely we came here by mistake. Indicate error
+		 * by returning NULL
+		 */
+		cs0_device_details = NULL;
+		cs1_device_details = NULL;
+	} else {
+		/*
+		 * Automatically find the device details:
+		 *
+		 * Reset the PHY after each call to get_lpddr2_details().
+		 * If there is nothing connected to a given chip select
+		 * (typically CS1) mode register reads will mess up with
+		 * the PHY state and subsequent initialization won't work.
+		 * PHY reset brings back PHY to a good state.
+		 */
+		cs0_device_details =
+		    get_lpddr2_details(base, CS0, cs0_device_details);
+		emif_reset_phy(base);
+
+		cs1_device_details =
+		    get_lpddr2_details(base, CS1, cs1_device_details);
+		emif_reset_phy(base);
+	}
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_sdram_init(u32 base)
 {
 	const struct emif_regs *regs;
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 9f82ef4..a8dd861 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -239,6 +239,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 6df1c3d..534f89a 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -245,6 +245,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH v4 08/12] armv7: start.S: fixes and enhancements for SPL

[Aneesh V]

- Allow SPL to have .bss disjoint from rest of the image
- Allow for .bss setup in CONFIG_SPL_BUILD case too.
- Take care of the special case where relocation offset = 0.
- Compile out exception handling code and install a simpler
  vector

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Taken care of the case where .bss is at a lower address
  comapred to  _start

V4:
* Rebased to the latest u-boot-ti/master
---
 arch/arm/cpu/armv7/start.S    |   49 +++++++++++++++++++++++++++++++----------
 arch/arm/cpu/armv7/u-boot.lds |    2 +
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5c87e9c..02a2535 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
 .global _end_vect
 _end_vect:
 
@@ -89,6 +100,10 @@ _armboot_start:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -182,12 +197,11 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_SPL_BUILD
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
@@ -235,20 +249,34 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 clear_bss:
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -276,12 +304,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
@@ -329,6 +351,8 @@ cpu_init_crit:
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
 #endif
+
+#ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
@@ -516,4 +540,5 @@ fiq:
 	bad_save_user_regs
 	bl	do_fiq
 
-#endif
+#endif /* CONFIG_USE_IRQ */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index dbae54d..40ecf78 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
-- 
1.7.0.4

[U-Boot] [PATCH v4 09/12] omap: add basic SPL support

[Aneesh V]

- Provide alternate implementations of board_init_f()
  board_init_r() for OMAP spl.
- Provide linker script
- Initialize global data
- Add serial console support
- Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move
  it to board config header from config.mk

Signed-off-by: Aneesh V <aneesh@ti.com>
---

This patch adds two checkpatch warnings that look like false
positives. Reported these to checkpatch maintainer.

V2:
* Removed the label __flash_image_end because _end serves the
  same purpose after rebasing to latest mainline

V3:
* Moved CONFIG_SYS_TEXT_BASE to board config header and
  deleted config.mk
* Changes for the struct based register accesses
* Removed usage of modify_reg_32() macro
* omap4_rev_string() reference changed to omap_rev_string()
* Folded the patches for linker script changes and console
  support into this patch
* Improved commit message

V4:
* Changed the CONFIG_SYS_SPL_* config flags to:
  CONFIG_SPL_*
* Changed the name omap4_rev_string used in spl.c as this
  file is common for OMAP3/4
---
 arch/arm/cpu/armv7/Makefile                   |    7 ++-
 arch/arm/cpu/armv7/omap-common/Makefile       |    4 +
 arch/arm/cpu/armv7/omap-common/spl.c          |   82 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds |   62 +++++++++++++++++++
 arch/arm/cpu/armv7/omap4/Makefile             |    5 +-
 arch/arm/cpu/armv7/omap4/board.c              |    7 ++
 arch/arm/cpu/armv7/omap4/clocks.c             |   33 ++++++++++
 arch/arm/include/asm/arch-omap4/sys_proto.h   |    1 +
 arch/arm/include/asm/omap_common.h            |    2 +
 board/ti/panda/Makefile                       |    2 +
 board/ti/panda/config.mk                      |   31 ---------
 board/ti/sdp4430/Makefile                     |    2 +
 board/ti/sdp4430/config.mk                    |   31 ---------
 include/configs/omap4_panda.h                 |   26 ++++++++
 include/configs/omap4_sdp4430.h               |   26 ++++++++
 15 files changed, 257 insertions(+), 64 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
 delete mode 100644 board/ti/panda/config.mk
 delete mode 100644 board/ti/sdp4430/config.mk

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 299792a..92a5a96 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	:= start.o
-COBJS	:= cpu.o cache_v7.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= cache_v7.o
+COBJS	+= cpu.o
+endif
+
 COBJS  += syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 8f698f8..0708796 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -30,6 +30,10 @@ SOBJS	:= reset.o
 COBJS	:= timer.o
 COBJS	+= utils.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS	+= spl.o
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
new file mode 100644
index 0000000..b201543
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * We call relocate_code() with relocation target same as the
+	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+	 * skipped. Instead, only .bss initialization will happen. That's
+	 * all we need
+	 */
+	debug(">>board_init_f()\n");
+	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}
+
+void preloader_console_init(void)
+{
+	const char *u_boot_rev = U_BOOT_VERSION;
+	char rev_string_buffer[50];
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	setup_clocks_for_console();
+	serial_init();		/* serial communications setup */
+
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+
+	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+		U_BOOT_TIME);
+	omap_rev_string(rev_string_buffer);
+	printf("Texas Instruments %s\n", rev_string_buffer);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
new file mode 100644
index 0000000..8867e06
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/armv7/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index e1ccd68..e7ee0b8 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -30,9 +30,12 @@ SOBJS	+= lowlevel_init.o
 COBJS	+= board.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
-COBJS	+= mem.o
 COBJS	+= sdram_elpida.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= mem.o
 COBJS	+= sys_info.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 786c239..54dd509 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -155,7 +155,14 @@ void s_init(void)
 	init_omap4_revision();
 	watchdog_init();
 	set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+#endif
 	prcm_init();
+#ifdef CONFIG_SPL_BUILD
+	/* For regular u-boot sdram_init() is called from dram_init() */
+	sdram_init();
+#endif
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index e8d3a52..f1e233a 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -791,6 +791,39 @@ void lock_dpll(u32 *const base)
 	wait_for_lock(base);
 }
 
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable all UARTs - console will be on one of them */
+	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
 void prcm_init(void)
 {
 	switch (omap4_hw_init_context()) {
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 1e62878..a81f8e5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,6 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void omap_rev_string(char *omap4_rev_string);
+void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);
 void freq_update_core(void);
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 33caa4e..69d53d2 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -34,4 +34,6 @@
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
+void preloader_console_init(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index 2186403..09f88ee 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/panda/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index f1ee544..12f2743 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+ifndef CONFIG_SPL_BUILD
 COBJS	:= sdp.o cmd_bat.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
deleted file mode 100644
index 33901a7..0000000
--- a/board/ti/sdp4430/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 4430 SDP
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# SDRAM Address Space:
-# 8000'0000 - 9fff'ffff (512 MB)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-CONFIG_SYS_TEXT_BASE = 0x80e80000
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index a8dd861..1112362 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -243,4 +243,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 534f89a..6a6be9e 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -249,4 +249,30 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 #endif
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40304350
+#define CONFIG_SPL_MAX_SIZE		0x8000	/* 32 K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
 #endif /* __CONFIG_H */
-- 
1.7.0.4

[U-Boot] [PATCH v4 10/12] Correct ih_os for u-boot.img

[Aneesh V]

Provide appropriate '-O u-boot' while doing mkimage
for u-boot.img

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 Makefile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 0707036..f8ae883 100644
--- a/Makefile
+++ b/Makefile
@@ -375,7 +375,7 @@ $(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
 
 $(obj)u-boot.img:	$(obj)u-boot.bin
 		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
-		-a $(CONFIG_SYS_TEXT_BASE) -e 0 \
+		-O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
 		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
-- 
1.7.0.4

[U-Boot] [PATCH v4 11/12] omap: add MMC and FAT support to SPL

[Aneesh V]

- Add MMC raw and FAT mode boot support for OMAP
- Provide a means by which parameters passed by ROM-code
  can be saved in u-boot.
- Save boot mode related information passed by OMAP4 ROM-code
  and use it to determine where to load the u-boot from
- Assumes that the image has a mkimage header. Gets the
  payload size and load address from this header. If the
  header is not detected assume u-boot.bin as payload

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
* Squashed the patches that provided MMC support, FAT support,
  start.S hook for saving parameters, and OMAP4 patch for saving
  the parameters all into this patch.
* Removed the assumption that payload is u-boot.bin. Payload
  size and address
---
 arch/arm/cpu/armv7/cpu.c                 |    7 +
 arch/arm/cpu/armv7/omap-common/spl.c     |  194 +++++++++++++++++++++++++++++-
 arch/arm/cpu/armv7/omap4/board.c         |   21 ++++
 arch/arm/cpu/armv7/omap4/lowlevel_init.S |   31 +++++
 arch/arm/cpu/armv7/start.S               |    1 +
 arch/arm/include/asm/arch-omap4/omap4.h  |    8 ++
 arch/arm/include/asm/omap_common.h       |   17 +++
 include/configs/omap4_panda.h            |    5 +
 include/configs/omap4_sdp4430.h          |    5 +
 9 files changed, 287 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index def9ced..091e3e0 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -37,6 +37,13 @@
 #include <asm/cache.h>
 #include <asm/armv7.h>
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index b201543..d177652 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -24,15 +24,27 @@
  */
 #include <common.h>
 #include <asm/u-boot.h>
+#include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
+#include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <image.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Define global data structure pointer to it*/
 static gd_t gdata __attribute__ ((section(".data")));
 static bd_t bdata __attribute__ ((section(".data")));
+static const char *image_name;
+static u8 image_os;
+static u32 image_load_addr;
+static u32 image_entry_point;
+static u32 image_size;
 
 inline void hang(void)
 {
@@ -53,10 +65,188 @@ void board_init_f(ulong dummy)
 	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0);
+		break;
+	case BOOT_DEVICE_MMC2:
+		omap_mmc_init(1);
+		break;
+	}
+	return 0;
+}
+#endif
+
+static void parse_image_header(const struct image_header *header)
+{
+	u32 header_size = sizeof(struct image_header);
+
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		image_size = __be32_to_cpu(header->ih_size) + header_size;
+		image_entry_point = __be32_to_cpu(header->ih_load);
+		/* Load including the header */
+		image_load_addr = image_entry_point - header_size;
+		image_os = header->ih_os;
+		image_name = (const char *)&header->ih_name;
+		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
+			image_name, image_load_addr, image_size);
+	} else {
+		/* Signature not found - assume u-boot.bin */
+		printf("mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		puts("Assuming u-boot.bin ..\n");
+		/* Let's assume U-Boot will not be more than 200 KB */
+		image_size = 200 * 1024;
+		image_entry_point = CONFIG_SYS_TEXT_BASE;
+		image_load_addr = CONFIG_SYS_TEXT_BASE;
+		image_os = IH_OS_U_BOOT;
+		image_name = "U-Boot";
+	}
+}
+
+static void mmc_load_image_raw(struct mmc *mmc)
+{
+	u32 image_size_sectors, err;
+	const struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	/* read image header to find the image size & load address */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)header);
+
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	/* convert size to sectors - round up */
+	image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) /
+				MMCSD_SECTOR_SIZE;
+
+	/* Read the header too to avoid extra memcpy */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+			image_size_sectors, (void *)image_load_addr);
+
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_image_fat(struct mmc *mmc)
+{
+	s32 err;
+	struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)image_load_addr, 0);
+
+end:
+	if (err <= 0) {
+		printf("spl: error reading image %s, err - %d\n",
+			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
+		hang();
+	}
+}
+
+static void mmc_load_image(void)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: err - %d\n", err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW) {
+		debug("boot mode - RAW\n");
+		mmc_load_image_raw(mmc);
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		debug("boot mode - FAT\n");
+		mmc_load_image_fat(mmc);
+	} else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) image_entry_point;
+
+	image_entry();
+}
+
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
 void board_init_r(gd_t *id, ulong dummy)
 {
-	for (;;)
-		;
+	u32 boot_device;
+	debug(">>spl:board_init_r()\n");
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	boot_device = omap_boot_device();
+	debug("boot device - %d\n", boot_device);
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_image();
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	switch (image_os) {
+	case IH_OS_U_BOOT:
+		debug("Jumping to U-Boot\n");
+		jump_to_image_no_args();
+		break;
+	default:
+		puts("Unsupported OS image.. Jumping nevertheless..\n");
+		jump_to_image_no_args();
+	}
 }
 
 void preloader_console_init(void)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 54dd509..2e5739a 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -39,6 +39,27 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 6abfbba..91525ec 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_SPL_BUILD
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 02a2535..db8e9d2 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -134,6 +134,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a8dbedb..563544f 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -144,4 +144,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_2	0x44300220
 #define OMAP4430_ES2_3	0x44300230
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 69d53d2..d3cb857 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -36,4 +36,21 @@
 
 void preloader_console_init(void);
 
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 1112362..f6f283a 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -252,6 +252,11 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 6a6be9e..346763d 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -258,6 +258,11 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-- 
1.7.0.4

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Aneesh V]

From: John Rigby <john.rigby@linaro.org>

- Add mkimage support for OMAP boot image
- Add support for OMAP boot image(MLO) generation in the new
  SPL framework

Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Aneesh V <aneesh@ti.com>
---
V3:
 * Fixed minor issue with casting away 'const'ness of
   pointers
 * Ensure lists are sorted alphabetically
 * Added an error message
 * Removed 'packed' attribute from structs
 * Fixed some other minor comments on V2
 * Adapted for the new SPL framework
V4:
 * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
---
 arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
 common/image.c                     |    9 +-
 include/image.h                    |    1 +
 spl/Makefile                       |    6 +
 tools/Makefile                     |    2 +
 tools/mkimage.c                    |    2 +
 tools/mkimage.h                    |    1 +
 tools/omapimage.c                  |  224 ++++++++++++++++++++++++++++++++++++
 tools/omapimage.h                  |   50 ++++++++
 9 files changed, 321 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap4/config.mk
 create mode 100644 tools/omapimage.c
 create mode 100644 tools/omapimage.h

diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk
new file mode 100644
index 0000000..b34fa64
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/common/image.c b/common/image.c
index 5c7d4f4..5f71c99 100644
--- a/common/image.c
+++ b/common/image.c
@@ -130,17 +130,18 @@ static const table_entry_t uimage_os[] = {
 };
 
 static const table_entry_t uimage_type[] = {
-	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
 	{	IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image",	},
 	{	IH_TYPE_FIRMWARE,   "firmware",	  "Firmware",		},
+	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
+	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	IH_TYPE_KERNEL,	    "kernel",	  "Kernel Image",	},
+	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
 	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
 	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
 	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
-	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
-	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
-	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index c31e862..c606644 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types
diff --git a/spl/Makefile b/spl/Makefile
index 638aab7..2a1fd11 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -85,6 +85,12 @@ LDPPFLAGS += \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
+ifdef CONFIG_OMAP
+$(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
+	$(OBJTREE)/tools/mkimage -T omapimage \
+		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
 ALL-y	+= $(obj)u-boot-spl.bin
 
 all:	$(ALL-y)
diff --git a/tools/Makefile b/tools/Makefile
index 97f83f8..cb7f92d 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -88,6 +88,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
 OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o
 NOPED_OBJ_FILES-y += kwbimage.o
 NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += omapimage.o
 NOPED_OBJ_FILES-y += mkimage.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 NOPED_OBJ_FILES-y += os_support.o
@@ -188,6 +189,7 @@ $(obj)mkimage$(SFX):	$(obj)crc32.o \
 			$(obj)md5.o \
 			$(obj)mkimage.o \
 			$(obj)os_support.o \
+			$(obj)omapimage.o \
 			$(obj)sha1.o \
 			$(LIBFDT_OBJS)
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 60f7263..b6a7cb7 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -156,6 +156,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 9033a7d..3b49645 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */
diff --git a/tools/omapimage.c b/tools/omapimage.c
new file mode 100644
index 0000000..29d91cc
--- /dev/null
+++ b/tools/omapimage.c
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Required to obtain the getline prototype from stdio.h */
+#define _GNU_SOURCE
+
+#include "mkimage.h"
+#include <image.h>
+#include "omapimage.h"
+
+/* Header size is CH header rounded up to 512 bytes plus GP header */
+#define OMAP_CH_HDR_SIZE 512
+#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
+#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
+
+static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
+
+static int omapimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_OMAPIMAGE)
+		return EXIT_SUCCESS;
+	else {
+		fprintf(stderr, "Unknown OMAP image type - %x", type);
+		return EXIT_FAILURE;
+	}
+}
+
+/*
+ * Only the simplest image type is currently supported:
+ * TOC pointing to CHSETTINGS
+ * TOC terminator
+ * CHSETTINGS
+ *
+ * padding to OMAP_CH_HDR_SIZE bytes
+ *
+ * gp header
+ *   size
+ *   load_addr
+ */
+static int valid_gph_size(uint32_t size)
+{
+	return size;
+}
+
+static int valid_gph_load_addr(uint32_t load_addr)
+{
+	return load_addr;
+}
+
+static int omapimage_verify_header(unsigned char *ptr, int image_size,
+			struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+		if (!offset || !size)
+			return -1;
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			return -1;
+		toc++;
+	}
+	if (!valid_gph_size(gph->size))
+		return -1;
+	if (!valid_gph_load_addr(gph->load_addr))
+		return -1;
+
+	return 0;
+}
+
+static void omapimage_print_section(struct ch_settings *chs)
+{
+	const char *section_name;
+
+	if (chs->section_key)
+		section_name = "CHSETTINGS";
+	else
+		section_name = "UNKNOWNKEY";
+
+	printf("%s (%x) "
+		"valid:%x "
+		"version:%x "
+		"reserved:%x "
+		"flags:%x\n",
+		section_name,
+		chs->section_key,
+		chs->valid,
+		chs->version,
+		chs->reserved,
+		chs->flags);
+}
+
+static void omapimage_print_header(const void *ptr)
+{
+	const struct ch_toc *toc = (struct ch_toc *)ptr;
+	const struct gp_header *gph =
+			(struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
+	uint32_t offset, size;
+
+	while (toc->section_offset != 0xffffffff
+			&& toc->section_size != 0xffffffff) {
+		offset = toc->section_offset;
+		size = toc->section_size;
+
+		if (offset >= OMAP_CH_HDR_SIZE ||
+		    offset+size >= OMAP_CH_HDR_SIZE)
+			exit(EXIT_FAILURE);
+
+		printf("Section %s offset %x length %x\n",
+			toc->section_name,
+			toc->section_offset,
+			toc->section_size);
+
+		omapimage_print_section((struct ch_settings *)(ptr+offset));
+		toc++;
+	}
+
+	if (!valid_gph_size(gph->size)) {
+		fprintf(stderr,
+			"Error: invalid image size %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	if (!valid_gph_load_addr(gph->load_addr)) {
+		fprintf(stderr,
+			"Error: invalid image load address %x\n",
+			gph->size);
+		exit(EXIT_FAILURE);
+	}
+
+	printf("GP Header: Size %x LoadAddr %x\n",
+		gph->size, gph->load_addr);
+}
+
+static int toc_offset(void *hdr, void *member)
+{
+	return member - hdr;
+}
+
+static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+				struct mkimage_params *params)
+{
+	struct ch_toc *toc = (struct ch_toc *)ptr;
+	struct ch_settings *chs = (struct ch_settings *)
+					(ptr + 2 * sizeof(*toc));
+	struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE);
+
+	toc->section_offset = toc_offset(ptr, chs);
+	toc->section_size = sizeof(struct ch_settings);
+	strcpy((char *)toc->section_name, "CHSETTINGS");
+
+	chs->section_key = KEY_CHSETTINGS;
+	chs->valid = 0;
+	chs->version = 1;
+	chs->reserved = 0;
+	chs->flags = 0;
+
+	toc++;
+	memset(toc, 0xff, sizeof(*toc));
+
+	gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
+	gph->load_addr = params->addr;
+}
+
+int omapimage_check_params(struct mkimage_params *params)
+{
+	return	(params->dflag && (params->fflag || params->lflag)) ||
+		(params->fflag && (params->dflag || params->lflag)) ||
+		(params->lflag && (params->dflag || params->fflag));
+}
+
+/*
+ * omapimage parameters
+ */
+static struct image_type_params omapimage_params = {
+	.name		= "TI OMAP CH/GP Boot Image support",
+	.header_size	= OMAP_FILE_HDR_SIZE,
+	.hdr		= (void *)&omapimage_header,
+	.check_image_type = omapimage_check_image_types,
+	.verify_header	= omapimage_verify_header,
+	.print_header	= omapimage_print_header,
+	.set_header	= omapimage_set_header,
+	.check_params	= omapimage_check_params,
+};
+
+void init_omap_image_type(void)
+{
+	mkimage_register(&omapimage_params);
+}
diff --git a/tools/omapimage.h b/tools/omapimage.h
new file mode 100644
index 0000000..719db00
--- /dev/null
+++ b/tools/omapimage.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author John Rigby <john.rigby@linaro.org>
+ * Based on TI's signGP.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAPIMAGE_H_
+#define _OMAPIMAGE_H_
+
+struct ch_toc {
+	uint32_t section_offset;
+	uint32_t section_size;
+	uint8_t unused[12];
+	uint8_t section_name[12];
+};
+
+struct ch_settings {
+	uint32_t section_key;
+	uint8_t valid;
+	uint8_t version;
+	uint16_t reserved;
+	uint32_t flags;
+};
+
+struct gp_header {
+	uint32_t size;
+	uint32_t load_addr;
+};
+
+#define KEY_CHSETTINGS 0xC0C0C0C1
+#endif /* _OMAPIMAGE_H_ */
-- 
1.7.0.4

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[Paulraj, Sandeep]

> 
> This series adds mmc SPL support for OMAP4. This is essentially
> an up-streaming effort for TI's x-loader for OMAP4 using the SPL
> framework
> 
> This work partly draws upon previous work done for x-loader by:
> 	Santosh Shilimkar <santosh.shilimkar@ti.com>
> 	Rajendra Nayak <rnayak@ti.com>
> and many others
> 
> This series depends on the following series for the new SPL framework:
> http://marc.info/?l=u-boot&m=131056990001719&w=2
> 
> Features supported:
> * Clock init - DPLL locking, clock domains/modules enabling
> * SDRAM/DMM initialization
> * Mux initialization
> * MMC raw read support
> * MMC FAT read support
> 
> Improvments over x-loader:
> * Code completely revamped
> * DPLL programming that works for all SYS_CLK frequencies
> * Automatic SDRAM identification and initialization
> * Board dependent parts(especially mux) deferred to u-boot. So, same
>   SPL will work for Panda and SDP and most likely on any other board
>   that comes along
> * Flexible about the payload. Any image with a mkimage header can be
>   loaded.
> * The core SPL logic is generic and available for OMAP3/4. So, OMAP3
>   platforms can easily extend this work to add SPL support for the
>   respective boards.
> 
> V2:
> * Some fixes in SDRAM init, clock init
> * Use of pre-calculated M & N values for DPLL locking instead
>   run-time calculation
> * Change in make files to allow reuse of common rules
>   between boards
> * Console initialization moved further earlier in the boot
>   allowing traces from even clock initialization code
> * Reuse utility macros from a previous series
> 
> V3:
> * Moved to the new SPL framework
> * struct based register access for clock init
> * Squashed together related patches as per Wolfgang's suggestions
> * Re-organization of code in sdram init for better readability
> * SPL loading the payload using mkimage header
> * Avoided using custom bit-field accessor macros
> * Several other minor changes(documented in respective patches)
> 
> V4:
> * Rebased on u-boot-ti/master as on 21 Jul 2011
> 
> Aneesh V (11):
>   omap4: utility function to identify the context of hw init
>   omap4: cleanup pin mux data
>   omap4: add OMAP4430 revision check
>   omap4: add clock support
>   omap4: add sdram init support
>   omap4: calculate EMIF register values
>   omap4: automatic sdram detection
>   armv7: start.S: fixes and enhancements for SPL
>   omap: add basic SPL support
>   Correct ih_os for u-boot.img
>   omap: add MMC and FAT support to SPL
> 
> John Rigby (1):
>   mkimage: Add OMAP boot image support
> 


Pushed the series to u-boot-ti

http://git.denx.de/?p=u-boot/u-boot-ti.git;a=summary


Thanks,
Sandeep

[U-Boot] [PATCH v4 00/12] U-Boot MMC SPL for OMAP4

[Paulraj, Sandeep]

> 
> There was v4 for just two of the patches of the framework series: 2/9 and
> 5/9.
> 
> I think you missed them. Can you correct this?

Corrected and applied the patches to u-boot-ti

Thanks,
Sandeep

[U-Boot] [PATCH v4 10/12] Correct ih_os for u-boot.img

[Wolfgang Denk]

Dear Aneesh V,

In message <1311004011-9073-11-git-send-email-aneesh@ti.com> you wrote:
> Provide appropriate '-O u-boot' while doing mkimage
> for u-boot.img
> 
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  Makefile |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
What about WRITING it first and rationalizing it afterwords?  :-)
                       - Larry Wall in <8162@jpl-devvax.JPL.NASA.GOV>

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Wolfgang Denk]

Dear Sandeep,

please pull this directly with the rest of the OMAP SPL patches.

In message <1311004011-9073-13-git-send-email-aneesh@ti.com> you wrote:
> From: John Rigby <john.rigby@linaro.org>
> 
> - Add mkimage support for OMAP boot image
> - Add support for OMAP boot image(MLO) generation in the new
>   SPL framework
> 
> Signed-off-by: John Rigby <john.rigby@linaro.org>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
> V3:
>  * Fixed minor issue with casting away 'const'ness of
>    pointers
>  * Ensure lists are sorted alphabetically
>  * Added an error message
>  * Removed 'packed' attribute from structs
>  * Fixed some other minor comments on V2
>  * Adapted for the new SPL framework
> V4:
>  * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
> ---
>  arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
>  common/image.c                     |    9 +-
>  include/image.h                    |    1 +
>  spl/Makefile                       |    6 +
>  tools/Makefile                     |    2 +
>  tools/mkimage.c                    |    2 +
>  tools/mkimage.h                    |    1 +
>  tools/omapimage.c                  |  224 ++++++++++++++++++++++++++++++++++++
>  tools/omapimage.h                  |   50 ++++++++
>  9 files changed, 321 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/omap4/config.mk
>  create mode 100644 tools/omapimage.c
>  create mode 100644 tools/omapimage.h

Acked-by: Wolfgang Denk <wd@denx.de>

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Never call a man a fool.  Borrow from him.

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Wolfgang Denk]

Dear Aneesh V,

In message <1311233298-17265-3-git-send-email-aneesh@ti.com> you wrote:
> - separate mux settings into essential and non essential parts
> - essential part is board independent as of now(so move it
>   to SoC directory). Will help in having single SPL for all
>   boards.
> - Non-essential part(the pins not essential for u-boot to function)
>   need to be phased out eventually.
> - Correct mux data by aligning to the latest settings in x-loader
...
> +	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
> +	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
> +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
> +	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
> +	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
> +	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
> +	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
> +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */

Lines too long, please fix globally.



Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Quote from the Boss after overriding the decision of a task force  he
created  to  find  a  solution:  "I'm  sorry  if  I ever gave you the
impression your input would have any effect on my  decision  for  the
outcome of this project!"

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Aneesh V]

Dear Wolfgang,

On Friday 29 July 2011 12:56 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1311233298-17265-3-git-send-email-aneesh@ti.com>  you wrote:
>> - separate mux settings into essential and non essential parts
>> - essential part is board independent as of now(so move it
>>    to SoC directory). Will help in having single SPL for all
>>    boards.
>> - Non-essential part(the pins not essential for u-boot to function)
>>    need to be phased out eventually.
>> - Correct mux data by aligning to the latest settings in x-loader
> ...
>> +	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
>> +	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
>> +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
>> +	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
>> +	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
>> +	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
>> +	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
>> +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
>
> Lines too long, please fix globally.

This table looks better and readable if each row is a single line. I
had mentioned this in the commit log. Does it make sense to make an
exception for this?

best regards,
Aneesh

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Wolfgang Denk]

Dear Aneesh V,

In message <4E32722C.6020707@ti.com> you wrote:
> Dear Wolfgang,
> 
> On Friday 29 July 2011 12:56 AM, Wolfgang Denk wrote:
> > Dear Aneesh V,
> >
> > In message<1311233298-17265-3-git-send-email-aneesh@ti.com>  you wrote:
> >> - separate mux settings into essential and non essential parts
> >> - essential part is board independent as of now(so move it
> >>    to SoC directory). Will help in having single SPL for all
> >>    boards.
> >> - Non-essential part(the pins not essential for u-boot to function)
> >>    need to be phased out eventually.
> >> - Correct mux data by aligning to the latest settings in x-loader
> > ...
> >> +	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
> >> +	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
> >> +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
> >> +	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
> >> +	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
> >> +	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
> >> +	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
> >> +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
> >
> > Lines too long, please fix globally.
> 
> This table looks better and readable if each row is a single line. I
> had mentioned this in the commit log. Does it make sense to make an
> exception for this?

I agree that it does not make sense to split the lines.

But it seems there is potential to reduce the line length: in may
cases, you can just reduce the indentation of the comments.

In many other places the commets are just useless and should be
omitted.  See for example the (old, existing) lines:

        {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},            /* cam_shutter */
        {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},             /* cam_strobe */
...
        {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat4 */
        {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat5 */
        {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat6 */
...
etc.

A comment that just repeats the content of the first argument without
any additional information carries zero information and should just
be removed.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you use modules, you pay the price. Sane embedded solutions
running in "tight" environments don't use modules :-)
    -- Benjamin Herrenschmidt in <1258234866.2140.451.camel@pasglop>

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Aneesh V]

Dear Wolfgang,

On Friday 29 July 2011 02:26 PM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<4E32722C.6020707@ti.com>  you wrote:
>> Dear Wolfgang,
>>
>> On Friday 29 July 2011 12:56 AM, Wolfgang Denk wrote:
>>> Dear Aneesh V,
>>>
>>> In message<1311233298-17265-3-git-send-email-aneesh@ti.com>   you wrote:
>>>> - separate mux settings into essential and non essential parts
>>>> - essential part is board independent as of now(so move it
>>>>     to SoC directory). Will help in having single SPL for all
>>>>     boards.
>>>> - Non-essential part(the pins not essential for u-boot to function)
>>>>     need to be phased out eventually.
>>>> - Correct mux data by aligning to the latest settings in x-loader
>>> ...
>>>> +	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
>>>> +	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
>>>> +	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
>>>> +	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
>>>> +	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
>>>> +	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
>>>> +	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
>>>> +	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
>>>
>>> Lines too long, please fix globally.
>>
>> This table looks better and readable if each row is a single line. I
>> had mentioned this in the commit log. Does it make sense to make an
>> exception for this?
>
> I agree that it does not make sense to split the lines.
>
> But it seems there is potential to reduce the line length: in may
> cases, you can just reduce the indentation of the comments.

Yes, for some lines there is potential to reduce the length. But I just
aligned the comments vertically for the entire table since more than
half of the rows were anyway overflowing.

>
> In many other places the commets are just useless and should be
> omitted.  See for example the (old, existing) lines:
>
>          {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},            /* cam_shutter */
>          {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},             /* cam_strobe */

The two are actually not same. The first column indicates the register
name. The documented name specifies the function selected which depends
on the last column, the mode(M0, M4 etc). The name of the register
happens to be the function selected by M0. So, in those cases, what you
said is correct. But IMHO, it's better to document the function
selected even in those cases, because when somebody changes the mode
here or for a new board, he/she is not likely to update the comment if
it is already absent.

> ...
>          {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat4 */
>          {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat5 */
>          {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat6 */
> ...
> etc.

For the above please note that first column and comments are indeed
different. Please note the difference between ULPI'TLL'_DATA4 and
ulpi'phy'_data4.

My patch is already in u-boot-arm. If I have to rework this patch
should I create a new patch to fix the problem or should I re-work the
original patch?

best regards,
Aneesh

[U-Boot] [PATCH v4 02/12] omap4: cleanup pin mux data

[Wolfgang Denk]

Dear Aneesh V,

In message <4E328E73.9080500@ti.com> you wrote:
> 
> My patch is already in u-boot-arm. If I have to rework this patch
> should I create a new patch to fix the problem or should I re-work the
> original patch?

It's not worth fighting about this. Please feel free to leave as is.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There is nothing new under the sun, but there are lots of old things
we don't know yet."                                  - Ambrose Bierce

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Reinhard Meyer]

Dear Albert,
> Dear Sandeep,
> 
> please pull this directly with the rest of the OMAP SPL patches.
> 
> In message <1311004011-9073-13-git-send-email-aneesh@ti.com> you wrote:
> > From: John Rigby <john.rigby@linaro.org>
> > 
> > - Add mkimage support for OMAP boot image
> > - Add support for OMAP boot image(MLO) generation in the new
> >   SPL framework
> > 
> > Signed-off-by: John Rigby <john.rigby@linaro.org>
> > Signed-off-by: Aneesh V <aneesh@ti.com>
> > ---
> > V3:
> >  * Fixed minor issue with casting away 'const'ness of
> >    pointers
> >  * Ensure lists are sorted alphabetically
> >  * Added an error message
> >  * Removed 'packed' attribute from structs
> >  * Fixed some other minor comments on V2
> >  * Adapted for the new SPL framework
> > V4:
> >  * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
> > ---
> >  arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
> >  common/image.c                     |    9 +-
> >  include/image.h                    |    1 +

For some reason the change to include/image.h has NOT made it into
u-boot-arm/master, therefore all builds are currently broken!

common/image.c:141:4: error: ?IH_TYPE_OMAPIMAGE? undeclared here (not in
a function)

Best Regards,
Reinhard

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Albert ARIBAUD]

Hi Reinhard,

Le 02/08/2011 11:08, Reinhard Meyer a ?crit :
> Dear Albert,
>> Dear Sandeep,
>>
>> please pull this directly with the rest of the OMAP SPL patches.
>>
>> In message<1311004011-9073-13-git-send-email-aneesh@ti.com>  you wrote:
>>> From: John Rigby<john.rigby@linaro.org>
>>>
>>> - Add mkimage support for OMAP boot image
>>> - Add support for OMAP boot image(MLO) generation in the new
>>>    SPL framework
>>>
>>> Signed-off-by: John Rigby<john.rigby@linaro.org>
>>> Signed-off-by: Aneesh V<aneesh@ti.com>
>>> ---
>>> V3:
>>>   * Fixed minor issue with casting away 'const'ness of
>>>     pointers
>>>   * Ensure lists are sorted alphabetically
>>>   * Added an error message
>>>   * Removed 'packed' attribute from structs
>>>   * Fixed some other minor comments on V2
>>>   * Adapted for the new SPL framework
>>> V4:
>>>   * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
>>> ---
>>>   arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
>>>   common/image.c                     |    9 +-
>>>   include/image.h                    |    1 +
>
> For some reason the change to include/image.h has NOT made it into
> u-boot-arm/master, therefore all builds are currently broken!
>
> common/image.c:141:4: error: ?IH_TYPE_OMAPIMAGE? undeclared here (not in
> a function)

My fault -- slipped a cam when rebasing. Please re-fetch master (and 
next and utf8 for anyone who wants them too).

Two notes BTW:

1. due to the merge conflict between UBL and OMAP image additions, I 
have re-numbered TH_TYPE_OMAPIMAGE value from 11 to 12.

2. after UBL addition, the table_entry_t uimage_type table in 
common/image.c is no longer sorted by image name. I did not fix this as 
this could require changes beyond what the merge conflict resolution 
required.

> Best Regards,
> Reinhard

Apologies for the merge issue.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH v4 12/12] mkimage: Add OMAP boot image support

[Reinhard Meyer]

Dear Albert,
> Le 02/08/2011 11:08, Reinhard Meyer a ?crit :
> > Dear Albert,
> >> Dear Sandeep,
> >>
> >> please pull this directly with the rest of the OMAP SPL patches.
> >>
> >> In message<1311004011-9073-13-git-send-email-aneesh@ti.com>  you wrote:
> >>> From: John Rigby<john.rigby@linaro.org>
> >>>
> >>> - Add mkimage support for OMAP boot image
> >>> - Add support for OMAP boot image(MLO) generation in the new
> >>>    SPL framework
> >>>
> >>> Signed-off-by: John Rigby<john.rigby@linaro.org>
> >>> Signed-off-by: Aneesh V<aneesh@ti.com>
> >>> ---
> >>> V3:
> >>>   * Fixed minor issue with casting away 'const'ness of
> >>>     pointers
> >>>   * Ensure lists are sorted alphabetically
> >>>   * Added an error message
> >>>   * Removed 'packed' attribute from structs
> >>>   * Fixed some other minor comments on V2
> >>>   * Adapted for the new SPL framework
> >>> V4:
> >>>   * Replaced CONFIG_SYS_SPL_TEXT_BASE with CONFIG_SPL_TEXT_BASE
> >>> ---
> >>>   arch/arm/cpu/armv7/omap4/config.mk |   30 +++++
> >>>   common/image.c                     |    9 +-
> >>>   include/image.h                    |    1 +
> >
> > For some reason the change to include/image.h has NOT made it into
> > u-boot-arm/master, therefore all builds are currently broken!
> >
> > common/image.c:141:4: error: ?IH_TYPE_OMAPIMAGE? undeclared here (not in
> > a function)
> 
> My fault -- slipped a cam when rebasing. Please re-fetch master (and 
> next and utf8 for anyone who wants them too).
> 
> Two notes BTW:
> 
> 1. due to the merge conflict between UBL and OMAP image additions, I 
> have re-numbered TH_TYPE_OMAPIMAGE value from 11 to 12.
> 
> 2. after UBL addition, the table_entry_t uimage_type table in 
> common/image.c is no longer sorted by image name. I did not fix this as 
> this could require changes beyond what the merge conflict resolution 
> required.
> 
> > Best Regards,
> > Reinhard
> 
> Apologies for the merge issue.
> 
> Amicalement,

I had locally fixed that define myself, but then got build warnings for
some undefined function in the same image-making business (can't recheck
that right now, a lengthy MAKEALL is in progress).

For the time being I rather stay based on u-boot/master until such
issues are fixed. Anyway a merge of my AT91 stuff with your ARM stuff
should not generate any merge conflicts, except maybe boards.cfg.

Best Regards,
Reinhard