From: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>, Matthias Kaehlcke <matthias-RprLehDfhQ3k1uMJSBkQmQ@public.gmane.org>, Kurt Van Dijck <kurt.van.dijck-/BeEPy95v10@public.gmane.org>, Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>, Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>, Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>, Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>, Richard Purdie <rpurdie-Fm38FmjxZ/leoWH0uzbU5w@public.gmane.org>, Mark Brown <broonie-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>, Mitch Bradley <wmb-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org>, Mike Frysinger <vapier-aBrp7R+bbdUdnm+yROfE0A@public.gmane.org>, Eric Miao <eric.y.miao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>, Ryan Mallon <rmallon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Bernhard Walle <walle-pDveNdigDaDu9UdzE1sIFA@public.gmane.org> Subject: [PATCH v6 08/17] pwm: Add NVIDIA Tegra SoC support Date: Tue, 10 Apr 2012 17:06:31 +0200 [thread overview] Message-ID: <1334070400-25013-9-git-send-email-thierry.reding@avionic-design.de> (raw) In-Reply-To: <1334070400-25013-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> This commit adds a generic PWM framework driver for the PWFM controller found on NVIDIA Tegra SoCs. The driver is based on code from the Chromium kernel tree and was originally written by Gary King (NVIDIA) and later modified by Simon Que (Chromium). Signed-off-by: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> --- Changes in v6: - return EADDRNOTAVAIL if devm_request_and_ioremap() fails - make tegra_pwm_ops constant Changes in v5: - use devm_request_and_ioremap() - use clk_prepare_enable() and clk_disable_unprepare() - call pwmchip_remove() after disabling PWM devices - remove tegra_pwm_chip.enable[] field and use the PWM flags instead - use pwm_readl()/pwm_writel() for register accesses and split out clock management to where it's needed - add MODULE_ALIAS to enable automatic module loading Changes in v4: - merge patch from ChromiumOS kernel to fix a rounding issue - move DT code to patch 7 Changes in v3: - use pwm_device.hwpwm instead of recomputing it - update pwm_ops for changes in patch 2 Changes in v2: - set pwm_chip.dev field - rename clk_enb to enable - introduce NUM_PWM macro instead of hard-coding the number of PWM devices - update comment in tegra_pwm_config - fix coding-style for multi-line comments - use module_platform_driver - change license to GPL drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-tegra.c | 254 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 265 insertions(+) create mode 100644 drivers/pwm/pwm-tegra.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 93c1052..bda6f23 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,4 +9,14 @@ menuconfig PWM if PWM +config PWM_TEGRA + tristate "NVIDIA Tegra PWM support" + depends on ARCH_TEGRA + help + Generic PWM framework driver for the PWFM controller found on NVIDIA + Tegra SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-tegra. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 3469c3d..12300f5 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_PWM) += core.o +obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c new file mode 100644 index 0000000..0950142 --- /dev/null +++ b/drivers/pwm/pwm-tegra.c @@ -0,0 +1,254 @@ +/* + * drivers/pwm/pwm-tegra.c + * + * Tegra pulse-width-modulation controller driver + * + * Copyright (c) 2010, NVIDIA Corporation. + * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pwm.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#define PWM_ENABLE (1 << 31) +#define PWM_DUTY_WIDTH 8 +#define PWM_DUTY_SHIFT 16 +#define PWM_SCALE_WIDTH 13 +#define PWM_SCALE_SHIFT 0 + +#define NUM_PWM 4 + +struct tegra_pwm_chip { + struct pwm_chip chip; + struct device *dev; + + struct clk *clk; + + void __iomem *mmio_base; +}; + +static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct tegra_pwm_chip, chip); +} + +static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num) +{ + return readl(chip->mmio_base + (num << 4)); +} + +static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num, + unsigned long val) +{ + writel(val, chip->mmio_base + (num << 4)); +} + +static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + unsigned long long c; + unsigned long rate, hz; + u32 val = 0; + int err; + + /* + * Convert from duty_ns / period_ns to a fixed number of duty ticks + * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * nearest integer during division. + */ + c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2; + do_div(c, period_ns); + + val = (u32)c << PWM_DUTY_SHIFT; + + /* + * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * cycles at the PWM clock rate will take period_ns nanoseconds. + */ + rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; + hz = 1000000000ul / period_ns; + + rate = (rate + (hz / 2)) / hz; + + /* + * Since the actual PWM divider is the register's frequency divider + * field minus 1, we need to decrement to get the correct value to + * write to the register. + */ + if (rate > 0) + rate--; + + /* + * Make sure that the rate will fit in the register's frequency + * divider field. + */ + if (rate >> PWM_SCALE_WIDTH) + return -EINVAL; + + val |= rate << PWM_SCALE_SHIFT; + + /* + * If the PWM channel is disabled, make sure to turn on the clock + * before writing the register. Otherwise, keep it enabled. + */ + if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + err = clk_prepare_enable(pc->clk); + if (err < 0) + return err; + } else + val |= PWM_ENABLE; + + pwm_writel(pc, pwm->hwpwm, val); + + /* + * If the PWM is not enabled, turn the clock off again to save power. + */ + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + clk_disable_unprepare(pc->clk); + + return 0; +} + +static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + int rc = 0; + u32 val; + + rc = clk_prepare_enable(pc->clk); + if (rc < 0) + return rc; + + val = pwm_readl(pc, pwm->hwpwm); + val |= PWM_ENABLE; + pwm_writel(pc, pwm->hwpwm, val); + + return 0; +} + +static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + u32 val; + + val = pwm_readl(pc, pwm->hwpwm); + val &= ~PWM_ENABLE; + pwm_writel(pc, pwm->hwpwm, val); + + clk_disable_unprepare(pc->clk); +} + +static const struct pwm_ops tegra_pwm_ops = { + .config = tegra_pwm_config, + .enable = tegra_pwm_enable, + .disable = tegra_pwm_disable, + .owner = THIS_MODULE, +}; + +static int tegra_pwm_probe(struct platform_device *pdev) +{ + struct tegra_pwm_chip *pwm; + struct resource *r; + int ret; + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + pwm->dev = &pdev->dev; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no memory resources defined\n"); + return -ENODEV; + } + + pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r); + if (!pwm->mmio_base) { + dev_err(&pdev->dev, "failed to ioremap() region\n"); + return -EADDRNOTAVAIL; + } + + platform_set_drvdata(pdev, pwm); + + pwm->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) + return PTR_ERR(pwm->clk); + + pwm->chip.dev = &pdev->dev; + pwm->chip.ops = &tegra_pwm_ops; + pwm->chip.base = -1; + pwm->chip.npwm = NUM_PWM; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); + clk_put(pwm->clk); + return ret; + } + + return 0; +} + +static int __devexit tegra_pwm_remove(struct platform_device *pdev) +{ + struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); + int i; + + if (WARN_ON(!pc)) + return -ENODEV; + + for (i = 0; i < NUM_PWM; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (clk_prepare_enable(pc->clk) < 0) + continue; + + pwm_writel(pc, i, 0); + + clk_disable_unprepare(pc->clk); + } + + pwmchip_remove(&pc->chip); + clk_put(pc->clk); + + return 0; +} + +static struct platform_driver tegra_pwm_driver = { + .driver = { + .name = "tegra-pwm", + }, + .probe = tegra_pwm_probe, + .remove = __devexit_p(tegra_pwm_remove), +}; + +module_platform_driver(tegra_pwm_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NVIDIA Corporation"); +MODULE_ALIAS("platform:tegra-pwm"); -- 1.7.9.6
WARNING: multiple messages have this Message-ID (diff)
From: thierry.reding@avionic-design.de (Thierry Reding) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 08/17] pwm: Add NVIDIA Tegra SoC support Date: Tue, 10 Apr 2012 17:06:31 +0200 [thread overview] Message-ID: <1334070400-25013-9-git-send-email-thierry.reding@avionic-design.de> (raw) In-Reply-To: <1334070400-25013-1-git-send-email-thierry.reding@avionic-design.de> This commit adds a generic PWM framework driver for the PWFM controller found on NVIDIA Tegra SoCs. The driver is based on code from the Chromium kernel tree and was originally written by Gary King (NVIDIA) and later modified by Simon Que (Chromium). Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> --- Changes in v6: - return EADDRNOTAVAIL if devm_request_and_ioremap() fails - make tegra_pwm_ops constant Changes in v5: - use devm_request_and_ioremap() - use clk_prepare_enable() and clk_disable_unprepare() - call pwmchip_remove() after disabling PWM devices - remove tegra_pwm_chip.enable[] field and use the PWM flags instead - use pwm_readl()/pwm_writel() for register accesses and split out clock management to where it's needed - add MODULE_ALIAS to enable automatic module loading Changes in v4: - merge patch from ChromiumOS kernel to fix a rounding issue - move DT code to patch 7 Changes in v3: - use pwm_device.hwpwm instead of recomputing it - update pwm_ops for changes in patch 2 Changes in v2: - set pwm_chip.dev field - rename clk_enb to enable - introduce NUM_PWM macro instead of hard-coding the number of PWM devices - update comment in tegra_pwm_config - fix coding-style for multi-line comments - use module_platform_driver - change license to GPL drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-tegra.c | 254 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 265 insertions(+) create mode 100644 drivers/pwm/pwm-tegra.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 93c1052..bda6f23 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,4 +9,14 @@ menuconfig PWM if PWM +config PWM_TEGRA + tristate "NVIDIA Tegra PWM support" + depends on ARCH_TEGRA + help + Generic PWM framework driver for the PWFM controller found on NVIDIA + Tegra SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-tegra. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 3469c3d..12300f5 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_PWM) += core.o +obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c new file mode 100644 index 0000000..0950142 --- /dev/null +++ b/drivers/pwm/pwm-tegra.c @@ -0,0 +1,254 @@ +/* + * drivers/pwm/pwm-tegra.c + * + * Tegra pulse-width-modulation controller driver + * + * Copyright (c) 2010, NVIDIA Corporation. + * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pwm.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#define PWM_ENABLE (1 << 31) +#define PWM_DUTY_WIDTH 8 +#define PWM_DUTY_SHIFT 16 +#define PWM_SCALE_WIDTH 13 +#define PWM_SCALE_SHIFT 0 + +#define NUM_PWM 4 + +struct tegra_pwm_chip { + struct pwm_chip chip; + struct device *dev; + + struct clk *clk; + + void __iomem *mmio_base; +}; + +static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct tegra_pwm_chip, chip); +} + +static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num) +{ + return readl(chip->mmio_base + (num << 4)); +} + +static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num, + unsigned long val) +{ + writel(val, chip->mmio_base + (num << 4)); +} + +static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + unsigned long long c; + unsigned long rate, hz; + u32 val = 0; + int err; + + /* + * Convert from duty_ns / period_ns to a fixed number of duty ticks + * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * nearest integer during division. + */ + c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2; + do_div(c, period_ns); + + val = (u32)c << PWM_DUTY_SHIFT; + + /* + * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * cycles@the PWM clock rate will take period_ns nanoseconds. + */ + rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; + hz = 1000000000ul / period_ns; + + rate = (rate + (hz / 2)) / hz; + + /* + * Since the actual PWM divider is the register's frequency divider + * field minus 1, we need to decrement to get the correct value to + * write to the register. + */ + if (rate > 0) + rate--; + + /* + * Make sure that the rate will fit in the register's frequency + * divider field. + */ + if (rate >> PWM_SCALE_WIDTH) + return -EINVAL; + + val |= rate << PWM_SCALE_SHIFT; + + /* + * If the PWM channel is disabled, make sure to turn on the clock + * before writing the register. Otherwise, keep it enabled. + */ + if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + err = clk_prepare_enable(pc->clk); + if (err < 0) + return err; + } else + val |= PWM_ENABLE; + + pwm_writel(pc, pwm->hwpwm, val); + + /* + * If the PWM is not enabled, turn the clock off again to save power. + */ + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + clk_disable_unprepare(pc->clk); + + return 0; +} + +static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + int rc = 0; + u32 val; + + rc = clk_prepare_enable(pc->clk); + if (rc < 0) + return rc; + + val = pwm_readl(pc, pwm->hwpwm); + val |= PWM_ENABLE; + pwm_writel(pc, pwm->hwpwm, val); + + return 0; +} + +static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); + u32 val; + + val = pwm_readl(pc, pwm->hwpwm); + val &= ~PWM_ENABLE; + pwm_writel(pc, pwm->hwpwm, val); + + clk_disable_unprepare(pc->clk); +} + +static const struct pwm_ops tegra_pwm_ops = { + .config = tegra_pwm_config, + .enable = tegra_pwm_enable, + .disable = tegra_pwm_disable, + .owner = THIS_MODULE, +}; + +static int tegra_pwm_probe(struct platform_device *pdev) +{ + struct tegra_pwm_chip *pwm; + struct resource *r; + int ret; + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + pwm->dev = &pdev->dev; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no memory resources defined\n"); + return -ENODEV; + } + + pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r); + if (!pwm->mmio_base) { + dev_err(&pdev->dev, "failed to ioremap() region\n"); + return -EADDRNOTAVAIL; + } + + platform_set_drvdata(pdev, pwm); + + pwm->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) + return PTR_ERR(pwm->clk); + + pwm->chip.dev = &pdev->dev; + pwm->chip.ops = &tegra_pwm_ops; + pwm->chip.base = -1; + pwm->chip.npwm = NUM_PWM; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); + clk_put(pwm->clk); + return ret; + } + + return 0; +} + +static int __devexit tegra_pwm_remove(struct platform_device *pdev) +{ + struct tegra_pwm_chip *pc = platform_get_drvdata(pdev); + int i; + + if (WARN_ON(!pc)) + return -ENODEV; + + for (i = 0; i < NUM_PWM; i++) { + struct pwm_device *pwm = &pc->chip.pwms[i]; + + if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (clk_prepare_enable(pc->clk) < 0) + continue; + + pwm_writel(pc, i, 0); + + clk_disable_unprepare(pc->clk); + } + + pwmchip_remove(&pc->chip); + clk_put(pc->clk); + + return 0; +} + +static struct platform_driver tegra_pwm_driver = { + .driver = { + .name = "tegra-pwm", + }, + .probe = tegra_pwm_probe, + .remove = __devexit_p(tegra_pwm_remove), +}; + +module_platform_driver(tegra_pwm_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NVIDIA Corporation"); +MODULE_ALIAS("platform:tegra-pwm"); -- 1.7.9.6
next prev parent reply other threads:[~2012-04-10 15:06 UTC|newest] Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top 2012-04-10 15:06 [PATCH v6 00/17] Add PWM framework and device tree support Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-1-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-10 15:06 ` [PATCH v6 01/17] pwm: Add PWM framework support Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 02/17] pwm: Allow chips to support multiple PWMs Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 03/17] pwm: Add debugfs interface Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-4-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-11 12:33 ` Shawn Guo 2012-04-11 12:33 ` Shawn Guo [not found] ` <20120411123352.GA2445-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org> 2012-04-11 12:38 ` Thierry Reding 2012-04-11 12:38 ` Thierry Reding 2012-04-11 15:11 ` Mark Brown 2012-04-11 15:11 ` Mark Brown 2012-04-10 15:06 ` [PATCH v6 04/17] pwm: Add table-based lookup for static mappings Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-5-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-11 12:38 ` Shawn Guo 2012-04-11 12:38 ` Shawn Guo [not found] ` <20120411123815.GB2445-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org> 2012-04-11 12:51 ` Thierry Reding 2012-04-11 12:51 ` Thierry Reding 2012-04-13 9:47 ` Mark Brown 2012-04-13 9:47 ` Mark Brown 2012-04-10 15:06 ` [PATCH v6 05/17] pwm: Add device tree support Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-6-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-11 13:02 ` Shawn Guo 2012-04-11 13:02 ` Shawn Guo [not found] ` <20120411130208.GC2445-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org> 2012-04-11 13:14 ` Thierry Reding 2012-04-11 13:14 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 06/17] ARM: tegra: Fix PWM clock programming Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 07/17] ARM: tegra: Provide clock for only one PWM controller Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` Thierry Reding [this message] 2012-04-10 15:06 ` [PATCH v6 08/17] pwm: Add NVIDIA Tegra SoC support Thierry Reding 2012-04-10 15:06 ` [PATCH v6 09/17] pwm: tegra: Add device tree support Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 10/17] pwm: Move Blackfin PWM driver to PWM framework Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 11/17] pwm: Move PXA " Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 12/17] ARM i.MX: Move i.MX pwm driver to pwm framework Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 13/17] ARM Samsung: Move s3c " Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 14/17] ARM vt8500: Move vt8500 " Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 15/17] pwm: add pwm-mxs support Thierry Reding 2012-04-10 15:06 ` Thierry Reding 2012-04-10 15:06 ` [PATCH v6 16/17] pwm-backlight: Add rudimentary device tree support Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-17-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-11 13:28 ` Shawn Guo 2012-04-11 13:28 ` Shawn Guo 2012-04-13 9:48 ` Mark Brown 2012-04-13 9:48 ` Mark Brown 2012-04-10 15:06 ` [PATCH v6 17/17] pwm: Take over maintainership of the PWM subsystem Thierry Reding 2012-04-10 15:06 ` Thierry Reding [not found] ` <1334070400-25013-18-git-send-email-thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> 2012-04-10 19:51 ` Arnd Bergmann 2012-04-10 19:51 ` Arnd Bergmann [not found] ` <201204101951.44198.arnd-r2nGTMty4D4@public.gmane.org> 2012-04-12 7:22 ` Thierry Reding 2012-04-12 7:22 ` Thierry Reding [not found] ` <20120412072206.GB18252-RM9K5IK7kjIQXX3q8xo1gnVAuStQJXxyR5q1nwbD4aMs9pC9oP6+/A@public.gmane.org> 2012-04-12 11:34 ` Arnd Bergmann 2012-04-12 11:34 ` Arnd Bergmann [not found] ` <201204121134.24892.arnd-r2nGTMty4D4@public.gmane.org> 2012-04-12 12:27 ` Thierry Reding 2012-04-12 12:27 ` Thierry Reding [not found] ` <20120412122740.GB5353-RM9K5IK7kjIyiCvfTdI0JKcOhU4Rzj621B7CTYaBSLdn68oJJulU0Q@public.gmane.org> 2012-04-16 5:50 ` Thierry Reding 2012-04-16 5:50 ` Thierry Reding [not found] ` <20120416055012.GA3037-RM9K5IK7kjIyiCvfTdI0JKcOhU4Rzj621B7CTYaBSLdn68oJJulU0Q@public.gmane.org> 2012-04-16 15:02 ` Arnd Bergmann 2012-04-16 15:02 ` Arnd Bergmann 2012-04-10 20:58 ` Sascha Hauer 2012-04-10 20:58 ` Sascha Hauer 2012-06-14 12:47 ` [PATCH v6 00/17] Add PWM framework and device tree support Hebbar, Gururaja 2012-06-14 12:47 ` Hebbar, Gururaja [not found] ` <1BAFE6F6C881BF42822005164F1491C33EA21A9F-Er742YJ7I/eIQmiDNMet8wC/G2K4zDHf@public.gmane.org> 2012-06-14 12:53 ` Thierry Reding 2012-06-14 12:53 ` Thierry Reding 2012-06-14 13:36 ` Hebbar, Gururaja 2012-06-14 13:36 ` Hebbar, Gururaja 2012-04-29 15:40 ` Eric Bénard 2012-04-29 15:40 ` Eric Bénard
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