From: Tero Kristo <t-kristo@ti.com> To: linux-omap@vger.kernel.org, paul@pwsan.com, khilman@linaro.org, tony@atomide.com, mturquette@linaro.org, nm@ti.com, rnayak@ti.com Cc: linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s Date: Tue, 23 Jul 2013 10:20:21 +0300 [thread overview] Message-ID: <1374564028-11352-27-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1374564028-11352-1-git-send-email-t-kristo@ti.com> OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset value after their respective PWRDN bits are set. Any dummy write (Any other value different from the Read value) to the corresponding CM_CLKSEL register will refresh the dividers. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- drivers/clk/omap/gate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c index b560ff4..50c7f2e 100644 --- a/drivers/clk/omap/gate.c +++ b/drivers/clk/omap/gate.c @@ -28,6 +28,10 @@ #ifdef CONFIG_OF +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk); + static const struct clk_ops omap_gate_clkdm_clk_ops = { .init = &omap2_init_clk_clkdm, .enable = &omap2_clkops_enable_clkdm, @@ -41,6 +45,54 @@ static const struct clk_ops omap_gate_clk_ops = { .is_enabled = &omap2_dflt_clk_is_enabled, }; +static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +/** + * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering + * from HSDivider PWRDN problem Implements Errata ID: i556. + * @clk: DPLL output struct clk + * + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, + * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset + * valueafter their respective PWRDN bits are set. Any dummy write + * (Any other value different from the Read value) to the + * corresponding CM_CLKSEL register will refresh the dividers. + */ +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_divider *parent; + struct clk_hw *parent_hw; + u32 dummy_v, orig_v; + int ret; + + /* Clear PWRDN bit of HSDIVIDER */ + ret = omap2_dflt_clk_enable(clk); + + /* Parent is the x2 node, get parent of parent for the m2 div */ + parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk))); + parent = to_clk_divider(parent_hw); + + /* Restore the dividers */ + if (!ret) { + orig_v = __raw_readl(parent->reg); + dummy_v = orig_v; + + /* Write any other value different from the Read value */ + dummy_v ^= (1 << parent->shift); + __raw_writel(dummy_v, parent->reg); + + /* Write the original divider */ + __raw_writel(orig_v, parent->reg); + } + + return ret; +} + void __init of_omap_gate_clk_setup(struct device_node *node) { struct clk *clk; @@ -70,7 +122,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node) /* No register, clkdm control only */ init.ops = &omap_gate_clkdm_clk_ops; } else { - init.ops = &omap_gate_clk_ops; + if (of_property_read_bool(node, "ti,hsdiv-restore")) + init.ops = &omap_gate_clk_hsdiv_restore_ops; + else + init.ops = &omap_gate_clk_ops; clk_hw->enable_reg = of_iomap(node, 0); of_property_read_u32(node, "ti,enable-bit", &val); clk_hw->enable_bit = val; -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: t-kristo@ti.com (Tero Kristo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s Date: Tue, 23 Jul 2013 10:20:21 +0300 [thread overview] Message-ID: <1374564028-11352-27-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1374564028-11352-1-git-send-email-t-kristo@ti.com> OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset value after their respective PWRDN bits are set. Any dummy write (Any other value different from the Read value) to the corresponding CM_CLKSEL register will refresh the dividers. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- drivers/clk/omap/gate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/clk/omap/gate.c b/drivers/clk/omap/gate.c index b560ff4..50c7f2e 100644 --- a/drivers/clk/omap/gate.c +++ b/drivers/clk/omap/gate.c @@ -28,6 +28,10 @@ #ifdef CONFIG_OF +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk); + static const struct clk_ops omap_gate_clkdm_clk_ops = { .init = &omap2_init_clk_clkdm, .enable = &omap2_clkops_enable_clkdm, @@ -41,6 +45,54 @@ static const struct clk_ops omap_gate_clk_ops = { .is_enabled = &omap2_dflt_clk_is_enabled, }; +static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +/** + * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering + * from HSDivider PWRDN problem Implements Errata ID: i556. + * @clk: DPLL output struct clk + * + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, + * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset + * valueafter their respective PWRDN bits are set. Any dummy write + * (Any other value different from the Read value) to the + * corresponding CM_CLKSEL register will refresh the dividers. + */ +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_divider *parent; + struct clk_hw *parent_hw; + u32 dummy_v, orig_v; + int ret; + + /* Clear PWRDN bit of HSDIVIDER */ + ret = omap2_dflt_clk_enable(clk); + + /* Parent is the x2 node, get parent of parent for the m2 div */ + parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk))); + parent = to_clk_divider(parent_hw); + + /* Restore the dividers */ + if (!ret) { + orig_v = __raw_readl(parent->reg); + dummy_v = orig_v; + + /* Write any other value different from the Read value */ + dummy_v ^= (1 << parent->shift); + __raw_writel(dummy_v, parent->reg); + + /* Write the original divider */ + __raw_writel(orig_v, parent->reg); + } + + return ret; +} + void __init of_omap_gate_clk_setup(struct device_node *node) { struct clk *clk; @@ -70,7 +122,10 @@ void __init of_omap_gate_clk_setup(struct device_node *node) /* No register, clkdm control only */ init.ops = &omap_gate_clkdm_clk_ops; } else { - init.ops = &omap_gate_clk_ops; + if (of_property_read_bool(node, "ti,hsdiv-restore")) + init.ops = &omap_gate_clk_hsdiv_restore_ops; + else + init.ops = &omap_gate_clk_ops; clk_hw->enable_reg = of_iomap(node, 0); of_property_read_u32(node, "ti,enable-bit", &val); clk_hw->enable_bit = val; -- 1.7.9.5
next prev parent reply other threads:[~2013-07-23 7:20 UTC|newest] Thread overview: 204+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-07-23 7:19 [PATCHv4 00/33] ARM: OMAP: clock conversion to DT Tero Kristo 2013-07-23 7:19 ` Tero Kristo 2013-07-23 7:19 ` [PATCHv4 01/33] CLK: clkdev: add support for looking up clocks from DT Tero Kristo 2013-07-23 7:19 ` Tero Kristo 2013-07-30 15:04 ` Nishanth Menon 2013-07-30 15:04 ` Nishanth Menon 2013-07-31 8:43 ` Tero Kristo 2013-07-31 8:43 ` Tero Kristo 2013-07-23 7:19 ` [PATCHv4 02/33] clk: omap: introduce clock driver Tero Kristo 2013-07-23 7:19 ` Tero Kristo 2013-07-30 15:21 ` Nishanth Menon 2013-07-30 15:21 ` Nishanth Menon 2013-07-31 8:59 ` Tero Kristo 2013-07-31 8:59 ` Tero Kristo 2013-08-01 13:44 ` Nishanth Menon 2013-08-01 13:44 ` Nishanth Menon 2013-08-01 14:59 ` Tero Kristo 2013-08-01 14:59 ` Tero Kristo 2013-07-23 7:19 ` [PATCHv4 03/33] CLK: OMAP4: Add DPLL clock support Tero Kristo 2013-07-23 7:19 ` Tero Kristo 2013-07-30 16:23 ` Nishanth Menon 2013-07-30 16:23 ` Nishanth Menon 2013-07-31 9:46 ` Tero Kristo 2013-07-31 9:46 ` Tero Kristo 2013-08-01 14:00 ` Nishanth Menon 2013-08-01 14:00 ` Nishanth Menon 2013-08-01 15:08 ` Tero Kristo 2013-08-01 15:08 ` Tero Kristo 2013-08-01 15:13 ` Nishanth Menon 2013-08-01 15:13 ` Nishanth Menon 2013-08-01 8:29 ` Rajendra Nayak 2013-08-01 8:29 ` Rajendra Nayak 2013-08-01 15:10 ` Nishanth Menon 2013-08-01 15:10 ` Nishanth Menon 2013-08-01 15:41 ` Tero Kristo 2013-08-01 15:41 ` Tero Kristo 2013-07-23 7:19 ` [PATCHv4 04/33] CLK: omap: move part of the machine specific clock header contents to driver Tero Kristo 2013-07-23 7:19 ` Tero Kristo 2013-07-30 18:22 ` Nishanth Menon 2013-07-30 18:22 ` Nishanth Menon 2013-07-31 9:59 ` Tero Kristo 2013-07-31 9:59 ` Tero Kristo 2013-08-01 14:04 ` Nishanth Menon 2013-08-01 14:04 ` Nishanth Menon 2013-08-01 15:12 ` Tero Kristo 2013-08-01 15:12 ` Tero Kristo 2013-08-01 15:21 ` Nishanth Menon 2013-08-01 15:21 ` Nishanth Menon 2013-07-23 7:20 ` [PATCHv4 05/33] CLK: omap: add DT duplicate clock registration mechanism Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 18:40 ` Nishanth Menon 2013-07-30 18:40 ` Nishanth Menon 2013-07-31 10:07 ` Tero Kristo 2013-07-31 10:07 ` Tero Kristo 2013-08-01 14:25 ` Nishanth Menon 2013-08-01 14:25 ` Nishanth Menon 2013-08-01 15:18 ` Tero Kristo 2013-08-01 15:18 ` Tero Kristo 2013-08-01 15:24 ` Nishanth Menon 2013-08-01 15:24 ` Nishanth Menon 2013-08-01 15:30 ` Tero Kristo 2013-08-01 15:30 ` Tero Kristo 2013-08-02 7:22 ` Tony Lindgren 2013-08-02 7:22 ` Tony Lindgren 2013-07-23 7:20 ` [PATCHv4 06/33] CLK: omap: add autoidle support Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 18:56 ` Nishanth Menon 2013-07-30 18:56 ` Nishanth Menon 2013-07-31 10:13 ` Tero Kristo 2013-07-31 10:13 ` Tero Kristo 2013-08-01 14:11 ` Nishanth Menon 2013-08-01 14:11 ` Nishanth Menon 2013-08-01 15:22 ` Tero Kristo 2013-08-01 15:22 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 07/33] CLK: omap: add support for OMAP gate clock Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:17 ` Nishanth Menon 2013-07-30 19:17 ` Nishanth Menon 2013-07-31 14:45 ` Tero Kristo 2013-07-31 14:45 ` Tero Kristo 2013-08-01 14:33 ` Nishanth Menon 2013-08-01 14:33 ` Nishanth Menon 2013-08-01 15:29 ` Tero Kristo 2013-08-01 15:29 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 08/33] ARM: dts: omap4 clock data Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:27 ` Nishanth Menon 2013-07-30 19:27 ` Nishanth Menon 2013-07-31 14:49 ` Tero Kristo 2013-07-31 14:49 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 09/33] CLK: omap: add omap4 clock init file Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:33 ` Nishanth Menon 2013-07-30 19:33 ` Nishanth Menon 2013-07-31 14:52 ` Tero Kristo 2013-07-31 14:52 ` Tero Kristo 2013-08-01 14:40 ` Nishanth Menon 2013-08-01 14:40 ` Nishanth Menon 2013-08-01 15:34 ` Tero Kristo 2013-08-01 15:34 ` Tero Kristo 2013-08-01 16:10 ` Nishanth Menon 2013-08-01 16:10 ` Nishanth Menon 2013-07-23 7:20 ` [PATCHv4 10/33] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:42 ` Nishanth Menon 2013-07-30 19:42 ` Nishanth Menon 2013-07-31 14:55 ` Tero Kristo 2013-07-31 14:55 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 11/33] ARM: dts: omap5 clock data Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 12/33] CLK: omap: add omap5 clock init file Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 13/33] ARM: dts: dra7 clock data Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 14/33] CLK: omap: add dra7 clock init file Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate Tero Kristo 2013-07-23 7:20 ` [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti, dpll-no-gate Tero Kristo 2013-07-30 19:18 ` [PATCHv4 15/33] CLK: OMAP: DPLL: add support for DT property ti,dpll-no-gate Nishanth Menon 2013-07-30 19:18 ` Nishanth Menon 2013-07-31 14:56 ` Tero Kristo 2013-07-31 14:56 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 16/33] CLK: OMAP: DPLL: do not of_iomap NULL autoidle register Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:49 ` Nishanth Menon 2013-07-30 19:49 ` Nishanth Menon 2013-07-31 14:57 ` Tero Kristo 2013-07-31 14:57 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 17/33] CLK: DT: add support for set-rate-parent flag Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 19:58 ` Nishanth Menon 2013-07-30 19:58 ` Nishanth Menon 2013-07-23 7:20 ` [PATCHv4 18/33] ARM: dts: am33xx clock data Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 19/33] CLK: omap: add am33xx clock init file Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 20:00 ` Nishanth Menon 2013-07-30 20:00 ` Nishanth Menon 2013-07-31 14:59 ` Tero Kristo 2013-07-31 14:59 ` Tero Kristo 2013-08-01 14:43 ` Nishanth Menon 2013-08-01 14:43 ` Nishanth Menon 2013-08-01 15:35 ` Tero Kristo 2013-08-01 15:35 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 20/33] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 21/33] CLK: OMAP: DPLL: add omap3 dpll support Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 20:08 ` Nishanth Menon 2013-07-30 20:08 ` Nishanth Menon 2013-07-31 15:03 ` Tero Kristo 2013-07-31 15:03 ` Tero Kristo 2013-08-01 14:46 ` Nishanth Menon 2013-08-01 14:46 ` Nishanth Menon 2013-07-23 7:20 ` [PATCHv4 22/33] CLK: OMAP: update gate clock setup for OMAP3 Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 20:13 ` Nishanth Menon 2013-07-30 20:13 ` Nishanth Menon 2013-07-31 15:05 ` Tero Kristo 2013-07-31 15:05 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 23/33] CLK: OMAP: add interface clock support " Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-30 20:23 ` Nishanth Menon 2013-07-30 20:23 ` Nishanth Menon 2013-07-31 15:09 ` Tero Kristo 2013-07-31 15:09 ` Tero Kristo 2013-08-01 14:50 ` Nishanth Menon 2013-08-01 14:50 ` Nishanth Menon 2013-07-23 7:20 ` [PATCHv4 24/33] CLK: OMAP: move some defines from machine to driver header Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 25/33] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` Tero Kristo [this message] 2013-07-23 7:20 ` [PATCHv4 26/33] CLK: omap: gate: add support for OMAP36xx dpllx_mx_ck:s Tero Kristo 2013-07-23 7:20 ` [PATCHv4 27/33] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 28/33] ARM: dts: omap3 clock data Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 30/33] clk: OMAP: DRA7: Add APLL support Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 31/33] ARM: dts: clk: Add apll related clocks Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 32/33] clk: OMAP: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 7:20 ` [PATCHv4 33/33] clk: DTS: DRA7: Add PCIe related clock nodes Tero Kristo 2013-07-23 7:20 ` Tero Kristo 2013-07-23 8:24 ` [PATCHv4 00/33] ARM: OMAP: clock conversion to DT Tero Kristo 2013-07-23 8:24 ` Tero Kristo 2013-07-24 14:16 ` Roger Quadros 2013-07-24 14:16 ` Roger Quadros 2013-07-24 14:29 ` Tero Kristo 2013-07-24 14:29 ` Tero Kristo 2013-07-24 14:34 ` Roger Quadros 2013-07-24 14:34 ` Roger Quadros 2013-07-24 14:43 ` Tero Kristo 2013-07-24 14:43 ` Tero Kristo [not found] ` <1374564028-11352-30-git-send-email-t-kristo@ti.com> 2013-07-30 20:19 ` [PATCHv4 29/33] CLK: omap: add omap3 clock init file Nishanth Menon 2013-07-30 20:19 ` Nishanth Menon 2013-07-31 6:35 ` Tony Lindgren 2013-07-31 6:35 ` Tony Lindgren 2013-07-31 15:10 ` Tero Kristo 2013-07-31 15:10 ` Tero Kristo 2013-08-02 7:24 ` Tony Lindgren 2013-08-02 7:24 ` Tony Lindgren
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