From: Tero Kristo <t-kristo@ti.com> To: linux-omap@vger.kernel.org, paul@pwsan.com, tony@atomide.com, nm@ti.com, rnayak@ti.com, bcousson@baylibre.com, mturquette@linaro.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, J Keerthy <j-keerthy@ti.com> Subject: [PATCHv10 15/41] CLK: TI: DRA7: Add APLL support Date: Tue, 26 Nov 2013 10:05:56 +0200 [thread overview] Message-ID: <1385453182-24421-16-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1385453182-24421-1-git-send-email-t-kristo@ti.com> From: J Keerthy <j-keerthy@ti.com> The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> --- .../devicetree/bindings/clock/ti/apll.txt | 31 +++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/apll.c | 239 ++++++++++++++++++++ 3 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt create mode 100644 drivers/clk/ti/apll.c diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt new file mode 100644 index 0000000..7faf5a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt @@ -0,0 +1,31 @@ +Binding for Texas Instruments APLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped APLL with usually two selectable input clocks +(reference clock and bypass clock), with analog phase locked +loop logic for multiplying the input clock to a desired output +clock. This clock also typically supports different operation +modes (locked, low power stop etc.) APLL mostly behaves like +a subtype of a DPLL [2], although a simplified one at that. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt + +Required properties: +- compatible : shall be "ti,dra7-apll-clock" +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks (clk-ref and clk-bypass) +- reg : address and length of the register set for controlling the APLL. + It contains the information of registers in the following order: + "control" - contains the control register base address + "idlest" - contains the idlest register base address + +Examples: + apll_pcie_ck: apll_pcie_ck@4a008200 { + #clock-cells = <0>; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; + compatible = "ti,dra7-apll-clock"; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 935e5d2..3d71e1e 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o dpll.o autoidle.o divider.o \ fixed-factor.o gate.o clockdomain.o \ - composite.o mux.o + composite.o mux.o apll.o obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o endif diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c new file mode 100644 index 0000000..5402b45 --- /dev/null +++ b/drivers/clk/ti/apll.c @@ -0,0 +1,239 @@ +/* + * OMAP APLL clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * J Keerthy <j-keerthy@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/log2.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/clk/ti.h> +#include <linux/delay.h> + +#define APLL_FORCE_LOCK 0x1 +#define APLL_AUTO_IDLE 0x2 +#define MAX_APLL_WAIT_TRIES 1000000 + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static int dra7_apll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int r = 0, i = 0; + struct dpll_data *ad; + const char *clk_name; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + if (!ad) + return -EINVAL; + + clk_name = __clk_get_name(clk->hw.clk); + + state <<= __ffs(ad->idlest_mask); + + /* Check is already locked */ + v = clk_readl(ad->idlest_reg); + + if ((v & ad->idlest_mask) == state) + return r; + + v = clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); + clk_writel(v, ad->control_reg); + + state <<= __ffs(ad->idlest_mask); + + while (1) { + v = clk_readl(ad->idlest_reg); + if ((v & ad->idlest_mask) == state) + break; + if (i > MAX_APLL_WAIT_TRIES) + break; + i++; + udelay(1); + } + + if (i == MAX_APLL_WAIT_TRIES) { + pr_warn("clock: %s failed transition to '%s'\n", + clk_name, (state) ? "locked" : "bypassed"); + } else { + pr_debug("clock: %s transition to '%s' in %d loops\n", + clk_name, (state) ? "locked" : "bypassed", i); + + r = 0; + } + + return r; +} + +static void dra7_apll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + + state <<= __ffs(ad->idlest_mask); + + v = clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); + clk_writel(v, ad->control_reg); +} + +static int dra7_apll_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u32 v; + + ad = clk->dpll_data; + + v = clk_readl(ad->control_reg); + v &= ad->enable_mask; + + v >>= __ffs(ad->enable_mask); + + return v == APLL_AUTO_IDLE ? 0 : 1; +} + +static u8 dra7_init_apll_parent(struct clk_hw *hw) +{ + return 0; +} + +static const struct clk_ops apll_ck_ops = { + .enable = &dra7_apll_enable, + .disable = &dra7_apll_disable, + .is_enabled = &dra7_apll_is_enabled, + .get_parent = &dra7_init_apll_parent, +}; + +static struct clk *omap_clk_register_apll(struct device *dev, const char *name, + const char **parent_names, int num_parents, unsigned long flags, + struct dpll_data *dpll_data, const char *clkdm_name, + const struct clk_ops *ops) +{ + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + if (!clk_hw) + return ERR_PTR(-ENOMEM); + + clk_hw->dpll_data = dpll_data; + clk_hw->hw.init = &init; + clk_hw->flags = REGMAP_ADDRESSING; + + init.name = name; + init.ops = ops; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + /* register the clock */ + clk = clk_register(dev, &clk_hw->hw); + + return clk; +} + +static int __init of_dra7_apll_setup(struct device_node *node) +{ + const struct clk_ops *ops; + struct clk *clk; + const char *clk_name = node->name; + int num_parents; + const char **parent_names = NULL; + u8 apll_flags = 0; + struct dpll_data *ad; + u32 idlest_mask = 0x1; + u32 autoidle_mask = 0x3; + int i; + int ret; + + ops = &apll_ck_ops; + ad = kzalloc(sizeof(*ad), GFP_KERNEL); + if (!ad) + return -ENOMEM; + + of_property_read_string(node, "clock-output-names", &clk_name); + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("dra7 apll %s must have parent(s)\n", node->name); + ret = -EINVAL; + goto cleanup; + } + + parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL); + + for (i = 0; i < num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + ad->clk_ref = of_clk_get(node, 0); + ad->clk_bypass = of_clk_get(node, 1); + + if (IS_ERR(ad->clk_ref)) { + pr_debug("ti,clk-ref for %s not found\n", clk_name); + ret = -EAGAIN; + goto cleanup; + } + + if (IS_ERR(ad->clk_bypass)) { + pr_debug("ti,clk-bypass for %s not found\n", clk_name); + ret = -EAGAIN; + goto cleanup; + } + + ad->control_reg = ti_clk_get_reg_addr(node, 0); + ad->idlest_reg = ti_clk_get_reg_addr(node, 1); + + if (!ad->control_reg || !ad->idlest_reg) { + ret = -EINVAL; + goto cleanup; + } + + ad->idlest_mask = idlest_mask; + ad->enable_mask = autoidle_mask; + + clk = omap_clk_register_apll(NULL, clk_name, parent_names, + num_parents, apll_flags, ad, + NULL, ops); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return 0; + } + + return PTR_ERR(clk); + +cleanup: + kfree(parent_names); + kfree(ad); + return ret; +} +CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: t-kristo@ti.com (Tero Kristo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv10 15/41] CLK: TI: DRA7: Add APLL support Date: Tue, 26 Nov 2013 10:05:56 +0200 [thread overview] Message-ID: <1385453182-24421-16-git-send-email-t-kristo@ti.com> (raw) In-Reply-To: <1385453182-24421-1-git-send-email-t-kristo@ti.com> From: J Keerthy <j-keerthy@ti.com> The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> --- .../devicetree/bindings/clock/ti/apll.txt | 31 +++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/apll.c | 239 ++++++++++++++++++++ 3 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt create mode 100644 drivers/clk/ti/apll.c diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt new file mode 100644 index 0000000..7faf5a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt @@ -0,0 +1,31 @@ +Binding for Texas Instruments APLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped APLL with usually two selectable input clocks +(reference clock and bypass clock), with analog phase locked +loop logic for multiplying the input clock to a desired output +clock. This clock also typically supports different operation +modes (locked, low power stop etc.) APLL mostly behaves like +a subtype of a DPLL [2], although a simplified one at that. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt + +Required properties: +- compatible : shall be "ti,dra7-apll-clock" +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks (clk-ref and clk-bypass) +- reg : address and length of the register set for controlling the APLL. + It contains the information of registers in the following order: + "control" - contains the control register base address + "idlest" - contains the idlest register base address + +Examples: + apll_pcie_ck: apll_pcie_ck at 4a008200 { + #clock-cells = <0>; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; + compatible = "ti,dra7-apll-clock"; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 935e5d2..3d71e1e 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o dpll.o autoidle.o divider.o \ fixed-factor.o gate.o clockdomain.o \ - composite.o mux.o + composite.o mux.o apll.o obj-$(CONFIG_ARCH_OMAP4) += clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += clk-54xx.o endif diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c new file mode 100644 index 0000000..5402b45 --- /dev/null +++ b/drivers/clk/ti/apll.c @@ -0,0 +1,239 @@ +/* + * OMAP APLL clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * J Keerthy <j-keerthy@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/log2.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/clk/ti.h> +#include <linux/delay.h> + +#define APLL_FORCE_LOCK 0x1 +#define APLL_AUTO_IDLE 0x2 +#define MAX_APLL_WAIT_TRIES 1000000 + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static int dra7_apll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int r = 0, i = 0; + struct dpll_data *ad; + const char *clk_name; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + if (!ad) + return -EINVAL; + + clk_name = __clk_get_name(clk->hw.clk); + + state <<= __ffs(ad->idlest_mask); + + /* Check is already locked */ + v = clk_readl(ad->idlest_reg); + + if ((v & ad->idlest_mask) == state) + return r; + + v = clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); + clk_writel(v, ad->control_reg); + + state <<= __ffs(ad->idlest_mask); + + while (1) { + v = clk_readl(ad->idlest_reg); + if ((v & ad->idlest_mask) == state) + break; + if (i > MAX_APLL_WAIT_TRIES) + break; + i++; + udelay(1); + } + + if (i == MAX_APLL_WAIT_TRIES) { + pr_warn("clock: %s failed transition to '%s'\n", + clk_name, (state) ? "locked" : "bypassed"); + } else { + pr_debug("clock: %s transition to '%s' in %d loops\n", + clk_name, (state) ? "locked" : "bypassed", i); + + r = 0; + } + + return r; +} + +static void dra7_apll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + + state <<= __ffs(ad->idlest_mask); + + v = clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); + clk_writel(v, ad->control_reg); +} + +static int dra7_apll_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u32 v; + + ad = clk->dpll_data; + + v = clk_readl(ad->control_reg); + v &= ad->enable_mask; + + v >>= __ffs(ad->enable_mask); + + return v == APLL_AUTO_IDLE ? 0 : 1; +} + +static u8 dra7_init_apll_parent(struct clk_hw *hw) +{ + return 0; +} + +static const struct clk_ops apll_ck_ops = { + .enable = &dra7_apll_enable, + .disable = &dra7_apll_disable, + .is_enabled = &dra7_apll_is_enabled, + .get_parent = &dra7_init_apll_parent, +}; + +static struct clk *omap_clk_register_apll(struct device *dev, const char *name, + const char **parent_names, int num_parents, unsigned long flags, + struct dpll_data *dpll_data, const char *clkdm_name, + const struct clk_ops *ops) +{ + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + if (!clk_hw) + return ERR_PTR(-ENOMEM); + + clk_hw->dpll_data = dpll_data; + clk_hw->hw.init = &init; + clk_hw->flags = REGMAP_ADDRESSING; + + init.name = name; + init.ops = ops; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + /* register the clock */ + clk = clk_register(dev, &clk_hw->hw); + + return clk; +} + +static int __init of_dra7_apll_setup(struct device_node *node) +{ + const struct clk_ops *ops; + struct clk *clk; + const char *clk_name = node->name; + int num_parents; + const char **parent_names = NULL; + u8 apll_flags = 0; + struct dpll_data *ad; + u32 idlest_mask = 0x1; + u32 autoidle_mask = 0x3; + int i; + int ret; + + ops = &apll_ck_ops; + ad = kzalloc(sizeof(*ad), GFP_KERNEL); + if (!ad) + return -ENOMEM; + + of_property_read_string(node, "clock-output-names", &clk_name); + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("dra7 apll %s must have parent(s)\n", node->name); + ret = -EINVAL; + goto cleanup; + } + + parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL); + + for (i = 0; i < num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + ad->clk_ref = of_clk_get(node, 0); + ad->clk_bypass = of_clk_get(node, 1); + + if (IS_ERR(ad->clk_ref)) { + pr_debug("ti,clk-ref for %s not found\n", clk_name); + ret = -EAGAIN; + goto cleanup; + } + + if (IS_ERR(ad->clk_bypass)) { + pr_debug("ti,clk-bypass for %s not found\n", clk_name); + ret = -EAGAIN; + goto cleanup; + } + + ad->control_reg = ti_clk_get_reg_addr(node, 0); + ad->idlest_reg = ti_clk_get_reg_addr(node, 1); + + if (!ad->control_reg || !ad->idlest_reg) { + ret = -EINVAL; + goto cleanup; + } + + ad->idlest_mask = idlest_mask; + ad->enable_mask = autoidle_mask; + + clk = omap_clk_register_apll(NULL, clk_name, parent_names, + num_parents, apll_flags, ad, + NULL, ops); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return 0; + } + + return PTR_ERR(clk); + +cleanup: + kfree(parent_names); + kfree(ad); + return ret; +} +CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); -- 1.7.9.5
next prev parent reply other threads:[~2013-11-26 8:05 UTC|newest] Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-11-26 8:05 [PATCHv10 00/41] ARM: TI SoC clock DT conversion Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 01/41] clk: add support for platform specific clock I/O wrapper functions Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-15 0:48 ` Mike Turquette 2013-12-15 0:48 ` Mike Turquette 2013-12-16 8:06 ` Tero Kristo 2013-12-16 8:06 ` Tero Kristo 2013-12-17 12:34 ` Paul Walmsley 2013-12-17 12:34 ` Paul Walmsley 2013-12-18 3:33 ` Paul Walmsley 2013-12-18 3:33 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 02/41] CLK: TI: add DT alias clock registration mechanism Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 03/41] CLK: ti: add init support for clock IP blocks Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 8:14 ` Paul Walmsley 2013-12-17 8:14 ` Paul Walmsley 2013-12-17 8:21 ` Tero Kristo 2013-12-17 8:21 ` Tero Kristo 2013-12-17 8:32 ` Paul Walmsley 2013-12-17 8:32 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 04/41] CLK: TI: Add DPLL clock support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 8:37 ` Paul Walmsley 2013-12-17 8:37 ` Paul Walmsley 2013-12-17 8:40 ` Paul Walmsley 2013-12-17 8:40 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 05/41] CLK: TI: add autoidle support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 06/41] clk: ti: add composite clock support Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 07/41] CLK: ti: add support for ti divider-clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 08/41] clk: ti: add support for TI fixed factor clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 09/41] CLK: TI: add support for gate clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 11/41] clk: ti: add support for basic mux clock Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 12/41] CLK: TI: add omap4 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-17 9:30 ` Paul Walmsley 2013-12-17 9:30 ` Paul Walmsley 2013-11-26 8:05 ` [PATCHv10 14/41] CLK: TI: omap5: Initialize USB_DPLL at boot Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` Tero Kristo [this message] 2013-11-26 8:05 ` [PATCHv10 15/41] CLK: TI: DRA7: Add APLL support Tero Kristo 2013-11-26 8:51 ` Alexander Aring 2013-11-26 8:51 ` Alexander Aring 2013-11-29 19:00 ` Tero Kristo 2013-11-29 19:00 ` Tero Kristo 2013-11-29 20:52 ` Alexander Aring 2013-11-29 20:52 ` Alexander Aring 2013-11-26 8:05 ` [PATCHv10 16/41] CLK: TI: add dra7 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 17/41] CLK: TI: add am33xx " Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 19/41] CLK: TI: add omap3 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 20/41] CLK: TI: add am43xx " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 21/41] ARM: dts: omap4 clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:44 ` Paul Walmsley 2013-12-17 9:44 ` Paul Walmsley 2013-12-17 9:57 ` Tero Kristo 2013-12-17 9:57 ` Tero Kristo 2013-12-20 11:15 ` Paul Walmsley 2013-12-20 11:15 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 23/41] ARM: dts: dra7 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:46 ` Paul Walmsley 2013-12-17 9:46 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 24/41] ARM: dts: clk: Add apll related clocks Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 26/41] ARM: dts: DRA7: Add PCIe related clock nodes Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 27/41] ARM: dts: am33xx clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:48 ` Paul Walmsley 2013-12-17 9:48 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 28/41] ARM: dts: omap3 " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:50 ` Paul Walmsley 2013-12-17 9:50 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 29/41] ARM: dts: AM35xx: use DT " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 30/41] ARM: dts: am43xx " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-17 9:52 ` Paul Walmsley 2013-12-17 9:52 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 31/41] ARM: OMAP2+: clock: add support for regmap Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 17:40 ` Tony Lindgren 2013-11-26 17:40 ` Tony Lindgren 2013-11-27 9:08 ` Tero Kristo 2013-11-27 9:08 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 32/41] ARM: OMAP2+: clock: use driver API instead of direct memory read/write Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 33/41] ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 34/41] ARM: OMAP3: hwmod: initialize clkdm from clkdm_name Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 35/41] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT Tero Kristo 2013-11-26 8:06 ` Tero Kristo [not found] ` <1385453182-24421-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org> 2013-11-26 8:05 ` [PATCHv10 10/41] CLK: TI: add support for clockdomain binding Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-12-15 4:23 ` Mike Turquette 2013-12-15 4:23 ` Mike Turquette 2013-12-16 8:13 ` Tero Kristo 2013-12-16 8:13 ` Tero Kristo 2013-12-18 3:07 ` Mike Turquette 2013-12-18 3:07 ` Mike Turquette 2013-11-26 8:05 ` [PATCHv10 13/41] CLK: TI: add omap5 clock init file Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:05 ` [PATCHv10 18/41] CLK: TI: add interface clock support for OMAP3 Tero Kristo 2013-11-26 8:05 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 22/41] ARM: dts: omap5 clock data Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-12-16 10:51 ` Paul Walmsley 2013-12-16 10:51 ` Paul Walmsley 2013-12-16 10:57 ` Tero Kristo 2013-12-16 10:57 ` Tero Kristo 2013-12-17 9:46 ` Paul Walmsley 2013-12-17 9:46 ` Paul Walmsley 2013-11-26 8:06 ` [PATCHv10 25/41] ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 36/41] ARM: OMAP2+: io: use new clock init API Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-28 0:49 ` [PATCHv10 00/41] ARM: TI SoC clock DT conversion Nishanth Menon 2013-11-28 0:49 ` Nishanth Menon [not found] ` <52969313.6090207-l0cyMroinI0@public.gmane.org> 2013-11-28 18:58 ` Paul Walmsley 2013-11-28 18:58 ` Paul Walmsley 2013-11-29 17:12 ` Tony Lindgren 2013-11-29 17:12 ` Tony Lindgren 2013-11-29 18:59 ` Tero Kristo 2013-11-29 18:59 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 37/41] ARM: OMAP4: remove old clock data and link in new clock init code Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 38/41] ARM: OMAP: DRA7: Enable clock init Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 39/41] ARM: AM43xx: " Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 40/41] ARM: AM33xx: remove old clock data and link in new clock init code Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 8:06 ` [PATCHv10 41/41] ARM: OMAP3: use DT clock init if DT data is available Tero Kristo 2013-11-26 8:06 ` Tero Kristo 2013-11-26 17:44 ` Tony Lindgren 2013-11-26 17:44 ` Tony Lindgren 2013-11-27 9:06 ` Tero Kristo 2013-11-27 9:06 ` Tero Kristo 2013-11-26 17:57 ` [PATCHv10 00/41] ARM: TI SoC clock DT conversion Tony Lindgren 2013-11-26 17:57 ` Tony Lindgren 2013-12-15 0:51 ` Mike Turquette 2013-12-15 0:51 ` Mike Turquette 2013-12-15 4:35 ` Mike Turquette 2013-12-15 4:35 ` Mike Turquette 2013-12-16 8:12 ` Tero Kristo 2013-12-16 8:12 ` Tero Kristo 2013-12-20 16:10 ` Felipe Balbi 2013-12-20 16:10 ` Felipe Balbi
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