[PATCH 00/40] CHV stuff mostly

[PATCH 00/40] CHV stuff mostly

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I was slaving over my bsw for most of the past week and this is the
result. It should really be split up into several series, but no
time now when vacation is calling. So I figured that I'll just post
the entire pile and disappear.

The whole lot can be found here (sitting on top of my earlier vlv
cdclk patches):
git://gitorious.org/vsyrjala/linux.git chv_stuff_5

This is mostly display stuff, with a few workaround things to make the
GT happy. The display stuff is mostly about power wells (several as of
now non working patches are also included) and the thrice cursed panel
power sequencer. Also some watermark patches are included.

The power sequencer stuff should apply equally to VLV, but I don't
have a suitable machine nor time to try it. I think it would fix a
lot of the weird link training failures people may have seen on VLV.
If someone else wants to play with it I recommend a machine with eDP+DP
and doing stuff like:
 xrandr --output DP1 --off --output eDP1 --off
 xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080 --crtc 0
 xrandr --output DP1 --off --output eDP1 --off
 xrandr --output DP1 --mode 1920x1080 --crtc 0 --output eDP1 --mode 1920x1080 --crtc 1
 xrandr --output DP1 --off --output eDP1 --off
 xrandr --output DP1 --mode 1920x1080 --crtc 1 --output eDP1 --mode 1920x1080 --crtc 0
 ...
or even just
 xrandr --output eDP1 --off
 xrandr --output eDP1 --mode 1920x1080 --crtc 0
 xrandr --output eDP1 --off
 xrandr --output eDP1 --mode 1920x1080 --crtc 1
 xrandr --output eDP1 --off
 xrandr --output eDP1 --mode 1920x1080 --crtc 0
 ...
so switching the pipe->port mapping around a lot.

The power well refcounts vs. the edp vdd code is still a mess. Occasionally it overflows
the refcounts, and occasionally it underflows. So it there are display problems I would
suggest looking at /sys/kernel/debug/dri/0/i915_power_domain_info and chencking if something
is 0 (or even negative) when it shouldn't be.

Kenneth Graunke (2):
  drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
  drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

Ville Syrjälä (37):
  drm/i915: Try to populate mem_freq for chv
  drm/i915: Use the cached min/min/rpe values in the vlv debugfs code
  drm/i915: Align chv rps min/max/rpe values
  drm/i915: Populate mem_freq in init_gt_powerwave()
  drm/i915: Don't disable PPGTT for CHV based in PCI rev
  drm/i915: Add cdclk change support for chv
  drm/i915: Disable cdclk changes for chv until Punit is ready
  drm/i915: Leave DPLL ref clocks on
  drm/i915: Split chv_update_pll() apart
  drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()
  drm/i915: Call intel_{dp,hdmi}_prepare for chv
  drm/i915: Clarify CHV swing margin/deemph bits
  drm/i915: Make sure hardware uses the correct swing margin/deemph bits
    on chv
  drm/i915: Override display PHY TX FIFO reset master on chv
  drm/i915: Clear TX FIFO reset master override bits on chv
  drm/i915: Add chv_power_wells[]
  drm/i915: Add chv cmnlane power wells
  drm/i915: Kill intel_reset_dpio()
  drm/i915: Add disp2d power well for chv
  drm/i915: Add per-pipe power wells for chv
  drm/i915: Add chv port B and C TX wells
  drm/i915: Add chv port D TX wells
  drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL
    values
  drm/i915: Fill out the FWx watermark register defines
  drm/i915: Parametrize VLV_DDL registers
  drm/i915: Split a few long debug prints
  drm/i915: Add cherryview_update_wm()
  drm/i916: Init chv workarounds at render ring init
  drm/i915: Hack to tie both common lanes together on chv
  drm/i915: Polish the chv cmnlane resrt macros
  drm/i915: Add DP training pattern 3 for CHV
  drm/i915: Fix vdd locking
  drm/i915: Allow vdd_off when vdd is already off
  drm/i915: Fix eDP link training when switching pipes
  drm/i915: Track which port is using which pipe's power sequencer
  drm/i915: Kick the power sequencer before AUX transactions
  drm/i915: Unstuck power sequencer when lighting up a DP port

Zhenyu Wang (1):
  drm/i915: Fix drain latency precision multipler for VLV

 drivers/gpu/drm/i915/i915_debugfs.c     |  27 +-
 drivers/gpu/drm/i915/i915_drv.h         |   2 -
 drivers/gpu/drm/i915/i915_gem_gtt.c     |   3 +-
 drivers/gpu/drm/i915/i915_reg.h         | 263 +++++++++++----
 drivers/gpu/drm/i915/intel_display.c    | 123 ++++---
 drivers/gpu/drm/i915/intel_dp.c         | 469 +++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h        |   6 +
 drivers/gpu/drm/i915/intel_hdmi.c       |  29 +-
 drivers/gpu/drm/i915/intel_pm.c         | 565 ++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_ringbuffer.c |  84 ++++-
 10 files changed, 1296 insertions(+), 275 deletions(-)

-- 
1.8.5.5

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[PATCH 01/40] drm/i915: Try to populate mem_freq for chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

mem_freq is needed to decode the GPU freq opcodes.

FIXME: Punit reg seems to contain garbage so this isn't right

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07c040c..ef00756 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq = 800;
+		break;
+	case 2:
+		dev_priv->mem_freq = 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq = 1333;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.8.5.5

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[PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No need to re-read the hardware rps fuses when we already have all the
values tucked away in dev_priv->rps.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
 drivers/gpu/drm/i915/i915_drv.h     |  2 --
 drivers/gpu/drm/i915/intel_pm.c     |  8 ++++----
 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a93b3bf..415010e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1131,20 +1131,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
 			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
 	} else if (IS_VALLEYVIEW(dev)) {
-		u32 freq_sts, val;
+		u32 freq_sts;
 
 		mutex_lock(&dev_priv->rps.hw_lock);
 		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 
-		val = valleyview_rps_max_freq(dev_priv);
 		seq_printf(m, "max GPU freq: %d MHz\n",
-			   vlv_gpu_freq(dev_priv, val));
+			   dev_priv->rps.max_freq);
 
-		val = valleyview_rps_min_freq(dev_priv);
 		seq_printf(m, "min GPU freq: %d MHz\n",
-			   vlv_gpu_freq(dev_priv, val));
+			   dev_priv->rps.min_freq);
+
+		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
+			   dev_priv->rps.efficient_freq);
 
 		seq_printf(m, "current GPU freq: %d MHz\n",
 			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
@@ -3565,8 +3566,8 @@ i915_max_freq_set(void *data, u64 val)
 	if (IS_VALLEYVIEW(dev)) {
 		val = vlv_freq_opcode(dev_priv, val);
 
-		hw_max = valleyview_rps_max_freq(dev_priv);
-		hw_min = valleyview_rps_min_freq(dev_priv);
+		hw_max = dev_priv->rps.max_freq;
+		hw_min = dev_priv->rps.min_freq;
 	} else {
 		do_div(val, GT_FREQUENCY_MULTIPLIER);
 
@@ -3646,8 +3647,8 @@ i915_min_freq_set(void *data, u64 val)
 	if (IS_VALLEYVIEW(dev)) {
 		val = vlv_freq_opcode(dev_priv, val);
 
-		hw_max = valleyview_rps_max_freq(dev_priv);
-		hw_min = valleyview_rps_min_freq(dev_priv);
+		hw_max = dev_priv->rps.max_freq;
+		hw_min = dev_priv->rps.min_freq;
 	} else {
 		do_div(val, GT_FREQUENCY_MULTIPLIER);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cea596..38859d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2646,8 +2646,6 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
-extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
-extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
 extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 extern int intel_enable_rc6(const struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef00756..10c9c02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3729,7 +3729,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;
 
@@ -3749,7 +3749,7 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 	return rpe;
 }
 
-int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rpn;
 
@@ -3758,7 +3758,7 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
 	return rpn;
 }
 
-int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
+static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;
 
@@ -3783,7 +3783,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 	return rpe;
 }
 
-int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
+static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
 	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
 }
-- 
1.8.5.5

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[PATCH 03/40] drm/i915: Align chv rps min/max/rpe values

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV wants even rps opcodes so make sure the min/max/rpe values are also
even.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  8 ++++++++
 drivers/gpu/drm/i915/intel_pm.c     | 19 ++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 415010e..9b01e7c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3566,6 +3566,10 @@ i915_max_freq_set(void *data, u64 val)
 	if (IS_VALLEYVIEW(dev)) {
 		val = vlv_freq_opcode(dev_priv, val);
 
+		/* CHV needs even encode values */
+		if (IS_CHERRYVIEW(dev))
+			val &= ~1;
+
 		hw_max = dev_priv->rps.max_freq;
 		hw_min = dev_priv->rps.min_freq;
 	} else {
@@ -3647,6 +3651,10 @@ i915_min_freq_set(void *data, u64 val)
 	if (IS_VALLEYVIEW(dev)) {
 		val = vlv_freq_opcode(dev_priv, val);
 
+		/* CHV needs even encode values */
+		if (IS_CHERRYVIEW(dev))
+			val = ALIGN(val, 2);
+
 		hw_max = dev_priv->rps.max_freq;
 		hw_min = dev_priv->rps.min_freq;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 10c9c02..e3f23c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3924,21 +3924,30 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	if (WARN_ON_ONCE(dev_priv->rps.max_freq & 1))
+		dev_priv->rps.max_freq &= ~1;
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
 			 dev_priv->rps.max_freq);
 
-	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
-	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
-			 dev_priv->rps.efficient_freq);
-
 	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
+		dev_priv->rps.min_freq = ALIGN(dev_priv->rps.min_freq, 2);
 	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
 			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
 			 dev_priv->rps.min_freq);
 
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
+		dev_priv->rps.efficient_freq &= ~1;
+	dev_priv->rps.efficient_freq = clamp(dev_priv->rps.efficient_freq,
+					     dev_priv->rps.min_freq,
+					     dev_priv->rps.max_freq);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
 	/* Preserve min/max settings in case of re-init */
 	if (dev_priv->rps.max_freq_softlimit == 0)
 		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
-- 
1.8.5.5

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[PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to init_gt_powersave().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e3f23c2..898654f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3884,11 +3884,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
 static void valleyview_init_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
 
 	valleyview_setup_pctx(dev);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq = 800;
+		break;
+	case 2:
+		dev_priv->mem_freq = 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq = 1333;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
 	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
 	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
 	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -3918,11 +3934,27 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 static void cherryview_init_gt_powersave(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
 
 	cherryview_setup_pctx(dev);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq = 800;
+		break;
+	case 2:
+		dev_priv->mem_freq = 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq = 1333;
+		break;
+	}
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
+
 	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
 	if (WARN_ON_ONCE(dev_priv->rps.max_freq & 1))
 		dev_priv->rps.max_freq &= ~1;
@@ -5545,24 +5577,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
-
-	mutex_lock(&dev_priv->rps.hw_lock);
-	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	switch ((val >> 6) & 3) {
-	case 0:
-	case 1:
-		dev_priv->mem_freq = 800;
-		break;
-	case 2:
-		dev_priv->mem_freq = 1066;
-		break;
-	case 3:
-		dev_priv->mem_freq = 1333;
-		break;
-	}
-	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
@@ -5638,24 +5652,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
-
-	mutex_lock(&dev_priv->rps.hw_lock);
-	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-	mutex_unlock(&dev_priv->rps.hw_lock);
-	switch ((val >> 6) & 3) {
-	case 0:
-	case 1:
-		dev_priv->mem_freq = 800;
-		break;
-	case 2:
-		dev_priv->mem_freq = 1066;
-		break;
-	case 3:
-		dev_priv->mem_freq = 1333;
-		break;
-	}
-	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
-- 
1.8.5.5

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[PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In
 commit 62942ed7279d3e06dc15ae3d47665eff3b373327
 Author: Jesse Barnes <jbarnes@virtuousgeek.org>
 Date:   Fri Jun 13 09:28:33 2014 -0700

    drm/i915/vlv: disable PPGTT on early revs v3

we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to
explicitly avoid disabling PPGTT on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4153ee..5188936 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -64,7 +64,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 #endif
 
 	/* Early VLV doesn't have this */
-	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
+	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+	    dev->pdev->revision < 0xb) {
 		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 		return 0;
 	}
-- 
1.8.5.5

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[PATCH 06/40] drm/i915: Add cdclk change support for chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks like the Punit is supposed to support the 400MHz cdclk directly on
chv, so we don't need the vlv tricks.

FIXME: Punit doesn't seem ready for this yet on current hw

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 +++
 drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++--
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f156591..e296312 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -491,6 +491,10 @@
 #define BUNIT_REG_BISOC				0x11
 
 #define PUNIT_REG_DSPFREQ			0x36
+#define   DSPFREQSTAT_SHIFT_CHV			24
+#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
+#define   DSPFREQGUAR_SHIFT_CHV			8
+#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
 #define   DSPFREQSTAT_SHIFT			30
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
 #define   DSPFREQGUAR_SHIFT			14
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 99c10d1..9af1d13 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	vlv_update_cdclk(dev);
 }
 
+static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val, cmd;
+
+	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
+
+	switch (cdclk) {
+	case 400000:
+		cmd = 3;
+		break;
+	case 333333:
+	case 320000:
+		cmd = 2;
+		break;
+	case 266667:
+		cmd = 1;
+		break;
+	case 200000:
+		cmd = 0;
+		break;
+	default:
+		WARN_ON(1);
+		return;
+	}
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+	val &= ~DSPFREQGUAR_MASK_CHV;
+	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
+	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
+		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
+		     50)) {
+		DRM_ERROR("timed out waiting for CDclk change\n");
+	}
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	vlv_update_cdclk(dev);
+}
+
 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 				 int max_pixclk)
 {
@@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
 	int max_pixclk = intel_mode_max_pixclk(dev_priv);
 	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
 
-	if (req_cdclk != dev_priv->vlv_cdclk_freq)
-		valleyview_set_cdclk(dev, req_cdclk);
+	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
+		if (IS_CHERRYVIEW(dev))
+			cherryview_set_cdclk(dev, req_cdclk);
+		else
+			valleyview_set_cdclk(dev, req_cdclk);
+	}
+
 	modeset_update_crtc_power_domains(dev);
 }
 
-- 
1.8.5.5

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[PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Punit seems a bit WIP still. Disable cdclk changes until we have
hardware where it works.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9af1d13..4abf8b6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4576,6 +4576,10 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 	int vco = valleyview_get_vco(dev_priv);
 	int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
 
+	/* FIXME: Punit isn't quite ready yet */
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		return 400000;
+
 	/*
 	 * Really only a few cases to deal with, as only 4 CDclks are supported:
 	 *   200MHz
@@ -5297,6 +5301,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
 	u32 val;
 	int divider;
 
+	/* FIXME: Punit isn't quite ready yet */
+	if (IS_CHERRYVIEW(dev))
+		return 400000;
+
 	mutex_lock(&dev_priv->dpio_lock);
 	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 	mutex_unlock(&dev_priv->dpio_lock);
-- 
1.8.5.5

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[PATCH 08/40] drm/i915: Leave DPLL ref clocks on

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4abf8b6f..a430699f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1709,7 +1709,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	assert_pipe_disabled(dev_priv, pipe);
 
 	/* Set PLL en = 0 */
-	val = DPLL_SSC_REF_CLOCK_CHV;
+	val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 	I915_WRITE(DPLL(pipe), val);
-- 
1.8.5.5

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[PATCH 09/40] drm/i915: Split chv_update_pll() apart

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split chv_update_pll() into two parts ala:
 commit bdd4b6a655749970cc632aafc5fd596c07b60b1c
 Author: Daniel Vetter <daniel.vetter@ffwll.ch>
 Date:   Thu Apr 24 23:55:11 2014 +0200

    drm/i915: Extract vlv_prepare_pll

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a430699f..3e4d570 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -100,6 +100,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 static void vlv_prepare_pll(struct intel_crtc *crtc);
+static void chv_prepare_pll(struct intel_crtc *crtc);
 
 typedef struct {
 	int	min, max;
@@ -4670,8 +4671,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
 	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
 
-	if (!is_dsi && !IS_CHERRYVIEW(dev))
-		vlv_prepare_pll(intel_crtc);
+	if (!is_dsi) {
+		if (IS_CHERRYVIEW(dev))
+			chv_prepare_pll(intel_crtc);
+		else
+			vlv_prepare_pll(intel_crtc);
+	}
 
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -5692,6 +5697,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
 
 static void chv_update_pll(struct intel_crtc *crtc)
 {
+	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
+		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+		DPLL_VCO_ENABLE;
+	if (crtc->pipe != PIPE_A)
+		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+	crtc->config.dpll_hw_state.dpll_md =
+		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+}
+
+static void chv_prepare_pll(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe = crtc->pipe;
@@ -5701,15 +5718,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	int refclk;
 
-	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
-		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
-		DPLL_VCO_ENABLE;
-	if (pipe != PIPE_A)
-		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
-	crtc->config.dpll_hw_state.dpll_md =
-		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-
 	bestn = crtc->config.dpll.n;
 	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
 	bestm1 = crtc->config.dpll.m1;
-- 
1.8.5.5

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[PATCH 10/40] drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV and CHV disable the DP port only in the .post_disable() hook, so we
need to make intel_sanitize_encoder() call that when it's trying to
disable encoders without an active pipes.

My bsw actaully hits this when an external display is connected. The
BIOS still likes to turn on the eDP port, but leaves the pipe disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e4d570..a16f635 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12772,6 +12772,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 				      encoder->base.base.id,
 				      encoder->base.name);
 			encoder->disable(encoder);
+			if (encoder->post_disable)
+				encoder->post_disable(encoder);
 		}
 		encoder->base.crtc = NULL;
 		encoder->connectors_active = false;
-- 
1.8.5.5

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[PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV was forgotten the intel_{dp,hdmi}_prepare() were introduced (or the
chv patches were still in flight?). Call these when enabling the ports.

Things tend to work much better when we actually write something
to the port registers :)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 2 ++
 drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b5ec489..e272f92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2197,6 +2197,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 	enum pipe pipe = intel_crtc->pipe;
 	u32 val;
 
+	intel_dp_prepare(encoder);
+
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* program left/right clock distribution */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2422413..c9d77d3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1240,6 +1240,8 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 	enum pipe pipe = intel_crtc->pipe;
 	u32 val;
 
+	intel_hdmi_prepare(encoder);
+
 	mutex_lock(&dev_priv->dpio_lock);
 
 	/* program left/right clock distribution */
-- 
1.8.5.5

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[PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV display PHY registes have two swing margin/deemph settings. Make it
clear which ones we're using.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 8 ++++++--
 drivers/gpu/drm/i915/intel_dp.c   | 4 ++--
 drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e296312..ba90320 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -831,8 +831,8 @@ enum punit_power_well {
 
 #define _VLV_TX_DW2_CH0			0x8288
 #define _VLV_TX_DW2_CH1			0x8488
-#define   DPIO_SWING_MARGIN_SHIFT	16
-#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
+#define   DPIO_SWING_MARGIN000_SHIFT	16
+#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
 
@@ -840,12 +840,16 @@ enum punit_power_well {
 #define _VLV_TX_DW3_CH1			0x848c
 /* The following bit for CHV phy */
 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
+#define   DPIO_SWING_MARGIN101_SHIFT	16
+#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
 
 #define _VLV_TX_DW4_CH0			0x8290
 #define _VLV_TX_DW4_CH1			0x8490
 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
+#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
+#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
 
 #define _VLV_TX3_DW4_CH0		0x690
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e272f92..4457f8f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	/* Program swing margin */
 	for (i = 0; i < 4; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-		val &= ~DPIO_SWING_MARGIN_MASK;
-		val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
+		val &= ~DPIO_SWING_MARGIN000_MASK;
+		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c9d77d3..c5c88127 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	for (i = 0; i < 4; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
-		val &= ~DPIO_SWING_MARGIN_MASK;
-		val |= 102 << DPIO_SWING_MARGIN_SHIFT;
+		val &= ~DPIO_SWING_MARGIN000_MASK;
+		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
 	}
 
-- 
1.8.5.5

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[PATCH 13/40] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The register can house two different swing marging/deemph settings at
once. However only one gets used based on some other bits. Make sure we
set those bits correctly to make the hardware use the settings we
provided.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 14 ++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ba90320..2a7bc22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -798,12 +798,31 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW9_CH0		0x8224
 #define _VLV_PCS_DW9_CH1		0x8424
+#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
+#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
+#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
+#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
+#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
+#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
 
+#define _VLV_PCS01_DW9_CH0		0x224
+#define _VLV_PCS23_DW9_CH0		0x424
+#define _VLV_PCS01_DW9_CH1		0x2624
+#define _VLV_PCS23_DW9_CH1		0x2824
+#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
+#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
+
 #define _CHV_PCS_DW10_CH0		0x8228
 #define _CHV_PCS_DW10_CH1		0x8428
 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
+#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
+#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
+#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
+#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
+#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
+#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
 
 #define _VLV_PCS01_DW10_CH0		0x0228
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4457f8f..c59e8fc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2548,12 +2548,26 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
 	/* Clear calc init */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+
 	/* Program swing deemph */
 	for (i = 0; i < 4; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c5c88127..cda6506 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1394,12 +1394,26 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	/* Clear calc init */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
+	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
+	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
+	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
+	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
+
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
 	for (i = 0; i < 4; i++) {
-- 
1.8.5.5

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[PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just an attempt to frob these bits. Apparently we should not need to
touch them (apart from maybe making sure the override is disabled so
that the hardware automagically does the right thing).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   | 23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++++
 3 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a7bc22..d246609 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -758,6 +758,8 @@ enum punit_power_well {
 #define _VLV_PCS_DW0_CH1		0x8400
 #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
 #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
 #define _VLV_PCS01_DW0_CH0		0x200
@@ -834,8 +836,18 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
+#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
 
+#define _VLV_PCS01_DW11_CH0		0x022c
+#define _VLV_PCS23_DW11_CH0		0x042c
+#define _VLV_PCS01_DW11_CH1		0x262c
+#define _VLV_PCS23_DW11_CH1		0x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW12_CH0		0x8230
 #define _VLV_PCS_DW12_CH1		0x8430
 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c59e8fc..814a950 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cda6506..47430d5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
+	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
+	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
+	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
+	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-- 
1.8.5.5

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[PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clear the override bits to make sure the hardware maanages
the TX FIFO reset master on its own.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 20 +++-----------------
 drivers/gpu/drm/i915/intel_hdmi.c | 20 +++-----------------
 2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 814a950..739dc43 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2139,27 +2139,13 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
-	/* TX FIFO reset source */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
-	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
+	/* allow hardware to manage TX FIFO reset source */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
-	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
-	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
-	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
-	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
-	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
 
 	/* Deassert soft data lane reset*/
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 47430d5..98bdf02 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1358,27 +1358,13 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
-	/* TX FIFO reset source */
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
-	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
-
+	/* allow hardware to manage TX FIFO reset source */
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
-	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
-	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
 
-	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
-	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
-
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
-	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
-	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
-	val |= DPIO_LANEDESKEW_STRAP_OVRD;
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
 
 	/* Deassert soft data lane reset*/
-- 
1.8.5.5

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[PATCH 16/40] drm/i915: Add chv_power_wells[]

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add chv_power_wells[] so we can start to build up the power well support
for chv. Just the "always on" well there initialy.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 898654f..e2b956e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6498,6 +6498,15 @@ static struct i915_power_well vlv_power_wells[] = {
 	},
 };
 
+static struct i915_power_well chv_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = 1,
+		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
+		.ops = &i9xx_always_on_power_well_ops,
+	},
+};
+
 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
 						 enum punit_power_well power_well_id)
 {
@@ -6534,6 +6543,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	} else if (IS_BROADWELL(dev_priv->dev)) {
 		set_power_wells(power_domains, bdw_power_wells);
 		hsw_pwr = power_domains;
+	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
+		set_power_wells(power_domains, chv_power_wells);
 	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
 		set_power_wells(power_domains, vlv_power_wells);
 	} else {
-- 
1.8.5.5

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[PATCH 17/40] drm/i915: Add chv cmnlane power wells

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d246609..19e68d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -512,6 +512,7 @@ enum punit_power_well {
 	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
 	PUNIT_POWER_WELL_DPIO_RX0		= 10,
 	PUNIT_POWER_WELL_DPIO_RX1		= 11,
+	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
 
 	PUNIT_POWER_WELL_NUM,
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2b956e..f88490b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 	vlv_set_power_well(dev_priv, power_well, false);
 }
 
+static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+					   struct i915_power_well *power_well)
+{
+	enum dpio_phy phy;
+
+	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
+
+	/*
+	 * Enable the CRI clock source so we can get at the
+	 * display and the reference clock for VGA
+	 * hotplug / manual detection.
+	 */
+	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+		phy = DPIO_PHY0;
+		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+			   DPLL_REFA_CLK_ENABLE_VLV);
+		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+	} else {
+		phy = DPIO_PHY1;
+		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
+			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+	}
+	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
+	vlv_set_power_well(dev_priv, power_well, true);
+
+	/* Poll for phypwrgood signal */
+	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
+		DRM_ERROR("Display PHY %d is not power up\n", phy);
+
+	I915_WRITE(DISPLAY_PHY_CONTROL,
+		   PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
+}
+
+static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+					    struct i915_power_well *power_well)
+{
+	enum dpio_phy phy;
+
+	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
+
+	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+		phy = DPIO_PHY0;
+		assert_pll_disabled(dev_priv, PIPE_A);
+		assert_pll_disabled(dev_priv, PIPE_B);
+	} else {
+		phy = DPIO_PHY1;
+		assert_pll_disabled(dev_priv, PIPE_C);
+	}
+
+	I915_WRITE(DISPLAY_PHY_CONTROL,
+		   PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
+
+	vlv_set_power_well(dev_priv, power_well, false);
+}
+
 static void check_power_well_state(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
@@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
 	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
 	BIT(POWER_DOMAIN_INIT))
 
+#define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
+	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
+	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
+	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
+	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
+	BIT(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_D_POWER_DOMAINS (		\
+	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
+	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
+	BIT(POWER_DOMAIN_INIT))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_always_on_power_well_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
+	.sync_hw = vlv_power_well_sync_hw,
+	.enable = chv_dpio_cmn_power_well_enable,
+	.disable = chv_dpio_cmn_power_well_disable,
+	.is_enabled = vlv_power_well_enabled,
+};
+
 static struct i915_power_well chv_power_wells[] = {
 	{
 		.name = "always-on",
@@ -6505,6 +6582,18 @@ static struct i915_power_well chv_power_wells[] = {
 		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
 		.ops = &i9xx_always_on_power_well_ops,
 	},
+	{
+		.name = "dpio-common-bc",
+		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
+		.ops = &chv_dpio_cmn_power_well_ops,
+	},
+	{
+		.name = "dpio-common-d",
+		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
+		.ops = &chv_dpio_cmn_power_well_ops,
+	},
 };
 
 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
-- 
1.8.5.5

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[PATCH 18/40] drm/i915: Kill intel_reset_dpio()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Both VLV and CHV handle the cmnreset stuff in the power well code now,
so intel_reset_dpio() is no longer needed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 -------------------------------
 1 file changed, 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a16f635..3cd73f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1511,34 +1511,6 @@ static void intel_init_dpio(struct drm_device *dev)
 	}
 }
 
-static void intel_reset_dpio(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	if (IS_CHERRYVIEW(dev)) {
-		enum dpio_phy phy;
-		u32 val;
-
-		for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
-			/* Poll for phypwrgood signal */
-			if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
-						PHY_POWERGOOD(phy), 1))
-				DRM_ERROR("Display PHY %d is not power up\n", phy);
-
-			/*
-			 * Deassert common lane reset for PHY.
-			 *
-			 * This should only be done on init and resume from S3
-			 * with both PLLs disabled, or we risk losing DPIO and
-			 * PLL synchronization.
-			 */
-			val = I915_READ(DISPLAY_PHY_CONTROL);
-			I915_WRITE(DISPLAY_PHY_CONTROL,
-				PHY_COM_LANE_RESET_DEASSERT(phy, val));
-		}
-	}
-}
-
 static void vlv_enable_pll(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
@@ -12473,8 +12445,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
 
 	intel_init_clock_gating(dev);
 
-	intel_reset_dpio(dev);
-
 	intel_enable_gt_powersave(dev);
 }
 
@@ -12545,7 +12515,6 @@ void intel_modeset_init(struct drm_device *dev)
 	}
 
 	intel_init_dpio(dev);
-	intel_reset_dpio(dev);
 
 	intel_cpu_pll_init(dev);
 	intel_shared_dpll_init(dev);
-- 
1.8.5.5

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[PATCH 19/40] drm/i915: Add disp2d power well for chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Not sure if it's still there since chv has per-pipe power wells.
At least with current Punit this doesn't work. Also the display
irq handling would need to be adjusted for pipe C. So leave the
code iffed out for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f88490b..46394fc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6582,6 +6582,14 @@ static struct i915_power_well chv_power_wells[] = {
 		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
 		.ops = &i9xx_always_on_power_well_ops,
 	},
+#if 0
+	{
+		.name = "display",
+		.domains = VLV_DISPLAY_POWER_DOMAINS,
+		.data = PUNIT_POWER_WELL_DISP2D,
+		.ops = &vlv_display_power_well_ops,
+	},
+#endif
 	{
 		.name = "dpio-common-bc",
 		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
-- 
1.8.5.5

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[PATCH 20/40] drm/i915: Add per-pipe power wells for chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a power well for each pipe. Add the code to deal with them.

The Punit in current hardware doesn't seem ready for this yet, so
leave it iffed out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  12 ++++
 drivers/gpu/drm/i915/intel_pm.c | 126 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 138 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19e68d6..3d1fef4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -499,6 +499,18 @@
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
 #define   DSPFREQGUAR_SHIFT			14
 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
+#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
+#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
+#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
+#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
+#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
+#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
+#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
+#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
+#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
+#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
+#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
+#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
 
 /* See the PUNIT HAS v0.8 for the below bits */
 enum punit_power_well {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 46394fc..de5416b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6258,6 +6258,95 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 	vlv_set_power_well(dev_priv, power_well, false);
 }
 
+static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	enum pipe pipe = power_well->data;
+	bool enabled;
+	u32 state, ctrl;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
+	/*
+	 * We only ever set the power-on and power-gate states, anything
+	 * else is unexpected.
+	 */
+	WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
+	enabled = state == DP_SSS_PWR_ON(pipe);
+
+	/*
+	 * A transient state at this point would mean some unexpected party
+	 * is poking at the power controls too.
+	 */
+	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
+	WARN_ON(ctrl << 16 != state);
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	return enabled;
+}
+
+static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
+				    struct i915_power_well *power_well,
+				    bool enable)
+{
+	enum pipe pipe = power_well->data;
+	u32 state;
+	u32 ctrl;
+
+	state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+#define COND \
+	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
+
+	if (COND)
+		goto out;
+
+	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+	ctrl &= ~DP_SSC_MASK(pipe);
+	ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
+	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
+
+	if (wait_for(COND, 100))
+		DRM_ERROR("timout setting power well state %08x (%08x)\n",
+			  state,
+			  vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
+
+#undef COND
+
+out:
+	mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
+static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
+}
+
+static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
+				       struct i915_power_well *power_well)
+{
+	WARN_ON_ONCE(power_well->data != PIPE_A &&
+		     power_well->data != PIPE_B &&
+		     power_well->data != PIPE_C);
+
+	chv_set_pipe_power_well(dev_priv, power_well, true);
+}
+
+static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	WARN_ON_ONCE(power_well->data != PIPE_A &&
+		     power_well->data != PIPE_B &&
+		     power_well->data != PIPE_C);
+
+	chv_set_pipe_power_well(dev_priv, power_well, false);
+}
+
 static void check_power_well_state(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
@@ -6427,6 +6516,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
 	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
 	BIT(POWER_DOMAIN_INIT))
 
+#define CHV_PIPE_A_POWER_DOMAINS (	\
+	BIT(POWER_DOMAIN_PIPE_A) |	\
+	BIT(POWER_DOMAIN_INIT))
+
+#define CHV_PIPE_B_POWER_DOMAINS (	\
+	BIT(POWER_DOMAIN_PIPE_B) |	\
+	BIT(POWER_DOMAIN_INIT))
+
+#define CHV_PIPE_C_POWER_DOMAINS (	\
+	BIT(POWER_DOMAIN_PIPE_C) |	\
+	BIT(POWER_DOMAIN_INIT))
+
 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
 	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
 	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
@@ -6568,6 +6669,13 @@ static struct i915_power_well vlv_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_ops chv_pipe_power_well_ops = {
+	.sync_hw = chv_pipe_power_well_sync_hw,
+	.enable = chv_pipe_power_well_enable,
+	.disable = chv_pipe_power_well_disable,
+	.is_enabled = chv_pipe_power_well_enabled,
+};
+
 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
 	.sync_hw = vlv_power_well_sync_hw,
 	.enable = chv_dpio_cmn_power_well_enable,
@@ -6589,6 +6697,24 @@ static struct i915_power_well chv_power_wells[] = {
 		.data = PUNIT_POWER_WELL_DISP2D,
 		.ops = &vlv_display_power_well_ops,
 	},
+	{
+		.name = "pipe-a",
+		.domains = CHV_PIPE_A_POWER_DOMAINS,
+		.data = PIPE_A,
+		.ops = &chv_pipe_power_well_ops,
+	},
+	{
+		.name = "pipe-b",
+		.domains = CHV_PIPE_B_POWER_DOMAINS,
+		.data = PIPE_B,
+		.ops = &chv_pipe_power_well_ops,
+	},
+	{
+		.name = "pipe-c",
+		.domains = CHV_PIPE_C_POWER_DOMAINS,
+		.data = PIPE_C,
+		.ops = &chv_pipe_power_well_ops,
+	},
 #endif
 	{
 		.name = "dpio-common-bc",
-- 
1.8.5.5

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[PATCH 21/40] drm/i915: Add chv port B and C TX wells

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the TX wells for ports B and C just like on VLV.

Again Punit doesn't seem ready (or the wells don't even exist anymore)
so leave it iffed out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de5416b..cae936c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6728,6 +6728,36 @@ static struct i915_power_well chv_power_wells[] = {
 		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
 		.ops = &chv_dpio_cmn_power_well_ops,
 	},
+#if 0
+	{
+		.name = "dpio-tx-b-01",
+		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+	},
+	{
+		.name = "dpio-tx-b-23",
+		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+	},
+	{
+		.name = "dpio-tx-c-01",
+		.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+	},
+	{
+		.name = "dpio-tx-c-23",
+		.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+	},
+#endif
 };
 
 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
-- 
1.8.5.5

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[PATCH 22/40] drm/i915: Add chv port D TX wells

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the TX wells for port D. The Punit subsystem numbers are a total
guess at this time. Also I'm not sure these even exist. Certainly the
Punit in current hardware doesn't deal with these.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  4 ++++
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d1fef4..191df9e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -525,6 +525,10 @@ enum punit_power_well {
 	PUNIT_POWER_WELL_DPIO_RX0		= 10,
 	PUNIT_POWER_WELL_DPIO_RX1		= 11,
 	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
+	/* FIXME: guesswork below */
+	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
+	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
+	PUNIT_POWER_WELL_DPIO_RX2		= 15,
 
 	PUNIT_POWER_WELL_NUM,
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cae936c..55f3e6b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
 	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
 	BIT(POWER_DOMAIN_INIT))
 
+#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
+	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
+	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
+	BIT(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
+	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
+	BIT(POWER_DOMAIN_INIT))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_always_on_power_well_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
 		.ops = &vlv_dpio_power_well_ops,
 		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
 	},
+	{
+		.name = "dpio-tx-d-01",
+		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
+			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
+	},
+	{
+		.name = "dpio-tx-d-23",
+		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
+			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
+		.ops = &vlv_dpio_power_well_ops,
+		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
+	},
 #endif
 };
 
-- 
1.8.5.5

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[PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[ville.syrjala]

From: Zhenyu Wang <zhenyuw@linux.intel.com>

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
 drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
 2 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 191df9e..7ab5a03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3909,47 +3909,47 @@ enum punit_power_well {
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
-#define DRAIN_LATENCY_PRECISION_16	16
+#define DRAIN_LATENCY_PRECISION_64	64
 #define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
-#define DDL_CURSORA_PRECISION_32	(1<<31)
-#define DDL_CURSORA_PRECISION_16	(0<<31)
+#define DDL_CURSORA_PRECISION_64	(1<<31)
+#define DDL_CURSORA_PRECISION_32	(0<<31)
 #define DDL_CURSORA_SHIFT		24
-#define DDL_SPRITEB_PRECISION_32	(1<<23)
-#define DDL_SPRITEB_PRECISION_16	(0<<23)
+#define DDL_SPRITEB_PRECISION_64	(1<<23)
+#define DDL_SPRITEB_PRECISION_32	(0<<23)
 #define DDL_SPRITEB_SHIFT		16
-#define DDL_SPRITEA_PRECISION_32	(1<<15)
-#define DDL_SPRITEA_PRECISION_16	(0<<15)
+#define DDL_SPRITEA_PRECISION_64	(1<<15)
+#define DDL_SPRITEA_PRECISION_32	(0<<15)
 #define DDL_SPRITEA_SHIFT		8
-#define DDL_PLANEA_PRECISION_32		(1<<7)
-#define DDL_PLANEA_PRECISION_16		(0<<7)
+#define DDL_PLANEA_PRECISION_64		(1<<7)
+#define DDL_PLANEA_PRECISION_32		(0<<7)
 #define DDL_PLANEA_SHIFT		0
 
 #define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
-#define DDL_CURSORB_PRECISION_32	(1<<31)
-#define DDL_CURSORB_PRECISION_16	(0<<31)
+#define DDL_CURSORB_PRECISION_64	(1<<31)
+#define DDL_CURSORB_PRECISION_32	(0<<31)
 #define DDL_CURSORB_SHIFT		24
-#define DDL_SPRITED_PRECISION_32	(1<<23)
-#define DDL_SPRITED_PRECISION_16	(0<<23)
+#define DDL_SPRITED_PRECISION_64	(1<<23)
+#define DDL_SPRITED_PRECISION_32	(0<<23)
 #define DDL_SPRITED_SHIFT		16
-#define DDL_SPRITEC_PRECISION_32	(1<<15)
-#define DDL_SPRITEC_PRECISION_16	(0<<15)
+#define DDL_SPRITEC_PRECISION_64	(1<<15)
+#define DDL_SPRITEC_PRECISION_32	(0<<15)
 #define DDL_SPRITEC_SHIFT		8
-#define DDL_PLANEB_PRECISION_32		(1<<7)
-#define DDL_PLANEB_PRECISION_16		(0<<7)
+#define DDL_PLANEB_PRECISION_64		(1<<7)
+#define DDL_PLANEB_PRECISION_32		(0<<7)
 #define DDL_PLANEB_SHIFT		0
 
 #define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
-#define DDL_CURSORC_PRECISION_32	(1<<31)
-#define DDL_CURSORC_PRECISION_16	(0<<31)
+#define DDL_CURSORC_PRECISION_64	(1<<31)
+#define DDL_CURSORC_PRECISION_32	(0<<31)
 #define DDL_CURSORC_SHIFT		24
-#define DDL_SPRITEF_PRECISION_32	(1<<23)
-#define DDL_SPRITEF_PRECISION_16	(0<<23)
+#define DDL_SPRITEF_PRECISION_64	(1<<23)
+#define DDL_SPRITEF_PRECISION_32	(0<<23)
 #define DDL_SPRITEF_SHIFT		16
-#define DDL_SPRITEE_PRECISION_32	(1<<15)
-#define DDL_SPRITEE_PRECISION_16	(0<<15)
+#define DDL_SPRITEE_PRECISION_64	(1<<15)
+#define DDL_SPRITEE_PRECISION_32	(0<<15)
 #define DDL_SPRITEE_SHIFT		8
-#define DDL_PLANEC_PRECISION_32		(1<<7)
-#define DDL_PLANEC_PRECISION_16		(0<<7)
+#define DDL_PLANEC_PRECISION_64		(1<<7)
+#define DDL_PLANEC_PRECISION_32		(0<<7)
 #define DDL_PLANEC_SHIFT		0
 
 /* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 55f3e6b..9413184 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
 
 	entries = (clock / 1000) * pixel_size;
 	*plane_prec_mult = (entries > 256) ?
-		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
 	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
 						     pixel_size);
 
 	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
 	*cursor_prec_mult = (entries > 256) ?
-		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
 	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
 
 	return true;
@@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
 	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
 				      &cursor_prec_mult, &cursora_dl)) {
 		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
+			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
 		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
+			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
 
 		I915_WRITE(VLV_DDL1, cursora_prec |
 				(cursora_dl << DDL_CURSORA_SHIFT) |
@@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
 	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
 				      &cursor_prec_mult, &cursorb_dl)) {
 		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
+			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
 		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
+			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
 
 		I915_WRITE(VLV_DDL2, cursorb_prec |
 				(cursorb_dl << DDL_CURSORB_SHIFT) |
-- 
1.8.5.5

[PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDL registers can hold 7bit numbers. Make the most of those seven
bits by adjusting the threshold where we switch between the 64 vs. 32
precision multipliers.

Also we compute 'entries' to make the decision about precision, and then
we recompute the same value to calculate the actual drain latency. Just
use the already calculate 'entries' there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9413184..3aa7959 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
 	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */
 
 	entries = (clock / 1000) * pixel_size;
-	*plane_prec_mult = (entries > 256) ?
+	*plane_prec_mult = (entries > 128) ?
 		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
-	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
-						     pixel_size);
+	*plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
 
 	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
-	*cursor_prec_mult = (entries > 256) ?
+	*cursor_prec_mult = (entries > 128) ?
 		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
-	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
+	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
 
 	return true;
 }
-- 
1.8.5.5

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[PATCH 25/40] drm/i915: Fill out the FWx watermark register defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add defines for all the watermark registers on modernish gmch platforms.

VLV has increased the number of bits available for certain watermaks so
expand the masks appropriately. Also vlv and chv have added some extra
FW registers.

Not sure what happened on chv because a new register called FW9 is now
at the offset where FW7 was on vlv, while FW7 and FW8 (another new
register) have been moved off somewhere else. Oh well, well just need
two defines for FW7 then.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_pm.c |  11 ++--
 2 files changed, 130 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ab5a03..9fab647 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3884,28 +3884,136 @@ enum punit_power_well {
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
+/* pnv/gen4/g4x/vlv/chv */
 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
-#define   DSPFW_SR_SHIFT	23
-#define   DSPFW_SR_MASK		(0x1ff<<23)
-#define   DSPFW_CURSORB_SHIFT	16
-#define   DSPFW_CURSORB_MASK	(0x3f<<16)
-#define   DSPFW_PLANEB_SHIFT	8
-#define   DSPFW_PLANEB_MASK	(0x7f<<8)
-#define   DSPFW_PLANEA_MASK	(0x7f)
+#define   DSPFW_SR_SHIFT		23
+#define   DSPFW_SR_MASK			(0x1ff<<23)
+#define   DSPFW_CURSORB_SHIFT		16
+#define   DSPFW_CURSORB_MASK		(0x3f<<16)
+#define   DSPFW_PLANEB_SHIFT		8
+#define   DSPFW_PLANEB_MASK		(0x7f<<8)
+#define   DSPFW_PLANEB_MASK_VLV		(0xff<<8) /* vlv/chv */
+#define   DSPFW_PLANEA_SHIFT		0
+#define   DSPFW_PLANEA_MASK		(0x7f<<0)
+#define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
 #define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
-#define   DSPFW_CURSORA_MASK	0x00003f00
-#define   DSPFW_CURSORA_SHIFT	8
-#define   DSPFW_PLANEC_MASK	(0x7f)
+#define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
+#define   DSPFW_FBC_SR_SHIFT		28
+#define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
+#define   DSPFW_FBC_HPLL_SR_SHIFT	24
+#define   DSPFW_FBC_HPLL_SR_MASK	(0xf<<24) /* g4x */
+#define   DSPFW_SPRITEB_SHIFT		(16)
+#define   DSPFW_SPRITEB_MASK		(0x7f<<16) /* g4x */
+#define   DSPFW_SPRITEB_MASK_VLV	(0xff<<16) /* vlv/chv */
+#define   DSPFW_CURSORA_SHIFT		8
+#define   DSPFW_CURSORA_MASK		(0x3f<<8)
+#define   DSPFW_PLANEC_SHIFT_OLD	0
+#define   DSPFW_PLANEC_MASK_OLD		(0x7f<<0) /* pre-gen4 sprite C */
+#define   DSPFW_SPRITEA_SHIFT		0
+#define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
+#define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
 #define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
-#define   DSPFW_HPLL_SR_EN	(1<<31)
-#define   DSPFW_CURSOR_SR_SHIFT	24
+#define   DSPFW_HPLL_SR_EN		(1<<31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
+#define   DSPFW_CURSOR_SR_SHIFT		24
 #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
 #define   DSPFW_HPLL_CURSOR_SHIFT	16
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
-#define   DSPFW_HPLL_SR_MASK		(0x1ff)
-#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
-#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
+#define   DSPFW_HPLL_SR_SHIFT		0
+#define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
+
+/* vlv/chv */
+#define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
+#define   DSPFW_SPRITEB_WM1_SHIFT	16
+#define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
+#define   DSPFW_CURSORA_WM1_SHIFT	8
+#define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
+#define   DSPFW_SPRITEA_WM1_SHIFT	0
+#define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
+#define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
+#define   DSPFW_PLANEB_WM1_SHIFT	24
+#define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
+#define   DSPFW_PLANEA_WM1_SHIFT	16
+#define   DSPFW_PLANEA_WM1_MASK		(0xff<<16)
+#define   DSPFW_CURSORB_WM1_SHIFT	8
+#define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
+#define   DSPFW_CURSOR_SR_WM1_SHIFT	0
+#define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
+#define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
+#define   DSPFW_SR_WM1_SHIFT		0
+#define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
+#define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
+#define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
+#define   DSPFW_SPRITED_WM1_SHIFT	24
+#define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
+#define   DSPFW_SPRITED_SHIFT		16
+#define   DSPFW_SPRITED_MASK		(0xff<<16)
+#define   DSPFW_SPRITEC_WM1_SHIFT	8
+#define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
+#define   DSPFW_SPRITEC_SHIFT		0
+#define   DSPFW_SPRITEC_MASK		(0xff<<0)
+#define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
+#define   DSPFW_SPRITEF_WM1_SHIFT	24
+#define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
+#define   DSPFW_SPRITEF_SHIFT		16
+#define   DSPFW_SPRITEF_MASK		(0xff<<16)
+#define   DSPFW_SPRITEE_WM1_SHIFT	8
+#define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
+#define   DSPFW_SPRITEE_SHIFT		0
+#define   DSPFW_SPRITEE_MASK		(0xff<<0)
+#define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
+#define   DSPFW_PLANEC_WM1_SHIFT	24
+#define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
+#define   DSPFW_PLANEC_SHIFT		16
+#define   DSPFW_PLANEC_MASK		(0xff<<16)
+#define   DSPFW_CURSORC_WM1_SHIFT	8
+#define   DSPFW_CURSORC_WM1_MASK	(0x3f<<16)
+#define   DSPFW_CURSORC_SHIFT		0
+#define   DSPFW_CURSORC_MASK		(0x3f<<0)
+
+/* vlv/chv high order bits */
+#define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
+#define   DSPFW_SR_HI_SHIFT		24
+#define   DSPFW_SR_HI_MASK		(1<<24)
+#define   DSPFW_SPRITEF_HI_SHIFT	23
+#define   DSPFW_SPRITEF_HI_MASK		(1<<23)
+#define   DSPFW_SPRITEE_HI_SHIFT	22
+#define   DSPFW_SPRITEE_HI_MASK		(1<<22)
+#define   DSPFW_PLANEC_HI_SHIFT		21
+#define   DSPFW_PLANEC_HI_MASK		(1<<21)
+#define   DSPFW_SPRITED_HI_SHIFT	20
+#define   DSPFW_SPRITED_HI_MASK		(1<<20)
+#define   DSPFW_SPRITEC_HI_SHIFT	16
+#define   DSPFW_SPRITEC_HI_MASK		(1<<16)
+#define   DSPFW_PLANEB_HI_SHIFT		12
+#define   DSPFW_PLANEB_HI_MASK		(1<<12)
+#define   DSPFW_SPRITEB_HI_SHIFT	8
+#define   DSPFW_SPRITEB_HI_MASK		(1<<8)
+#define   DSPFW_SPRITEA_HI_SHIFT	4
+#define   DSPFW_SPRITEA_HI_MASK		(1<<4)
+#define   DSPFW_PLANEA_HI_SHIFT		0
+#define   DSPFW_PLANEA_HI_MASK		(1<<0)
+#define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70064)
+#define   DSPFW_SR_WM1_HI_SHIFT		24
+#define   DSPFW_SR_WM1_HI_MASK		(1<<24)
+#define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
+#define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
+#define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
+#define   DSPFW_SPRITEE_WM1_HI_MASK	(1<<22)
+#define   DSPFW_PLANEC_WM1_HI_SHIFT	21
+#define   DSPFW_PLANEC_WM1_HI_MASK	(1<<21)
+#define   DSPFW_SPRITED_WM1_HI_SHIFT	20
+#define   DSPFW_SPRITED_WM1_HI_MASK	(1<<20)
+#define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
+#define   DSPFW_SPRITEC_WM1_HI_MASK	(1<<16)
+#define   DSPFW_PLANEB_WM1_HI_SHIFT	12
+#define   DSPFW_PLANEB_WM1_HI_MASK	(1<<12)
+#define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
+#define   DSPFW_SPRITEB_WM1_HI_MASK	(1<<8)
+#define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
+#define   DSPFW_SPRITEA_WM1_HI_MASK	(1<<4)
+#define   DSPFW_PLANEA_WM1_HI_SHIFT	0
+#define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3aa7959..dc858b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1360,7 +1360,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		   (plane_sr << DSPFW_SR_SHIFT) |
 		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   planea_wm);
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
 	I915_WRITE(DSPFW2,
 		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 		   (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1412,7 +1412,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
 		   (plane_sr << DSPFW_SR_SHIFT) |
 		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   planea_wm);
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
 	I915_WRITE(DSPFW2,
 		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 		   (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1484,8 +1484,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
 
 	/* 965 has limitations... */
 	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
-		   (8 << 16) | (8 << 8) | (8 << 0));
-	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+		   (8 << DSPFW_CURSORB_SHIFT) |
+		   (8 << DSPFW_PLANEB_SHIFT) |
+		   (8 << DSPFW_PLANEA_SHIFT));
+	I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
+		   (8 << DSPFW_PLANEC_SHIFT_OLD));
 	/* update cursor SR watermark */
 	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
-- 
1.8.5.5

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[PATCH 26/40] drm/i915: Parametrize VLV_DDL registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++-------------------------------
 drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++---------------------
 2 files changed, 36 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fab647..60dd19c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4018,47 +4018,19 @@ enum punit_power_well {
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
 #define DRAIN_LATENCY_PRECISION_64	64
-#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
-#define DDL_CURSORA_PRECISION_64	(1<<31)
-#define DDL_CURSORA_PRECISION_32	(0<<31)
-#define DDL_CURSORA_SHIFT		24
-#define DDL_SPRITEB_PRECISION_64	(1<<23)
-#define DDL_SPRITEB_PRECISION_32	(0<<23)
-#define DDL_SPRITEB_SHIFT		16
-#define DDL_SPRITEA_PRECISION_64	(1<<15)
-#define DDL_SPRITEA_PRECISION_32	(0<<15)
-#define DDL_SPRITEA_SHIFT		8
-#define DDL_PLANEA_PRECISION_64		(1<<7)
-#define DDL_PLANEA_PRECISION_32		(0<<7)
-#define DDL_PLANEA_SHIFT		0
-
-#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
-#define DDL_CURSORB_PRECISION_64	(1<<31)
-#define DDL_CURSORB_PRECISION_32	(0<<31)
-#define DDL_CURSORB_SHIFT		24
-#define DDL_SPRITED_PRECISION_64	(1<<23)
-#define DDL_SPRITED_PRECISION_32	(0<<23)
-#define DDL_SPRITED_SHIFT		16
-#define DDL_SPRITEC_PRECISION_64	(1<<15)
-#define DDL_SPRITEC_PRECISION_32	(0<<15)
-#define DDL_SPRITEC_SHIFT		8
-#define DDL_PLANEB_PRECISION_64		(1<<7)
-#define DDL_PLANEB_PRECISION_32		(0<<7)
-#define DDL_PLANEB_SHIFT		0
-
-#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
-#define DDL_CURSORC_PRECISION_64	(1<<31)
-#define DDL_CURSORC_PRECISION_32	(0<<31)
-#define DDL_CURSORC_SHIFT		24
-#define DDL_SPRITEF_PRECISION_64	(1<<23)
-#define DDL_SPRITEF_PRECISION_32	(0<<23)
-#define DDL_SPRITEF_SHIFT		16
-#define DDL_SPRITEE_PRECISION_64	(1<<15)
-#define DDL_SPRITEE_PRECISION_32	(0<<15)
-#define DDL_SPRITEE_SHIFT		8
-#define DDL_PLANEC_PRECISION_64		(1<<7)
-#define DDL_PLANEC_PRECISION_32		(0<<7)
-#define DDL_PLANEC_SHIFT		0
+#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
+#define DDL_CURSOR_PRECISION_64		(1<<31)
+#define DDL_CURSOR_PRECISION_32		(0<<31)
+#define DDL_CURSOR_SHIFT		24
+#define DDL_SPRITE1_PRECISION_64	(1<<23)
+#define DDL_SPRITE1_PRECISION_32	(0<<23)
+#define DDL_SPRITE1_SHIFT		16
+#define DDL_SPRITE0_PRECISION_64	(1<<15)
+#define DDL_SPRITE0_PRECISION_32	(0<<15)
+#define DDL_SPRITE0_SHIFT		8
+#define DDL_PLANE_PRECISION_64		(1<<7)
+#define DDL_PLANE_PRECISION_32		(0<<7)
+#define DDL_PLANE_SHIFT			0
 
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc858b5..f0516a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1275,35 +1275,29 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
 static void vlv_update_drain_latency(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int planea_prec, planea_dl, planeb_prec, planeb_dl;
-	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
-	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
-							either 16 or 32 */
-
-	/* For plane A, Cursor A */
-	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
-				      &cursor_prec_mult, &cursora_dl)) {
-		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
-		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
-
-		I915_WRITE(VLV_DDL1, cursora_prec |
-				(cursora_dl << DDL_CURSORA_SHIFT) |
-				planea_prec | planea_dl);
-	}
-
-	/* For plane B, Cursor B */
-	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
-				      &cursor_prec_mult, &cursorb_dl)) {
-		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
-		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
-
-		I915_WRITE(VLV_DDL2, cursorb_prec |
-				(cursorb_dl << DDL_CURSORB_SHIFT) |
-				planeb_prec | planeb_dl);
+	enum pipe pipe;
+
+	for_each_pipe(pipe) {
+		int plane_prec, plane_dl;
+		int cursor_prec, cursor_dl;
+		int plane_prec_mult, cursor_prec_mult;
+
+		if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
+					       &cursor_prec_mult, &cursor_dl))
+			continue;
+
+		/*
+		 * FIXME CHV spec still lists 16 and 32 as the precision
+		 * values. Need to figure out if spec is outdated or what.
+		 */
+		cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+			DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
+		plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+			DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
+
+		I915_WRITE(VLV_DDL(pipe), cursor_prec |
+			   (cursor_dl << DDL_CURSOR_SHIFT) |
+			   plane_prec | (plane_dl << DDL_PLANE_SHIFT));
 	}
 }
 
-- 
1.8.5.5

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[PATCH 27/40] drm/i915: Split a few long debug prints

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split some WM debug prints to multiple lines. This shouldn't hurt
grappability since the important part is at the start and the rest
is just repeated stuff for each pipe.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f0516a7..cb0b4b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1345,7 +1345,8 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		plane_sr = cursor_sr = 0;
 	}
 
-	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
+		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 		      planea_wm, cursora_wm,
 		      planeb_wm, cursorb_wm,
 		      plane_sr, cursor_sr);
@@ -1397,7 +1398,8 @@ static void g4x_update_wm(struct drm_crtc *crtc)
 		plane_sr = cursor_sr = 0;
 	}
 
-	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
+		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 		      planea_wm, cursora_wm,
 		      planeb_wm, cursorb_wm,
 		      plane_sr, cursor_sr);
-- 
1.8.5.5

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[PATCH 28/40] drm/i915: Add cherryview_update_wm()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 77 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 76 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cb0b4b4..346dced 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1364,6 +1364,81 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
+static void cherryview_update_wm(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	static const int sr_latency_ns = 12000;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_wm, planeb_wm, planec_wm;
+	int cursora_wm, cursorb_wm, cursorc_wm;
+	int plane_sr, cursor_sr;
+	int ignore_plane_sr, ignore_cursor_sr;
+	unsigned int enabled = 0;
+
+	vlv_update_drain_latency(dev);
+
+	if (g4x_compute_wm0(dev, PIPE_A,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planea_wm, &cursora_wm))
+		enabled |= 1 << PIPE_A;
+
+	if (g4x_compute_wm0(dev, PIPE_B,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planeb_wm, &cursorb_wm))
+		enabled |= 1 << PIPE_B;
+
+	if (g4x_compute_wm0(dev, PIPE_C,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planec_wm, &cursorc_wm))
+		enabled |= 1 << PIPE_C;
+
+	if (single_plane_enabled(enabled) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &plane_sr, &ignore_cursor_sr) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     2*sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &ignore_plane_sr, &cursor_sr)) {
+		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
+	} else {
+		I915_WRITE(FW_BLC_SELF_VLV,
+			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+		plane_sr = cursor_sr = 0;
+	}
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
+		      "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
+		      "SR: plane=%d, cursor=%d\n",
+		      planea_wm, cursora_wm,
+		      planeb_wm, cursorb_wm,
+		      planec_wm, cursorc_wm,
+		      plane_sr, cursor_sr);
+
+	I915_WRITE(DSPFW1,
+		   (plane_sr << DSPFW_SR_SHIFT) |
+		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
+		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
+	I915_WRITE(DSPFW2,
+		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
+		   (cursora_wm << DSPFW_CURSORA_SHIFT));
+	I915_WRITE(DSPFW3,
+		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
+		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+	I915_WRITE(DSPFW9_CHV,
+		   (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
+					      DSPFW_CURSORC_MASK)) |
+		   (planec_wm << DSPFW_PLANEC_SHIFT) |
+		   (cursorc_wm << DSPFW_CURSORC_SHIFT));
+}
+
 static void g4x_update_wm(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -7046,7 +7121,7 @@ void intel_init_pm(struct drm_device *dev)
 		else if (INTEL_INFO(dev)->gen == 8)
 			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
 	} else if (IS_CHERRYVIEW(dev)) {
-		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.update_wm = cherryview_update_wm;
 		dev_priv->display.init_clock_gating =
 			cherryview_init_clock_gating;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.8.5.5

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[PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

[ville.syrjala]

From: Kenneth Graunke <kenneth@whitecape.org>

We'll want to reuse this for a workaround.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 36 ++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2faef26..97796b1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
 }
 
 static int
+gen8_emit_pipe_control(struct intel_engine_cs *ring,
+		       u32 flags, u32 scratch_addr)
+{
+	int ret;
+
+	ret = intel_ring_begin(ring, 6);
+	if (ret)
+		return ret;
+
+	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+	intel_ring_emit(ring, flags);
+	intel_ring_emit(ring, scratch_addr);
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, 0);
+	intel_ring_emit(ring, 0);
+	intel_ring_advance(ring);
+
+	return 0;
+}
+
+static int
 gen8_render_ring_flush(struct intel_engine_cs *ring,
 		       u32 invalidate_domains, u32 flush_domains)
 {
@@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 	}
 
-	ret = intel_ring_begin(ring, 6);
-	if (ret)
-		return ret;
-
-	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
-	intel_ring_emit(ring, flags);
-	intel_ring_emit(ring, scratch_addr);
-	intel_ring_emit(ring, 0);
-	intel_ring_emit(ring, 0);
-	intel_ring_emit(ring, 0);
-	intel_ring_advance(ring);
-
-	return 0;
-
+	return gen8_emit_pipe_control(ring, flags, scratch_addr);
 }
 
 static void ring_write_tail(struct intel_engine_cs *ring,
-- 
1.8.5.5

[PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

[ville.syrjala]

From: Kenneth Graunke <kenneth@whitecape.org>

On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.

Documented on the BSpec 3D workarounds page.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[vsyrjala: add chv w/a note too]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 97796b1..ceb1295 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -424,6 +424,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
+		ret = gen8_emit_pipe_control(ring,
+					     PIPE_CONTROL_CS_STALL |
+					     PIPE_CONTROL_STALL_AT_SCOREBOARD,
+					     0);
+		if (ret)
+			return ret;
 	}
 
 	return gen8_emit_pipe_control(ring, flags, scratch_addr);
-- 
1.8.5.5

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[PATCH 31/40] drm/i916: Init chv workarounds at render ring init

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

My bsw is an unhappy camper if we delay the workaround init until
init_clock_gating(). Move a bunch of it to the render ring init.

FIXME: need to do this for all platforms since some of the registers
       also get clobbered at reset. Just need to figure out which
       registers those actually are. This patch is based on a
       slightly educated guess, but verifying on actual hw would
       be a good idea. Also should maybe move the init_clock_gating
       earlier too since we set up a bunch of clock gating stuff
       there that might be important for a properly working GT.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c         | 40 +++++++--------------------------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 40 +++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 346dced..158c3f5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5720,6 +5720,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * in the reporting of vblank events.
 	 */
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
+
+	/* WaDisableDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void cherryview_init_clock_gating(struct drm_device *dev)
@@ -5730,49 +5734,21 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 
-	/* WaDisablePartialInstShootdown:chv */
-	I915_WRITE(GEN8_ROW_CHICKEN,
-		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
-
-	/* WaDisableThreadStallDopClockGating:chv */
-	I915_WRITE(GEN8_ROW_CHICKEN,
-		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
-
-	/* WaVSRefCountFullforceMissDisable:chv */
-	/* WaDSRefCountFullforceMissDisable:chv */
-	I915_WRITE(GEN7_FF_THREAD_MODE,
-		   I915_READ(GEN7_FF_THREAD_MODE) &
-		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
-
-	/* WaDisableSemaphoreAndSyncFlipWait:chv */
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-
 	/* WaDisableCSUnitClockGating:chv */
 	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
 		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 
+	/* WaDisableDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
+
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
-	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-	I915_WRITE(HALF_SLICE_CHICKEN3,
-		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
-
 	/* WaDisableGunitClockGating:chv (pre-production hw) */
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
 		   GINT_DIS);
-
-	/* WaDisableFfDopClockGating:chv (pre-production hw) */
-	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
-		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
-
-	/* WaDisableDopClockGating:chv (pre-production hw) */
-	I915_WRITE(GEN7_ROW_CHICKEN2,
-		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ceb1295..9e81c28 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -615,6 +615,43 @@ err:
 	return ret;
 }
 
+static void cherryview_init_workarounds(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* WaDisablePartialInstShootdown:chv */
+	I915_WRITE(GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
+
+	/* WaDisableThreadStallDopClockGating:chv */
+	I915_WRITE(GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+
+	/* WaVSRefCountFullforceMissDisable:chv */
+	/* WaDSRefCountFullforceMissDisable:chv */
+	I915_WRITE(GEN7_FF_THREAD_MODE,
+		   I915_READ(GEN7_FF_THREAD_MODE) &
+		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
+
+	/* WaDisableSemaphoreAndSyncFlipWait:chv */
+	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+
+	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
+	I915_WRITE(HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+
+	/* WaDisableFfDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
+
+	/* WaDisableDopClockGating:chv (pre-production hw) */
+	I915_WRITE(GEN7_ROW_CHICKEN2,
+		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
+}
+
 static int init_render_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -670,6 +707,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
 	if (HAS_L3_DPF(dev))
 		I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 
+	if (IS_CHERRYVIEW(dev))
+		cherryview_init_workarounds(dev);
+
 	return ret;
 }
 
-- 
1.8.5.5

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[PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It looks like frobbing the cmnreset line on pne PHY disturbs the other
PHY on chv. The result is a black screen. On HDMI it's just a flash of
black, but DP usually falls over and can't get back up.

As a workaround set up the power domains so that both common lane
wells power up and down together. I also tried leaving the cmnreset
deasserted even the if the power well goes down but that didn't seem
acceptable to the PHY.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 158c3f5..879d14c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6776,13 +6776,23 @@ static struct i915_power_well chv_power_wells[] = {
 #endif
 	{
 		.name = "dpio-common-bc",
-		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+		/*
+		 * XXX: cmnreset for one PHY seems to disturb the other.
+		 * As a workaround keep both powered on at the same
+		 * time for now.
+		 */
+		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
 		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
 		.ops = &chv_dpio_cmn_power_well_ops,
 	},
 	{
 		.name = "dpio-common-d",
-		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+		/*
+		 * XXX: cmnreset for one PHY seems to disturb the other.
+		 * As a workaround keep both powered on at the same
+		 * time for now.
+		 */
+		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
 		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
 		.ops = &chv_dpio_cmn_power_well_ops,
 	},
-- 
1.8.5.5

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[PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the semi-funky cmnlane assert/deassert macros with something a
bit more conventional. Also protect the macro arguments properly (also
for  PHY_POWERGOOD()).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 7 ++-----
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 60dd19c..85b59c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1717,12 +1717,9 @@ enum punit_power_well {
 #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
-#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
-				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
-#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
-				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
+#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
-#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
+#define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
 
 /*
  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 879d14c..f193d95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6280,8 +6280,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
 		DRM_ERROR("Display PHY %d is not power up\n", phy);
 
-	I915_WRITE(DISPLAY_PHY_CONTROL,
-		   PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
+	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
+		   PHY_COM_LANE_RESET_DEASSERT(phy));
 }
 
 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
@@ -6301,8 +6301,8 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 		assert_pll_disabled(dev_priv, PIPE_C);
 	}
 
-	I915_WRITE(DISPLAY_PHY_CONTROL,
-		   PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
+	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
+		   ~PHY_COM_LANE_RESET_DEASSERT(phy));
 
 	vlv_set_power_well(dev_priv, power_well, false);
 }
-- 
1.8.5.5

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[PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV supports DP training pattern 3. Add the required stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85b59c4..8debe61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3515,6 +3515,8 @@ enum punit_power_well {
 #define   DP_LINK_TRAIN_OFF		(3 << 28)
 #define   DP_LINK_TRAIN_MASK		(3 << 28)
 #define   DP_LINK_TRAIN_SHIFT		28
+#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
+#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
 
 /* CPT Link training mode */
 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 739dc43..a825ff1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 		}
 
 	} else {
-		*DP &= ~DP_LINK_TRAIN_MASK;
+		if (IS_CHERRYVIEW(dev))
+			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
+		else
+			*DP &= ~DP_LINK_TRAIN_MASK;
 
 		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
 		case DP_TRAINING_PATTERN_DISABLE:
@@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 			*DP |= DP_LINK_TRAIN_PAT_2;
 			break;
 		case DP_TRAINING_PATTERN_3:
-			DRM_ERROR("DP training pattern 3 not supported\n");
-			*DP |= DP_LINK_TRAIN_PAT_2;
+			if (IS_CHERRYVIEW(dev)) {
+				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
+			} else {
+				DRM_ERROR("DP training pattern 3 not supported\n");
+				*DP |= DP_LINK_TRAIN_PAT_2;
+			}
 			break;
 		}
 	}
@@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
 	} else {
-		DP &= ~DP_LINK_TRAIN_MASK;
+		if (IS_CHERRYVIEW(dev))
+			DP &= ~DP_LINK_TRAIN_MASK_CHV;
+		else
+			DP &= ~DP_LINK_TRAIN_MASK;
 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
 	}
 	POSTING_READ(intel_dp->output_reg);
-- 
1.8.5.5

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[PATCH 35/40] drm/i915: Fix vdd locking

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we do all kinds vdd frobbing from both the modeset and
->detect. ->detect isn't protected by the connection_mutex as the
current locking stuff seems to expect. Switch it all over the
mode_config.mutex instead since we hold that in both places.

In the long run we'll maybe need a private vdd mutex or somehting.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a825ff1..03ee9e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1192,7 +1192,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 	u32 pp;
 	u32 pp_stat_reg, pp_ctrl_reg;
 
-	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 
 	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
 		struct intel_digital_port *intel_dig_port =
@@ -1229,9 +1229,9 @@ static void edp_panel_vdd_work(struct work_struct *__work)
 						 struct intel_dp, panel_vdd_work);
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
-	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+	mutex_lock(&dev->mode_config.mutex);
 	edp_panel_vdd_off_sync(intel_dp);
-	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
 }
 
 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
-- 
1.8.5.5

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[PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Allow calling the vdd off functions when vdd is already off. Makes
things simpler later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03ee9e8..65ab54c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1239,7 +1239,11 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 	if (!is_edp(intel_dp))
 		return;
 
-	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
+	if (!edp_have_panel_vdd(intel_dp))
+		return;
+
+	if (!intel_dp->want_panel_vdd)
+		return;
 
 	intel_dp->want_panel_vdd = false;
 
-- 
1.8.5.5

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[PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When switching from one pipe to another, the power sequencer of the new
pipe seems to need a bit of kicking to lock into the port. Even the vdd
force bit doesn't work before the power sequencer has been sufficiently
kicked, so this must be done even before any AUX transactions.

This sequence has been found to do the trick:
1) enable port with idle pattern
2) enable the power sequencer
3) proceed with link training

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 65ab54c..07b0320 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void intel_edp_init_train(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (!is_edp(intel_dp))
+		return;
+
+	/*
+	 * Need to enable the port with idle pattern to allow the power
+	 * sequencer to lock into the port. Otherwise the power sequencer
+	 * (including vdd force bit!) doesn't work on this port.
+	 */
+	if (IS_VALLEYVIEW(dev)) {
+		intel_dp->DP |= DP_PORT_EN;
+
+		if (IS_CHERRYVIEW(dev))
+			intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CHV;
+		else
+			intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
+		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
+
+		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+		POSTING_READ(intel_dp->output_reg);
+	}
+
+	intel_edp_panel_on(intel_dp);
+	edp_panel_vdd_off(intel_dp, true);
+}
+
 static void intel_enable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
 		return;
 
 	intel_edp_panel_vdd_on(intel_dp);
+	intel_edp_init_train(intel_dp);
 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_start_link_train(intel_dp);
-	intel_edp_panel_on(intel_dp);
-	edp_panel_vdd_off(intel_dp, true);
 	intel_dp_complete_link_train(intel_dp);
 	intel_dp_stop_link_train(intel_dp);
 }
-- 
1.8.5.5

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[PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The panel power sequencer locks into the port once used. We need to keep
track wich power sequencers are locked to which ports.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 172 ++++++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_drv.h |   6 ++
 2 files changed, 150 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 07b0320..240bc98 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -292,28 +292,84 @@ static enum pipe
 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct intel_encoder *encoder;
+	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
+	struct edp_power_seq power_seq;
+
+	if (intel_dp->pipe != INVALID_PIPE)
+		return intel_dp->pipe;
+
+	/*
+	 * We don't have power sequencer currently.
+	 * Pick one that's not used by other ports.
+	 */
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
+		struct intel_dp *tmp;
+
+		if (encoder->type != INTEL_OUTPUT_EDP)
+			continue;
+
+		tmp = enc_to_intel_dp(&encoder->base);
+
+		if (tmp->pipe != INVALID_PIPE)
+			pipes &= ~(1 << tmp->pipe);
+	}
+
+	/*
+	 * Didn't find one. This should not happen since there
+	 * are two power sequencers and up two eDP ports.
+	 */
+	if (WARN_ON(pipes == 0))
+		return PIPE_A;
+
+	intel_dp->pipe = ffs(pipes) - 1;
+
+	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
+		      pipe_name(intel_dp->pipe), port_name(intel_dig_port->port));
+
+	/* init power sequencer on this pipe and port */
+	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+						      &power_seq);
+
+	return intel_dp->pipe;
+}
+
+static void
+vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct edp_power_seq power_seq;
 	enum port port = intel_dig_port->port;
 	enum pipe pipe;
 
-	/* modeset should have pipe */
-	if (crtc)
-		return to_intel_crtc(crtc)->pipe;
-
-	/* init time, try to find a pipe with this port selected */
+	/* try to find a pipe with this port selected */
 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 			PANEL_PORT_SELECT_MASK;
-		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
-			return pipe;
-		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
-			return pipe;
+		if ((port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) ||
+		    (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)) {
+			intel_dp->pipe = pipe;
+			break;
+		}
 	}
 
-	/* shrug */
-	return PIPE_A;
+	/* just let vlv_power_sequencer_pipe() pick one when needed */
+	if (intel_dp->pipe == INVALID_PIPE) {
+		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
+			      port_name(port));
+		return;
+	}
+
+	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
+		      port_name(port), pipe_name(intel_dp->pipe));
+
+	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+						      &power_seq);
 }
 
 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
@@ -2088,6 +2144,70 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder)
 	}
 }
 
+static void vlv_steal_power_sequencer(struct drm_device *dev,
+				      enum pipe pipe)
+{
+	struct intel_encoder *encoder;
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
+		struct intel_dp *intel_dp;
+
+		if (encoder->type != INTEL_OUTPUT_EDP)
+			continue;
+
+		intel_dp = enc_to_intel_dp(&encoder->base);
+
+		if (intel_dp->pipe != pipe)
+			continue;
+
+		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
+			      pipe_name(pipe),
+			      port_name(dp_to_dig_port(intel_dp)->port));
+
+		/* make sure vdd is off before we steal it */
+		edp_panel_vdd_off(intel_dp, false);
+
+		intel_dp->pipe = INVALID_PIPE;
+	}
+}
+
+static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	struct drm_device *dev = encoder->base.dev;
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+	struct edp_power_seq power_seq;
+
+	if (intel_dp->pipe == crtc->pipe)
+		return;
+
+	/*
+	 * If another power sequencer was being used on this
+	 * port previosuly make sure to turn off vdd there while
+	 * we still have control of it.
+	 */
+	if (intel_dp->pipe != INVALID_PIPE)
+		edp_panel_vdd_off(intel_dp, false);
+
+	/*
+	 * We may be stealing the power
+	 * sequencer from another port.
+	 */
+	vlv_steal_power_sequencer(dev, crtc->pipe);
+
+	/* now it's all ours */
+	intel_dp->pipe = crtc->pipe;
+
+	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
+		      pipe_name(intel_dp->pipe), port_name(intel_dig_port->port));
+
+	/* init power sequencer on this pipe and port */
+	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+						      &power_seq);
+}
+
 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2097,7 +2217,6 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
-	struct edp_power_seq power_seq;
 	u32 val;
 
 	mutex_lock(&dev_priv->dpio_lock);
@@ -2115,12 +2234,8 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_unlock(&dev_priv->dpio_lock);
 
-	if (is_edp(intel_dp)) {
-		/* init power sequencer on this pipe and port */
-		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
-		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
-							      &power_seq);
-	}
+	if (is_edp(intel_dp))
+		vlv_init_panel_power_sequencer(intel_dp);
 
 	intel_enable_dp(encoder);
 
@@ -2163,7 +2278,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct edp_power_seq power_seq;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
 	enum dpio_channel ch = vlv_dport_to_channel(dport);
@@ -2217,12 +2331,8 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_unlock(&dev_priv->dpio_lock);
 
-	if (is_edp(intel_dp)) {
-		/* init power sequencer on this pipe and port */
-		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
-		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
-							      &power_seq);
-	}
+	if (is_edp(intel_dp))
+		vlv_init_panel_power_sequencer(intel_dp);
 
 	intel_enable_dp(encoder);
 
@@ -4350,6 +4460,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	struct edp_power_seq power_seq = { 0 };
 	int type;
 
+	intel_dp->pipe = INVALID_PIPE;
+
 	/* intel_dp vfuncs */
 	if (IS_VALLEYVIEW(dev))
 		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
@@ -4420,8 +4532,12 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	}
 
 	if (is_edp(intel_dp)) {
-		intel_dp_init_panel_power_timestamps(intel_dp);
-		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+		if (IS_VALLEYVIEW(dev)) {
+			vlv_initial_power_sequencer_setup(intel_dp);
+		} else {
+			intel_dp_init_panel_power_timestamps(intel_dp);
+			intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+		}
 	}
 
 	intel_dp_aux_init(intel_dp, intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0ef04ea..984627c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -542,6 +542,12 @@ struct intel_dp {
 	unsigned long last_power_on;
 	unsigned long last_backlight_off;
 	bool use_tps3;
+	/*
+	 * Pipe whose power sequencer is currently locked into
+	 * this port. Ie. the last pipe that was feeding this
+	 * port. Only relevant on VLV/CHV.
+	 */
+	enum pipe pipe;
 	struct intel_connector *attached_connector;
 
 	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
-- 
1.8.5.5

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[PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When we pick a new power sequencer for the port but we're not doing a
full modeset, the power sequencer may have locked on to another port.
So kick it a bit to make sure it controls the port we want.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 57 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 240bc98..c2b3112 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -288,6 +288,51 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 					      struct intel_dp *intel_dp,
 					      struct edp_power_seq *out);
 
+static void
+vlv_power_sequencer_kick(struct intel_dp *intel_dp,
+			 enum pipe pipe)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t DP;
+
+	/* Preserve the BIOS-computed detected bit. This is
+	 * supposed to be read-only.
+	 */
+	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+	DP |= DP_PORT_WIDTH(intel_dp->lane_count);
+
+	if (!IS_CHERRYVIEW(dev)) {
+		if (pipe == PIPE_B)
+			DP |= DP_PIPEB_SELECT;
+	} else {
+		DP |= DP_PIPE_SELECT_CHV(pipe);
+	}
+
+	/*
+	 * Need to enable the port with idle pattern to allow the power
+	 * sequencer to lock into the port. Otherwise the power sequence
+	 * (including vdd force bit!) doesn't work on this port.
+	 *
+	 * FIXME do we need a clock from the DPLL?
+	 * FIXME and what if the pipe is active, does it matter?
+	 */
+	DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_IDLE;
+
+	I915_WRITE(intel_dp->output_reg, DP);
+	POSTING_READ(intel_dp->output_reg);
+
+	intel_edp_panel_vdd_on(intel_dp);
+	intel_edp_panel_on(intel_dp);
+	intel_edp_panel_off(intel_dp);
+
+	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
+	POSTING_READ(intel_dp->output_reg);
+	msleep(intel_dp->panel_power_down_delay);
+}
+
 static enum pipe
 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 {
@@ -333,6 +378,15 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
 						      &power_seq);
 
+	/*
+	 * Even vdd force doesn't work until we've made
+	 * the power sequencer lock in on the port.
+	 */
+	DRM_DEBUG_KMS("kicking pipe %c power sequencer\n",
+		      pipe_name(intel_dp->pipe));
+
+	vlv_power_sequencer_kick(intel_dp, intel_dp->pipe);
+
 	return intel_dp->pipe;
 }
 
@@ -370,6 +424,9 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
 	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
 						      &power_seq);
+
+	/* kick it just in case someone left it in a stuck state */
+	vlv_power_sequencer_kick(intel_dp, intel_dp->pipe);
 }
 
 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
-- 
1.8.5.5

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[PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In case the pipe's power sequencer has been locked to another port, we
need to kick it to make it unstuck. Otherwise it will prevent the port
from starting up even if it's a regular DP port and not eDP.

We can't use the regular panel power sequencer function on a DP port,
so add a some functions that allow us to do that.

FIXME: refactor things so that code duplication could be avoided

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 149 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 148 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c2b3112..3e04147 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2123,14 +2123,161 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpio_lock);
 }
 
+static void vlv_panel_on(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp;
+	u32 pp_ctrl_reg;
+
+	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
+
+	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+	pp = ironlake_get_pp_control(intel_dp);
+	pp |= POWER_TARGET_ON | PANEL_POWER_RESET;
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
+
+	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
+}
+
+static void vlv_panel_off(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 pp;
+	u32 pp_ctrl_reg;
+
+	pp = ironlake_get_pp_control(intel_dp);
+	/* We need to switch off panel power _and_ force vdd, for otherwise some
+	 * panels get very unhappy and cease to work. */
+	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
+		EDP_BLC_ENABLE);
+
+	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+
+	I915_WRITE(pp_ctrl_reg, pp);
+	POSTING_READ(pp_ctrl_reg);
+
+	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
+}
+
+static void
+vlv_kick_power_seqeuencer_for_dp(struct intel_dp *intel_dp,
+				 enum pipe pipe)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t DP;
+
+	intel_dp->pipe = pipe;
+
+	/* Preserve the BIOS-computed detected bit. This is
+	 * supposed to be read-only.
+	 */
+	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
+	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+	DP |= DP_PORT_WIDTH(1);
+
+	if (!IS_CHERRYVIEW(dev)) {
+		if (pipe == PIPE_B)
+			DP |= DP_PIPEB_SELECT;
+	} else {
+		DP |= DP_PIPE_SELECT_CHV(pipe);
+	}
+
+	/*
+	 * Need to enable the port with idle pattern to allow the power
+	 * sequencer to lock into the port. Otherwise the power sequencer
+	 * (including vdd force bit!) doesn't work on this port.
+	 *
+	 * FIXME do we need a clock from the DPLL?
+	 * FIXME and what if the pipe is active, does it matter?
+	 */
+	DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_IDLE;
+
+	I915_WRITE(intel_dp->output_reg, DP);
+	POSTING_READ(intel_dp->output_reg);
+
+	vlv_panel_on(intel_dp);
+	vlv_panel_off(intel_dp);
+
+	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
+	POSTING_READ(intel_dp->output_reg);
+
+	intel_dp->pipe = INVALID_PIPE;
+}
+
+static void vlv_unstuck_power_sequencer(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
+	bool need_kick = false;
+
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
+		struct intel_dp *tmp;
+
+		if (encoder->type != INTEL_OUTPUT_EDP)
+			continue;
+
+		tmp = enc_to_intel_dp(&encoder->base);
+
+		if (tmp->pipe != pipe)
+			continue;
+
+		DRM_DEBUG_KMS("pipe %c power sequencer previously in use on port %c\n",
+			      pipe_name(pipe),
+			      port_name(dp_to_dig_port(tmp)->port));
+
+		/*
+		 * Turn off vdd on the other port before we kick
+		 * the power sequencer and make it lock on to this
+		 * port.
+		 */
+		edp_panel_vdd_off(tmp, false);
+		tmp->pipe = INVALID_PIPE;
+
+		need_kick = true;
+	}
+
+	if (!need_kick)
+		return;
+
+	DRM_DEBUG_KMS("kicking pipe %c power sequencer\n",
+		      pipe_name(pipe));
+
+	/* just the port select and ref divider seem appropriate here */
+	I915_WRITE(VLV_PIPE_PP_ON_DELAYS(pipe),
+		   dp_to_dig_port(intel_dp)->port == PORT_B ?
+		   PANEL_PORT_SELECT_DPB_VLV : PANEL_PORT_SELECT_DPC_VLV);
+	I915_WRITE(VLV_PIPE_PP_OFF_DELAYS(pipe), 0);
+	I915_WRITE(VLV_PIPE_PP_DIVISOR(pipe),
+		   I915_READ(VLV_PIPE_PP_DIVISOR(pipe)) & PP_REFERENCE_DIVIDER_MASK);
+
+	vlv_kick_power_seqeuencer_for_dp(intel_dp, pipe);
+}
+
 static void intel_edp_init_train(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (!is_edp(intel_dp))
+	if (!is_edp(intel_dp)) {
+		/*
+		 * Need to kick the power sequencer even on DP if it it
+		 * was alrady locked to another port. Otherwise the port
+		 * just refuses to operate.
+		 */
+		if (IS_VALLEYVIEW(dev))
+			vlv_unstuck_power_sequencer(intel_dp);
 		return;
+	}
 
 	/*
 	 * Need to enable the port with idle pattern to allow the power
-- 
1.8.5.5

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Re: [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:28 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When switching from one pipe to another, the power sequencer of the new
> pipe seems to need a bit of kicking to lock into the port. Even the vdd
> force bit doesn't work before the power sequencer has been sufficiently
> kicked, so this must be done even before any AUX transactions.
> 
> This sequence has been found to do the trick:
> 1) enable port with idle pattern
> 2) enable the power sequencer
> 3) proceed with link training
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 65ab54c..07b0320 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static void intel_edp_init_train(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	if (!is_edp(intel_dp))
> +		return;
> +
> +	/*
> +	 * Need to enable the port with idle pattern to allow the power
> +	 * sequencer to lock into the port. Otherwise the power sequencer
> +	 * (including vdd force bit!) doesn't work on this port.
> +	 */
> +	if (IS_VALLEYVIEW(dev)) {
> +		intel_dp->DP |= DP_PORT_EN;
> +
> +		if (IS_CHERRYVIEW(dev))
> +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CHV;
> +		else
> +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> +		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> +
> +		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
> +		POSTING_READ(intel_dp->output_reg);
> +	}
> +
> +	intel_edp_panel_on(intel_dp);
> +	edp_panel_vdd_off(intel_dp, true);
> +}
> +
>  static void intel_enable_dp(struct intel_encoder *encoder)
>  {
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> @@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
>  		return;
>  
>  	intel_edp_panel_vdd_on(intel_dp);
> +	intel_edp_init_train(intel_dp);
>  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>  	intel_dp_start_link_train(intel_dp);
> -	intel_edp_panel_on(intel_dp);
> -	edp_panel_vdd_off(intel_dp, true);
>  	intel_dp_complete_link_train(intel_dp);
>  	intel_dp_stop_link_train(intel_dp);
>  }

Yeah I think this matches the doc too.  I never pushed this change
because I could never find anything that it actually fixed.

I guess you have something now though!

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
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Re: [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 30/40] drm/i915: Add the
> WaCsStallBeforeStateCacheInvalidate:bdw workaround.
> 
> From: Kenneth Graunke <kenneth@whitecape.org>
> 
> On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
> must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.
> 
> Documented on the BSpec 3D workarounds page.
> 
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> [vsyrjala: add chv w/a note too]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


There is a gotcha here that this workaround name has been used for a different bug in Gen7.5 and below. The workaround name clash came from the docs rather than a mistake by the patch authors, this is the correct workaround for all gen8 based devices

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 97796b1..ceb1295 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -424,6 +424,14 @@ gen8_render_ring_flush(struct intel_engine_cs
> *ring,
>  		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>  		flags |= PIPE_CONTROL_QW_WRITE;
>  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> +		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
> +		ret = gen8_emit_pipe_control(ring,
> +					     PIPE_CONTROL_CS_STALL |
> +
> PIPE_CONTROL_STALL_AT_SCOREBOARD,
> +					     0);
> +		if (ret)
> +			return ret;
>  	}
> 
>  	return gen8_emit_pipe_control(ring, flags, scratch_addr);
> --
> 1.8.5.5
> 
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Re: [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev

[Daniel Vetter]

On Sat, Jul 12, 2014 at 07:18:30PM +0530, Deepak S wrote:
> 
> On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >In
> >  commit 62942ed7279d3e06dc15ae3d47665eff3b373327
> >  Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> >  Date:   Fri Jun 13 09:28:33 2014 -0700
> >
> >     drm/i915/vlv: disable PPGTT on early revs v3
> >
> >we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to
> >explicitly avoid disabling PPGTT on CHV.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >index a4153ee..5188936 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >@@ -64,7 +64,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
> >  #endif
> >  	/* Early VLV doesn't have this */
> >-	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
> >+	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> >+	    dev->pdev->revision < 0xb) {
> >  		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
> >  		return 0;
> >  	}
> 
> Reviewed-by: Deepak S <deepak.s@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code

[Daniel Vetter]

On Sat, Jul 12, 2014 at 07:00:05PM +0530, Deepak S wrote:
> 
> On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >No need to re-read the hardware rps fuses when we already have all the
> >values tucked away in dev_priv->rps.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
> >  drivers/gpu/drm/i915/i915_drv.h     |  2 --
> >  drivers/gpu/drm/i915/intel_pm.c     |  8 ++++----
> >  3 files changed, 14 insertions(+), 15 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >index a93b3bf..415010e 100644
> >--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >@@ -1131,20 +1131,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >  		seq_printf(m, "Max overclocked frequency: %dMHz\n",
> >  			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
> >  	} else if (IS_VALLEYVIEW(dev)) {
> >-		u32 freq_sts, val;
> >+		u32 freq_sts;
> >  		mutex_lock(&dev_priv->rps.hw_lock);
> >  		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> >  		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> >  		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
> >-		val = valleyview_rps_max_freq(dev_priv);
> >  		seq_printf(m, "max GPU freq: %d MHz\n",
> >-			   vlv_gpu_freq(dev_priv, val));
> >+			   dev_priv->rps.max_freq);
> >-		val = valleyview_rps_min_freq(dev_priv);
> >  		seq_printf(m, "min GPU freq: %d MHz\n",
> >-			   vlv_gpu_freq(dev_priv, val));
> >+			   dev_priv->rps.min_freq);
> >+
> >+		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> >+			   dev_priv->rps.efficient_freq);
> >  		seq_printf(m, "current GPU freq: %d MHz\n",
> >  			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> >@@ -3565,8 +3566,8 @@ i915_max_freq_set(void *data, u64 val)
> >  	if (IS_VALLEYVIEW(dev)) {
> >  		val = vlv_freq_opcode(dev_priv, val);
> >-		hw_max = valleyview_rps_max_freq(dev_priv);
> >-		hw_min = valleyview_rps_min_freq(dev_priv);
> >+		hw_max = dev_priv->rps.max_freq;
> >+		hw_min = dev_priv->rps.min_freq;
> >  	} else {
> >  		do_div(val, GT_FREQUENCY_MULTIPLIER);
> >@@ -3646,8 +3647,8 @@ i915_min_freq_set(void *data, u64 val)
> >  	if (IS_VALLEYVIEW(dev)) {
> >  		val = vlv_freq_opcode(dev_priv, val);
> >-		hw_max = valleyview_rps_max_freq(dev_priv);
> >-		hw_min = valleyview_rps_min_freq(dev_priv);
> >+		hw_max = dev_priv->rps.max_freq;
> >+		hw_min = dev_priv->rps.min_freq;
> >  	} else {
> >  		do_div(val, GT_FREQUENCY_MULTIPLIER);
> >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >index 8cea596..38859d1 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.h
> >+++ b/drivers/gpu/drm/i915/i915_drv.h
> >@@ -2646,8 +2646,6 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
> >  extern void intel_init_pch_refclk(struct drm_device *dev);
> >  extern void gen6_set_rps(struct drm_device *dev, u8 val);
> >  extern void valleyview_set_rps(struct drm_device *dev, u8 val);
> >-extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
> >-extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
> >  extern void intel_detect_pch(struct drm_device *dev);
> >  extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
> >  extern int intel_enable_rc6(const struct drm_device *dev);
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index ef00756..10c9c02 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3729,7 +3729,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
> >  	mutex_unlock(&dev_priv->rps.hw_lock);
> >  }
> >-int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> >+static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 val, rp0;
> >@@ -3749,7 +3749,7 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> >  	return rpe;
> >  }
> >-int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> >+static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 val, rpn;
> >@@ -3758,7 +3758,7 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  	return rpn;
> >  }
> >-int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> >+static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 val, rp0;
> >@@ -3783,7 +3783,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> >  	return rpe;
> >  }
> >-int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> >+static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  {
> >  	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> >  }
> 
> Looks good. Reviewed-by: Deepak S <deepak.s@linux.intel.com>

Queued for -next, thanks for the patch. Since Ville is on vacation can you
perhaps pick up the rps patches that lack some polish and rebase them on
top of your vlv rps work? That way we also avoid conflicts when merging.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 16/40] drm/i915: Add chv_power_wells[]

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 16/40] drm/i915: Add chv_power_wells[]
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add chv_power_wells[] so we can start to build up the power well support
> for chv. Just the "always on" well there initialy.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 898654f..e2b956e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6498,6 +6498,15 @@ static struct i915_power_well vlv_power_wells[] =
> {
>  	},
>  };
> 
> +static struct i915_power_well chv_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = 1,
> +		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
> +		.ops = &i9xx_always_on_power_well_ops,
> +	},
> +};
> +
>  static struct i915_power_well *lookup_power_well(struct drm_i915_private
> *dev_priv,
>  						 enum punit_power_well
> power_well_id)
>  {
> @@ -6534,6 +6543,8 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
>  	} else if (IS_BROADWELL(dev_priv->dev)) {
>  		set_power_wells(power_domains, bdw_power_wells);
>  		hsw_pwr = power_domains;
> +	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> +		set_power_wells(power_domains, chv_power_wells);
>  	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
>  		set_power_wells(power_domains, vlv_power_wells);
>  	} else {
> --
> 1.8.5.5
> 

Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>

> _______________________________________________
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Re: [PATCH 10/40] drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 10/40] drm/i915: Call encoder->post_disable() in
> intel_sanitize_encoder()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> VLV and CHV disable the DP port only in the .post_disable() hook, so we
> need to make intel_sanitize_encoder() call that when it's trying to
> disable encoders without an active pipes.
> 
> My bsw actaully hits this when an external display is connected. The
> BIOS still likes to turn on the eDP port, but leaves the pipe disabled.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3e4d570..a16f635 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12772,6 +12772,8 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
>  				      encoder->base.base.id,
>  				      encoder->base.name);
>  			encoder->disable(encoder);
> +			if (encoder->post_disable)
> +				encoder->post_disable(encoder);
>  		}
>  		encoder->base.crtc = NULL;
>  		encoder->connectors_active = false;
> --
> 1.8.5.5
> 

I haven't done as much DP testing on my CHT but that makes sense.

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> _______________________________________________
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Re: [PATCH 01/40] drm/i915: Try to populate mem_freq for chv

[Deepak S]

[-- Attachment #1.1: Type: text/plain, Size: 1520 bytes --]


On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> mem_freq is needed to decode the GPU freq opcodes.
>
> FIXME: Punit reg seems to contain garbage so this isn't right
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 07c040c..ef00756 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>   static void cherryview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   

Added the right way of getting the mem_freq for CHV

*http://lists.freedesktop.org/archives/intel-gfx/2014-July/048897.html*


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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code

[Deepak S]

On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No need to re-read the hardware rps fuses when we already have all the
> values tucked away in dev_priv->rps.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
>   drivers/gpu/drm/i915/i915_drv.h     |  2 --
>   drivers/gpu/drm/i915/intel_pm.c     |  8 ++++----
>   3 files changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a93b3bf..415010e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1131,20 +1131,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>   		seq_printf(m, "Max overclocked frequency: %dMHz\n",
>   			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
>   	} else if (IS_VALLEYVIEW(dev)) {
> -		u32 freq_sts, val;
> +		u32 freq_sts;
>   
>   		mutex_lock(&dev_priv->rps.hw_lock);
>   		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>   		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
>   		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>   
> -		val = valleyview_rps_max_freq(dev_priv);
>   		seq_printf(m, "max GPU freq: %d MHz\n",
> -			   vlv_gpu_freq(dev_priv, val));
> +			   dev_priv->rps.max_freq);
>   
> -		val = valleyview_rps_min_freq(dev_priv);
>   		seq_printf(m, "min GPU freq: %d MHz\n",
> -			   vlv_gpu_freq(dev_priv, val));
> +			   dev_priv->rps.min_freq);
> +
> +		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> +			   dev_priv->rps.efficient_freq);
>   
>   		seq_printf(m, "current GPU freq: %d MHz\n",
>   			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> @@ -3565,8 +3566,8 @@ i915_max_freq_set(void *data, u64 val)
>   	if (IS_VALLEYVIEW(dev)) {
>   		val = vlv_freq_opcode(dev_priv, val);
>   
> -		hw_max = valleyview_rps_max_freq(dev_priv);
> -		hw_min = valleyview_rps_min_freq(dev_priv);
> +		hw_max = dev_priv->rps.max_freq;
> +		hw_min = dev_priv->rps.min_freq;
>   	} else {
>   		do_div(val, GT_FREQUENCY_MULTIPLIER);
>   
> @@ -3646,8 +3647,8 @@ i915_min_freq_set(void *data, u64 val)
>   	if (IS_VALLEYVIEW(dev)) {
>   		val = vlv_freq_opcode(dev_priv, val);
>   
> -		hw_max = valleyview_rps_max_freq(dev_priv);
> -		hw_min = valleyview_rps_min_freq(dev_priv);
> +		hw_max = dev_priv->rps.max_freq;
> +		hw_min = dev_priv->rps.min_freq;
>   	} else {
>   		do_div(val, GT_FREQUENCY_MULTIPLIER);
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8cea596..38859d1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2646,8 +2646,6 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
>   extern void intel_init_pch_refclk(struct drm_device *dev);
>   extern void gen6_set_rps(struct drm_device *dev, u8 val);
>   extern void valleyview_set_rps(struct drm_device *dev, u8 val);
> -extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
> -extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
>   extern void intel_detect_pch(struct drm_device *dev);
>   extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
>   extern int intel_enable_rc6(const struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef00756..10c9c02 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3729,7 +3729,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
>   	mutex_unlock(&dev_priv->rps.hw_lock);
>   }
>   
> -int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
> +static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
>   {
>   	u32 val, rp0;
>   
> @@ -3749,7 +3749,7 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>   	return rpe;
>   }
>   
> -int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> +static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>   {
>   	u32 val, rpn;
>   
> @@ -3758,7 +3758,7 @@ int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>   	return rpn;
>   }
>   
> -int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
> +static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
>   {
>   	u32 val, rp0;
>   
> @@ -3783,7 +3783,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>   	return rpe;
>   }
>   
> -int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> +static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>   {
>   	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
>   }

Looks good. Reviewed-by: Deepak S <deepak.s@linux.intel.com>

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Re: [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values

[Deepak S]

On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV wants even rps opcodes so make sure the min/max/rpe values are also
> even.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c |  8 ++++++++
>   drivers/gpu/drm/i915/intel_pm.c     | 19 ++++++++++++++-----
>   2 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 415010e..9b01e7c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3566,6 +3566,10 @@ i915_max_freq_set(void *data, u64 val)
>   	if (IS_VALLEYVIEW(dev)) {
>   		val = vlv_freq_opcode(dev_priv, val);
>   
> +		/* CHV needs even encode values */
> +		if (IS_CHERRYVIEW(dev))
> +			val &= ~1;
> +
>   		hw_max = dev_priv->rps.max_freq;
>   		hw_min = dev_priv->rps.min_freq;
>   	} else {
> @@ -3647,6 +3651,10 @@ i915_min_freq_set(void *data, u64 val)
>   	if (IS_VALLEYVIEW(dev)) {
>   		val = vlv_freq_opcode(dev_priv, val);
>   
> +		/* CHV needs even encode values */
> +		if (IS_CHERRYVIEW(dev))
> +			val = ALIGN(val, 2);
> +
>   		hw_max = dev_priv->rps.max_freq;
>   		hw_min = dev_priv->rps.min_freq;
>   	} else {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 10c9c02..e3f23c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,21 +3924,30 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   
>   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> +	if (WARN_ON_ONCE(dev_priv->rps.max_freq & 1))
> +		dev_priv->rps.max_freq &= ~1;

Cannot we use ALIGN Here?

Other than this it looks fine

Reviewed-by: Deepak S <deepak.s@linux.intel.com>


>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
>   			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
>   			 dev_priv->rps.max_freq);
>   
> -	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> -	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> -			 dev_priv->rps.efficient_freq);
> -
>   	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> +	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
> +		dev_priv->rps.min_freq = ALIGN(dev_priv->rps.min_freq, 2);
>   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>   			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
>   			 dev_priv->rps.min_freq);
>   
> +	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> +	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
> +		dev_priv->rps.efficient_freq &= ~1;
> +	dev_priv->rps.efficient_freq = clamp(dev_priv->rps.efficient_freq,
> +					     dev_priv->rps.min_freq,
> +					     dev_priv->rps.max_freq);
> +	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> +			 dev_priv->rps.efficient_freq);
> +
>   	/* Preserve min/max settings in case of re-init */
>   	if (dev_priv->rps.max_freq_softlimit == 0)
>   		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;

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Re: [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev

[Deepak S]

On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In
>   commit 62942ed7279d3e06dc15ae3d47665eff3b373327
>   Author: Jesse Barnes <jbarnes@virtuousgeek.org>
>   Date:   Fri Jun 13 09:28:33 2014 -0700
>
>      drm/i915/vlv: disable PPGTT on early revs v3
>
> we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to
> explicitly avoid disabling PPGTT on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a4153ee..5188936 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -64,7 +64,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
>   #endif
>   
>   	/* Early VLV doesn't have this */
> -	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
> +	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> +	    dev->pdev->revision < 0xb) {
>   		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
>   		return 0;
>   	}

Reviewed-by: Deepak S <deepak.s@linux.intel.com>

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Re: [PATCH 17/40] drm/i915: Add chv cmnlane power wells

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 5696 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV has two display PHYs so there are also two cmnlane power wells. Add
> the approriate code to power the wells up/down.
> 
> Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
> enabling at approriate times.
> 
> This code actually works on my bsw.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 90 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d246609..19e68d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -512,6 +512,7 @@ enum punit_power_well {
>  	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
>  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
>  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> +	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
>  
>  	PUNIT_POWER_WELL_NUM,
>  };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e2b956e..f88490b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>  	vlv_set_power_well(dev_priv, power_well, false);
>  }
>  
> +static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> +					   struct i915_power_well *power_well)
> +{
> +	enum dpio_phy phy;
> +
> +	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
> +		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
> +
> +	/*
> +	 * Enable the CRI clock source so we can get at the
> +	 * display and the reference clock for VGA
> +	 * hotplug / manual detection.
> +	 */
> +	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> +		phy = DPIO_PHY0;
> +		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
> +			   DPLL_REFA_CLK_ENABLE_VLV);
> +		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
> +			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);

Any reason the two clocks are enabled sequentially? For PHY1 you don't
do this.. In any case:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	} else {
> +		phy = DPIO_PHY1;
> +		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
> +			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> +	}
> +	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> +	vlv_set_power_well(dev_priv, power_well, true);
> +
> +	/* Poll for phypwrgood signal */
> +	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
> +		DRM_ERROR("Display PHY %d is not power up\n", phy);
> +
> +	I915_WRITE(DISPLAY_PHY_CONTROL,
> +		   PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
> +}
> +
> +static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> +					    struct i915_power_well *power_well)
> +{
> +	enum dpio_phy phy;
> +
> +	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
> +		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
> +
> +	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> +		phy = DPIO_PHY0;
> +		assert_pll_disabled(dev_priv, PIPE_A);
> +		assert_pll_disabled(dev_priv, PIPE_B);
> +	} else {
> +		phy = DPIO_PHY1;
> +		assert_pll_disabled(dev_priv, PIPE_C);
> +	}
> +
> +	I915_WRITE(DISPLAY_PHY_CONTROL,
> +		   PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
> +
> +	vlv_set_power_well(dev_priv, power_well, false);
> +}
> +
>  static void check_power_well_state(struct drm_i915_private *dev_priv,
>  				   struct i915_power_well *power_well)
>  {
> @@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
>  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +#define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
> +	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
> +#define CHV_DPIO_CMN_D_POWER_DOMAINS (		\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_always_on_power_well_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = {
>  	},
>  };
>  
> +static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
> +	.sync_hw = vlv_power_well_sync_hw,
> +	.enable = chv_dpio_cmn_power_well_enable,
> +	.disable = chv_dpio_cmn_power_well_disable,
> +	.is_enabled = vlv_power_well_enabled,
> +};
> +
>  static struct i915_power_well chv_power_wells[] = {
>  	{
>  		.name = "always-on",
> @@ -6505,6 +6582,18 @@ static struct i915_power_well chv_power_wells[] = {
>  		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
>  		.ops = &i9xx_always_on_power_well_ops,
>  	},
> +	{
> +		.name = "dpio-common-bc",
> +		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> +		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
> +		.ops = &chv_dpio_cmn_power_well_ops,
> +	},
> +	{
> +		.name = "dpio-common-d",
> +		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> +		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
> +		.ops = &chv_dpio_cmn_power_well_ops,
> +	},
>  };
>  
>  static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,


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Re: [PATCH 18/40] drm/i915: Kill intel_reset_dpio()

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 2183 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Both VLV and CHV handle the cmnreset stuff in the power well code now,
> so intel_reset_dpio() is no longer needed.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 31 -------------------------------
>  1 file changed, 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a16f635..3cd73f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1511,34 +1511,6 @@ static void intel_init_dpio(struct drm_device *dev)
>  	}
>  }
>  
> -static void intel_reset_dpio(struct drm_device *dev)
> -{
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
> -	if (IS_CHERRYVIEW(dev)) {
> -		enum dpio_phy phy;
> -		u32 val;
> -
> -		for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
> -			/* Poll for phypwrgood signal */
> -			if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> -						PHY_POWERGOOD(phy), 1))
> -				DRM_ERROR("Display PHY %d is not power up\n", phy);
> -
> -			/*
> -			 * Deassert common lane reset for PHY.
> -			 *
> -			 * This should only be done on init and resume from S3
> -			 * with both PLLs disabled, or we risk losing DPIO and
> -			 * PLL synchronization.
> -			 */
> -			val = I915_READ(DISPLAY_PHY_CONTROL);
> -			I915_WRITE(DISPLAY_PHY_CONTROL,
> -				PHY_COM_LANE_RESET_DEASSERT(phy, val));
> -		}
> -	}
> -}
> -
>  static void vlv_enable_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> @@ -12473,8 +12445,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
>  
>  	intel_init_clock_gating(dev);
>  
> -	intel_reset_dpio(dev);
> -
>  	intel_enable_gt_powersave(dev);
>  }
>  
> @@ -12545,7 +12515,6 @@ void intel_modeset_init(struct drm_device *dev)
>  	}
>  
>  	intel_init_dpio(dev);
> -	intel_reset_dpio(dev);
>  
>  	intel_cpu_pll_init(dev);
>  	intel_shared_dpll_init(dev);


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Re: [PATCH 19/40] drm/i915: Add disp2d power well for chv

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 1228 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Not sure if it's still there since chv has per-pipe power wells.
> At least with current Punit this doesn't work. Also the display
> irq handling would need to be adjusted for pipe C. So leave the
> code iffed out for now.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f88490b..46394fc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6582,6 +6582,14 @@ static struct i915_power_well chv_power_wells[] = {
>  		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
>  		.ops = &i9xx_always_on_power_well_ops,
>  	},
> +#if 0
> +	{
> +		.name = "display",
> +		.domains = VLV_DISPLAY_POWER_DOMAINS,
> +		.data = PUNIT_POWER_WELL_DISP2D,
> +		.ops = &vlv_display_power_well_ops,
> +	},
> +#endif
>  	{
>  		.name = "dpio-common-bc",
>  		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,


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Re: [PATCH 20/40] drm/i915: Add per-pipe power wells for chv

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 6810 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV has a power well for each pipe. Add the code to deal with them.
> 
> The Punit in current hardware doesn't seem ready for this yet, so
> leave it iffed out.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  12 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 126 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 138 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 19e68d6..3d1fef4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -499,6 +499,18 @@
>  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>  #define   DSPFREQGUAR_SHIFT			14
>  #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
> +#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
> +#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> +#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
> +#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
> +#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
> +#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
> +#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
> +#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
> +#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
> +#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
> +#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
>  
>  /* See the PUNIT HAS v0.8 for the below bits */
>  enum punit_power_well {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 46394fc..de5416b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6258,6 +6258,95 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>  	vlv_set_power_well(dev_priv, power_well, false);
>  }
>  
> +static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
> +					struct i915_power_well *power_well)
> +{
> +	enum pipe pipe = power_well->data;
> +	bool enabled;
> +	u32 state, ctrl;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +
> +	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
> +	/*
> +	 * We only ever set the power-on and power-gate states, anything
> +	 * else is unexpected.
> +	 */
> +	WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
> +	enabled = state == DP_SSS_PWR_ON(pipe);
> +
> +	/*
> +	 * A transient state at this point would mean some unexpected party
> +	 * is poking at the power controls too.
> +	 */
> +	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
> +	WARN_ON(ctrl << 16 != state);
> +
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	return enabled;
> +}
> +
> +static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
> +				    struct i915_power_well *power_well,
> +				    bool enable)
> +{
> +	enum pipe pipe = power_well->data;
> +	u32 state;
> +	u32 ctrl;
> +
> +	state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +
> +#define COND \
> +	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
> +
> +	if (COND)
> +		goto out;
> +
> +	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +	ctrl &= ~DP_SSC_MASK(pipe);
> +	ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
> +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
> +
> +	if (wait_for(COND, 100))
> +		DRM_ERROR("timout setting power well state %08x (%08x)\n",
> +			  state,
> +			  vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
> +
> +#undef COND
> +
> +out:
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +}
> +
> +static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
> +					struct i915_power_well *power_well)
> +{
> +	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
> +}
> +
> +static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
> +				       struct i915_power_well *power_well)
> +{
> +	WARN_ON_ONCE(power_well->data != PIPE_A &&
> +		     power_well->data != PIPE_B &&
> +		     power_well->data != PIPE_C);
> +
> +	chv_set_pipe_power_well(dev_priv, power_well, true);
> +}
> +
> +static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
> +					struct i915_power_well *power_well)
> +{
> +	WARN_ON_ONCE(power_well->data != PIPE_A &&
> +		     power_well->data != PIPE_B &&
> +		     power_well->data != PIPE_C);
> +
> +	chv_set_pipe_power_well(dev_priv, power_well, false);
> +}
> +
>  static void check_power_well_state(struct drm_i915_private *dev_priv,
>  				   struct i915_power_well *power_well)
>  {
> @@ -6427,6 +6516,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
>  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +#define CHV_PIPE_A_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PIPE_A) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
> +#define CHV_PIPE_B_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PIPE_B) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
> +#define CHV_PIPE_C_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PIPE_C) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
>  #define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
>  	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
>  	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
> @@ -6568,6 +6669,13 @@ static struct i915_power_well vlv_power_wells[] = {
>  	},
>  };
>  
> +static const struct i915_power_well_ops chv_pipe_power_well_ops = {
> +	.sync_hw = chv_pipe_power_well_sync_hw,
> +	.enable = chv_pipe_power_well_enable,
> +	.disable = chv_pipe_power_well_disable,
> +	.is_enabled = chv_pipe_power_well_enabled,
> +};
> +
>  static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
>  	.sync_hw = vlv_power_well_sync_hw,
>  	.enable = chv_dpio_cmn_power_well_enable,
> @@ -6589,6 +6697,24 @@ static struct i915_power_well chv_power_wells[] = {
>  		.data = PUNIT_POWER_WELL_DISP2D,
>  		.ops = &vlv_display_power_well_ops,
>  	},
> +	{
> +		.name = "pipe-a",
> +		.domains = CHV_PIPE_A_POWER_DOMAINS,
> +		.data = PIPE_A,
> +		.ops = &chv_pipe_power_well_ops,
> +	},
> +	{
> +		.name = "pipe-b",
> +		.domains = CHV_PIPE_B_POWER_DOMAINS,
> +		.data = PIPE_B,
> +		.ops = &chv_pipe_power_well_ops,
> +	},
> +	{
> +		.name = "pipe-c",
> +		.domains = CHV_PIPE_C_POWER_DOMAINS,
> +		.data = PIPE_C,
> +		.ops = &chv_pipe_power_well_ops,
> +	},
>  #endif
>  	{
>  		.name = "dpio-common-bc",


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Re: [PATCH 21/40] drm/i915: Add chv port B and C TX wells

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 1982 bytes --]

On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the TX wells for ports B and C just like on VLV.
> 
> Again Punit doesn't seem ready (or the wells don't even exist anymore)
> so leave it iffed out.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index de5416b..cae936c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6728,6 +6728,36 @@ static struct i915_power_well chv_power_wells[] = {
>  		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
>  		.ops = &chv_dpio_cmn_power_well_ops,
>  	},
> +#if 0
> +	{
> +		.name = "dpio-tx-b-01",
> +		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> +			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
> +	},
> +	{
> +		.name = "dpio-tx-b-23",
> +		.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> +			   VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
> +	},
> +	{
> +		.name = "dpio-tx-c-01",
> +		.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> +			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
> +	},
> +	{
> +		.name = "dpio-tx-c-23",
> +		.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> +			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> +	},
> +#endif
>  };
>  
>  static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,


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Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Imre Deak]

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On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the TX wells for port D. The Punit subsystem numbers are a total
> guess at this time. Also I'm not sure these even exist. Certainly the
> Punit in current hardware doesn't deal with these.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d1fef4..191df9e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -525,6 +525,10 @@ enum punit_power_well {
>  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
>  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
>  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> +	/* FIXME: guesswork below */
> +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
>  
>  	PUNIT_POWER_WELL_NUM,
>  };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cae936c..55f3e6b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
>  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
>  	BIT(POWER_DOMAIN_INIT))
>  
> +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> +	BIT(POWER_DOMAIN_INIT))
> +
> +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\

Atm, for all other ports we power up all lanes regardless of the actual
configuration (until the PHY side setup is proved to work fine). So for
consistency I'd do the same here too. With that change:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	BIT(POWER_DOMAIN_INIT))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_always_on_power_well_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
>  		.ops = &vlv_dpio_power_well_ops,
>  		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
>  	},
> +	{
> +		.name = "dpio-tx-d-01",
> +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> +	},
> +	{
> +		.name = "dpio-tx-d-23",
> +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> +		.ops = &vlv_dpio_power_well_ops,
> +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> +	},
>  #endif
>  };
>  


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Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Daniel Vetter]

On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
> On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add the TX wells for port D. The Punit subsystem numbers are a total
> > guess at this time. Also I'm not sure these even exist. Certainly the
> > Punit in current hardware doesn't deal with these.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> >  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> >  2 files changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3d1fef4..191df9e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -525,6 +525,10 @@ enum punit_power_well {
> >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> >  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> > +	/* FIXME: guesswork below */
> > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> > +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
> >  
> >  	PUNIT_POWER_WELL_NUM,
> >  };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cae936c..55f3e6b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> >  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> >  	BIT(POWER_DOMAIN_INIT))
> >  
> > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> 
> Atm, for all other ports we power up all lanes regardless of the actual
> configuration (until the PHY side setup is proved to work fine). So for
> consistency I'd do the same here too. With that change:
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Pulled in all the power well patches Imre reviewed except this one.

Thanks, Daniel

> 
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_always_on_power_well_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
> >  		.ops = &vlv_dpio_power_well_ops,
> >  		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> >  	},
> > +	{
> > +		.name = "dpio-tx-d-01",
> > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > +		.ops = &vlv_dpio_power_well_ops,
> > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> > +	},
> > +	{
> > +		.name = "dpio-tx-d-23",
> > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > +		.ops = &vlv_dpio_power_well_ops,
> > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> > +	},
> >  #endif
> >  };
> >  
> 



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> Intel-gfx@lists.freedesktop.org
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values

[Ville Syrjälä]

On Sat, Jul 12, 2014 at 07:16:15PM +0530, Deepak S wrote:
> 
> On Saturday 28 June 2014 04:33 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV wants even rps opcodes so make sure the min/max/rpe values are also
> > even.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c |  8 ++++++++
> >   drivers/gpu/drm/i915/intel_pm.c     | 19 ++++++++++++++-----
> >   2 files changed, 22 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 415010e..9b01e7c 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3566,6 +3566,10 @@ i915_max_freq_set(void *data, u64 val)
> >   	if (IS_VALLEYVIEW(dev)) {
> >   		val = vlv_freq_opcode(dev_priv, val);
> >   
> > +		/* CHV needs even encode values */
> > +		if (IS_CHERRYVIEW(dev))
> > +			val &= ~1;
> > +
> >   		hw_max = dev_priv->rps.max_freq;
> >   		hw_min = dev_priv->rps.min_freq;
> >   	} else {
> > @@ -3647,6 +3651,10 @@ i915_min_freq_set(void *data, u64 val)
> >   	if (IS_VALLEYVIEW(dev)) {
> >   		val = vlv_freq_opcode(dev_priv, val);
> >   
> > +		/* CHV needs even encode values */
> > +		if (IS_CHERRYVIEW(dev))
> > +			val = ALIGN(val, 2);
> > +
> >   		hw_max = dev_priv->rps.max_freq;
> >   		hw_min = dev_priv->rps.min_freq;
> >   	} else {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 10c9c02..e3f23c2 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3924,21 +3924,30 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
> >   	mutex_lock(&dev_priv->rps.hw_lock);
> >   
> >   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> > +	if (WARN_ON_ONCE(dev_priv->rps.max_freq & 1))
> > +		dev_priv->rps.max_freq &= ~1;
> 
> Cannot we use ALIGN Here?

The idea was to round max freq down and min freq up.

> 
> Other than this it looks fine
> 
> Reviewed-by: Deepak S <deepak.s@linux.intel.com>
> 
> 
> >   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> >   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> >   			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> >   			 dev_priv->rps.max_freq);
> >   
> > -	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> > -	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > -			 dev_priv->rps.efficient_freq);
> > -
> >   	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> > +	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
> > +		dev_priv->rps.min_freq = ALIGN(dev_priv->rps.min_freq, 2);
> >   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> >   			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> >   			 dev_priv->rps.min_freq);
> >   
> > +	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> > +	if (WARN_ON_ONCE(dev_priv->rps.min_freq & 1))
> > +		dev_priv->rps.efficient_freq &= ~1;
> > +	dev_priv->rps.efficient_freq = clamp(dev_priv->rps.efficient_freq,
> > +					     dev_priv->rps.min_freq,
> > +					     dev_priv->rps.max_freq);
> > +	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > +			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > +			 dev_priv->rps.efficient_freq);
> > +
> >   	/* Preserve min/max settings in case of re-init */
> >   	if (dev_priv->rps.max_freq_softlimit == 0)
> >   		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 17/40] drm/i915: Add chv cmnlane power wells

[Ville Syrjälä]

On Fri, Jul 25, 2014 at 02:55:00PM +0300, Imre Deak wrote:
> On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > CHV has two display PHYs so there are also two cmnlane power wells. Add
> > the approriate code to power the wells up/down.
> > 
> > Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
> > enabling at approriate times.
> > 
> > This code actually works on my bsw.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 90 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d246609..19e68d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -512,6 +512,7 @@ enum punit_power_well {
> >  	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
> >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> > +	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> >  
> >  	PUNIT_POWER_WELL_NUM,
> >  };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index e2b956e..f88490b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6200,6 +6200,64 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> >  	vlv_set_power_well(dev_priv, power_well, false);
> >  }
> >  
> > +static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> > +					   struct i915_power_well *power_well)
> > +{
> > +	enum dpio_phy phy;
> > +
> > +	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
> > +		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
> > +
> > +	/*
> > +	 * Enable the CRI clock source so we can get at the
> > +	 * display and the reference clock for VGA
> > +	 * hotplug / manual detection.
> > +	 */
> > +	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> > +		phy = DPIO_PHY0;
> > +		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
> > +			   DPLL_REFA_CLK_ENABLE_VLV);
> > +		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
> > +			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> 
> Any reason the two clocks are enabled sequentially? For PHY1 you don't
> do this..

I think I meant to enable the ref clock for both pipes A and B. So the
first rmw should have hit DPLL(PIPE_A).

> In any case:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +	} else {
> > +		phy = DPIO_PHY1;
> > +		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
> > +			   DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> > +	}
> > +	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> > +	vlv_set_power_well(dev_priv, power_well, true);
> > +
> > +	/* Poll for phypwrgood signal */
> > +	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
> > +		DRM_ERROR("Display PHY %d is not power up\n", phy);
> > +
> > +	I915_WRITE(DISPLAY_PHY_CONTROL,
> > +		   PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
> > +}
> > +
> > +static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> > +					    struct i915_power_well *power_well)
> > +{
> > +	enum dpio_phy phy;
> > +
> > +	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
> > +		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
> > +
> > +	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> > +		phy = DPIO_PHY0;
> > +		assert_pll_disabled(dev_priv, PIPE_A);
> > +		assert_pll_disabled(dev_priv, PIPE_B);
> > +	} else {
> > +		phy = DPIO_PHY1;
> > +		assert_pll_disabled(dev_priv, PIPE_C);
> > +	}
> > +
> > +	I915_WRITE(DISPLAY_PHY_CONTROL,
> > +		   PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
> > +
> > +	vlv_set_power_well(dev_priv, power_well, false);
> > +}
> > +
> >  static void check_power_well_state(struct drm_i915_private *dev_priv,
> >  				   struct i915_power_well *power_well)
> >  {
> > @@ -6369,6 +6427,18 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> >  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
> >  	BIT(POWER_DOMAIN_INIT))
> >  
> > +#define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
> > +	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> > +#define CHV_DPIO_CMN_D_POWER_DOMAINS (		\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_always_on_power_well_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -6498,6 +6568,13 @@ static struct i915_power_well vlv_power_wells[] = {
> >  	},
> >  };
> >  
> > +static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
> > +	.sync_hw = vlv_power_well_sync_hw,
> > +	.enable = chv_dpio_cmn_power_well_enable,
> > +	.disable = chv_dpio_cmn_power_well_disable,
> > +	.is_enabled = vlv_power_well_enabled,
> > +};
> > +
> >  static struct i915_power_well chv_power_wells[] = {
> >  	{
> >  		.name = "always-on",
> > @@ -6505,6 +6582,18 @@ static struct i915_power_well chv_power_wells[] = {
> >  		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
> >  		.ops = &i9xx_always_on_power_well_ops,
> >  	},
> > +	{
> > +		.name = "dpio-common-bc",
> > +		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> > +		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
> > +		.ops = &chv_dpio_cmn_power_well_ops,
> > +	},
> > +	{
> > +		.name = "dpio-common-d",
> > +		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> > +		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
> > +		.ops = &chv_dpio_cmn_power_well_ops,
> > +	},
> >  };
> >  
> >  static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
> 



-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Ville Syrjälä]

On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
> On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add the TX wells for port D. The Punit subsystem numbers are a total
> > guess at this time. Also I'm not sure these even exist. Certainly the
> > Punit in current hardware doesn't deal with these.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> >  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> >  2 files changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3d1fef4..191df9e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -525,6 +525,10 @@ enum punit_power_well {
> >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> >  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> > +	/* FIXME: guesswork below */
> > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> > +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
> >  
> >  	PUNIT_POWER_WELL_NUM,
> >  };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cae936c..55f3e6b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> >  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> >  	BIT(POWER_DOMAIN_INIT))
> >  
> > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> 
> Atm, for all other ports we power up all lanes regardless of the actual
> configuration (until the PHY side setup is proved to work fine). So for
> consistency I'd do the same here too. With that change:

We do that here too. '.domains = 01 | 23' for both tx-d wells. Or am I
missing something?

> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +	BIT(POWER_DOMAIN_INIT))
> > +
> >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_always_on_power_well_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
> >  		.ops = &vlv_dpio_power_well_ops,
> >  		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> >  	},
> > +	{
> > +		.name = "dpio-tx-d-01",
> > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > +		.ops = &vlv_dpio_power_well_ops,
> > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> > +	},
> > +	{
> > +		.name = "dpio-tx-d-23",
> > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > +		.ops = &vlv_dpio_power_well_ops,
> > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> > +	},
> >  #endif
> >  };
> >  
> 



-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Imre Deak]

[-- Attachment #1.1: Type: text/plain, Size: 3551 bytes --]

On Mon, 2014-07-28 at 18:19 +0300, Ville Syrjälä wrote:
> On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
> > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Add the TX wells for port D. The Punit subsystem numbers are a total
> > > guess at this time. Also I'm not sure these even exist. Certainly the
> > > Punit in current hardware doesn't deal with these.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> > >  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> > >  2 files changed, 27 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 3d1fef4..191df9e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -525,6 +525,10 @@ enum punit_power_well {
> > >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> > >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> > >  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> > > +	/* FIXME: guesswork below */
> > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> > > +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
> > >  
> > >  	PUNIT_POWER_WELL_NUM,
> > >  };
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index cae936c..55f3e6b 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> > >  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > >  	BIT(POWER_DOMAIN_INIT))
> > >  
> > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> > > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > +	BIT(POWER_DOMAIN_INIT))
> > > +
> > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > 
> > Atm, for all other ports we power up all lanes regardless of the actual
> > configuration (until the PHY side setup is proved to work fine). So for
> > consistency I'd do the same here too. With that change:
> 
> We do that here too. '.domains = 01 | 23' for both tx-d wells. Or am I
> missing something?

Ah, right I should've read a couple of lines below. So my above comment
can be ignored and my r-b applies as-is.

> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > > +	BIT(POWER_DOMAIN_INIT))
> > > +
> > >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > >  	.sync_hw = i9xx_always_on_power_well_noop,
> > >  	.enable = i9xx_always_on_power_well_noop,
> > > @@ -6757,6 +6766,20 @@ static struct i915_power_well chv_power_wells[] = {
> > >  		.ops = &vlv_dpio_power_well_ops,
> > >  		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> > >  	},
> > > +	{
> > > +		.name = "dpio-tx-d-01",
> > > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > > +		.ops = &vlv_dpio_power_well_ops,
> > > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> > > +	},
> > > +	{
> > > +		.name = "dpio-tx-d-23",
> > > +		.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> > > +			   CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> > > +		.ops = &vlv_dpio_power_well_ops,
> > > +		.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> > > +	},
> > >  #endif
> > >  };
> > >  
> > 
> 
> 
> 


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Re: [PATCH 22/40] drm/i915: Add chv port D TX wells

[Daniel Vetter]

On Tue, Jul 29, 2014 at 12:54:36PM +0300, Imre Deak wrote:
> On Mon, 2014-07-28 at 18:19 +0300, Ville Syrjälä wrote:
> > On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
> > > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Add the TX wells for port D. The Punit subsystem numbers are a total
> > > > guess at this time. Also I'm not sure these even exist. Certainly the
> > > > Punit in current hardware doesn't deal with these.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> > > >  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> > > >  2 files changed, 27 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 3d1fef4..191df9e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -525,6 +525,10 @@ enum punit_power_well {
> > > >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> > > >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> > > >  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> > > > +	/* FIXME: guesswork below */
> > > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> > > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> > > > +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
> > > >  
> > > >  	PUNIT_POWER_WELL_NUM,
> > > >  };
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index cae936c..55f3e6b 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> > > >  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > >  	BIT(POWER_DOMAIN_INIT))
> > > >  
> > > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > > +	BIT(POWER_DOMAIN_INIT))
> > > > +
> > > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > 
> > > Atm, for all other ports we power up all lanes regardless of the actual
> > > configuration (until the PHY side setup is proved to work fine). So for
> > > consistency I'd do the same here too. With that change:
> > 
> > We do that here too. '.domains = 01 | 23' for both tx-d wells. Or am I
> > missing something?
> 
> Ah, right I should've read a couple of lines below. So my above comment
> can be ignored and my r-b applies as-is.
> 
> > > Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 06/40] drm/i915: Add cdclk change support for chv

[Jesse Barnes]

On Sat, 28 Jun 2014 02:03:57 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Looks like the Punit is supposed to support the 400MHz cdclk directly on
> chv, so we don't need the vlv tricks.
> 
> FIXME: Punit doesn't seem ready for this yet on current hw
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 +++
>  drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++--
>  2 files changed, 52 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f156591..e296312 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -491,6 +491,10 @@
>  #define BUNIT_REG_BISOC				0x11
>  
>  #define PUNIT_REG_DSPFREQ			0x36
> +#define   DSPFREQSTAT_SHIFT_CHV			24
> +#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> +#define   DSPFREQGUAR_SHIFT_CHV			8
> +#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
>  #define   DSPFREQSTAT_SHIFT			30
>  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>  #define   DSPFREQGUAR_SHIFT			14
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 99c10d1..9af1d13 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	vlv_update_cdclk(dev);
>  }
>  
> +static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val, cmd;
> +
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +
> +	switch (cdclk) {
> +	case 400000:
> +		cmd = 3;
> +		break;
> +	case 333333:
> +	case 320000:
> +		cmd = 2;
> +		break;
> +	case 266667:
> +		cmd = 1;
> +		break;
> +	case 200000:
> +		cmd = 0;
> +		break;
> +	default:
> +		WARN_ON(1);
> +		return;
> +	}
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +	val &= ~DSPFREQGUAR_MASK_CHV;
> +	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> +	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> +		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> +		     50)) {
> +		DRM_ERROR("timed out waiting for CDclk change\n");
> +	}
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	vlv_update_cdclk(dev);
> +}
> +
>  static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  				 int max_pixclk)
>  {
> @@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>  
> -	if (req_cdclk != dev_priv->vlv_cdclk_freq)
> -		valleyview_set_cdclk(dev, req_cdclk);
> +	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> +		if (IS_CHERRYVIEW(dev))
> +			cherryview_set_cdclk(dev, req_cdclk);
> +		else
> +			valleyview_set_cdclk(dev, req_cdclk);
> +	}
> +
>  	modeset_update_crtc_power_domains(dev);
>  }
>  

Which doc has these Punit commands?  I'm assuming you have them
correct, but a ref would be good if we don't already have one.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

There should probably be a JIRA for this too so QA can verify once we
have updated punit support.

-- 
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Re: [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready

[Jesse Barnes]

On Sat, 28 Jun 2014 02:03:58 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Punit seems a bit WIP still. Disable cdclk changes until we have
> hardware where it works.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9af1d13..4abf8b6f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4576,6 +4576,10 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  	int vco = valleyview_get_vco(dev_priv);
>  	int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
>  
> +	/* FIXME: Punit isn't quite ready yet */
> +	if (IS_CHERRYVIEW(dev_priv->dev))
> +		return 400000;
> +
>  	/*
>  	 * Really only a few cases to deal with, as only 4 CDclks are supported:
>  	 *   200MHz
> @@ -5297,6 +5301,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
>  	u32 val;
>  	int divider;
>  
> +	/* FIXME: Punit isn't quite ready yet */
> +	if (IS_CHERRYVIEW(dev))
> +		return 400000;
> +
>  	mutex_lock(&dev_priv->dpio_lock);
>  	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
>  	mutex_unlock(&dev_priv->dpio_lock);

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
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Re: [PATCH 08/40] drm/i915: Leave DPLL ref clocks on

[Jesse Barnes]

On Sat, 28 Jun 2014 02:03:59 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We enable the DPLL refclock already when bringing up the cmnlane power
> well, so also leave it on when otherwise disabling the DPLL.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4abf8b6f..a430699f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1709,7 +1709,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	assert_pipe_disabled(dev_priv, pipe);
>  
>  	/* Set PLL en = 0 */
> -	val = DPLL_SSC_REF_CLOCK_CHV;
> +	val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  	I915_WRITE(DPLL(pipe), val);

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
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Re: [PATCH 09/40] drm/i915: Split chv_update_pll() apart

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:00 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Split chv_update_pll() into two parts ala:
>  commit bdd4b6a655749970cc632aafc5fd596c07b60b1c
>  Author: Daniel Vetter <daniel.vetter@ffwll.ch>
>  Date:   Thu Apr 24 23:55:11 2014 +0200
> 
>     drm/i915: Extract vlv_prepare_pll
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++-----------
>  1 file changed, 19 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a430699f..3e4d570 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -100,6 +100,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
>  static void haswell_set_pipeconf(struct drm_crtc *crtc);
>  static void intel_set_pipe_csc(struct drm_crtc *crtc);
>  static void vlv_prepare_pll(struct intel_crtc *crtc);
> +static void chv_prepare_pll(struct intel_crtc *crtc);
>  
>  typedef struct {
>  	int	min, max;
> @@ -4670,8 +4671,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  
>  	is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
>  
> -	if (!is_dsi && !IS_CHERRYVIEW(dev))
> -		vlv_prepare_pll(intel_crtc);
> +	if (!is_dsi) {
> +		if (IS_CHERRYVIEW(dev))
> +			chv_prepare_pll(intel_crtc);
> +		else
> +			vlv_prepare_pll(intel_crtc);
> +	}
>  
>  	/* Set up the display plane register */
>  	dspcntr = DISPPLANE_GAMMA_ENABLE;
> @@ -5692,6 +5697,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
>  
>  static void chv_update_pll(struct intel_crtc *crtc)
>  {
> +	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
> +		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> +		DPLL_VCO_ENABLE;
> +	if (crtc->pipe != PIPE_A)
> +		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> +	crtc->config.dpll_hw_state.dpll_md =
> +		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +}
> +
> +static void chv_prepare_pll(struct intel_crtc *crtc)
> +{
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int pipe = crtc->pipe;
> @@ -5701,15 +5718,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	int refclk;
>  
> -	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
> -		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> -		DPLL_VCO_ENABLE;
> -	if (pipe != PIPE_A)
> -		crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> -
> -	crtc->config.dpll_hw_state.dpll_md =
> -		(crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -
>  	bestn = crtc->config.dpll.n;
>  	bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
>  	bestm1 = crtc->config.dpll.m1;

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
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Re: [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:02 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV was forgotten the intel_{dp,hdmi}_prepare() were introduced (or the
> chv patches were still in flight?). Call these when enabling the ports.
> 
> Things tend to work much better when we actually write something
> to the port registers :)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 2 ++
>  drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b5ec489..e272f92 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2197,6 +2197,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
>  	enum pipe pipe = intel_crtc->pipe;
>  	u32 val;
>  
> +	intel_dp_prepare(encoder);
> +
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* program left/right clock distribution */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 2422413..c9d77d3 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1240,6 +1240,8 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	enum pipe pipe = intel_crtc->pipe;
>  	u32 val;
>  
> +	intel_hdmi_prepare(encoder);
> +
>  	mutex_lock(&dev_priv->dpio_lock);
>  
>  	/* program left/right clock distribution */

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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Re: [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:03 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV display PHY registes have two swing margin/deemph settings. Make it
> clear which ones we're using.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 8 ++++++--
>  drivers/gpu/drm/i915/intel_dp.c   | 4 ++--
>  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
>  3 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e296312..ba90320 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -831,8 +831,8 @@ enum punit_power_well {
>  
>  #define _VLV_TX_DW2_CH0			0x8288
>  #define _VLV_TX_DW2_CH1			0x8488
> -#define   DPIO_SWING_MARGIN_SHIFT	16
> -#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
> +#define   DPIO_SWING_MARGIN000_SHIFT	16
> +#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
>  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
>  #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
>  
> @@ -840,12 +840,16 @@ enum punit_power_well {
>  #define _VLV_TX_DW3_CH1			0x848c
>  /* The following bit for CHV phy */
>  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
> +#define   DPIO_SWING_MARGIN101_SHIFT	16
> +#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
>  #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
>  
>  #define _VLV_TX_DW4_CH0			0x8290
>  #define _VLV_TX_DW4_CH1			0x8490
>  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
>  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> +#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
> +#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
>  #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
>  
>  #define _VLV_TX3_DW4_CH0		0x690
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e272f92..4457f8f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
>  	/* Program swing margin */
>  	for (i = 0; i < 4; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -		val &= ~DPIO_SWING_MARGIN_MASK;
> -		val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
> +		val &= ~DPIO_SWING_MARGIN000_MASK;
> +		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
>  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c9d77d3..c5c88127 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  
>  	for (i = 0; i < 4; i++) {
>  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> -		val &= ~DPIO_SWING_MARGIN_MASK;
> -		val |= 102 << DPIO_SWING_MARGIN_SHIFT;
> +		val &= ~DPIO_SWING_MARGIN000_MASK;
> +		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
>  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
>  	}
>  

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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Re: [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:05 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Just an attempt to frob these bits. Apparently we should not need to
> touch them (apart from maybe making sure the override is disabled so
> that the hardware automagically does the right thing).
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c   | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++++
>  3 files changed, 58 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a7bc22..d246609 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -758,6 +758,8 @@ enum punit_power_well {
>  #define _VLV_PCS_DW0_CH1		0x8400
>  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
>  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
>  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>  
>  #define _VLV_PCS01_DW0_CH0		0x200
> @@ -834,8 +836,18 @@ enum punit_power_well {
>  
>  #define _VLV_PCS_DW11_CH0		0x822c
>  #define _VLV_PCS_DW11_CH1		0x842c
> +#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
>  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
>  
> +#define _VLV_PCS01_DW11_CH0		0x022c
> +#define _VLV_PCS23_DW11_CH0		0x042c
> +#define _VLV_PCS01_DW11_CH1		0x262c
> +#define _VLV_PCS23_DW11_CH1		0x282c
> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
>  #define _VLV_PCS_DW12_CH0		0x8230
>  #define _VLV_PCS_DW12_CH1		0x8430
>  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c59e8fc..814a950 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* TX FIFO reset source */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> +	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>  	/* Deassert soft data lane reset*/
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index cda6506..47430d5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> +	/* TX FIFO reset source */
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> +	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> +
>  	/* Deassert soft data lane reset*/
>  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
>  	val |= CHV_PCS_REQ_SOFTRESET_EN;

Did this actually make a difference?  Would be nice to get some
clarification from the phy guys on this and update our docs...

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 27/40] drm/i915: Split a few long debug prints

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:18 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Split some WM debug prints to multiple lines. This shouldn't hurt
> grappability since the important part is at the start and the rest
> is just repeated stuff for each pipe.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f0516a7..cb0b4b4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1345,7 +1345,8 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
>  		plane_sr = cursor_sr = 0;
>  	}
>  
> -	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
> +		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
>  		      planea_wm, cursora_wm,
>  		      planeb_wm, cursorb_wm,
>  		      plane_sr, cursor_sr);
> @@ -1397,7 +1398,8 @@ static void g4x_update_wm(struct drm_crtc *crtc)
>  		plane_sr = cursor_sr = 0;
>  	}
>  
> -	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
> +		      "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
>  		      planea_wm, cursora_wm,
>  		      planeb_wm, cursorb_wm,
>  		      plane_sr, cursor_sr);

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:20 +0300
ville.syrjala@linux.intel.com wrote:

> From: Kenneth Graunke <kenneth@whitecape.org>
> 
> We'll want to reuse this for a workaround.
> 
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 36 ++++++++++++++++++++-------------
>  1 file changed, 22 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2faef26..97796b1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
>  }
>  
>  static int
> +gen8_emit_pipe_control(struct intel_engine_cs *ring,
> +		       u32 flags, u32 scratch_addr)
> +{
> +	int ret;
> +
> +	ret = intel_ring_begin(ring, 6);
> +	if (ret)
> +		return ret;
> +
> +	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> +	intel_ring_emit(ring, flags);
> +	intel_ring_emit(ring, scratch_addr);
> +	intel_ring_emit(ring, 0);
> +	intel_ring_emit(ring, 0);
> +	intel_ring_emit(ring, 0);
> +	intel_ring_advance(ring);
> +
> +	return 0;
> +}
> +
> +static int
>  gen8_render_ring_flush(struct intel_engine_cs *ring,
>  		       u32 invalidate_domains, u32 flush_domains)
>  {
> @@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
>  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
>  	}
>  
> -	ret = intel_ring_begin(ring, 6);
> -	if (ret)
> -		return ret;
> -
> -	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> -	intel_ring_emit(ring, flags);
> -	intel_ring_emit(ring, scratch_addr);
> -	intel_ring_emit(ring, 0);
> -	intel_ring_emit(ring, 0);
> -	intel_ring_emit(ring, 0);
> -	intel_ring_advance(ring);
> -
> -	return 0;
> -
> +	return gen8_emit_pipe_control(ring, flags, scratch_addr);
>  }
>  
>  static void ring_write_tail(struct intel_engine_cs *ring,

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

[Jesse Barnes]

On Sat, 28 Jun 2014 02:04:25 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CHV supports DP training pattern 3. Add the required stuff.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
>  2 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85b59c4..8debe61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3515,6 +3515,8 @@ enum punit_power_well {
>  #define   DP_LINK_TRAIN_OFF		(3 << 28)
>  #define   DP_LINK_TRAIN_MASK		(3 << 28)
>  #define   DP_LINK_TRAIN_SHIFT		28
> +#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
> +#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
>  
>  /* CPT Link training mode */
>  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 739dc43..a825ff1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		}
>  
>  	} else {
> -		*DP &= ~DP_LINK_TRAIN_MASK;
> +		if (IS_CHERRYVIEW(dev))
> +			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> +		else
> +			*DP &= ~DP_LINK_TRAIN_MASK;
>  
>  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
>  		case DP_TRAINING_PATTERN_DISABLE:
> @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  			*DP |= DP_LINK_TRAIN_PAT_2;
>  			break;
>  		case DP_TRAINING_PATTERN_3:
> -			DRM_ERROR("DP training pattern 3 not supported\n");
> -			*DP |= DP_LINK_TRAIN_PAT_2;
> +			if (IS_CHERRYVIEW(dev)) {
> +				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> +			} else {
> +				DRM_ERROR("DP training pattern 3 not supported\n");
> +				*DP |= DP_LINK_TRAIN_PAT_2;
> +			}
>  			break;
>  		}
>  	}
> @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
>  	} else {
> -		DP &= ~DP_LINK_TRAIN_MASK;
> +		if (IS_CHERRYVIEW(dev))
> +			DP &= ~DP_LINK_TRAIN_MASK_CHV;
> +		else
> +			DP &= ~DP_LINK_TRAIN_MASK;
>  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
>  	}
>  	POSTING_READ(intel_dp->output_reg);

I guess we could have a whole IS_CHV block, but that would probably add
more code than it saved...

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
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Re: [PATCH 06/40] drm/i915: Add cdclk change support for chv

[Daniel Vetter]

On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:03:57 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Looks like the Punit is supposed to support the 400MHz cdclk directly on
> > chv, so we don't need the vlv tricks.
> > 
> > FIXME: Punit doesn't seem ready for this yet on current hw
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  4 +++
> >  drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++--
> >  2 files changed, 52 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f156591..e296312 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -491,6 +491,10 @@
> >  #define BUNIT_REG_BISOC				0x11
> >  
> >  #define PUNIT_REG_DSPFREQ			0x36
> > +#define   DSPFREQSTAT_SHIFT_CHV			24
> > +#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> > +#define   DSPFREQGUAR_SHIFT_CHV			8
> > +#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
> >  #define   DSPFREQSTAT_SHIFT			30
> >  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> >  #define   DSPFREQGUAR_SHIFT			14
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 99c10d1..9af1d13 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	vlv_update_cdclk(dev);
> >  }
> >  
> > +static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 val, cmd;
> > +
> > +	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> > +
> > +	switch (cdclk) {
> > +	case 400000:
> > +		cmd = 3;
> > +		break;
> > +	case 333333:
> > +	case 320000:
> > +		cmd = 2;
> > +		break;
> > +	case 266667:
> > +		cmd = 1;
> > +		break;
> > +	case 200000:
> > +		cmd = 0;
> > +		break;
> > +	default:
> > +		WARN_ON(1);
> > +		return;
> > +	}
> > +
> > +	mutex_lock(&dev_priv->rps.hw_lock);
> > +	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> > +	val &= ~DSPFREQGUAR_MASK_CHV;
> > +	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> > +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> > +	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> > +		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> > +		     50)) {
> > +		DRM_ERROR("timed out waiting for CDclk change\n");
> > +	}
> > +	mutex_unlock(&dev_priv->rps.hw_lock);
> > +
> > +	vlv_update_cdclk(dev);
> > +}
> > +
> >  static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> >  				 int max_pixclk)
> >  {
> > @@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> >  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> >  
> > -	if (req_cdclk != dev_priv->vlv_cdclk_freq)
> > -		valleyview_set_cdclk(dev, req_cdclk);
> > +	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > +		if (IS_CHERRYVIEW(dev))
> > +			cherryview_set_cdclk(dev, req_cdclk);
> > +		else
> > +			valleyview_set_cdclk(dev, req_cdclk);
> > +	}
> > +
> >  	modeset_update_crtc_power_domains(dev);
> >  }
> >  
> 
> Which doc has these Punit commands?  I'm assuming you have them
> correct, but a ref would be good if we don't already have one.

Yeah I think I'll hold off on this until the doc has diffused better. For
byt this was too much fun with jumping back&forth a few times ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

[Daniel Vetter]

On Tue, Jul 29, 2014 at 09:59:53AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:20 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Kenneth Graunke <kenneth@whitecape.org>
> > 
> > We'll want to reuse this for a workaround.
> > 
> > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 36 ++++++++++++++++++++-------------
> >  1 file changed, 22 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 2faef26..97796b1 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
> >  }
> >  
> >  static int
> > +gen8_emit_pipe_control(struct intel_engine_cs *ring,
> > +		       u32 flags, u32 scratch_addr)
> > +{
> > +	int ret;
> > +
> > +	ret = intel_ring_begin(ring, 6);
> > +	if (ret)
> > +		return ret;
> > +
> > +	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> > +	intel_ring_emit(ring, flags);
> > +	intel_ring_emit(ring, scratch_addr);
> > +	intel_ring_emit(ring, 0);
> > +	intel_ring_emit(ring, 0);
> > +	intel_ring_emit(ring, 0);
> > +	intel_ring_advance(ring);
> > +
> > +	return 0;
> > +}
> > +
> > +static int
> >  gen8_render_ring_flush(struct intel_engine_cs *ring,
> >  		       u32 invalidate_domains, u32 flush_domains)
> >  {
> > @@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
> >  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> >  	}
> >  
> > -	ret = intel_ring_begin(ring, 6);
> > -	if (ret)
> > -		return ret;
> > -
> > -	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> > -	intel_ring_emit(ring, flags);
> > -	intel_ring_emit(ring, scratch_addr);
> > -	intel_ring_emit(ring, 0);
> > -	intel_ring_emit(ring, 0);
> > -	intel_ring_emit(ring, 0);
> > -	intel_ring_advance(ring);
> > -
> > -	return 0;
> > -
> > +	return gen8_emit_pipe_control(ring, flags, scratch_addr);
> >  }
> >  
> >  static void ring_write_tail(struct intel_engine_cs *ring,
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Aside: checkpatch complains about this since it makes it harder to grep
for dmesg noise. But I guess if 3 people here like it I should merge it
;-)

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

[Daniel Vetter]

On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:25 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > CHV supports DP training pattern 3. Add the required stuff.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  2 ++
> >  drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
> >  2 files changed, 16 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 85b59c4..8debe61 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3515,6 +3515,8 @@ enum punit_power_well {
> >  #define   DP_LINK_TRAIN_OFF		(3 << 28)
> >  #define   DP_LINK_TRAIN_MASK		(3 << 28)
> >  #define   DP_LINK_TRAIN_SHIFT		28
> > +#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
> > +#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
> >  
> >  /* CPT Link training mode */
> >  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 739dc43..a825ff1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  		}
> >  
> >  	} else {
> > -		*DP &= ~DP_LINK_TRAIN_MASK;
> > +		if (IS_CHERRYVIEW(dev))
> > +			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > +		else
> > +			*DP &= ~DP_LINK_TRAIN_MASK;
> >  
> >  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> >  		case DP_TRAINING_PATTERN_DISABLE:
> > @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> >  			*DP |= DP_LINK_TRAIN_PAT_2;
> >  			break;
> >  		case DP_TRAINING_PATTERN_3:
> > -			DRM_ERROR("DP training pattern 3 not supported\n");
> > -			*DP |= DP_LINK_TRAIN_PAT_2;
> > +			if (IS_CHERRYVIEW(dev)) {
> > +				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > +			} else {
> > +				DRM_ERROR("DP training pattern 3 not supported\n");
> > +				*DP |= DP_LINK_TRAIN_PAT_2;
> > +			}
> >  			break;
> >  		}
> >  	}
> > @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> >  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
> >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
> >  	} else {
> > -		DP &= ~DP_LINK_TRAIN_MASK;
> > +		if (IS_CHERRYVIEW(dev))
> > +			DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > +		else
> > +			DP &= ~DP_LINK_TRAIN_MASK;
> >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
> >  	}
> >  	POSTING_READ(intel_dp->output_reg);
> 
> I guess we could have a whole IS_CHV block, but that would probably add
> more code than it saved...
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

This won't do a hole lot without adding HBR2 support ...  Queued for
-next anyway, thanks for the patch.
-Daniel
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

[Daniel Vetter]

On Mon, Jun 30, 2014 at 02:52:12PM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:28 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > When switching from one pipe to another, the power sequencer of the new
> > pipe seems to need a bit of kicking to lock into the port. Even the vdd
> > force bit doesn't work before the power sequencer has been sufficiently
> > kicked, so this must be done even before any AUX transactions.
> > 
> > This sequence has been found to do the trick:
> > 1) enable port with idle pattern
> > 2) enable the power sequencer
> > 3) proceed with link training
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++--
> >  1 file changed, 32 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 65ab54c..07b0320 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
> >  	mutex_unlock(&dev_priv->dpio_lock);
> >  }
> >  
> > +static void intel_edp_init_train(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > +	struct drm_device *dev = intel_dig_port->base.base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	if (!is_edp(intel_dp))
> > +		return;

This changes the order of events as observed by the sink, so I really
wonder why this is edp specific?

We do have bug reports about external DP monitors not waking up from the
sink_dpms call properly ...
-Daniel

> > +
> > +	/*
> > +	 * Need to enable the port with idle pattern to allow the power
> > +	 * sequencer to lock into the port. Otherwise the power sequencer
> > +	 * (including vdd force bit!) doesn't work on this port.
> > +	 */
> > +	if (IS_VALLEYVIEW(dev)) {
> > +		intel_dp->DP |= DP_PORT_EN;
> > +
> > +		if (IS_CHERRYVIEW(dev))
> > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > +		else
> > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> > +		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> > +
> > +		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
> > +		POSTING_READ(intel_dp->output_reg);
> > +	}
> > +
> > +	intel_edp_panel_on(intel_dp);
> > +	edp_panel_vdd_off(intel_dp, true);
> > +}
> > +
> >  static void intel_enable_dp(struct intel_encoder *encoder)
> >  {
> >  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > @@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> >  		return;
> >  
> >  	intel_edp_panel_vdd_on(intel_dp);
> > +	intel_edp_init_train(intel_dp);
> >  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> >  	intel_dp_start_link_train(intel_dp);
> > -	intel_edp_panel_on(intel_dp);
> > -	edp_panel_vdd_off(intel_dp, true);
> >  	intel_dp_complete_link_train(intel_dp);
> >  	intel_dp_stop_link_train(intel_dp);
> >  }
> 
> Yeah I think this matches the doc too.  I never pushed this change
> because I could never find anything that it actually fixed.
> 
> I guess you have something now though!
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 06/40] drm/i915: Add cdclk change support for chv

[Jesse Barnes]

On Tue, 29 Jul 2014 19:59:26 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
> > On Sat, 28 Jun 2014 02:03:57 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Looks like the Punit is supposed to support the 400MHz cdclk directly on
> > > chv, so we don't need the vlv tricks.
> > > 
> > > FIXME: Punit doesn't seem ready for this yet on current hw
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h      |  4 +++
> > >  drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++--
> > >  2 files changed, 52 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f156591..e296312 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -491,6 +491,10 @@
> > >  #define BUNIT_REG_BISOC				0x11
> > >  
> > >  #define PUNIT_REG_DSPFREQ			0x36
> > > +#define   DSPFREQSTAT_SHIFT_CHV			24
> > > +#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> > > +#define   DSPFREQGUAR_SHIFT_CHV			8
> > > +#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
> > >  #define   DSPFREQSTAT_SHIFT			30
> > >  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> > >  #define   DSPFREQGUAR_SHIFT			14
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 99c10d1..9af1d13 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> > >  	vlv_update_cdclk(dev);
> > >  }
> > >  
> > > +static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
> > > +{
> > > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > > +	u32 val, cmd;
> > > +
> > > +	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> > > +
> > > +	switch (cdclk) {
> > > +	case 400000:
> > > +		cmd = 3;
> > > +		break;
> > > +	case 333333:
> > > +	case 320000:
> > > +		cmd = 2;
> > > +		break;
> > > +	case 266667:
> > > +		cmd = 1;
> > > +		break;
> > > +	case 200000:
> > > +		cmd = 0;
> > > +		break;
> > > +	default:
> > > +		WARN_ON(1);
> > > +		return;
> > > +	}
> > > +
> > > +	mutex_lock(&dev_priv->rps.hw_lock);
> > > +	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> > > +	val &= ~DSPFREQGUAR_MASK_CHV;
> > > +	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> > > +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> > > +	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> > > +		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> > > +		     50)) {
> > > +		DRM_ERROR("timed out waiting for CDclk change\n");
> > > +	}
> > > +	mutex_unlock(&dev_priv->rps.hw_lock);
> > > +
> > > +	vlv_update_cdclk(dev);
> > > +}
> > > +
> > >  static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> > >  				 int max_pixclk)
> > >  {
> > > @@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> > >  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> > >  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> > >  
> > > -	if (req_cdclk != dev_priv->vlv_cdclk_freq)
> > > -		valleyview_set_cdclk(dev, req_cdclk);
> > > +	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > > +		if (IS_CHERRYVIEW(dev))
> > > +			cherryview_set_cdclk(dev, req_cdclk);
> > > +		else
> > > +			valleyview_set_cdclk(dev, req_cdclk);
> > > +	}
> > > +
> > >  	modeset_update_crtc_power_domains(dev);
> > >  }
> > >  
> > 
> > Which doc has these Punit commands?  I'm assuming you have them
> > correct, but a ref would be good if we don't already have one.
> 
> Yeah I think I'll hold off on this until the doc has diffused better. For
> byt this was too much fun with jumping back&forth a few times ...

Well, the next patch disables this until we can test anyway, so it
should be fine to add and fixup/add the doc link later.

-- 
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

[Ville Syrjälä]

On Tue, Jul 29, 2014 at 08:04:59PM +0200, Daniel Vetter wrote:
> On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote:
> > On Sat, 28 Jun 2014 02:04:25 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > CHV supports DP training pattern 3. Add the required stuff.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h |  2 ++
> > >  drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
> > >  2 files changed, 16 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 85b59c4..8debe61 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3515,6 +3515,8 @@ enum punit_power_well {
> > >  #define   DP_LINK_TRAIN_OFF		(3 << 28)
> > >  #define   DP_LINK_TRAIN_MASK		(3 << 28)
> > >  #define   DP_LINK_TRAIN_SHIFT		28
> > > +#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
> > > +#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
> > >  
> > >  /* CPT Link training mode */
> > >  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 739dc43..a825ff1 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > >  		}
> > >  
> > >  	} else {
> > > -		*DP &= ~DP_LINK_TRAIN_MASK;
> > > +		if (IS_CHERRYVIEW(dev))
> > > +			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > +		else
> > > +			*DP &= ~DP_LINK_TRAIN_MASK;
> > >  
> > >  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> > >  		case DP_TRAINING_PATTERN_DISABLE:
> > > @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > >  			*DP |= DP_LINK_TRAIN_PAT_2;
> > >  			break;
> > >  		case DP_TRAINING_PATTERN_3:
> > > -			DRM_ERROR("DP training pattern 3 not supported\n");
> > > -			*DP |= DP_LINK_TRAIN_PAT_2;
> > > +			if (IS_CHERRYVIEW(dev)) {
> > > +				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > > +			} else {
> > > +				DRM_ERROR("DP training pattern 3 not supported\n");
> > > +				*DP |= DP_LINK_TRAIN_PAT_2;
> > > +			}
> > >  			break;
> > >  		}
> > >  	}
> > > @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> > >  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
> > >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
> > >  	} else {
> > > -		DP &= ~DP_LINK_TRAIN_MASK;
> > > +		if (IS_CHERRYVIEW(dev))
> > > +			DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > +		else
> > > +			DP &= ~DP_LINK_TRAIN_MASK;
> > >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
> > >  	}
> > >  	POSTING_READ(intel_dp->output_reg);
> > 
> > I guess we could have a whole IS_CHV block, but that would probably add
> > more code than it saved...
> > 
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> This won't do a hole lot without adding HBR2 support ...  Queued for
> -next anyway, thanks for the patch.

What else is missing for HBR2?

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 06/40] drm/i915: Add cdclk change support for chv

[Ville Syrjälä]

On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:03:57 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Looks like the Punit is supposed to support the 400MHz cdclk directly on
> > chv, so we don't need the vlv tricks.
> > 
> > FIXME: Punit doesn't seem ready for this yet on current hw
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  4 +++
> >  drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++--
> >  2 files changed, 52 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f156591..e296312 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -491,6 +491,10 @@
> >  #define BUNIT_REG_BISOC				0x11
> >  
> >  #define PUNIT_REG_DSPFREQ			0x36
> > +#define   DSPFREQSTAT_SHIFT_CHV			24
> > +#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> > +#define   DSPFREQGUAR_SHIFT_CHV			8
> > +#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
> >  #define   DSPFREQSTAT_SHIFT			30
> >  #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> >  #define   DSPFREQGUAR_SHIFT			14
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 99c10d1..9af1d13 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4529,6 +4529,47 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	vlv_update_cdclk(dev);
> >  }
> >  
> > +static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 val, cmd;
> > +
> > +	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> > +
> > +	switch (cdclk) {
> > +	case 400000:
> > +		cmd = 3;
> > +		break;
> > +	case 333333:
> > +	case 320000:
> > +		cmd = 2;
> > +		break;
> > +	case 266667:
> > +		cmd = 1;
> > +		break;
> > +	case 200000:
> > +		cmd = 0;
> > +		break;
> > +	default:
> > +		WARN_ON(1);
> > +		return;
> > +	}
> > +
> > +	mutex_lock(&dev_priv->rps.hw_lock);
> > +	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> > +	val &= ~DSPFREQGUAR_MASK_CHV;
> > +	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> > +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> > +	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> > +		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
> > +		     50)) {
> > +		DRM_ERROR("timed out waiting for CDclk change\n");
> > +	}
> > +	mutex_unlock(&dev_priv->rps.hw_lock);
> > +
> > +	vlv_update_cdclk(dev);
> > +}
> > +
> >  static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> >  				 int max_pixclk)
> >  {
> > @@ -4597,8 +4638,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> >  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> >  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> >  
> > -	if (req_cdclk != dev_priv->vlv_cdclk_freq)
> > -		valleyview_set_cdclk(dev, req_cdclk);
> > +	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > +		if (IS_CHERRYVIEW(dev))
> > +			cherryview_set_cdclk(dev, req_cdclk);
> > +		else
> > +			valleyview_set_cdclk(dev, req_cdclk);
> > +	}
> > +
> >  	modeset_update_crtc_power_domains(dev);
> >  }
> >  
> 
> Which doc has these Punit commands?  I'm assuming you have them
> correct, but a ref would be good if we don't already have one.

These were in the punit has. The display cluster has still had the old
vlv information last I looked.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> There should probably be a JIRA for this too so QA can verify once we
> have updated punit support.
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits

[Daniel Vetter]

On Tue, Jul 29, 2014 at 09:55:39AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:03 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > CHV display PHY registes have two swing margin/deemph settings. Make it
> > clear which ones we're using.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 8 ++++++--
> >  drivers/gpu/drm/i915/intel_dp.c   | 4 ++--
> >  drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
> >  3 files changed, 10 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e296312..ba90320 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -831,8 +831,8 @@ enum punit_power_well {
> >  
> >  #define _VLV_TX_DW2_CH0			0x8288
> >  #define _VLV_TX_DW2_CH1			0x8488
> > -#define   DPIO_SWING_MARGIN_SHIFT	16
> > -#define   DPIO_SWING_MARGIN_MASK	(0xff << DPIO_SWING_MARGIN_SHIFT)
> > +#define   DPIO_SWING_MARGIN000_SHIFT	16
> > +#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
> >  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> >  #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
> >  
> > @@ -840,12 +840,16 @@ enum punit_power_well {
> >  #define _VLV_TX_DW3_CH1			0x848c
> >  /* The following bit for CHV phy */
> >  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
> > +#define   DPIO_SWING_MARGIN101_SHIFT	16
> > +#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
> >  #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
> >  
> >  #define _VLV_TX_DW4_CH0			0x8290
> >  #define _VLV_TX_DW4_CH1			0x8490
> >  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
> >  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> > +#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
> > +#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> >  #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
> >  
> >  #define _VLV_TX3_DW4_CH0		0x690
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index e272f92..4457f8f 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
> >  	/* Program swing margin */
> >  	for (i = 0; i < 4; i++) {
> >  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> > -		val &= ~DPIO_SWING_MARGIN_MASK;
> > -		val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
> > +		val &= ~DPIO_SWING_MARGIN000_MASK;
> > +		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
> >  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> >  	}
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index c9d77d3..c5c88127 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  
> >  	for (i = 0; i < 4; i++) {
> >  		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
> > -		val &= ~DPIO_SWING_MARGIN_MASK;
> > -		val |= 102 << DPIO_SWING_MARGIN_SHIFT;
> > +		val &= ~DPIO_SWING_MARGIN000_MASK;
> > +		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
> >  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
> >  	}
> >  
> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Ok, pulled in the pile of patches Jesse just reviewed.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV

[Daniel Vetter]

On Tue, Jul 29, 2014 at 09:34:34PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 29, 2014 at 08:04:59PM +0200, Daniel Vetter wrote:
> > On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote:
> > > On Sat, 28 Jun 2014 02:04:25 +0300
> > > ville.syrjala@linux.intel.com wrote:
> > > 
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > CHV supports DP training pattern 3. Add the required stuff.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h |  2 ++
> > > >  drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
> > > >  2 files changed, 16 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 85b59c4..8debe61 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -3515,6 +3515,8 @@ enum punit_power_well {
> > > >  #define   DP_LINK_TRAIN_OFF		(3 << 28)
> > > >  #define   DP_LINK_TRAIN_MASK		(3 << 28)
> > > >  #define   DP_LINK_TRAIN_SHIFT		28
> > > > +#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)
> > > > +#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))
> > > >  
> > > >  /* CPT Link training mode */
> > > >  #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 739dc43..a825ff1 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > >  		}
> > > >  
> > > >  	} else {
> > > > -		*DP &= ~DP_LINK_TRAIN_MASK;
> > > > +		if (IS_CHERRYVIEW(dev))
> > > > +			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > > +		else
> > > > +			*DP &= ~DP_LINK_TRAIN_MASK;
> > > >  
> > > >  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> > > >  		case DP_TRAINING_PATTERN_DISABLE:
> > > > @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > >  			*DP |= DP_LINK_TRAIN_PAT_2;
> > > >  			break;
> > > >  		case DP_TRAINING_PATTERN_3:
> > > > -			DRM_ERROR("DP training pattern 3 not supported\n");
> > > > -			*DP |= DP_LINK_TRAIN_PAT_2;
> > > > +			if (IS_CHERRYVIEW(dev)) {
> > > > +				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > > > +			} else {
> > > > +				DRM_ERROR("DP training pattern 3 not supported\n");
> > > > +				*DP |= DP_LINK_TRAIN_PAT_2;
> > > > +			}
> > > >  			break;
> > > >  		}
> > > >  	}
> > > > @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> > > >  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
> > > >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
> > > >  	} else {
> > > > -		DP &= ~DP_LINK_TRAIN_MASK;
> > > > +		if (IS_CHERRYVIEW(dev))
> > > > +			DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > > +		else
> > > > +			DP &= ~DP_LINK_TRAIN_MASK;
> > > >  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
> > > >  	}
> > > >  	POSTING_READ(intel_dp->output_reg);
> > > 
> > > I guess we could have a whole IS_CHV block, but that would probably add
> > > more code than it saved...
> > > 
> > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > This won't do a hole lot without adding HBR2 support ...  Queued for
> > -next anyway, thanks for the patch.
> 
> What else is missing for HBR2?

Adjusting the check in intel_dp_max_link_bw. At least I haven't seen a
patch for that yet. Maybe missed it.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

[Ville Syrjälä]

On Tue, Jul 29, 2014 at 08:06:57PM +0200, Daniel Vetter wrote:
> On Mon, Jun 30, 2014 at 02:52:12PM -0700, Jesse Barnes wrote:
> > On Sat, 28 Jun 2014 02:04:28 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > When switching from one pipe to another, the power sequencer of the new
> > > pipe seems to need a bit of kicking to lock into the port. Even the vdd
> > > force bit doesn't work before the power sequencer has been sufficiently
> > > kicked, so this must be done even before any AUX transactions.
> > > 
> > > This sequence has been found to do the trick:
> > > 1) enable port with idle pattern
> > > 2) enable the power sequencer
> > > 3) proceed with link training
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++--
> > >  1 file changed, 32 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 65ab54c..07b0320 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
> > >  	mutex_unlock(&dev_priv->dpio_lock);
> > >  }
> > >  
> > > +static void intel_edp_init_train(struct intel_dp *intel_dp)
> > > +{
> > > +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > +	struct drm_device *dev = intel_dig_port->base.base.dev;
> > > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > > +
> > > +	if (!is_edp(intel_dp))
> > > +		return;
> 
> This changes the order of events as observed by the sink, so I really
> wonder why this is edp specific?

It's not really. I need to kick the power sequencer for regular DP ports
too (in a later patch), and recently I started to wonder if we also need
it for HDMI ports but I didn't test that theory yet.

Based on my observations there are several problems intermingled here:
1. the power sequencer prevents the port from starting up until the
   power up sequence has finished
2. vdd force bit doesn't work until the power sequencer has finished
3. the power sequencer won't finish the power up sequence unless idle
   pattern is used

So the fix is to enable the port with idle pattern and enable the power
sequencer even before doing any aux transactions (including the sink
dpms write).

Once the power sequencer has finished powering up on to the port once.
the vdd force bit will keep working on the port even if the port and
power sequencer are later disabled. Also iirc the power sequencer will
no longer prevent the port from starting up even if the power sequencer
is left disabled when re-enabling the port later. But the same problem
will reappear when we change the pipe->port mapping, and then we need
to kick the power sequencer again.

> We do have bug reports about external DP monitors not waking up from the
> sink_dpms call properly ...

On vlv or something else? I'm not quite sure if the same problems would
be possible on other platforms since they only have one power sequencer.
But maybe that too locks into the port and would need a similar kick.

But IIRC on PCH platforms the spec says that we must enable the port
with training pattern 1. So the use of idle pattern would at least go
against the spec. Which is why I left that part as vlv/chv specific.

> -Daniel
> 
> > > +
> > > +	/*
> > > +	 * Need to enable the port with idle pattern to allow the power
> > > +	 * sequencer to lock into the port. Otherwise the power sequencer
> > > +	 * (including vdd force bit!) doesn't work on this port.
> > > +	 */
> > > +	if (IS_VALLEYVIEW(dev)) {
> > > +		intel_dp->DP |= DP_PORT_EN;
> > > +
> > > +		if (IS_CHERRYVIEW(dev))
> > > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > +		else
> > > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> > > +		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> > > +
> > > +		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
> > > +		POSTING_READ(intel_dp->output_reg);
> > > +	}
> > > +
> > > +	intel_edp_panel_on(intel_dp);
> > > +	edp_panel_vdd_off(intel_dp, true);
> > > +}
> > > +
> > >  static void intel_enable_dp(struct intel_encoder *encoder)
> > >  {
> > >  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > > @@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> > >  		return;
> > >  
> > >  	intel_edp_panel_vdd_on(intel_dp);
> > > +	intel_edp_init_train(intel_dp);
> > >  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > >  	intel_dp_start_link_train(intel_dp);
> > > -	intel_edp_panel_on(intel_dp);
> > > -	edp_panel_vdd_off(intel_dp, true);
> > >  	intel_dp_complete_link_train(intel_dp);
> > >  	intel_dp_stop_link_train(intel_dp);
> > >  }
> > 
> > Yeah I think this matches the doc too.  I never pushed this change
> > because I could never find anything that it actually fixed.
> > 
> > I guess you have something now though!
> > 
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > -- 
> > Jesse Barnes, Intel Open Source Technology Center
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes

[Daniel Vetter]

On Tue, Jul 29, 2014 at 10:18:46PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 29, 2014 at 08:06:57PM +0200, Daniel Vetter wrote:
> > On Mon, Jun 30, 2014 at 02:52:12PM -0700, Jesse Barnes wrote:
> > > On Sat, 28 Jun 2014 02:04:28 +0300
> > > ville.syrjala@linux.intel.com wrote:
> > > 
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > When switching from one pipe to another, the power sequencer of the new
> > > > pipe seems to need a bit of kicking to lock into the port. Even the vdd
> > > > force bit doesn't work before the power sequencer has been sufficiently
> > > > kicked, so this must be done even before any AUX transactions.
> > > > 
> > > > This sequence has been found to do the trick:
> > > > 1) enable port with idle pattern
> > > > 2) enable the power sequencer
> > > > 3) proceed with link training
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++--
> > > >  1 file changed, 32 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 65ab54c..07b0320 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -2010,6 +2010,37 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
> > > >  	mutex_unlock(&dev_priv->dpio_lock);
> > > >  }
> > > >  
> > > > +static void intel_edp_init_train(struct intel_dp *intel_dp)
> > > > +{
> > > > +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> > > > +	struct drm_device *dev = intel_dig_port->base.base.dev;
> > > > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > > > +
> > > > +	if (!is_edp(intel_dp))
> > > > +		return;
> > 
> > This changes the order of events as observed by the sink, so I really
> > wonder why this is edp specific?
> 
> It's not really. I need to kick the power sequencer for regular DP ports
> too (in a later patch), and recently I started to wonder if we also need
> it for HDMI ports but I didn't test that theory yet.
> 
> Based on my observations there are several problems intermingled here:
> 1. the power sequencer prevents the port from starting up until the
>    power up sequence has finished
> 2. vdd force bit doesn't work until the power sequencer has finished
> 3. the power sequencer won't finish the power up sequence unless idle
>    pattern is used
> 
> So the fix is to enable the port with idle pattern and enable the power
> sequencer even before doing any aux transactions (including the sink
> dpms write).
> 
> Once the power sequencer has finished powering up on to the port once.
> the vdd force bit will keep working on the port even if the port and
> power sequencer are later disabled. Also iirc the power sequencer will
> no longer prevent the port from starting up even if the power sequencer
> is left disabled when re-enabling the port later. But the same problem
> will reappear when we change the pipe->port mapping, and then we need
> to kick the power sequencer again.
> 
> > We do have bug reports about external DP monitors not waking up from the
> > sink_dpms call properly ...
> 
> On vlv or something else? I'm not quite sure if the same problems would
> be possible on other platforms since they only have one power sequencer.
> But maybe that too locks into the port and would need a similar kick.
> 
> But IIRC on PCH platforms the spec says that we must enable the port
> with training pattern 1. So the use of idle pattern would at least go
> against the spec. Which is why I left that part as vlv/chv specific.

Hm ... tricky. And especially since it seems to be required only once. I'm
just concerned about the slight behavioural difference between the general
dp link enabling where we do the sink dpms aux transaction first, then
start with link training. But on vlv/chv here we first kick the port a bit
and enable the idle pattern. If now a few displays don't like this or
require this we have a problem.

In general I really want us to try as hard as possible to have 0
differences in sink-visible behaviour. DP is simply too fickle imo. But if
there's nothing we can do I guess good explanations in commit message and
comments is all I can ask for. I.e. something like the above should go
into the commit message and maybe we should make the comment a bit more
dangerously-sounding.
-Daniel
> 
> > -Daniel
> > 
> > > > +
> > > > +	/*
> > > > +	 * Need to enable the port with idle pattern to allow the power
> > > > +	 * sequencer to lock into the port. Otherwise the power sequencer
> > > > +	 * (including vdd force bit!) doesn't work on this port.
> > > > +	 */
> > > > +	if (IS_VALLEYVIEW(dev)) {
> > > > +		intel_dp->DP |= DP_PORT_EN;
> > > > +
> > > > +		if (IS_CHERRYVIEW(dev))
> > > > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > > +		else
> > > > +			intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> > > > +		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> > > > +
> > > > +		I915_WRITE(intel_dp->output_reg, intel_dp->DP);
> > > > +		POSTING_READ(intel_dp->output_reg);
> > > > +	}
> > > > +
> > > > +	intel_edp_panel_on(intel_dp);
> > > > +	edp_panel_vdd_off(intel_dp, true);
> > > > +}
> > > > +
> > > >  static void intel_enable_dp(struct intel_encoder *encoder)
> > > >  {
> > > >  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > > > @@ -2021,10 +2052,9 @@ static void intel_enable_dp(struct intel_encoder *encoder)
> > > >  		return;
> > > >  
> > > >  	intel_edp_panel_vdd_on(intel_dp);
> > > > +	intel_edp_init_train(intel_dp);
> > > >  	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > > >  	intel_dp_start_link_train(intel_dp);
> > > > -	intel_edp_panel_on(intel_dp);
> > > > -	edp_panel_vdd_off(intel_dp, true);
> > > >  	intel_dp_complete_link_train(intel_dp);
> > > >  	intel_dp_stop_link_train(intel_dp);
> > > >  }
> > > 
> > > Yeah I think this matches the doc too.  I never pushed this change
> > > because I could never find anything that it actually fixed.
> > > 
> > > I guess you have something now though!
> > > 
> > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > 
> > > -- 
> > > Jesse Barnes, Intel Open Source Technology Center
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 16/40] drm/i915: Add chv_power_wells[]

[Daniel Vetter]

On Fri, Jul 11, 2014 at 02:09:40PM +0000, Barbalho, Rafael wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of ville.syrjala@linux.intel.com
> > Sent: Saturday, June 28, 2014 12:04 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 16/40] drm/i915: Add chv_power_wells[]
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add chv_power_wells[] so we can start to build up the power well support
> > for chv. Just the "always on" well there initialy.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 898654f..e2b956e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6498,6 +6498,15 @@ static struct i915_power_well vlv_power_wells[] =
> > {
> >  	},
> >  };
> > 
> > +static struct i915_power_well chv_power_wells[] = {
> > +	{
> > +		.name = "always-on",
> > +		.always_on = 1,
> > +		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
> > +		.ops = &i9xx_always_on_power_well_ops,
> > +	},
> > +};
> > +
> >  static struct i915_power_well *lookup_power_well(struct drm_i915_private
> > *dev_priv,
> >  						 enum punit_power_well
> > power_well_id)
> >  {
> > @@ -6534,6 +6543,8 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> >  	} else if (IS_BROADWELL(dev_priv->dev)) {
> >  		set_power_wells(power_domains, bdw_power_wells);
> >  		hsw_pwr = power_domains;
> > +	} else if (IS_CHERRYVIEW(dev_priv->dev)) {
> > +		set_power_wells(power_domains, chv_power_wells);
> >  	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
> >  		set_power_wells(power_domains, vlv_power_wells);
> >  	} else {
> > --
> > 1.8.5.5
> > 
> 
> Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>

Ok, pulled this one in too to undo my giant merge fumble. My apologies to
everyone for the mess.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 32/40] drm/i915: Hack to tie both common lanes
> together on chv
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It looks like frobbing the cmnreset line on pne PHY disturbs the other
> PHY on chv. The result is a black screen. On HDMI it's just a flash of
> black, but DP usually falls over and can't get back up.
> 
> As a workaround set up the power domains so that both common lane
> wells power up and down together. I also tried leaving the cmnreset
> deasserted even the if the power well goes down but that didn't seem
> acceptable to the PHY.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I think we need to talk to the SoC people to figure out why we need to this. But otherwise
it's for me.

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 158c3f5..879d14c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6776,13 +6776,23 @@ static struct i915_power_well chv_power_wells[]
> = {
>  #endif
>  	{
>  		.name = "dpio-common-bc",
> -		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> +		/*
> +		 * XXX: cmnreset for one PHY seems to disturb the other.
> +		 * As a workaround keep both powered on at the same
> +		 * time for now.
> +		 */
> +		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS |
> CHV_DPIO_CMN_D_POWER_DOMAINS,
>  		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
>  		.ops = &chv_dpio_cmn_power_well_ops,
>  	},
>  	{
>  		.name = "dpio-common-d",
> -		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> +		/*
> +		 * XXX: cmnreset for one PHY seems to disturb the other.
> +		 * As a workaround keep both powered on at the same
> +		 * time for now.
> +		 */
> +		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS |
> CHV_DPIO_CMN_D_POWER_DOMAINS,
>  		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
>  		.ops = &chv_dpio_cmn_power_well_ops,
>  	},
> --
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt
> macros
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the semi-funky cmnlane assert/deassert macros with something a
> bit more conventional. Also protect the macro arguments properly (also
> for  PHY_POWERGOOD()).
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 7 ++-----
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
>  2 files changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 60dd19c..85b59c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1717,12 +1717,9 @@ enum punit_power_well {
>  #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE +
> 0x6240)
>  #define   DPLL_PORTD_READY_MASK		(0xf)
>  #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> -#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
> -				((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
> -#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
> -				((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
> +#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
>  #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
> -#define   PHY_POWERGOOD(phy)	((phy == DPIO_PHY0) ? (1<<31) :
> (1<<30))
> +#define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1<<31) :
> (1<<30))
> 
>  /*
>   * The i830 generation, in LVDS mode, defines P1 as the bit number set
> within
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 879d14c..f193d95 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6280,8 +6280,8 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>  	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> PHY_POWERGOOD(phy), 1))
>  		DRM_ERROR("Display PHY %d is not power up\n", phy);
> 
> -	I915_WRITE(DISPLAY_PHY_CONTROL,
> -		   PHY_COM_LANE_RESET_DEASSERT(phy,
> I915_READ(DISPLAY_PHY_CONTROL)));
> +	I915_WRITE(DISPLAY_PHY_CONTROL,
> I915_READ(DISPLAY_PHY_CONTROL) |
> +		   PHY_COM_LANE_RESET_DEASSERT(phy));
>  }
> 
>  static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> @@ -6301,8 +6301,8 @@ static void
> chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>  		assert_pll_disabled(dev_priv, PIPE_C);
>  	}
> 
> -	I915_WRITE(DISPLAY_PHY_CONTROL,
> -		   PHY_COM_LANE_RESET_ASSERT(phy,
> I915_READ(DISPLAY_PHY_CONTROL)));
> +	I915_WRITE(DISPLAY_PHY_CONTROL,
> I915_READ(DISPLAY_PHY_CONTROL) &
> +		   ~PHY_COM_LANE_RESET_DEASSERT(phy));
> 
>  	vlv_set_power_well(dev_priv, power_well, false);
>  }
> --
> 1.8.5.5

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>

> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 31/40] drm/i916: Init chv workarounds at render ring init

[Barbalho, Rafael]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of ville.syrjala@linux.intel.com
> Sent: Saturday, June 28, 2014 12:04 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 31/40] drm/i916: Init chv workarounds at render
> ring init
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> My bsw is an unhappy camper if we delay the workaround init until
> init_clock_gating(). Move a bunch of it to the render ring init.
> 
> FIXME: need to do this for all platforms since some of the registers
>        also get clobbered at reset. Just need to figure out which
>        registers those actually are. This patch is based on a
>        slightly educated guess, but verifying on actual hw would
>        be a good idea. Also should maybe move the init_clock_gating
>        earlier too since we set up a bunch of clock gating stuff
>        there that might be important for a properly working GT.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c         | 40 +++++++--------------------------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 40
> +++++++++++++++++++++++++++++++++
>  2 files changed, 48 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 346dced..158c3f5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5720,6 +5720,10 @@ static void valleyview_init_clock_gating(struct
> drm_device *dev)
>  	 * in the reporting of vblank events.
>  	 */
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> +
> +	/* WaDisableDopClockGating:chv (pre-production hw) */
> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }

Did you really mean to add a cherryview workaround to valleyview?

> 
>  static void cherryview_init_clock_gating(struct drm_device *dev)
> @@ -5730,49 +5734,21 @@ static void cherryview_init_clock_gating(struct
> drm_device *dev)
> 
>  	I915_WRITE(MI_ARB_VLV,
> MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> 
> -	/* WaDisablePartialInstShootdown:chv */
> -	I915_WRITE(GEN8_ROW_CHICKEN,
> -
> _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
> -
> -	/* WaDisableThreadStallDopClockGating:chv */
> -	I915_WRITE(GEN8_ROW_CHICKEN,
> -		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> -
> -	/* WaVSRefCountFullforceMissDisable:chv */
> -	/* WaDSRefCountFullforceMissDisable:chv */
> -	I915_WRITE(GEN7_FF_THREAD_MODE,
> -		   I915_READ(GEN7_FF_THREAD_MODE) &
> -		   ~(GEN8_FF_DS_REF_CNT_FFME |
> GEN7_FF_VS_REF_CNT_FFME));
> -
> -	/* WaDisableSemaphoreAndSyncFlipWait:chv */
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> -
> _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> -
>  	/* WaDisableCSUnitClockGating:chv */
>  	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> 
> +	/* WaDisableDopClockGating:chv (pre-production hw) */

Shouldn't this be WaDisableTCUnitClock gating?

> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> +
>  	/* WaDisableSDEUnitClockGating:chv */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> 
> -	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> -	I915_WRITE(HALF_SLICE_CHICKEN3,
> -
> _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> -
>  	/* WaDisableGunitClockGating:chv (pre-production hw) */
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE,
> I915_READ(VLV_GUNIT_CLOCK_GATE) |
>  		   GINT_DIS);
> -
> -	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> -
> _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> -
> -	/* WaDisableDopClockGating:chv (pre-production hw) */
> -	I915_WRITE(GEN7_ROW_CHICKEN2,
> -		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> -		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>  }
> 
>  static void g4x_init_clock_gating(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ceb1295..9e81c28 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -615,6 +615,43 @@ err:
>  	return ret;
>  }
> 

I think we can share the cherryview_init_workarounds functions with broadwell
and just call it gen8_init_workarounds with a bit of code to just enable the
cheryview functions. I'll mark down the workarounds that are shared and the ones
that are not. It will also simplify the bdw clock gating init functions.

> +static void cherryview_init_workarounds(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* WaDisablePartialInstShootdown:chv */

Applies to bdw.

> +	I915_WRITE(GEN8_ROW_CHICKEN,
> +
> _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
> +
> +	/* WaDisableThreadStallDopClockGating:chv */

Applies to bdw.

> +	I915_WRITE(GEN8_ROW_CHICKEN,
> +		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> +
> +	/* WaVSRefCountFullforceMissDisable:chv */
> +	/* WaDSRefCountFullforceMissDisable:chv */

Applies to bdw.

> +	I915_WRITE(GEN7_FF_THREAD_MODE,
> +		   I915_READ(GEN7_FF_THREAD_MODE) &
> +		   ~(GEN8_FF_DS_REF_CNT_FFME |
> GEN7_FF_VS_REF_CNT_FFME));
> +
> +	/* WaDisableSemaphoreAndSyncFlipWait:chv */

Chv specific.

> +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +
> _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> +
> +	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */

Chv specific.

> +	I915_WRITE(HALF_SLICE_CHICKEN3,
> +
> _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> +
> +	/* WaDisableFfDopClockGating:chv (pre-production hw) */

Chv specific.

> +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> +
> _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> +
> +	/* WaDisableDopClockGating:chv (pre-production hw) */

This first register write as applies to broadwell.

> +	I915_WRITE(GEN7_ROW_CHICKEN2,
> +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

I think we need a split here and add WaDisableTCUnitClockGating. This also shows up in
the init clock gating function. Do we need to have it in both places?  This second register
write also only applies to chv.

> +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> +}
> +
>  static int init_render_ring(struct intel_engine_cs *ring)
>  {
>  	struct drm_device *dev = ring->dev;
> @@ -670,6 +707,9 @@ static int init_render_ring(struct intel_engine_cs
> *ring)
>  	if (HAS_L3_DPF(dev))
>  		I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
> 
> +	if (IS_CHERRYVIEW(dev))

If we modify the function init_workaround functions then we change from IS_CHERRYVIEW
to IS_GEN8.

Thanks,
Raf

> +		cherryview_init_workarounds(dev);
> +
>  	return ret;
>  }
> 
> --
> 1.8.5.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH 31/40] drm/i916: Init chv workarounds at render ring init

[Ville Syrjälä]

On Wed, Jul 30, 2014 at 12:35:49PM +0000, Barbalho, Rafael wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of ville.syrjala@linux.intel.com
> > Sent: Saturday, June 28, 2014 12:04 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 31/40] drm/i916: Init chv workarounds at render
> > ring init
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > My bsw is an unhappy camper if we delay the workaround init until
> > init_clock_gating(). Move a bunch of it to the render ring init.
> > 
> > FIXME: need to do this for all platforms since some of the registers
> >        also get clobbered at reset. Just need to figure out which
> >        registers those actually are. This patch is based on a
> >        slightly educated guess, but verifying on actual hw would
> >        be a good idea. Also should maybe move the init_clock_gating
> >        earlier too since we set up a bunch of clock gating stuff
> >        there that might be important for a properly working GT.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c         | 40 +++++++--------------------------
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 40
> > +++++++++++++++++++++++++++++++++
> >  2 files changed, 48 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 346dced..158c3f5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5720,6 +5720,10 @@ static void valleyview_init_clock_gating(struct
> > drm_device *dev)
> >  	 * in the reporting of vblank events.
> >  	 */
> >  	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> > +
> > +	/* WaDisableDopClockGating:chv (pre-production hw) */
> > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >  }
> 
> Did you really mean to add a cherryview workaround to valleyview?

Nope. Not sure what happened with this patch.

Maybe it's best to wait and see what Arun comes up for BDW and once
that's sorted we deal with CHV (and all the other platforms).

> 
> > 
> >  static void cherryview_init_clock_gating(struct drm_device *dev)
> > @@ -5730,49 +5734,21 @@ static void cherryview_init_clock_gating(struct
> > drm_device *dev)
> > 
> >  	I915_WRITE(MI_ARB_VLV,
> > MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > 
> > -	/* WaDisablePartialInstShootdown:chv */
> > -	I915_WRITE(GEN8_ROW_CHICKEN,
> > -
> > _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
> > -
> > -	/* WaDisableThreadStallDopClockGating:chv */
> > -	I915_WRITE(GEN8_ROW_CHICKEN,
> > -		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> > -
> > -	/* WaVSRefCountFullforceMissDisable:chv */
> > -	/* WaDSRefCountFullforceMissDisable:chv */
> > -	I915_WRITE(GEN7_FF_THREAD_MODE,
> > -		   I915_READ(GEN7_FF_THREAD_MODE) &
> > -		   ~(GEN8_FF_DS_REF_CNT_FFME |
> > GEN7_FF_VS_REF_CNT_FFME));
> > -
> > -	/* WaDisableSemaphoreAndSyncFlipWait:chv */
> > -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> > -
> > _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> > -
> >  	/* WaDisableCSUnitClockGating:chv */
> >  	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >  		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> > 
> > +	/* WaDisableDopClockGating:chv (pre-production hw) */
> 
> Shouldn't this be WaDisableTCUnitClock gating?
> 
> > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> > +
> >  	/* WaDisableSDEUnitClockGating:chv */
> >  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> >  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> > 
> > -	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> > -	I915_WRITE(HALF_SLICE_CHICKEN3,
> > -
> > _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> > -
> >  	/* WaDisableGunitClockGating:chv (pre-production hw) */
> >  	I915_WRITE(VLV_GUNIT_CLOCK_GATE,
> > I915_READ(VLV_GUNIT_CLOCK_GATE) |
> >  		   GINT_DIS);
> > -
> > -	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> > -	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> > -
> > _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> > -
> > -	/* WaDisableDopClockGating:chv (pre-production hw) */
> > -	I915_WRITE(GEN7_ROW_CHICKEN2,
> > -		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> > -	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > -		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >  }
> > 
> >  static void g4x_init_clock_gating(struct drm_device *dev)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index ceb1295..9e81c28 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -615,6 +615,43 @@ err:
> >  	return ret;
> >  }
> > 
> 
> I think we can share the cherryview_init_workarounds functions with broadwell
> and just call it gen8_init_workarounds with a bit of code to just enable the
> cheryview functions. I'll mark down the workarounds that are shared and the ones
> that are not. It will also simplify the bdw clock gating init functions.
> 
> > +static void cherryview_init_workarounds(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	/* WaDisablePartialInstShootdown:chv */
> 
> Applies to bdw.
> 
> > +	I915_WRITE(GEN8_ROW_CHICKEN,
> > +
> > _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
> > +
> > +	/* WaDisableThreadStallDopClockGating:chv */
> 
> Applies to bdw.
> 
> > +	I915_WRITE(GEN8_ROW_CHICKEN,
> > +		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> > +
> > +	/* WaVSRefCountFullforceMissDisable:chv */
> > +	/* WaDSRefCountFullforceMissDisable:chv */
> 
> Applies to bdw.
> 
> > +	I915_WRITE(GEN7_FF_THREAD_MODE,
> > +		   I915_READ(GEN7_FF_THREAD_MODE) &
> > +		   ~(GEN8_FF_DS_REF_CNT_FFME |
> > GEN7_FF_VS_REF_CNT_FFME));
> > +
> > +	/* WaDisableSemaphoreAndSyncFlipWait:chv */
> 
> Chv specific.
> 
> > +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> > +
> > _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> > +
> > +	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> 
> Chv specific.
> 
> > +	I915_WRITE(HALF_SLICE_CHICKEN3,
> > +
> > _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> > +
> > +	/* WaDisableFfDopClockGating:chv (pre-production hw) */
> 
> Chv specific.
> 
> > +	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> > +
> > _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
> > +
> > +	/* WaDisableDopClockGating:chv (pre-production hw) */
> 
> This first register write as applies to broadwell.
> 
> > +	I915_WRITE(GEN7_ROW_CHICKEN2,
> > +		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> 
> I think we need a split here and add WaDisableTCUnitClockGating. This also shows up in
> the init clock gating function. Do we need to have it in both places?  This second register
> write also only applies to chv.
> 
> > +	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > +		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> > +}
> > +
> >  static int init_render_ring(struct intel_engine_cs *ring)
> >  {
> >  	struct drm_device *dev = ring->dev;
> > @@ -670,6 +707,9 @@ static int init_render_ring(struct intel_engine_cs
> > *ring)
> >  	if (HAS_L3_DPF(dev))
> >  		I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
> > 
> > +	if (IS_CHERRYVIEW(dev))
> 
> If we modify the function init_workaround functions then we change from IS_CHERRYVIEW
> to IS_GEN8.
> 
> Thanks,
> Raf
> 
> > +		cherryview_init_workarounds(dev);
> > +
> >  	return ret;
> >  }
> > 
> > --
> > 1.8.5.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.

[Daniel Vetter]

On Tue, Jul 29, 2014 at 08:01:53PM +0200, Daniel Vetter wrote:
> On Tue, Jul 29, 2014 at 09:59:53AM -0700, Jesse Barnes wrote:
> > On Sat, 28 Jun 2014 02:04:20 +0300
> > ville.syrjala@linux.intel.com wrote:
> > 
> > > From: Kenneth Graunke <kenneth@whitecape.org>
> > > 
> > > We'll want to reuse this for a workaround.
> > > 
> > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> > > ---
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 36 ++++++++++++++++++++-------------
> > >  1 file changed, 22 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index 2faef26..97796b1 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -381,6 +381,27 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
> > >  }
> > >  
> > >  static int
> > > +gen8_emit_pipe_control(struct intel_engine_cs *ring,
> > > +		       u32 flags, u32 scratch_addr)
> > > +{
> > > +	int ret;
> > > +
> > > +	ret = intel_ring_begin(ring, 6);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> > > +	intel_ring_emit(ring, flags);
> > > +	intel_ring_emit(ring, scratch_addr);
> > > +	intel_ring_emit(ring, 0);
> > > +	intel_ring_emit(ring, 0);
> > > +	intel_ring_emit(ring, 0);
> > > +	intel_ring_advance(ring);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int
> > >  gen8_render_ring_flush(struct intel_engine_cs *ring,
> > >  		       u32 invalidate_domains, u32 flush_domains)
> > >  {
> > > @@ -405,20 +426,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
> > >  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> > >  	}
> > >  
> > > -	ret = intel_ring_begin(ring, 6);
> > > -	if (ret)
> > > -		return ret;
> > > -
> > > -	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> > > -	intel_ring_emit(ring, flags);
> > > -	intel_ring_emit(ring, scratch_addr);
> > > -	intel_ring_emit(ring, 0);
> > > -	intel_ring_emit(ring, 0);
> > > -	intel_ring_emit(ring, 0);
> > > -	intel_ring_advance(ring);
> > > -
> > > -	return 0;
> > > -
> > > +	return gen8_emit_pipe_control(ring, flags, scratch_addr);
> > >  }
> > >  
> > >  static void ring_write_tail(struct intel_engine_cs *ring,
> > 
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Aside: checkpatch complains about this since it makes it harder to grep
> for dmesg noise. But I guess if 3 people here like it I should merge it
> ;-)

That reply was meant for 27/40, not this patch here ofc.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers

[Paulo Zanoni]

2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The VLV/CHV DDL registers are uniform, and neatly enough the register
> offsets are sane so we can easily unify them to a single set of defines
> and just pass the pipe as the parameter to compute the register offset.

What the commit message doesn't tell is that now we will call
vlv_compute_drain_latency() for pipe C on CHV since I see CHV is
defined with num_pipes=3. I think this is quite an important detail,
since it's the only way this patch changes the behavior of the code.

If that is intentional and correct, then I suggest amending the commit
message, even maybe the patch title. Then you can add: Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com>.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++-------------------------------
>  drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++---------------------
>  2 files changed, 36 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9fab647..60dd19c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4018,47 +4018,19 @@ enum punit_power_well {
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32     32
>  #define DRAIN_LATENCY_PRECISION_64     64
> -#define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
> -#define DDL_CURSORA_PRECISION_64       (1<<31)
> -#define DDL_CURSORA_PRECISION_32       (0<<31)
> -#define DDL_CURSORA_SHIFT              24
> -#define DDL_SPRITEB_PRECISION_64       (1<<23)
> -#define DDL_SPRITEB_PRECISION_32       (0<<23)
> -#define DDL_SPRITEB_SHIFT              16
> -#define DDL_SPRITEA_PRECISION_64       (1<<15)
> -#define DDL_SPRITEA_PRECISION_32       (0<<15)
> -#define DDL_SPRITEA_SHIFT              8
> -#define DDL_PLANEA_PRECISION_64                (1<<7)
> -#define DDL_PLANEA_PRECISION_32                (0<<7)
> -#define DDL_PLANEA_SHIFT               0
> -
> -#define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
> -#define DDL_CURSORB_PRECISION_64       (1<<31)
> -#define DDL_CURSORB_PRECISION_32       (0<<31)
> -#define DDL_CURSORB_SHIFT              24
> -#define DDL_SPRITED_PRECISION_64       (1<<23)
> -#define DDL_SPRITED_PRECISION_32       (0<<23)
> -#define DDL_SPRITED_SHIFT              16
> -#define DDL_SPRITEC_PRECISION_64       (1<<15)
> -#define DDL_SPRITEC_PRECISION_32       (0<<15)
> -#define DDL_SPRITEC_SHIFT              8
> -#define DDL_PLANEB_PRECISION_64                (1<<7)
> -#define DDL_PLANEB_PRECISION_32                (0<<7)
> -#define DDL_PLANEB_SHIFT               0
> -
> -#define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
> -#define DDL_CURSORC_PRECISION_64       (1<<31)
> -#define DDL_CURSORC_PRECISION_32       (0<<31)
> -#define DDL_CURSORC_SHIFT              24
> -#define DDL_SPRITEF_PRECISION_64       (1<<23)
> -#define DDL_SPRITEF_PRECISION_32       (0<<23)
> -#define DDL_SPRITEF_SHIFT              16
> -#define DDL_SPRITEE_PRECISION_64       (1<<15)
> -#define DDL_SPRITEE_PRECISION_32       (0<<15)
> -#define DDL_SPRITEE_SHIFT              8
> -#define DDL_PLANEC_PRECISION_64                (1<<7)
> -#define DDL_PLANEC_PRECISION_32                (0<<7)
> -#define DDL_PLANEC_SHIFT               0
> +#define VLV_DDL(pipe)                  (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
> +#define DDL_CURSOR_PRECISION_64                (1<<31)
> +#define DDL_CURSOR_PRECISION_32                (0<<31)
> +#define DDL_CURSOR_SHIFT               24
> +#define DDL_SPRITE1_PRECISION_64       (1<<23)
> +#define DDL_SPRITE1_PRECISION_32       (0<<23)
> +#define DDL_SPRITE1_SHIFT              16
> +#define DDL_SPRITE0_PRECISION_64       (1<<15)
> +#define DDL_SPRITE0_PRECISION_32       (0<<15)
> +#define DDL_SPRITE0_SHIFT              8
> +#define DDL_PLANE_PRECISION_64         (1<<7)
> +#define DDL_PLANE_PRECISION_32         (0<<7)
> +#define DDL_PLANE_SHIFT                        0
>
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE     64
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dc858b5..f0516a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1275,35 +1275,29 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>  static void vlv_update_drain_latency(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
> -       int planea_prec, planea_dl, planeb_prec, planeb_dl;
> -       int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
> -       int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
> -                                                       either 16 or 32 */
> -
> -       /* For plane A, Cursor A */
> -       if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
> -                                     &cursor_prec_mult, &cursora_dl)) {
> -               cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
> -               planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
> -
> -               I915_WRITE(VLV_DDL1, cursora_prec |
> -                               (cursora_dl << DDL_CURSORA_SHIFT) |
> -                               planea_prec | planea_dl);
> -       }
> -
> -       /* For plane B, Cursor B */
> -       if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
> -                                     &cursor_prec_mult, &cursorb_dl)) {
> -               cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
> -               planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
> -
> -               I915_WRITE(VLV_DDL2, cursorb_prec |
> -                               (cursorb_dl << DDL_CURSORB_SHIFT) |
> -                               planeb_prec | planeb_dl);
> +       enum pipe pipe;
> +
> +       for_each_pipe(pipe) {
> +               int plane_prec, plane_dl;
> +               int cursor_prec, cursor_dl;
> +               int plane_prec_mult, cursor_prec_mult;
> +
> +               if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
> +                                              &cursor_prec_mult, &cursor_dl))
> +                       continue;
> +
> +               /*
> +                * FIXME CHV spec still lists 16 and 32 as the precision
> +                * values. Need to figure out if spec is outdated or what.
> +                */
> +               cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
> +                       DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
> +               plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
> +                       DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
> +
> +               I915_WRITE(VLV_DDL(pipe), cursor_prec |
> +                          (cursor_dl << DDL_CURSOR_SHIFT) |
> +                          plane_prec | (plane_dl << DDL_PLANE_SHIFT));
>         }
>  }
>
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers

[Ville Syrjälä]

On Wed, Jul 30, 2014 at 05:43:10PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The VLV/CHV DDL registers are uniform, and neatly enough the register
> > offsets are sane so we can easily unify them to a single set of defines
> > and just pass the pipe as the parameter to compute the register offset.
> 
> What the commit message doesn't tell is that now we will call
> vlv_compute_drain_latency() for pipe C on CHV since I see CHV is
> defined with num_pipes=3. I think this is quite an important detail,
> since it's the only way this patch changes the behavior of the code.
> 
> If that is intentional and correct, then I suggest amending the commit
> message, even maybe the patch title. Then you can add: Reviewed-by:
> Paulo Zanoni <paulo.r.zanoni@intel.com>.

One of the following patches will add a proper cherryview_update_wm()
function which also fills out the actual watermarks for pipe C. Ideally
I probably should have reordered these patches. But I'll add a note
of some sort here to avoid bigger reordering pains now.

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 26/40] drm/i915: Parametrize VLV_DDL registers

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.

Note that we now fill out the drain latency for pipe C on CHV which we
didn't do before. The rest of the pipe C watermarks are still untouched
but that will be remedied later by adding a proper cherryview_update_wm()
function.

v2: Add a note about CHV pipe C changes (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++-------------------------------
 drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++---------------------
 2 files changed, 36 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9fab647..60dd19c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4018,47 +4018,19 @@ enum punit_power_well {
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
 #define DRAIN_LATENCY_PRECISION_64	64
-#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
-#define DDL_CURSORA_PRECISION_64	(1<<31)
-#define DDL_CURSORA_PRECISION_32	(0<<31)
-#define DDL_CURSORA_SHIFT		24
-#define DDL_SPRITEB_PRECISION_64	(1<<23)
-#define DDL_SPRITEB_PRECISION_32	(0<<23)
-#define DDL_SPRITEB_SHIFT		16
-#define DDL_SPRITEA_PRECISION_64	(1<<15)
-#define DDL_SPRITEA_PRECISION_32	(0<<15)
-#define DDL_SPRITEA_SHIFT		8
-#define DDL_PLANEA_PRECISION_64		(1<<7)
-#define DDL_PLANEA_PRECISION_32		(0<<7)
-#define DDL_PLANEA_SHIFT		0
-
-#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
-#define DDL_CURSORB_PRECISION_64	(1<<31)
-#define DDL_CURSORB_PRECISION_32	(0<<31)
-#define DDL_CURSORB_SHIFT		24
-#define DDL_SPRITED_PRECISION_64	(1<<23)
-#define DDL_SPRITED_PRECISION_32	(0<<23)
-#define DDL_SPRITED_SHIFT		16
-#define DDL_SPRITEC_PRECISION_64	(1<<15)
-#define DDL_SPRITEC_PRECISION_32	(0<<15)
-#define DDL_SPRITEC_SHIFT		8
-#define DDL_PLANEB_PRECISION_64		(1<<7)
-#define DDL_PLANEB_PRECISION_32		(0<<7)
-#define DDL_PLANEB_SHIFT		0
-
-#define VLV_DDL3			(VLV_DISPLAY_BASE + 0x70058)
-#define DDL_CURSORC_PRECISION_64	(1<<31)
-#define DDL_CURSORC_PRECISION_32	(0<<31)
-#define DDL_CURSORC_SHIFT		24
-#define DDL_SPRITEF_PRECISION_64	(1<<23)
-#define DDL_SPRITEF_PRECISION_32	(0<<23)
-#define DDL_SPRITEF_SHIFT		16
-#define DDL_SPRITEE_PRECISION_64	(1<<15)
-#define DDL_SPRITEE_PRECISION_32	(0<<15)
-#define DDL_SPRITEE_SHIFT		8
-#define DDL_PLANEC_PRECISION_64		(1<<7)
-#define DDL_PLANEC_PRECISION_32		(0<<7)
-#define DDL_PLANEC_SHIFT		0
+#define VLV_DDL(pipe)			(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
+#define DDL_CURSOR_PRECISION_64		(1<<31)
+#define DDL_CURSOR_PRECISION_32		(0<<31)
+#define DDL_CURSOR_SHIFT		24
+#define DDL_SPRITE1_PRECISION_64	(1<<23)
+#define DDL_SPRITE1_PRECISION_32	(0<<23)
+#define DDL_SPRITE1_SHIFT		16
+#define DDL_SPRITE0_PRECISION_64	(1<<15)
+#define DDL_SPRITE0_PRECISION_32	(0<<15)
+#define DDL_SPRITE0_SHIFT		8
+#define DDL_PLANE_PRECISION_64		(1<<7)
+#define DDL_PLANE_PRECISION_32		(0<<7)
+#define DDL_PLANE_SHIFT			0
 
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc858b5..f0516a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1275,35 +1275,29 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
 static void vlv_update_drain_latency(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int planea_prec, planea_dl, planeb_prec, planeb_dl;
-	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
-	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
-							either 16 or 32 */
-
-	/* For plane A, Cursor A */
-	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
-				      &cursor_prec_mult, &cursora_dl)) {
-		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
-		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
-
-		I915_WRITE(VLV_DDL1, cursora_prec |
-				(cursora_dl << DDL_CURSORA_SHIFT) |
-				planea_prec | planea_dl);
-	}
-
-	/* For plane B, Cursor B */
-	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
-				      &cursor_prec_mult, &cursorb_dl)) {
-		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
-		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
-			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
-
-		I915_WRITE(VLV_DDL2, cursorb_prec |
-				(cursorb_dl << DDL_CURSORB_SHIFT) |
-				planeb_prec | planeb_dl);
+	enum pipe pipe;
+
+	for_each_pipe(pipe) {
+		int plane_prec, plane_dl;
+		int cursor_prec, cursor_dl;
+		int plane_prec_mult, cursor_prec_mult;
+
+		if (!vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
+					       &cursor_prec_mult, &cursor_dl))
+			continue;
+
+		/*
+		 * FIXME CHV spec still lists 16 and 32 as the precision
+		 * values. Need to figure out if spec is outdated or what.
+		 */
+		cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+			DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
+		plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
+			DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
+
+		I915_WRITE(VLV_DDL(pipe), cursor_prec |
+			   (cursor_dl << DDL_CURSOR_SHIFT) |
+			   plane_prec | (plane_dl << DDL_PLANE_SHIFT));
 	}
 }
 
-- 
1.8.5.5

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Re: [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[Paulo Zanoni]

2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Zhenyu Wang <zhenyuw@linux.intel.com>
>

I guess this affects both VLV and CHV, but my CHV docs still contain
16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
an explanation on the commit message?


> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
>  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
>  2 files changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 191df9e..7ab5a03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3909,47 +3909,47 @@ enum punit_power_well {
>
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32     32
> -#define DRAIN_LATENCY_PRECISION_16     16
> +#define DRAIN_LATENCY_PRECISION_64     64
>  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
> -#define DDL_CURSORA_PRECISION_32       (1<<31)
> -#define DDL_CURSORA_PRECISION_16       (0<<31)
> +#define DDL_CURSORA_PRECISION_64       (1<<31)
> +#define DDL_CURSORA_PRECISION_32       (0<<31)
>  #define DDL_CURSORA_SHIFT              24
> -#define DDL_SPRITEB_PRECISION_32       (1<<23)
> -#define DDL_SPRITEB_PRECISION_16       (0<<23)
> +#define DDL_SPRITEB_PRECISION_64       (1<<23)
> +#define DDL_SPRITEB_PRECISION_32       (0<<23)
>  #define DDL_SPRITEB_SHIFT              16
> -#define DDL_SPRITEA_PRECISION_32       (1<<15)
> -#define DDL_SPRITEA_PRECISION_16       (0<<15)
> +#define DDL_SPRITEA_PRECISION_64       (1<<15)
> +#define DDL_SPRITEA_PRECISION_32       (0<<15)
>  #define DDL_SPRITEA_SHIFT              8
> -#define DDL_PLANEA_PRECISION_32                (1<<7)
> -#define DDL_PLANEA_PRECISION_16                (0<<7)
> +#define DDL_PLANEA_PRECISION_64                (1<<7)
> +#define DDL_PLANEA_PRECISION_32                (0<<7)
>  #define DDL_PLANEA_SHIFT               0
>
>  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
> -#define DDL_CURSORB_PRECISION_32       (1<<31)
> -#define DDL_CURSORB_PRECISION_16       (0<<31)
> +#define DDL_CURSORB_PRECISION_64       (1<<31)
> +#define DDL_CURSORB_PRECISION_32       (0<<31)
>  #define DDL_CURSORB_SHIFT              24
> -#define DDL_SPRITED_PRECISION_32       (1<<23)
> -#define DDL_SPRITED_PRECISION_16       (0<<23)
> +#define DDL_SPRITED_PRECISION_64       (1<<23)
> +#define DDL_SPRITED_PRECISION_32       (0<<23)
>  #define DDL_SPRITED_SHIFT              16
> -#define DDL_SPRITEC_PRECISION_32       (1<<15)
> -#define DDL_SPRITEC_PRECISION_16       (0<<15)
> +#define DDL_SPRITEC_PRECISION_64       (1<<15)
> +#define DDL_SPRITEC_PRECISION_32       (0<<15)
>  #define DDL_SPRITEC_SHIFT              8
> -#define DDL_PLANEB_PRECISION_32                (1<<7)
> -#define DDL_PLANEB_PRECISION_16                (0<<7)
> +#define DDL_PLANEB_PRECISION_64                (1<<7)
> +#define DDL_PLANEB_PRECISION_32                (0<<7)
>  #define DDL_PLANEB_SHIFT               0
>
>  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
> -#define DDL_CURSORC_PRECISION_32       (1<<31)
> -#define DDL_CURSORC_PRECISION_16       (0<<31)
> +#define DDL_CURSORC_PRECISION_64       (1<<31)
> +#define DDL_CURSORC_PRECISION_32       (0<<31)
>  #define DDL_CURSORC_SHIFT              24
> -#define DDL_SPRITEF_PRECISION_32       (1<<23)
> -#define DDL_SPRITEF_PRECISION_16       (0<<23)
> +#define DDL_SPRITEF_PRECISION_64       (1<<23)
> +#define DDL_SPRITEF_PRECISION_32       (0<<23)
>  #define DDL_SPRITEF_SHIFT              16
> -#define DDL_SPRITEE_PRECISION_32       (1<<15)
> -#define DDL_SPRITEE_PRECISION_16       (0<<15)
> +#define DDL_SPRITEE_PRECISION_64       (1<<15)
> +#define DDL_SPRITEE_PRECISION_32       (0<<15)
>  #define DDL_SPRITEE_SHIFT              8
> -#define DDL_PLANEC_PRECISION_32                (1<<7)
> -#define DDL_PLANEC_PRECISION_16                (0<<7)
> +#define DDL_PLANEC_PRECISION_64                (1<<7)
> +#define DDL_PLANEC_PRECISION_32                (0<<7)
>  #define DDL_PLANEC_SHIFT               0
>
>  /* FIFO watermark sizes etc */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 55f3e6b..9413184 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>
>         entries = (clock / 1000) * pixel_size;
>         *plane_prec_mult = (entries > 256) ?
> -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
>                                                      pixel_size);
>
>         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
>         *cursor_prec_mult = (entries > 256) ?
> -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
>
>         return true;
> @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
>                                       &cursor_prec_mult, &cursora_dl)) {
>                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
>                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
>
>                 I915_WRITE(VLV_DDL1, cursora_prec |
>                                 (cursora_dl << DDL_CURSORA_SHIFT) |
> @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
>                                       &cursor_prec_mult, &cursorb_dl)) {
>                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
>                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
>
>                 I915_WRITE(VLV_DDL2, cursorb_prec |
>                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

Re: [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[Ville Syrjälä]

On Thu, Jul 31, 2014 at 12:08:09PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Zhenyu Wang <zhenyuw@linux.intel.com>
> >
> 
> I guess this affects both VLV and CHV, but my CHV docs still contain
> 16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
> an explanation on the commit message?

I added a FIXME about that in patch 26.

According to this http://patchwork.freedesktop.org/patch/29860/
CHV has been confirmed to use the 32/64 values too. Hopefully
we'll get the spec updated too...

> 
> 
> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
> >  2 files changed, 31 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 191df9e..7ab5a03 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3909,47 +3909,47 @@ enum punit_power_well {
> >
> >  /* drain latency register values*/
> >  #define DRAIN_LATENCY_PRECISION_32     32
> > -#define DRAIN_LATENCY_PRECISION_16     16
> > +#define DRAIN_LATENCY_PRECISION_64     64
> >  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
> > -#define DDL_CURSORA_PRECISION_32       (1<<31)
> > -#define DDL_CURSORA_PRECISION_16       (0<<31)
> > +#define DDL_CURSORA_PRECISION_64       (1<<31)
> > +#define DDL_CURSORA_PRECISION_32       (0<<31)
> >  #define DDL_CURSORA_SHIFT              24
> > -#define DDL_SPRITEB_PRECISION_32       (1<<23)
> > -#define DDL_SPRITEB_PRECISION_16       (0<<23)
> > +#define DDL_SPRITEB_PRECISION_64       (1<<23)
> > +#define DDL_SPRITEB_PRECISION_32       (0<<23)
> >  #define DDL_SPRITEB_SHIFT              16
> > -#define DDL_SPRITEA_PRECISION_32       (1<<15)
> > -#define DDL_SPRITEA_PRECISION_16       (0<<15)
> > +#define DDL_SPRITEA_PRECISION_64       (1<<15)
> > +#define DDL_SPRITEA_PRECISION_32       (0<<15)
> >  #define DDL_SPRITEA_SHIFT              8
> > -#define DDL_PLANEA_PRECISION_32                (1<<7)
> > -#define DDL_PLANEA_PRECISION_16                (0<<7)
> > +#define DDL_PLANEA_PRECISION_64                (1<<7)
> > +#define DDL_PLANEA_PRECISION_32                (0<<7)
> >  #define DDL_PLANEA_SHIFT               0
> >
> >  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
> > -#define DDL_CURSORB_PRECISION_32       (1<<31)
> > -#define DDL_CURSORB_PRECISION_16       (0<<31)
> > +#define DDL_CURSORB_PRECISION_64       (1<<31)
> > +#define DDL_CURSORB_PRECISION_32       (0<<31)
> >  #define DDL_CURSORB_SHIFT              24
> > -#define DDL_SPRITED_PRECISION_32       (1<<23)
> > -#define DDL_SPRITED_PRECISION_16       (0<<23)
> > +#define DDL_SPRITED_PRECISION_64       (1<<23)
> > +#define DDL_SPRITED_PRECISION_32       (0<<23)
> >  #define DDL_SPRITED_SHIFT              16
> > -#define DDL_SPRITEC_PRECISION_32       (1<<15)
> > -#define DDL_SPRITEC_PRECISION_16       (0<<15)
> > +#define DDL_SPRITEC_PRECISION_64       (1<<15)
> > +#define DDL_SPRITEC_PRECISION_32       (0<<15)
> >  #define DDL_SPRITEC_SHIFT              8
> > -#define DDL_PLANEB_PRECISION_32                (1<<7)
> > -#define DDL_PLANEB_PRECISION_16                (0<<7)
> > +#define DDL_PLANEB_PRECISION_64                (1<<7)
> > +#define DDL_PLANEB_PRECISION_32                (0<<7)
> >  #define DDL_PLANEB_SHIFT               0
> >
> >  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
> > -#define DDL_CURSORC_PRECISION_32       (1<<31)
> > -#define DDL_CURSORC_PRECISION_16       (0<<31)
> > +#define DDL_CURSORC_PRECISION_64       (1<<31)
> > +#define DDL_CURSORC_PRECISION_32       (0<<31)
> >  #define DDL_CURSORC_SHIFT              24
> > -#define DDL_SPRITEF_PRECISION_32       (1<<23)
> > -#define DDL_SPRITEF_PRECISION_16       (0<<23)
> > +#define DDL_SPRITEF_PRECISION_64       (1<<23)
> > +#define DDL_SPRITEF_PRECISION_32       (0<<23)
> >  #define DDL_SPRITEF_SHIFT              16
> > -#define DDL_SPRITEE_PRECISION_32       (1<<15)
> > -#define DDL_SPRITEE_PRECISION_16       (0<<15)
> > +#define DDL_SPRITEE_PRECISION_64       (1<<15)
> > +#define DDL_SPRITEE_PRECISION_32       (0<<15)
> >  #define DDL_SPRITEE_SHIFT              8
> > -#define DDL_PLANEC_PRECISION_32                (1<<7)
> > -#define DDL_PLANEC_PRECISION_16                (0<<7)
> > +#define DDL_PLANEC_PRECISION_64                (1<<7)
> > +#define DDL_PLANEC_PRECISION_32                (0<<7)
> >  #define DDL_PLANEC_SHIFT               0
> >
> >  /* FIFO watermark sizes etc */
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 55f3e6b..9413184 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
> >
> >         entries = (clock / 1000) * pixel_size;
> >         *plane_prec_mult = (entries > 256) ?
> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> >         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
> >                                                      pixel_size);
> >
> >         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
> >         *cursor_prec_mult = (entries > 256) ?
> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> >         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
> >
> >         return true;
> > @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
> >         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
> >                                       &cursor_prec_mult, &cursora_dl)) {
> >                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> > -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> > +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
> >                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> > -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> > +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
> >
> >                 I915_WRITE(VLV_DDL1, cursora_prec |
> >                                 (cursora_dl << DDL_CURSORA_SHIFT) |
> > @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
> >         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
> >                                       &cursor_prec_mult, &cursorb_dl)) {
> >                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> > -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> > +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
> >                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> > -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> > +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
> >
> >                 I915_WRITE(VLV_DDL2, cursorb_prec |
> >                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
> > --
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[Paulo Zanoni]

2014-07-31 12:16 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
> On Thu, Jul 31, 2014 at 12:08:09PM -0300, Paulo Zanoni wrote:
>> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
>> > From: Zhenyu Wang <zhenyuw@linux.intel.com>
>> >
>>
>> I guess this affects both VLV and CHV, but my CHV docs still contain
>> 16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
>> an explanation on the commit message?
>
> I added a FIXME about that in patch 26.
>
> According to this http://patchwork.freedesktop.org/patch/29860/
> CHV has been confirmed to use the 32/64 values too. Hopefully
> we'll get the spec updated too...

Ok, but on this case it's quite hard to give a reviewed-by stamp to
the patch, since there's no way to review. I guess this is one of the
cases where we just have to believe the authors and merge the patch?

>
>>
>>
>> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
>> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
>> >  2 files changed, 31 insertions(+), 31 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 191df9e..7ab5a03 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -3909,47 +3909,47 @@ enum punit_power_well {
>> >
>> >  /* drain latency register values*/
>> >  #define DRAIN_LATENCY_PRECISION_32     32
>> > -#define DRAIN_LATENCY_PRECISION_16     16
>> > +#define DRAIN_LATENCY_PRECISION_64     64
>> >  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
>> > -#define DDL_CURSORA_PRECISION_32       (1<<31)
>> > -#define DDL_CURSORA_PRECISION_16       (0<<31)
>> > +#define DDL_CURSORA_PRECISION_64       (1<<31)
>> > +#define DDL_CURSORA_PRECISION_32       (0<<31)
>> >  #define DDL_CURSORA_SHIFT              24
>> > -#define DDL_SPRITEB_PRECISION_32       (1<<23)
>> > -#define DDL_SPRITEB_PRECISION_16       (0<<23)
>> > +#define DDL_SPRITEB_PRECISION_64       (1<<23)
>> > +#define DDL_SPRITEB_PRECISION_32       (0<<23)
>> >  #define DDL_SPRITEB_SHIFT              16
>> > -#define DDL_SPRITEA_PRECISION_32       (1<<15)
>> > -#define DDL_SPRITEA_PRECISION_16       (0<<15)
>> > +#define DDL_SPRITEA_PRECISION_64       (1<<15)
>> > +#define DDL_SPRITEA_PRECISION_32       (0<<15)
>> >  #define DDL_SPRITEA_SHIFT              8
>> > -#define DDL_PLANEA_PRECISION_32                (1<<7)
>> > -#define DDL_PLANEA_PRECISION_16                (0<<7)
>> > +#define DDL_PLANEA_PRECISION_64                (1<<7)
>> > +#define DDL_PLANEA_PRECISION_32                (0<<7)
>> >  #define DDL_PLANEA_SHIFT               0
>> >
>> >  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
>> > -#define DDL_CURSORB_PRECISION_32       (1<<31)
>> > -#define DDL_CURSORB_PRECISION_16       (0<<31)
>> > +#define DDL_CURSORB_PRECISION_64       (1<<31)
>> > +#define DDL_CURSORB_PRECISION_32       (0<<31)
>> >  #define DDL_CURSORB_SHIFT              24
>> > -#define DDL_SPRITED_PRECISION_32       (1<<23)
>> > -#define DDL_SPRITED_PRECISION_16       (0<<23)
>> > +#define DDL_SPRITED_PRECISION_64       (1<<23)
>> > +#define DDL_SPRITED_PRECISION_32       (0<<23)
>> >  #define DDL_SPRITED_SHIFT              16
>> > -#define DDL_SPRITEC_PRECISION_32       (1<<15)
>> > -#define DDL_SPRITEC_PRECISION_16       (0<<15)
>> > +#define DDL_SPRITEC_PRECISION_64       (1<<15)
>> > +#define DDL_SPRITEC_PRECISION_32       (0<<15)
>> >  #define DDL_SPRITEC_SHIFT              8
>> > -#define DDL_PLANEB_PRECISION_32                (1<<7)
>> > -#define DDL_PLANEB_PRECISION_16                (0<<7)
>> > +#define DDL_PLANEB_PRECISION_64                (1<<7)
>> > +#define DDL_PLANEB_PRECISION_32                (0<<7)
>> >  #define DDL_PLANEB_SHIFT               0
>> >
>> >  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
>> > -#define DDL_CURSORC_PRECISION_32       (1<<31)
>> > -#define DDL_CURSORC_PRECISION_16       (0<<31)
>> > +#define DDL_CURSORC_PRECISION_64       (1<<31)
>> > +#define DDL_CURSORC_PRECISION_32       (0<<31)
>> >  #define DDL_CURSORC_SHIFT              24
>> > -#define DDL_SPRITEF_PRECISION_32       (1<<23)
>> > -#define DDL_SPRITEF_PRECISION_16       (0<<23)
>> > +#define DDL_SPRITEF_PRECISION_64       (1<<23)
>> > +#define DDL_SPRITEF_PRECISION_32       (0<<23)
>> >  #define DDL_SPRITEF_SHIFT              16
>> > -#define DDL_SPRITEE_PRECISION_32       (1<<15)
>> > -#define DDL_SPRITEE_PRECISION_16       (0<<15)
>> > +#define DDL_SPRITEE_PRECISION_64       (1<<15)
>> > +#define DDL_SPRITEE_PRECISION_32       (0<<15)
>> >  #define DDL_SPRITEE_SHIFT              8
>> > -#define DDL_PLANEC_PRECISION_32                (1<<7)
>> > -#define DDL_PLANEC_PRECISION_16                (0<<7)
>> > +#define DDL_PLANEC_PRECISION_64                (1<<7)
>> > +#define DDL_PLANEC_PRECISION_32                (0<<7)
>> >  #define DDL_PLANEC_SHIFT               0
>> >
>> >  /* FIFO watermark sizes etc */
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index 55f3e6b..9413184 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>> >
>> >         entries = (clock / 1000) * pixel_size;
>> >         *plane_prec_mult = (entries > 256) ?
>> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
>> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>> >         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
>> >                                                      pixel_size);
>> >
>> >         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
>> >         *cursor_prec_mult = (entries > 256) ?
>> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
>> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>> >         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
>> >
>> >         return true;
>> > @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>> >         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
>> >                                       &cursor_prec_mult, &cursora_dl)) {
>> >                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> > -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
>> > +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
>> >                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> > -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
>> > +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
>> >
>> >                 I915_WRITE(VLV_DDL1, cursora_prec |
>> >                                 (cursora_dl << DDL_CURSORA_SHIFT) |
>> > @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>> >         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
>> >                                       &cursor_prec_mult, &cursorb_dl)) {
>> >                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> > -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
>> > +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
>> >                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> > -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
>> > +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
>> >
>> >                 I915_WRITE(VLV_DDL2, cursorb_prec |
>> >                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
>> > --
>> > 1.8.5.5
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Paulo Zanoni
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Paulo Zanoni
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[Ville Syrjälä]

On Thu, Jul 31, 2014 at 02:05:49PM -0300, Paulo Zanoni wrote:
> 2014-07-31 12:16 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
> > On Thu, Jul 31, 2014 at 12:08:09PM -0300, Paulo Zanoni wrote:
> >> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> >> > From: Zhenyu Wang <zhenyuw@linux.intel.com>
> >> >
> >>
> >> I guess this affects both VLV and CHV, but my CHV docs still contain
> >> 16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
> >> an explanation on the commit message?
> >
> > I added a FIXME about that in patch 26.
> >
> > According to this http://patchwork.freedesktop.org/patch/29860/
> > CHV has been confirmed to use the 32/64 values too. Hopefully
> > we'll get the spec updated too...
> 
> Ok, but on this case it's quite hard to give a reviewed-by stamp to
> the patch, since there's no way to review. I guess this is one of the
> cases where we just have to believe the authors and merge the patch?

The VLV docs have the new 32/64 values.

> 
> >
> >>
> >>
> >> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
> >> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
> >> >  2 files changed, 31 insertions(+), 31 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 191df9e..7ab5a03 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -3909,47 +3909,47 @@ enum punit_power_well {
> >> >
> >> >  /* drain latency register values*/
> >> >  #define DRAIN_LATENCY_PRECISION_32     32
> >> > -#define DRAIN_LATENCY_PRECISION_16     16
> >> > +#define DRAIN_LATENCY_PRECISION_64     64
> >> >  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
> >> > -#define DDL_CURSORA_PRECISION_32       (1<<31)
> >> > -#define DDL_CURSORA_PRECISION_16       (0<<31)
> >> > +#define DDL_CURSORA_PRECISION_64       (1<<31)
> >> > +#define DDL_CURSORA_PRECISION_32       (0<<31)
> >> >  #define DDL_CURSORA_SHIFT              24
> >> > -#define DDL_SPRITEB_PRECISION_32       (1<<23)
> >> > -#define DDL_SPRITEB_PRECISION_16       (0<<23)
> >> > +#define DDL_SPRITEB_PRECISION_64       (1<<23)
> >> > +#define DDL_SPRITEB_PRECISION_32       (0<<23)
> >> >  #define DDL_SPRITEB_SHIFT              16
> >> > -#define DDL_SPRITEA_PRECISION_32       (1<<15)
> >> > -#define DDL_SPRITEA_PRECISION_16       (0<<15)
> >> > +#define DDL_SPRITEA_PRECISION_64       (1<<15)
> >> > +#define DDL_SPRITEA_PRECISION_32       (0<<15)
> >> >  #define DDL_SPRITEA_SHIFT              8
> >> > -#define DDL_PLANEA_PRECISION_32                (1<<7)
> >> > -#define DDL_PLANEA_PRECISION_16                (0<<7)
> >> > +#define DDL_PLANEA_PRECISION_64                (1<<7)
> >> > +#define DDL_PLANEA_PRECISION_32                (0<<7)
> >> >  #define DDL_PLANEA_SHIFT               0
> >> >
> >> >  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
> >> > -#define DDL_CURSORB_PRECISION_32       (1<<31)
> >> > -#define DDL_CURSORB_PRECISION_16       (0<<31)
> >> > +#define DDL_CURSORB_PRECISION_64       (1<<31)
> >> > +#define DDL_CURSORB_PRECISION_32       (0<<31)
> >> >  #define DDL_CURSORB_SHIFT              24
> >> > -#define DDL_SPRITED_PRECISION_32       (1<<23)
> >> > -#define DDL_SPRITED_PRECISION_16       (0<<23)
> >> > +#define DDL_SPRITED_PRECISION_64       (1<<23)
> >> > +#define DDL_SPRITED_PRECISION_32       (0<<23)
> >> >  #define DDL_SPRITED_SHIFT              16
> >> > -#define DDL_SPRITEC_PRECISION_32       (1<<15)
> >> > -#define DDL_SPRITEC_PRECISION_16       (0<<15)
> >> > +#define DDL_SPRITEC_PRECISION_64       (1<<15)
> >> > +#define DDL_SPRITEC_PRECISION_32       (0<<15)
> >> >  #define DDL_SPRITEC_SHIFT              8
> >> > -#define DDL_PLANEB_PRECISION_32                (1<<7)
> >> > -#define DDL_PLANEB_PRECISION_16                (0<<7)
> >> > +#define DDL_PLANEB_PRECISION_64                (1<<7)
> >> > +#define DDL_PLANEB_PRECISION_32                (0<<7)
> >> >  #define DDL_PLANEB_SHIFT               0
> >> >
> >> >  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
> >> > -#define DDL_CURSORC_PRECISION_32       (1<<31)
> >> > -#define DDL_CURSORC_PRECISION_16       (0<<31)
> >> > +#define DDL_CURSORC_PRECISION_64       (1<<31)
> >> > +#define DDL_CURSORC_PRECISION_32       (0<<31)
> >> >  #define DDL_CURSORC_SHIFT              24
> >> > -#define DDL_SPRITEF_PRECISION_32       (1<<23)
> >> > -#define DDL_SPRITEF_PRECISION_16       (0<<23)
> >> > +#define DDL_SPRITEF_PRECISION_64       (1<<23)
> >> > +#define DDL_SPRITEF_PRECISION_32       (0<<23)
> >> >  #define DDL_SPRITEF_SHIFT              16
> >> > -#define DDL_SPRITEE_PRECISION_32       (1<<15)
> >> > -#define DDL_SPRITEE_PRECISION_16       (0<<15)
> >> > +#define DDL_SPRITEE_PRECISION_64       (1<<15)
> >> > +#define DDL_SPRITEE_PRECISION_32       (0<<15)
> >> >  #define DDL_SPRITEE_SHIFT              8
> >> > -#define DDL_PLANEC_PRECISION_32                (1<<7)
> >> > -#define DDL_PLANEC_PRECISION_16                (0<<7)
> >> > +#define DDL_PLANEC_PRECISION_64                (1<<7)
> >> > +#define DDL_PLANEC_PRECISION_32                (0<<7)
> >> >  #define DDL_PLANEC_SHIFT               0
> >> >
> >> >  /* FIFO watermark sizes etc */
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index 55f3e6b..9413184 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
> >> >
> >> >         entries = (clock / 1000) * pixel_size;
> >> >         *plane_prec_mult = (entries > 256) ?
> >> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> >> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> >> >         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
> >> >                                                      pixel_size);
> >> >
> >> >         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
> >> >         *cursor_prec_mult = (entries > 256) ?
> >> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> >> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> >> >         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
> >> >
> >> >         return true;
> >> > @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
> >> >         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
> >> >                                       &cursor_prec_mult, &cursora_dl)) {
> >> >                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> >> > -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> >> > +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
> >> >                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> >> > -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> >> > +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
> >> >
> >> >                 I915_WRITE(VLV_DDL1, cursora_prec |
> >> >                                 (cursora_dl << DDL_CURSORA_SHIFT) |
> >> > @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
> >> >         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
> >> >                                       &cursor_prec_mult, &cursorb_dl)) {
> >> >                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> >> > -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> >> > +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
> >> >                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> >> > -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> >> > +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
> >> >
> >> >                 I915_WRITE(VLV_DDL2, cursorb_prec |
> >> >                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
> >> > --
> >> > 1.8.5.5
> >> >
> >> > _______________________________________________
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >>
> >>
> >> --
> >> Paulo Zanoni
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

[Paulo Zanoni]

2014-07-31 14:13 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
> On Thu, Jul 31, 2014 at 02:05:49PM -0300, Paulo Zanoni wrote:
>> 2014-07-31 12:16 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>:
>> > On Thu, Jul 31, 2014 at 12:08:09PM -0300, Paulo Zanoni wrote:
>> >> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
>> >> > From: Zhenyu Wang <zhenyuw@linux.intel.com>
>> >> >
>> >>
>> >> I guess this affects both VLV and CHV, but my CHV docs still contain
>> >> 16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
>> >> an explanation on the commit message?
>> >
>> > I added a FIXME about that in patch 26.
>> >
>> > According to this http://patchwork.freedesktop.org/patch/29860/
>> > CHV has been confirmed to use the 32/64 values too. Hopefully
>> > we'll get the spec updated too...
>>
>> Ok, but on this case it's quite hard to give a reviewed-by stamp to
>> the patch, since there's no way to review. I guess this is one of the
>> cases where we just have to believe the authors and merge the patch?
>
> The VLV docs have the new 32/64 values.

Ok, found it :)
If we assume CHV uses 32/64 just like VLV: Reviewed-by: Paulo Zanoni
<paulo.r.zanoni@intel.com>

>
>>
>> >
>> >>
>> >>
>> >> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
>> >> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
>> >> >  2 files changed, 31 insertions(+), 31 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >> > index 191df9e..7ab5a03 100644
>> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> > @@ -3909,47 +3909,47 @@ enum punit_power_well {
>> >> >
>> >> >  /* drain latency register values*/
>> >> >  #define DRAIN_LATENCY_PRECISION_32     32
>> >> > -#define DRAIN_LATENCY_PRECISION_16     16
>> >> > +#define DRAIN_LATENCY_PRECISION_64     64
>> >> >  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
>> >> > -#define DDL_CURSORA_PRECISION_32       (1<<31)
>> >> > -#define DDL_CURSORA_PRECISION_16       (0<<31)
>> >> > +#define DDL_CURSORA_PRECISION_64       (1<<31)
>> >> > +#define DDL_CURSORA_PRECISION_32       (0<<31)
>> >> >  #define DDL_CURSORA_SHIFT              24
>> >> > -#define DDL_SPRITEB_PRECISION_32       (1<<23)
>> >> > -#define DDL_SPRITEB_PRECISION_16       (0<<23)
>> >> > +#define DDL_SPRITEB_PRECISION_64       (1<<23)
>> >> > +#define DDL_SPRITEB_PRECISION_32       (0<<23)
>> >> >  #define DDL_SPRITEB_SHIFT              16
>> >> > -#define DDL_SPRITEA_PRECISION_32       (1<<15)
>> >> > -#define DDL_SPRITEA_PRECISION_16       (0<<15)
>> >> > +#define DDL_SPRITEA_PRECISION_64       (1<<15)
>> >> > +#define DDL_SPRITEA_PRECISION_32       (0<<15)
>> >> >  #define DDL_SPRITEA_SHIFT              8
>> >> > -#define DDL_PLANEA_PRECISION_32                (1<<7)
>> >> > -#define DDL_PLANEA_PRECISION_16                (0<<7)
>> >> > +#define DDL_PLANEA_PRECISION_64                (1<<7)
>> >> > +#define DDL_PLANEA_PRECISION_32                (0<<7)
>> >> >  #define DDL_PLANEA_SHIFT               0
>> >> >
>> >> >  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
>> >> > -#define DDL_CURSORB_PRECISION_32       (1<<31)
>> >> > -#define DDL_CURSORB_PRECISION_16       (0<<31)
>> >> > +#define DDL_CURSORB_PRECISION_64       (1<<31)
>> >> > +#define DDL_CURSORB_PRECISION_32       (0<<31)
>> >> >  #define DDL_CURSORB_SHIFT              24
>> >> > -#define DDL_SPRITED_PRECISION_32       (1<<23)
>> >> > -#define DDL_SPRITED_PRECISION_16       (0<<23)
>> >> > +#define DDL_SPRITED_PRECISION_64       (1<<23)
>> >> > +#define DDL_SPRITED_PRECISION_32       (0<<23)
>> >> >  #define DDL_SPRITED_SHIFT              16
>> >> > -#define DDL_SPRITEC_PRECISION_32       (1<<15)
>> >> > -#define DDL_SPRITEC_PRECISION_16       (0<<15)
>> >> > +#define DDL_SPRITEC_PRECISION_64       (1<<15)
>> >> > +#define DDL_SPRITEC_PRECISION_32       (0<<15)
>> >> >  #define DDL_SPRITEC_SHIFT              8
>> >> > -#define DDL_PLANEB_PRECISION_32                (1<<7)
>> >> > -#define DDL_PLANEB_PRECISION_16                (0<<7)
>> >> > +#define DDL_PLANEB_PRECISION_64                (1<<7)
>> >> > +#define DDL_PLANEB_PRECISION_32                (0<<7)
>> >> >  #define DDL_PLANEB_SHIFT               0
>> >> >
>> >> >  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
>> >> > -#define DDL_CURSORC_PRECISION_32       (1<<31)
>> >> > -#define DDL_CURSORC_PRECISION_16       (0<<31)
>> >> > +#define DDL_CURSORC_PRECISION_64       (1<<31)
>> >> > +#define DDL_CURSORC_PRECISION_32       (0<<31)
>> >> >  #define DDL_CURSORC_SHIFT              24
>> >> > -#define DDL_SPRITEF_PRECISION_32       (1<<23)
>> >> > -#define DDL_SPRITEF_PRECISION_16       (0<<23)
>> >> > +#define DDL_SPRITEF_PRECISION_64       (1<<23)
>> >> > +#define DDL_SPRITEF_PRECISION_32       (0<<23)
>> >> >  #define DDL_SPRITEF_SHIFT              16
>> >> > -#define DDL_SPRITEE_PRECISION_32       (1<<15)
>> >> > -#define DDL_SPRITEE_PRECISION_16       (0<<15)
>> >> > +#define DDL_SPRITEE_PRECISION_64       (1<<15)
>> >> > +#define DDL_SPRITEE_PRECISION_32       (0<<15)
>> >> >  #define DDL_SPRITEE_SHIFT              8
>> >> > -#define DDL_PLANEC_PRECISION_32                (1<<7)
>> >> > -#define DDL_PLANEC_PRECISION_16                (0<<7)
>> >> > +#define DDL_PLANEC_PRECISION_64                (1<<7)
>> >> > +#define DDL_PLANEC_PRECISION_32                (0<<7)
>> >> >  #define DDL_PLANEC_SHIFT               0
>> >> >
>> >> >  /* FIFO watermark sizes etc */
>> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> >> > index 55f3e6b..9413184 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> >> > @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>> >> >
>> >> >         entries = (clock / 1000) * pixel_size;
>> >> >         *plane_prec_mult = (entries > 256) ?
>> >> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
>> >> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>> >> >         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
>> >> >                                                      pixel_size);
>> >> >
>> >> >         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
>> >> >         *cursor_prec_mult = (entries > 256) ?
>> >> > -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
>> >> > +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>> >> >         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
>> >> >
>> >> >         return true;
>> >> > @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>> >> >         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
>> >> >                                       &cursor_prec_mult, &cursora_dl)) {
>> >> >                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> >> > -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
>> >> > +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
>> >> >                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> >> > -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
>> >> > +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
>> >> >
>> >> >                 I915_WRITE(VLV_DDL1, cursora_prec |
>> >> >                                 (cursora_dl << DDL_CURSORA_SHIFT) |
>> >> > @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>> >> >         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
>> >> >                                       &cursor_prec_mult, &cursorb_dl)) {
>> >> >                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> >> > -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
>> >> > +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
>> >> >                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
>> >> > -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
>> >> > +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
>> >> >
>> >> >                 I915_WRITE(VLV_DDL2, cursorb_prec |
>> >> >                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
>> >> > --
>> >> > 1.8.5.5
>> >> >
>> >> > _______________________________________________
>> >> > Intel-gfx mailing list
>> >> > Intel-gfx@lists.freedesktop.org
>> >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>
>> >>
>> >>
>> >> --
>> >> Paulo Zanoni
>> >
>> > --
>> > Ville Syrjälä
>> > Intel OTC
>>
>>
>>
>> --
>> Paulo Zanoni
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Paulo Zanoni
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values

[Paulo Zanoni]

2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The DDL registers can hold 7bit numbers. Make the most of those seven
> bits by adjusting the threshold where we switch between the 64 vs. 32
> precision multipliers.
>
> Also we compute 'entries' to make the decision about precision, and then
> we recompute the same value to calculate the actual drain latency. Just
> use the already calculate 'entries' there.

Just an addition: don't we also want to WARN in case "entires < 64"
(or in case the final result exceeds 7 bits, which is equivalent)?
Could be a separate patch too.

With or without that: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9413184..3aa7959 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
>
>         entries = (clock / 1000) * pixel_size;
> -       *plane_prec_mult = (entries > 256) ?
> +       *plane_prec_mult = (entries > 128) ?
>                 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> -       *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
> -                                                    pixel_size);
> +       *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
>
>         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
> -       *cursor_prec_mult = (entries > 256) ?
> +       *cursor_prec_mult = (entries > 128) ?
>                 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> -       *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
> +       *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
>
>         return true;
>  }
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines

[Paulo Zanoni]

2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add defines for all the watermark registers on modernish gmch platforms.
>
> VLV has increased the number of bits available for certain watermaks so
> expand the masks appropriately. Also vlv and chv have added some extra
> FW registers.
>
> Not sure what happened on chv because a new register called FW9 is now
> at the offset where FW7 was on vlv, while FW7 and FW8 (another new
> register) have been moved off somewhere else. Oh well, well just need
> two defines for FW7 then.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++++++++++++++++-----
>  drivers/gpu/drm/i915/intel_pm.c |  11 ++--
>  2 files changed, 130 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ab5a03..9fab647 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3884,28 +3884,136 @@ enum punit_power_well {
>  #define   DSPARB_BEND_SHIFT    9 /* on 855 */
>  #define   DSPARB_AEND_SHIFT    0
>
> +/* pnv/gen4/g4x/vlv/chv */
>  #define DSPFW1                 (dev_priv->info.display_mmio_offset + 0x70034)
> -#define   DSPFW_SR_SHIFT       23
> -#define   DSPFW_SR_MASK                (0x1ff<<23)
> -#define   DSPFW_CURSORB_SHIFT  16
> -#define   DSPFW_CURSORB_MASK   (0x3f<<16)
> -#define   DSPFW_PLANEB_SHIFT   8
> -#define   DSPFW_PLANEB_MASK    (0x7f<<8)
> -#define   DSPFW_PLANEA_MASK    (0x7f)
> +#define   DSPFW_SR_SHIFT               23
> +#define   DSPFW_SR_MASK                        (0x1ff<<23)
> +#define   DSPFW_CURSORB_SHIFT          16
> +#define   DSPFW_CURSORB_MASK           (0x3f<<16)
> +#define   DSPFW_PLANEB_SHIFT           8
> +#define   DSPFW_PLANEB_MASK            (0x7f<<8)
> +#define   DSPFW_PLANEB_MASK_VLV                (0xff<<8) /* vlv/chv */
> +#define   DSPFW_PLANEA_SHIFT           0
> +#define   DSPFW_PLANEA_MASK            (0x7f<<0)
> +#define   DSPFW_PLANEA_MASK_VLV                (0xff<<0) /* vlv/chv */
>  #define DSPFW2                 (dev_priv->info.display_mmio_offset + 0x70038)
> -#define   DSPFW_CURSORA_MASK   0x00003f00
> -#define   DSPFW_CURSORA_SHIFT  8
> -#define   DSPFW_PLANEC_MASK    (0x7f)
> +#define   DSPFW_FBC_SR_EN              (1<<31)   /* g4x */
> +#define   DSPFW_FBC_SR_SHIFT           28
> +#define   DSPFW_FBC_SR_MASK            (0x7<<28) /* g4x */
> +#define   DSPFW_FBC_HPLL_SR_SHIFT      24
> +#define   DSPFW_FBC_HPLL_SR_MASK       (0xf<<24) /* g4x */
> +#define   DSPFW_SPRITEB_SHIFT          (16)
> +#define   DSPFW_SPRITEB_MASK           (0x7f<<16) /* g4x */
> +#define   DSPFW_SPRITEB_MASK_VLV       (0xff<<16) /* vlv/chv */
> +#define   DSPFW_CURSORA_SHIFT          8
> +#define   DSPFW_CURSORA_MASK           (0x3f<<8)
> +#define   DSPFW_PLANEC_SHIFT_OLD       0
> +#define   DSPFW_PLANEC_MASK_OLD                (0x7f<<0) /* pre-gen4 sprite C */
> +#define   DSPFW_SPRITEA_SHIFT          0
> +#define   DSPFW_SPRITEA_MASK           (0x7f<<0) /* g4x */
> +#define   DSPFW_SPRITEA_MASK_VLV       (0xff<<0) /* vlv/chv */
>  #define DSPFW3                 (dev_priv->info.display_mmio_offset + 0x7003c)
> -#define   DSPFW_HPLL_SR_EN     (1<<31)
> -#define   DSPFW_CURSOR_SR_SHIFT        24
> +#define   DSPFW_HPLL_SR_EN             (1<<31)
>  #define   PINEVIEW_SELF_REFRESH_EN     (1<<30)
> +#define   DSPFW_CURSOR_SR_SHIFT                24
>  #define   DSPFW_CURSOR_SR_MASK         (0x3f<<24)
>  #define   DSPFW_HPLL_CURSOR_SHIFT      16
>  #define   DSPFW_HPLL_CURSOR_MASK       (0x3f<<16)
> -#define   DSPFW_HPLL_SR_MASK           (0x1ff)
> -#define DSPFW4                 (dev_priv->info.display_mmio_offset + 0x70070)
> -#define DSPFW7                 (dev_priv->info.display_mmio_offset + 0x7007c)
> +#define   DSPFW_HPLL_SR_SHIFT          0
> +#define   DSPFW_HPLL_SR_MASK           (0x1ff<<0)
> +
> +/* vlv/chv */
> +#define DSPFW4                 (VLV_DISPLAY_BASE + 0x70070)
> +#define   DSPFW_SPRITEB_WM1_SHIFT      16
> +#define   DSPFW_SPRITEB_WM1_MASK       (0xff<<16)
> +#define   DSPFW_CURSORA_WM1_SHIFT      8
> +#define   DSPFW_CURSORA_WM1_MASK       (0x3f<<8)
> +#define   DSPFW_SPRITEA_WM1_SHIFT      0
> +#define   DSPFW_SPRITEA_WM1_MASK       (0xff<<0)
> +#define DSPFW5                 (VLV_DISPLAY_BASE + 0x70074)
> +#define   DSPFW_PLANEB_WM1_SHIFT       24
> +#define   DSPFW_PLANEB_WM1_MASK                (0xff<<24)
> +#define   DSPFW_PLANEA_WM1_SHIFT       16
> +#define   DSPFW_PLANEA_WM1_MASK                (0xff<<16)
> +#define   DSPFW_CURSORB_WM1_SHIFT      8
> +#define   DSPFW_CURSORB_WM1_MASK       (0x3f<<8)
> +#define   DSPFW_CURSOR_SR_WM1_SHIFT    0
> +#define   DSPFW_CURSOR_SR_WM1_MASK     (0x3f<<0)
> +#define DSPFW6                 (VLV_DISPLAY_BASE + 0x70078)
> +#define   DSPFW_SR_WM1_SHIFT           0
> +#define   DSPFW_SR_WM1_MASK            (0x1ff<<0)
> +#define DSPFW7                 (VLV_DISPLAY_BASE + 0x7007c)
> +#define DSPFW7_CHV             (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
> +#define   DSPFW_SPRITED_WM1_SHIFT      24
> +#define   DSPFW_SPRITED_WM1_MASK       (0xff<<24)
> +#define   DSPFW_SPRITED_SHIFT          16
> +#define   DSPFW_SPRITED_MASK           (0xff<<16)
> +#define   DSPFW_SPRITEC_WM1_SHIFT      8
> +#define   DSPFW_SPRITEC_WM1_MASK       (0xff<<8)
> +#define   DSPFW_SPRITEC_SHIFT          0
> +#define   DSPFW_SPRITEC_MASK           (0xff<<0)
> +#define DSPFW8_CHV             (VLV_DISPLAY_BASE + 0x700b8)
> +#define   DSPFW_SPRITEF_WM1_SHIFT      24
> +#define   DSPFW_SPRITEF_WM1_MASK       (0xff<<24)
> +#define   DSPFW_SPRITEF_SHIFT          16
> +#define   DSPFW_SPRITEF_MASK           (0xff<<16)
> +#define   DSPFW_SPRITEE_WM1_SHIFT      8
> +#define   DSPFW_SPRITEE_WM1_MASK       (0xff<<8)
> +#define   DSPFW_SPRITEE_SHIFT          0
> +#define   DSPFW_SPRITEE_MASK           (0xff<<0)
> +#define DSPFW9_CHV             (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
> +#define   DSPFW_PLANEC_WM1_SHIFT       24
> +#define   DSPFW_PLANEC_WM1_MASK                (0xff<<24)
> +#define   DSPFW_PLANEC_SHIFT           16
> +#define   DSPFW_PLANEC_MASK            (0xff<<16)
> +#define   DSPFW_CURSORC_WM1_SHIFT      8
> +#define   DSPFW_CURSORC_WM1_MASK       (0x3f<<16)
> +#define   DSPFW_CURSORC_SHIFT          0
> +#define   DSPFW_CURSORC_MASK           (0x3f<<0)
> +
> +/* vlv/chv high order bits */
> +#define DSPHOWM                        (VLV_DISPLAY_BASE + 0x70064)
> +#define   DSPFW_SR_HI_SHIFT            24
> +#define   DSPFW_SR_HI_MASK             (1<<24)
> +#define   DSPFW_SPRITEF_HI_SHIFT       23
> +#define   DSPFW_SPRITEF_HI_MASK                (1<<23)
> +#define   DSPFW_SPRITEE_HI_SHIFT       22
> +#define   DSPFW_SPRITEE_HI_MASK                (1<<22)
> +#define   DSPFW_PLANEC_HI_SHIFT                21
> +#define   DSPFW_PLANEC_HI_MASK         (1<<21)

It looks like bits 23:21 were removed. They are just marked as reserved now.


> +#define   DSPFW_SPRITED_HI_SHIFT       20
> +#define   DSPFW_SPRITED_HI_MASK                (1<<20)
> +#define   DSPFW_SPRITEC_HI_SHIFT       16
> +#define   DSPFW_SPRITEC_HI_MASK                (1<<16)
> +#define   DSPFW_PLANEB_HI_SHIFT                12
> +#define   DSPFW_PLANEB_HI_MASK         (1<<12)
> +#define   DSPFW_SPRITEB_HI_SHIFT       8
> +#define   DSPFW_SPRITEB_HI_MASK                (1<<8)
> +#define   DSPFW_SPRITEA_HI_SHIFT       4
> +#define   DSPFW_SPRITEA_HI_MASK                (1<<4)
> +#define   DSPFW_PLANEA_HI_SHIFT                0
> +#define   DSPFW_PLANEA_HI_MASK         (1<<0)
> +#define DSPHOWM1               (VLV_DISPLAY_BASE + 0x70064)

Should be 0x70068.


> +#define   DSPFW_SR_WM1_HI_SHIFT                24
> +#define   DSPFW_SR_WM1_HI_MASK         (1<<24)
> +#define   DSPFW_SPRITEF_WM1_HI_SHIFT   23
> +#define   DSPFW_SPRITEF_WM1_HI_MASK    (1<<23)
> +#define   DSPFW_SPRITEE_WM1_HI_SHIFT   22
> +#define   DSPFW_SPRITEE_WM1_HI_MASK    (1<<22)
> +#define   DSPFW_PLANEC_WM1_HI_SHIFT    21
> +#define   DSPFW_PLANEC_WM1_HI_MASK     (1<<21)

Same story about 23:21 here.

Everything else looks correct. With the details above
fixed/addressed/explained: Reviewed-by: Paulo Zanoni
<paulo.r.zanoni@intel.com>.

> +#define   DSPFW_SPRITED_WM1_HI_SHIFT   20
> +#define   DSPFW_SPRITED_WM1_HI_MASK    (1<<20)
> +#define   DSPFW_SPRITEC_WM1_HI_SHIFT   16
> +#define   DSPFW_SPRITEC_WM1_HI_MASK    (1<<16)
> +#define   DSPFW_PLANEB_WM1_HI_SHIFT    12
> +#define   DSPFW_PLANEB_WM1_HI_MASK     (1<<12)
> +#define   DSPFW_SPRITEB_WM1_HI_SHIFT   8
> +#define   DSPFW_SPRITEB_WM1_HI_MASK    (1<<8)
> +#define   DSPFW_SPRITEA_WM1_HI_SHIFT   4
> +#define   DSPFW_SPRITEA_WM1_HI_MASK    (1<<4)
> +#define   DSPFW_PLANEA_WM1_HI_SHIFT    0
> +#define   DSPFW_PLANEA_WM1_HI_MASK     (1<<0)
>
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32     32
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3aa7959..dc858b5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1360,7 +1360,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
>                    (plane_sr << DSPFW_SR_SHIFT) |
>                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
>                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
> -                  planea_wm);
> +                  (planea_wm << DSPFW_PLANEA_SHIFT));
>         I915_WRITE(DSPFW2,
>                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
>                    (cursora_wm << DSPFW_CURSORA_SHIFT));
> @@ -1412,7 +1412,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
>                    (plane_sr << DSPFW_SR_SHIFT) |
>                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
>                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
> -                  planea_wm);
> +                  (planea_wm << DSPFW_PLANEA_SHIFT));
>         I915_WRITE(DSPFW2,
>                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
>                    (cursora_wm << DSPFW_CURSORA_SHIFT));
> @@ -1484,8 +1484,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
>
>         /* 965 has limitations... */
>         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
> -                  (8 << 16) | (8 << 8) | (8 << 0));
> -       I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
> +                  (8 << DSPFW_CURSORB_SHIFT) |
> +                  (8 << DSPFW_PLANEB_SHIFT) |
> +                  (8 << DSPFW_PLANEA_SHIFT));
> +       I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
> +                  (8 << DSPFW_PLANEC_SHIFT_OLD));
>         /* update cursor SR watermark */
>         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
>  }
> --
> 1.8.5.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
_______________________________________________
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Re: [PATCH 28/40] drm/i915: Add cherryview_update_wm()

[Paulo Zanoni]

2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV has a third pipe so we need to compute the watermarks for its
> planes. Add cherryview_update_wm() to do just that.

Ok, so basically the only real difference between this code and VLV's
code is when you enable CXSR: on VLV you just enable CXSR after the
other WM registers are already written. I wonder if this is to prevent
any intermediate situations where the previous WM values did not allow
CXSR, so enabling it first would result in errors/underruns. On this
case, the CHV function would need to do the same thing as VLV, right?
Do you have any specific reason for keeping the CXSR code different on
CHV?

Also, instead of adding a new function, you could probably just
rewrite vlv_update_wm to use for_each_pipe() instead of the current
method. You'd define plane_wm[num_pipes] arrays instead of one
variable per pipe, then you would be able to use the same function for
both VLV and CHV. Anyway, I don't think we should block your patch
based on this suggestion, so if you just provide a good explanation
for the CXSR question - or a new patch - I'll give a R-B tag.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 77 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 76 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cb0b4b4..346dced 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1364,6 +1364,81 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
>                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
>  }
>
> +static void cherryview_update_wm(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       static const int sr_latency_ns = 12000;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       int planea_wm, planeb_wm, planec_wm;
> +       int cursora_wm, cursorb_wm, cursorc_wm;
> +       int plane_sr, cursor_sr;
> +       int ignore_plane_sr, ignore_cursor_sr;
> +       unsigned int enabled = 0;
> +
> +       vlv_update_drain_latency(dev);
> +
> +       if (g4x_compute_wm0(dev, PIPE_A,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planea_wm, &cursora_wm))
> +               enabled |= 1 << PIPE_A;
> +
> +       if (g4x_compute_wm0(dev, PIPE_B,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planeb_wm, &cursorb_wm))
> +               enabled |= 1 << PIPE_B;
> +
> +       if (g4x_compute_wm0(dev, PIPE_C,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planec_wm, &cursorc_wm))
> +               enabled |= 1 << PIPE_C;
> +
> +       if (single_plane_enabled(enabled) &&
> +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> +                            sr_latency_ns,
> +                            &valleyview_wm_info,
> +                            &valleyview_cursor_wm_info,
> +                            &plane_sr, &ignore_cursor_sr) &&
> +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> +                            2*sr_latency_ns,
> +                            &valleyview_wm_info,
> +                            &valleyview_cursor_wm_info,
> +                            &ignore_plane_sr, &cursor_sr)) {
> +               I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> +       } else {
> +               I915_WRITE(FW_BLC_SELF_VLV,
> +                          I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
> +               plane_sr = cursor_sr = 0;
> +       }
> +
> +       DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
> +                     "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
> +                     "SR: plane=%d, cursor=%d\n",
> +                     planea_wm, cursora_wm,
> +                     planeb_wm, cursorb_wm,
> +                     planec_wm, cursorc_wm,
> +                     plane_sr, cursor_sr);
> +
> +       I915_WRITE(DSPFW1,
> +                  (plane_sr << DSPFW_SR_SHIFT) |
> +                  (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> +                  (planeb_wm << DSPFW_PLANEB_SHIFT) |
> +                  (planea_wm << DSPFW_PLANEA_SHIFT));
> +       I915_WRITE(DSPFW2,
> +                  (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> +                  (cursora_wm << DSPFW_CURSORA_SHIFT));
> +       I915_WRITE(DSPFW3,
> +                  (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
> +                  (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> +       I915_WRITE(DSPFW9_CHV,
> +                  (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
> +                                             DSPFW_CURSORC_MASK)) |
> +                  (planec_wm << DSPFW_PLANEC_SHIFT) |
> +                  (cursorc_wm << DSPFW_CURSORC_SHIFT));
> +}
> +
>  static void g4x_update_wm(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
> @@ -7046,7 +7121,7 @@ void intel_init_pm(struct drm_device *dev)
>                 else if (INTEL_INFO(dev)->gen == 8)
>                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
>         } else if (IS_CHERRYVIEW(dev)) {
> -               dev_priv->display.update_wm = valleyview_update_wm;
> +               dev_priv->display.update_wm = cherryview_update_wm;
>                 dev_priv->display.init_clock_gating =
>                         cherryview_init_clock_gating;
>         } else if (IS_VALLEYVIEW(dev)) {
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines

[Ville Syrjälä]

On Thu, Jul 31, 2014 at 05:16:21PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add defines for all the watermark registers on modernish gmch platforms.
> >
> > VLV has increased the number of bits available for certain watermaks so
> > expand the masks appropriately. Also vlv and chv have added some extra
> > FW registers.
> >
> > Not sure what happened on chv because a new register called FW9 is now
> > at the offset where FW7 was on vlv, while FW7 and FW8 (another new
> > register) have been moved off somewhere else. Oh well, well just need
> > two defines for FW7 then.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++++++++++++++++-----
> >  drivers/gpu/drm/i915/intel_pm.c |  11 ++--
> >  2 files changed, 130 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7ab5a03..9fab647 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3884,28 +3884,136 @@ enum punit_power_well {
> >  #define   DSPARB_BEND_SHIFT    9 /* on 855 */
> >  #define   DSPARB_AEND_SHIFT    0
> >
> > +/* pnv/gen4/g4x/vlv/chv */
> >  #define DSPFW1                 (dev_priv->info.display_mmio_offset + 0x70034)
> > -#define   DSPFW_SR_SHIFT       23
> > -#define   DSPFW_SR_MASK                (0x1ff<<23)
> > -#define   DSPFW_CURSORB_SHIFT  16
> > -#define   DSPFW_CURSORB_MASK   (0x3f<<16)
> > -#define   DSPFW_PLANEB_SHIFT   8
> > -#define   DSPFW_PLANEB_MASK    (0x7f<<8)
> > -#define   DSPFW_PLANEA_MASK    (0x7f)
> > +#define   DSPFW_SR_SHIFT               23
> > +#define   DSPFW_SR_MASK                        (0x1ff<<23)
> > +#define   DSPFW_CURSORB_SHIFT          16
> > +#define   DSPFW_CURSORB_MASK           (0x3f<<16)
> > +#define   DSPFW_PLANEB_SHIFT           8
> > +#define   DSPFW_PLANEB_MASK            (0x7f<<8)
> > +#define   DSPFW_PLANEB_MASK_VLV                (0xff<<8) /* vlv/chv */
> > +#define   DSPFW_PLANEA_SHIFT           0
> > +#define   DSPFW_PLANEA_MASK            (0x7f<<0)
> > +#define   DSPFW_PLANEA_MASK_VLV                (0xff<<0) /* vlv/chv */
> >  #define DSPFW2                 (dev_priv->info.display_mmio_offset + 0x70038)
> > -#define   DSPFW_CURSORA_MASK   0x00003f00
> > -#define   DSPFW_CURSORA_SHIFT  8
> > -#define   DSPFW_PLANEC_MASK    (0x7f)
> > +#define   DSPFW_FBC_SR_EN              (1<<31)   /* g4x */
> > +#define   DSPFW_FBC_SR_SHIFT           28
> > +#define   DSPFW_FBC_SR_MASK            (0x7<<28) /* g4x */
> > +#define   DSPFW_FBC_HPLL_SR_SHIFT      24
> > +#define   DSPFW_FBC_HPLL_SR_MASK       (0xf<<24) /* g4x */
> > +#define   DSPFW_SPRITEB_SHIFT          (16)
> > +#define   DSPFW_SPRITEB_MASK           (0x7f<<16) /* g4x */
> > +#define   DSPFW_SPRITEB_MASK_VLV       (0xff<<16) /* vlv/chv */
> > +#define   DSPFW_CURSORA_SHIFT          8
> > +#define   DSPFW_CURSORA_MASK           (0x3f<<8)
> > +#define   DSPFW_PLANEC_SHIFT_OLD       0
> > +#define   DSPFW_PLANEC_MASK_OLD                (0x7f<<0) /* pre-gen4 sprite C */
> > +#define   DSPFW_SPRITEA_SHIFT          0
> > +#define   DSPFW_SPRITEA_MASK           (0x7f<<0) /* g4x */
> > +#define   DSPFW_SPRITEA_MASK_VLV       (0xff<<0) /* vlv/chv */
> >  #define DSPFW3                 (dev_priv->info.display_mmio_offset + 0x7003c)
> > -#define   DSPFW_HPLL_SR_EN     (1<<31)
> > -#define   DSPFW_CURSOR_SR_SHIFT        24
> > +#define   DSPFW_HPLL_SR_EN             (1<<31)
> >  #define   PINEVIEW_SELF_REFRESH_EN     (1<<30)
> > +#define   DSPFW_CURSOR_SR_SHIFT                24
> >  #define   DSPFW_CURSOR_SR_MASK         (0x3f<<24)
> >  #define   DSPFW_HPLL_CURSOR_SHIFT      16
> >  #define   DSPFW_HPLL_CURSOR_MASK       (0x3f<<16)
> > -#define   DSPFW_HPLL_SR_MASK           (0x1ff)
> > -#define DSPFW4                 (dev_priv->info.display_mmio_offset + 0x70070)
> > -#define DSPFW7                 (dev_priv->info.display_mmio_offset + 0x7007c)
> > +#define   DSPFW_HPLL_SR_SHIFT          0
> > +#define   DSPFW_HPLL_SR_MASK           (0x1ff<<0)
> > +
> > +/* vlv/chv */
> > +#define DSPFW4                 (VLV_DISPLAY_BASE + 0x70070)
> > +#define   DSPFW_SPRITEB_WM1_SHIFT      16
> > +#define   DSPFW_SPRITEB_WM1_MASK       (0xff<<16)
> > +#define   DSPFW_CURSORA_WM1_SHIFT      8
> > +#define   DSPFW_CURSORA_WM1_MASK       (0x3f<<8)
> > +#define   DSPFW_SPRITEA_WM1_SHIFT      0
> > +#define   DSPFW_SPRITEA_WM1_MASK       (0xff<<0)
> > +#define DSPFW5                 (VLV_DISPLAY_BASE + 0x70074)
> > +#define   DSPFW_PLANEB_WM1_SHIFT       24
> > +#define   DSPFW_PLANEB_WM1_MASK                (0xff<<24)
> > +#define   DSPFW_PLANEA_WM1_SHIFT       16
> > +#define   DSPFW_PLANEA_WM1_MASK                (0xff<<16)
> > +#define   DSPFW_CURSORB_WM1_SHIFT      8
> > +#define   DSPFW_CURSORB_WM1_MASK       (0x3f<<8)
> > +#define   DSPFW_CURSOR_SR_WM1_SHIFT    0
> > +#define   DSPFW_CURSOR_SR_WM1_MASK     (0x3f<<0)
> > +#define DSPFW6                 (VLV_DISPLAY_BASE + 0x70078)
> > +#define   DSPFW_SR_WM1_SHIFT           0
> > +#define   DSPFW_SR_WM1_MASK            (0x1ff<<0)
> > +#define DSPFW7                 (VLV_DISPLAY_BASE + 0x7007c)
> > +#define DSPFW7_CHV             (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
> > +#define   DSPFW_SPRITED_WM1_SHIFT      24
> > +#define   DSPFW_SPRITED_WM1_MASK       (0xff<<24)
> > +#define   DSPFW_SPRITED_SHIFT          16
> > +#define   DSPFW_SPRITED_MASK           (0xff<<16)
> > +#define   DSPFW_SPRITEC_WM1_SHIFT      8
> > +#define   DSPFW_SPRITEC_WM1_MASK       (0xff<<8)
> > +#define   DSPFW_SPRITEC_SHIFT          0
> > +#define   DSPFW_SPRITEC_MASK           (0xff<<0)
> > +#define DSPFW8_CHV             (VLV_DISPLAY_BASE + 0x700b8)
> > +#define   DSPFW_SPRITEF_WM1_SHIFT      24
> > +#define   DSPFW_SPRITEF_WM1_MASK       (0xff<<24)
> > +#define   DSPFW_SPRITEF_SHIFT          16
> > +#define   DSPFW_SPRITEF_MASK           (0xff<<16)
> > +#define   DSPFW_SPRITEE_WM1_SHIFT      8
> > +#define   DSPFW_SPRITEE_WM1_MASK       (0xff<<8)
> > +#define   DSPFW_SPRITEE_SHIFT          0
> > +#define   DSPFW_SPRITEE_MASK           (0xff<<0)
> > +#define DSPFW9_CHV             (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
> > +#define   DSPFW_PLANEC_WM1_SHIFT       24
> > +#define   DSPFW_PLANEC_WM1_MASK                (0xff<<24)
> > +#define   DSPFW_PLANEC_SHIFT           16
> > +#define   DSPFW_PLANEC_MASK            (0xff<<16)
> > +#define   DSPFW_CURSORC_WM1_SHIFT      8
> > +#define   DSPFW_CURSORC_WM1_MASK       (0x3f<<16)
> > +#define   DSPFW_CURSORC_SHIFT          0
> > +#define   DSPFW_CURSORC_MASK           (0x3f<<0)
> > +
> > +/* vlv/chv high order bits */
> > +#define DSPHOWM                        (VLV_DISPLAY_BASE + 0x70064)
> > +#define   DSPFW_SR_HI_SHIFT            24
> > +#define   DSPFW_SR_HI_MASK             (1<<24)
> > +#define   DSPFW_SPRITEF_HI_SHIFT       23
> > +#define   DSPFW_SPRITEF_HI_MASK                (1<<23)
> > +#define   DSPFW_SPRITEE_HI_SHIFT       22
> > +#define   DSPFW_SPRITEE_HI_MASK                (1<<22)
> > +#define   DSPFW_PLANEC_HI_SHIFT                21
> > +#define   DSPFW_PLANEC_HI_MASK         (1<<21)
> 
> It looks like bits 23:21 were removed. They are just marked as reserved now.

I see them in the CHV doc. They're for pipe C planes, so CHV only.

> 
> 
> > +#define   DSPFW_SPRITED_HI_SHIFT       20
> > +#define   DSPFW_SPRITED_HI_MASK                (1<<20)
> > +#define   DSPFW_SPRITEC_HI_SHIFT       16
> > +#define   DSPFW_SPRITEC_HI_MASK                (1<<16)
> > +#define   DSPFW_PLANEB_HI_SHIFT                12
> > +#define   DSPFW_PLANEB_HI_MASK         (1<<12)
> > +#define   DSPFW_SPRITEB_HI_SHIFT       8
> > +#define   DSPFW_SPRITEB_HI_MASK                (1<<8)
> > +#define   DSPFW_SPRITEA_HI_SHIFT       4
> > +#define   DSPFW_SPRITEA_HI_MASK                (1<<4)
> > +#define   DSPFW_PLANEA_HI_SHIFT                0
> > +#define   DSPFW_PLANEA_HI_MASK         (1<<0)
> > +#define DSPHOWM1               (VLV_DISPLAY_BASE + 0x70064)
> 
> Should be 0x70068.

Nice catch. Will fix.

> 
> 
> > +#define   DSPFW_SR_WM1_HI_SHIFT                24
> > +#define   DSPFW_SR_WM1_HI_MASK         (1<<24)
> > +#define   DSPFW_SPRITEF_WM1_HI_SHIFT   23
> > +#define   DSPFW_SPRITEF_WM1_HI_MASK    (1<<23)
> > +#define   DSPFW_SPRITEE_WM1_HI_SHIFT   22
> > +#define   DSPFW_SPRITEE_WM1_HI_MASK    (1<<22)
> > +#define   DSPFW_PLANEC_WM1_HI_SHIFT    21
> > +#define   DSPFW_PLANEC_WM1_HI_MASK     (1<<21)
> 
> Same story about 23:21 here.
> 
> Everything else looks correct. With the details above
> fixed/addressed/explained: Reviewed-by: Paulo Zanoni
> <paulo.r.zanoni@intel.com>.
> 
> > +#define   DSPFW_SPRITED_WM1_HI_SHIFT   20
> > +#define   DSPFW_SPRITED_WM1_HI_MASK    (1<<20)
> > +#define   DSPFW_SPRITEC_WM1_HI_SHIFT   16
> > +#define   DSPFW_SPRITEC_WM1_HI_MASK    (1<<16)
> > +#define   DSPFW_PLANEB_WM1_HI_SHIFT    12
> > +#define   DSPFW_PLANEB_WM1_HI_MASK     (1<<12)
> > +#define   DSPFW_SPRITEB_WM1_HI_SHIFT   8
> > +#define   DSPFW_SPRITEB_WM1_HI_MASK    (1<<8)
> > +#define   DSPFW_SPRITEA_WM1_HI_SHIFT   4
> > +#define   DSPFW_SPRITEA_WM1_HI_MASK    (1<<4)
> > +#define   DSPFW_PLANEA_WM1_HI_SHIFT    0
> > +#define   DSPFW_PLANEA_WM1_HI_MASK     (1<<0)
> >
> >  /* drain latency register values*/
> >  #define DRAIN_LATENCY_PRECISION_32     32
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3aa7959..dc858b5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1360,7 +1360,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
> >                    (plane_sr << DSPFW_SR_SHIFT) |
> >                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> >                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > -                  planea_wm);
> > +                  (planea_wm << DSPFW_PLANEA_SHIFT));
> >         I915_WRITE(DSPFW2,
> >                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> >                    (cursora_wm << DSPFW_CURSORA_SHIFT));
> > @@ -1412,7 +1412,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
> >                    (plane_sr << DSPFW_SR_SHIFT) |
> >                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> >                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > -                  planea_wm);
> > +                  (planea_wm << DSPFW_PLANEA_SHIFT));
> >         I915_WRITE(DSPFW2,
> >                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> >                    (cursora_wm << DSPFW_CURSORA_SHIFT));
> > @@ -1484,8 +1484,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> >
> >         /* 965 has limitations... */
> >         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
> > -                  (8 << 16) | (8 << 8) | (8 << 0));
> > -       I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
> > +                  (8 << DSPFW_CURSORB_SHIFT) |
> > +                  (8 << DSPFW_PLANEB_SHIFT) |
> > +                  (8 << DSPFW_PLANEA_SHIFT));
> > +       I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
> > +                  (8 << DSPFW_PLANEC_SHIFT_OLD));
> >         /* update cursor SR watermark */
> >         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> >  }
> > --
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 28/40] drm/i915: Add cherryview_update_wm()

[Ville Syrjälä]

On Thu, Jul 31, 2014 at 05:57:33PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV has a third pipe so we need to compute the watermarks for its
> > planes. Add cherryview_update_wm() to do just that.
> 
> Ok, so basically the only real difference between this code and VLV's
> code is when you enable CXSR: on VLV you just enable CXSR after the
> other WM registers are already written. I wonder if this is to prevent
> any intermediate situations where the previous WM values did not allow
> CXSR, so enabling it first would result in errors/underruns. On this
> case, the CHV function would need to do the same thing as VLV, right?
> Do you have any specific reason for keeping the CXSR code different on
> CHV?

I think the difference is just due to me copy pasting the VLV function
before Imre's cxsr fixes went in. I'll respin the patch based on the
latest VLV code.

> 
> Also, instead of adding a new function, you could probably just
> rewrite vlv_update_wm to use for_each_pipe() instead of the current
> method. You'd define plane_wm[num_pipes] arrays instead of one
> variable per pipe, then you would be able to use the same function for
> both VLV and CHV. Anyway, I don't think we should block your patch
> based on this suggestion, so if you just provide a good explanation
> for the CXSR question - or a new patch - I'll give a R-B tag.

I did consider it, but I didn't want to start refactoring too much in
this patch. We might be able to unify more of the gmch watermark code
using your suggestion, or even making it just recompute the watermarks
for the current pipe. But that's better left for another patch/series.

> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 77 ++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 76 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cb0b4b4..346dced 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1364,6 +1364,81 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
> >                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> >  }
> >
> > +static void cherryview_update_wm(struct drm_crtc *crtc)
> > +{
> > +       struct drm_device *dev = crtc->dev;
> > +       static const int sr_latency_ns = 12000;
> > +       struct drm_i915_private *dev_priv = dev->dev_private;
> > +       int planea_wm, planeb_wm, planec_wm;
> > +       int cursora_wm, cursorb_wm, cursorc_wm;
> > +       int plane_sr, cursor_sr;
> > +       int ignore_plane_sr, ignore_cursor_sr;
> > +       unsigned int enabled = 0;
> > +
> > +       vlv_update_drain_latency(dev);
> > +
> > +       if (g4x_compute_wm0(dev, PIPE_A,
> > +                           &valleyview_wm_info, latency_ns,
> > +                           &valleyview_cursor_wm_info, latency_ns,
> > +                           &planea_wm, &cursora_wm))
> > +               enabled |= 1 << PIPE_A;
> > +
> > +       if (g4x_compute_wm0(dev, PIPE_B,
> > +                           &valleyview_wm_info, latency_ns,
> > +                           &valleyview_cursor_wm_info, latency_ns,
> > +                           &planeb_wm, &cursorb_wm))
> > +               enabled |= 1 << PIPE_B;
> > +
> > +       if (g4x_compute_wm0(dev, PIPE_C,
> > +                           &valleyview_wm_info, latency_ns,
> > +                           &valleyview_cursor_wm_info, latency_ns,
> > +                           &planec_wm, &cursorc_wm))
> > +               enabled |= 1 << PIPE_C;
> > +
> > +       if (single_plane_enabled(enabled) &&
> > +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> > +                            sr_latency_ns,
> > +                            &valleyview_wm_info,
> > +                            &valleyview_cursor_wm_info,
> > +                            &plane_sr, &ignore_cursor_sr) &&
> > +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> > +                            2*sr_latency_ns,
> > +                            &valleyview_wm_info,
> > +                            &valleyview_cursor_wm_info,
> > +                            &ignore_plane_sr, &cursor_sr)) {
> > +               I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> > +       } else {
> > +               I915_WRITE(FW_BLC_SELF_VLV,
> > +                          I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
> > +               plane_sr = cursor_sr = 0;
> > +       }
> > +
> > +       DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
> > +                     "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
> > +                     "SR: plane=%d, cursor=%d\n",
> > +                     planea_wm, cursora_wm,
> > +                     planeb_wm, cursorb_wm,
> > +                     planec_wm, cursorc_wm,
> > +                     plane_sr, cursor_sr);
> > +
> > +       I915_WRITE(DSPFW1,
> > +                  (plane_sr << DSPFW_SR_SHIFT) |
> > +                  (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> > +                  (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > +                  (planea_wm << DSPFW_PLANEA_SHIFT));
> > +       I915_WRITE(DSPFW2,
> > +                  (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> > +                  (cursora_wm << DSPFW_CURSORA_SHIFT));
> > +       I915_WRITE(DSPFW3,
> > +                  (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
> > +                  (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> > +       I915_WRITE(DSPFW9_CHV,
> > +                  (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
> > +                                             DSPFW_CURSORC_MASK)) |
> > +                  (planec_wm << DSPFW_PLANEC_SHIFT) |
> > +                  (cursorc_wm << DSPFW_CURSORC_SHIFT));
> > +}
> > +
> >  static void g4x_update_wm(struct drm_crtc *crtc)
> >  {
> >         struct drm_device *dev = crtc->dev;
> > @@ -7046,7 +7121,7 @@ void intel_init_pm(struct drm_device *dev)
> >                 else if (INTEL_INFO(dev)->gen == 8)
> >                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
> >         } else if (IS_CHERRYVIEW(dev)) {
> > -               dev_priv->display.update_wm = valleyview_update_wm;
> > +               dev_priv->display.update_wm = cherryview_update_wm;
> >                 dev_priv->display.init_clock_gating =
> >                         cherryview_init_clock_gating;
> >         } else if (IS_VALLEYVIEW(dev)) {
> > --
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 25/40] drm/i915: Fill out the FWx watermark register defines

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add defines for all the watermark registers on modernish gmch platforms.

VLV has increased the number of bits available for certain watermaks so
expand the masks appropriately. Also vlv and chv have added some extra
FW registers.

Not sure what happened on chv because a new register called FW9 is now
at the offset where FW7 was on vlv, while FW7 and FW8 (another new
register) have been moved off somewhere else. Oh well, well just need
two defines for FW7 then.

v2: Fix DSPHOWM1 offset (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_pm.c |  11 ++--
 2 files changed, 130 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53117a9..e4163fe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3901,28 +3901,136 @@ enum punit_power_well {
 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
 #define   DSPARB_AEND_SHIFT	0
 
+/* pnv/gen4/g4x/vlv/chv */
 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
-#define   DSPFW_SR_SHIFT	23
-#define   DSPFW_SR_MASK		(0x1ff<<23)
-#define   DSPFW_CURSORB_SHIFT	16
-#define   DSPFW_CURSORB_MASK	(0x3f<<16)
-#define   DSPFW_PLANEB_SHIFT	8
-#define   DSPFW_PLANEB_MASK	(0x7f<<8)
-#define   DSPFW_PLANEA_MASK	(0x7f)
+#define   DSPFW_SR_SHIFT		23
+#define   DSPFW_SR_MASK			(0x1ff<<23)
+#define   DSPFW_CURSORB_SHIFT		16
+#define   DSPFW_CURSORB_MASK		(0x3f<<16)
+#define   DSPFW_PLANEB_SHIFT		8
+#define   DSPFW_PLANEB_MASK		(0x7f<<8)
+#define   DSPFW_PLANEB_MASK_VLV		(0xff<<8) /* vlv/chv */
+#define   DSPFW_PLANEA_SHIFT		0
+#define   DSPFW_PLANEA_MASK		(0x7f<<0)
+#define   DSPFW_PLANEA_MASK_VLV		(0xff<<0) /* vlv/chv */
 #define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
-#define   DSPFW_CURSORA_MASK	0x00003f00
-#define   DSPFW_CURSORA_SHIFT	8
-#define   DSPFW_PLANEC_MASK	(0x7f)
+#define   DSPFW_FBC_SR_EN		(1<<31)	  /* g4x */
+#define   DSPFW_FBC_SR_SHIFT		28
+#define   DSPFW_FBC_SR_MASK		(0x7<<28) /* g4x */
+#define   DSPFW_FBC_HPLL_SR_SHIFT	24
+#define   DSPFW_FBC_HPLL_SR_MASK	(0xf<<24) /* g4x */
+#define   DSPFW_SPRITEB_SHIFT		(16)
+#define   DSPFW_SPRITEB_MASK		(0x7f<<16) /* g4x */
+#define   DSPFW_SPRITEB_MASK_VLV	(0xff<<16) /* vlv/chv */
+#define   DSPFW_CURSORA_SHIFT		8
+#define   DSPFW_CURSORA_MASK		(0x3f<<8)
+#define   DSPFW_PLANEC_SHIFT_OLD	0
+#define   DSPFW_PLANEC_MASK_OLD		(0x7f<<0) /* pre-gen4 sprite C */
+#define   DSPFW_SPRITEA_SHIFT		0
+#define   DSPFW_SPRITEA_MASK		(0x7f<<0) /* g4x */
+#define   DSPFW_SPRITEA_MASK_VLV	(0xff<<0) /* vlv/chv */
 #define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
-#define   DSPFW_HPLL_SR_EN	(1<<31)
-#define   DSPFW_CURSOR_SR_SHIFT	24
+#define   DSPFW_HPLL_SR_EN		(1<<31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
+#define   DSPFW_CURSOR_SR_SHIFT		24
 #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
 #define   DSPFW_HPLL_CURSOR_SHIFT	16
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
-#define   DSPFW_HPLL_SR_MASK		(0x1ff)
-#define DSPFW4			(dev_priv->info.display_mmio_offset + 0x70070)
-#define DSPFW7			(dev_priv->info.display_mmio_offset + 0x7007c)
+#define   DSPFW_HPLL_SR_SHIFT		0
+#define   DSPFW_HPLL_SR_MASK		(0x1ff<<0)
+
+/* vlv/chv */
+#define DSPFW4			(VLV_DISPLAY_BASE + 0x70070)
+#define   DSPFW_SPRITEB_WM1_SHIFT	16
+#define   DSPFW_SPRITEB_WM1_MASK	(0xff<<16)
+#define   DSPFW_CURSORA_WM1_SHIFT	8
+#define   DSPFW_CURSORA_WM1_MASK	(0x3f<<8)
+#define   DSPFW_SPRITEA_WM1_SHIFT	0
+#define   DSPFW_SPRITEA_WM1_MASK	(0xff<<0)
+#define DSPFW5			(VLV_DISPLAY_BASE + 0x70074)
+#define   DSPFW_PLANEB_WM1_SHIFT	24
+#define   DSPFW_PLANEB_WM1_MASK		(0xff<<24)
+#define   DSPFW_PLANEA_WM1_SHIFT	16
+#define   DSPFW_PLANEA_WM1_MASK		(0xff<<16)
+#define   DSPFW_CURSORB_WM1_SHIFT	8
+#define   DSPFW_CURSORB_WM1_MASK	(0x3f<<8)
+#define   DSPFW_CURSOR_SR_WM1_SHIFT	0
+#define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f<<0)
+#define DSPFW6			(VLV_DISPLAY_BASE + 0x70078)
+#define   DSPFW_SR_WM1_SHIFT		0
+#define   DSPFW_SR_WM1_MASK		(0x1ff<<0)
+#define DSPFW7			(VLV_DISPLAY_BASE + 0x7007c)
+#define DSPFW7_CHV		(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
+#define   DSPFW_SPRITED_WM1_SHIFT	24
+#define   DSPFW_SPRITED_WM1_MASK	(0xff<<24)
+#define   DSPFW_SPRITED_SHIFT		16
+#define   DSPFW_SPRITED_MASK		(0xff<<16)
+#define   DSPFW_SPRITEC_WM1_SHIFT	8
+#define   DSPFW_SPRITEC_WM1_MASK	(0xff<<8)
+#define   DSPFW_SPRITEC_SHIFT		0
+#define   DSPFW_SPRITEC_MASK		(0xff<<0)
+#define DSPFW8_CHV		(VLV_DISPLAY_BASE + 0x700b8)
+#define   DSPFW_SPRITEF_WM1_SHIFT	24
+#define   DSPFW_SPRITEF_WM1_MASK	(0xff<<24)
+#define   DSPFW_SPRITEF_SHIFT		16
+#define   DSPFW_SPRITEF_MASK		(0xff<<16)
+#define   DSPFW_SPRITEE_WM1_SHIFT	8
+#define   DSPFW_SPRITEE_WM1_MASK	(0xff<<8)
+#define   DSPFW_SPRITEE_SHIFT		0
+#define   DSPFW_SPRITEE_MASK		(0xff<<0)
+#define DSPFW9_CHV		(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
+#define   DSPFW_PLANEC_WM1_SHIFT	24
+#define   DSPFW_PLANEC_WM1_MASK		(0xff<<24)
+#define   DSPFW_PLANEC_SHIFT		16
+#define   DSPFW_PLANEC_MASK		(0xff<<16)
+#define   DSPFW_CURSORC_WM1_SHIFT	8
+#define   DSPFW_CURSORC_WM1_MASK	(0x3f<<16)
+#define   DSPFW_CURSORC_SHIFT		0
+#define   DSPFW_CURSORC_MASK		(0x3f<<0)
+
+/* vlv/chv high order bits */
+#define DSPHOWM			(VLV_DISPLAY_BASE + 0x70064)
+#define   DSPFW_SR_HI_SHIFT		24
+#define   DSPFW_SR_HI_MASK		(1<<24)
+#define   DSPFW_SPRITEF_HI_SHIFT	23
+#define   DSPFW_SPRITEF_HI_MASK		(1<<23)
+#define   DSPFW_SPRITEE_HI_SHIFT	22
+#define   DSPFW_SPRITEE_HI_MASK		(1<<22)
+#define   DSPFW_PLANEC_HI_SHIFT		21
+#define   DSPFW_PLANEC_HI_MASK		(1<<21)
+#define   DSPFW_SPRITED_HI_SHIFT	20
+#define   DSPFW_SPRITED_HI_MASK		(1<<20)
+#define   DSPFW_SPRITEC_HI_SHIFT	16
+#define   DSPFW_SPRITEC_HI_MASK		(1<<16)
+#define   DSPFW_PLANEB_HI_SHIFT		12
+#define   DSPFW_PLANEB_HI_MASK		(1<<12)
+#define   DSPFW_SPRITEB_HI_SHIFT	8
+#define   DSPFW_SPRITEB_HI_MASK		(1<<8)
+#define   DSPFW_SPRITEA_HI_SHIFT	4
+#define   DSPFW_SPRITEA_HI_MASK		(1<<4)
+#define   DSPFW_PLANEA_HI_SHIFT		0
+#define   DSPFW_PLANEA_HI_MASK		(1<<0)
+#define DSPHOWM1		(VLV_DISPLAY_BASE + 0x70068)
+#define   DSPFW_SR_WM1_HI_SHIFT		24
+#define   DSPFW_SR_WM1_HI_MASK		(1<<24)
+#define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
+#define   DSPFW_SPRITEF_WM1_HI_MASK	(1<<23)
+#define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
+#define   DSPFW_SPRITEE_WM1_HI_MASK	(1<<22)
+#define   DSPFW_PLANEC_WM1_HI_SHIFT	21
+#define   DSPFW_PLANEC_WM1_HI_MASK	(1<<21)
+#define   DSPFW_SPRITED_WM1_HI_SHIFT	20
+#define   DSPFW_SPRITED_WM1_HI_MASK	(1<<20)
+#define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
+#define   DSPFW_SPRITEC_WM1_HI_MASK	(1<<16)
+#define   DSPFW_PLANEB_WM1_HI_SHIFT	12
+#define   DSPFW_PLANEB_WM1_HI_MASK	(1<<12)
+#define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
+#define   DSPFW_SPRITEB_WM1_HI_MASK	(1<<8)
+#define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
+#define   DSPFW_SPRITEA_WM1_HI_MASK	(1<<4)
+#define   DSPFW_PLANEA_WM1_HI_SHIFT	0
+#define   DSPFW_PLANEA_WM1_HI_MASK	(1<<0)
 
 /* drain latency register values*/
 #define DRAIN_LATENCY_PRECISION_32	32
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 675d3c7..1a83e2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1397,7 +1397,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		   (plane_sr << DSPFW_SR_SHIFT) |
 		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   planea_wm);
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
 	I915_WRITE(DSPFW2,
 		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 		   (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1454,7 +1454,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
 		   (plane_sr << DSPFW_SR_SHIFT) |
 		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
-		   planea_wm);
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
 	I915_WRITE(DSPFW2,
 		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
 		   (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1528,8 +1528,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
 
 	/* 965 has limitations... */
 	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
-		   (8 << 16) | (8 << 8) | (8 << 0));
-	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+		   (8 << DSPFW_CURSORB_SHIFT) |
+		   (8 << DSPFW_PLANEB_SHIFT) |
+		   (8 << DSPFW_PLANEA_SHIFT));
+	I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
+		   (8 << DSPFW_PLANEC_SHIFT_OLD));
 	/* update cursor SR watermark */
 	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 
-- 
1.8.5.5

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Re: [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values

[Ville Syrjälä]

On Thu, Jul 31, 2014 at 03:08:29PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The DDL registers can hold 7bit numbers. Make the most of those seven
> > bits by adjusting the threshold where we switch between the 64 vs. 32
> > precision multipliers.
> >
> > Also we compute 'entries' to make the decision about precision, and then
> > we recompute the same value to calculate the actual drain latency. Just
> > use the already calculate 'entries' there.
> 
> Just an addition: don't we also want to WARN in case "entires < 64"
> (or in case the final result exceeds 7 bits, which is equivalent)?
> Could be a separate patch too.

Yeah we could WARN when things go south. But there are some patches from 
Gajanan pending that touch this code too, so probably best to wait until
those have gone in to avoid too much rebase pain.

> 
> With or without that: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 9 ++++-----
> >  1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 9413184..3aa7959 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1252,15 +1252,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
> >         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
> >
> >         entries = (clock / 1000) * pixel_size;
> > -       *plane_prec_mult = (entries > 256) ?
> > +       *plane_prec_mult = (entries > 128) ?
> >                 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> > -       *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
> > -                                                    pixel_size);
> > +       *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
> >
> >         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
> > -       *cursor_prec_mult = (entries > 256) ?
> > +       *cursor_prec_mult = (entries > 128) ?
> >                 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
> > -       *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
> > +       *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
> >
> >         return true;
> >  }
> > --
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 28/40] drm/i915: Add cherryview_update_wm()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.

v2: Rebase on top of Imre's cxsr changes (Paulo)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 81 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 69a099e..a8fc474 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1403,6 +1403,85 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
 		intel_set_memory_cxsr(dev_priv, true);
 }
 
+static void cherryview_update_wm(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	static const int sr_latency_ns = 12000;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_wm, planeb_wm, planec_wm;
+	int cursora_wm, cursorb_wm, cursorc_wm;
+	int plane_sr, cursor_sr;
+	int ignore_plane_sr, ignore_cursor_sr;
+	unsigned int enabled = 0;
+	bool cxsr_enabled;
+
+	vlv_update_drain_latency(dev);
+
+	if (g4x_compute_wm0(dev, PIPE_A,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planea_wm, &cursora_wm))
+		enabled |= 1 << PIPE_A;
+
+	if (g4x_compute_wm0(dev, PIPE_B,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planeb_wm, &cursorb_wm))
+		enabled |= 1 << PIPE_B;
+
+	if (g4x_compute_wm0(dev, PIPE_C,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planec_wm, &cursorc_wm))
+		enabled |= 1 << PIPE_C;
+
+	if (single_plane_enabled(enabled) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &plane_sr, &ignore_cursor_sr) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     2*sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &ignore_plane_sr, &cursor_sr)) {
+		cxsr_enabled = true;
+	} else {
+		cxsr_enabled = false;
+		intel_set_memory_cxsr(dev_priv, false);
+		plane_sr = cursor_sr = 0;
+	}
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
+		      "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
+		      "SR: plane=%d, cursor=%d\n",
+		      planea_wm, cursora_wm,
+		      planeb_wm, cursorb_wm,
+		      planec_wm, cursorc_wm,
+		      plane_sr, cursor_sr);
+
+	I915_WRITE(DSPFW1,
+		   (plane_sr << DSPFW_SR_SHIFT) |
+		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
+		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
+		   (planea_wm << DSPFW_PLANEA_SHIFT));
+	I915_WRITE(DSPFW2,
+		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
+		   (cursora_wm << DSPFW_CURSORA_SHIFT));
+	I915_WRITE(DSPFW3,
+		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
+		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+	I915_WRITE(DSPFW9_CHV,
+		   (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
+					      DSPFW_CURSORC_MASK)) |
+		   (planec_wm << DSPFW_PLANEC_SHIFT) |
+		   (cursorc_wm << DSPFW_CURSORC_SHIFT));
+
+	if (cxsr_enabled)
+		intel_set_memory_cxsr(dev_priv, true);
+}
+
 static void g4x_update_wm(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -7170,7 +7249,7 @@ void intel_init_pm(struct drm_device *dev)
 		else if (INTEL_INFO(dev)->gen == 8)
 			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
 	} else if (IS_CHERRYVIEW(dev)) {
-		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.update_wm = cherryview_update_wm;
 		dev_priv->display.init_clock_gating =
 			cherryview_init_clock_gating;
 	} else if (IS_VALLEYVIEW(dev)) {
-- 
1.8.5.5

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Re: [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master on chv

[Ville Syrjälä]

On Tue, Jul 29, 2014 at 09:57:09AM -0700, Jesse Barnes wrote:
> On Sat, 28 Jun 2014 02:04:05 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Just an attempt to frob these bits. Apparently we should not need to
> > touch them (apart from maybe making sure the override is disabled so
> > that the hardware automagically does the right thing).
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
> >  drivers/gpu/drm/i915/intel_dp.c   | 23 +++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_hdmi.c | 23 +++++++++++++++++++++++
> >  3 files changed, 58 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2a7bc22..d246609 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -758,6 +758,8 @@ enum punit_power_well {
> >  #define _VLV_PCS_DW0_CH1		0x8400
> >  #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
> >  #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
> >  #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> >  
> >  #define _VLV_PCS01_DW0_CH0		0x200
> > @@ -834,8 +836,18 @@ enum punit_power_well {
> >  
> >  #define _VLV_PCS_DW11_CH0		0x822c
> >  #define _VLV_PCS_DW11_CH1		0x842c
> > +#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
> >  #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> >  
> > +#define _VLV_PCS01_DW11_CH0		0x022c
> > +#define _VLV_PCS23_DW11_CH0		0x042c
> > +#define _VLV_PCS01_DW11_CH1		0x262c
> > +#define _VLV_PCS23_DW11_CH1		0x282c
> > +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> > +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> > +
> >  #define _VLV_PCS_DW12_CH0		0x8230
> >  #define _VLV_PCS_DW12_CH1		0x8430
> >  #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index c59e8fc..814a950 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2139,6 +2139,29 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > index cda6506..47430d5 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1358,6 +1358,29 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
> >  
> >  	mutex_lock(&dev_priv->dpio_lock);
> >  
> > +	/* TX FIFO reset source */
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> > +	val |= DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER2;
> > +	val &= ~DPIO_RIGHT_TXFIFO_RST_MASTER2;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> > +
> > +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> > +	val &= ~DPIO_LEFT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_RIGHT_TXFIFO_RST_MASTER;
> > +	val |= DPIO_LANEDESKEW_STRAP_OVRD;
> > +	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> > +
> >  	/* Deassert soft data lane reset*/
> >  	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> >  	val |= CHV_PCS_REQ_SOFTRESET_EN;
> 
> Did this actually make a difference?  Would be nice to get some
> clarification from the phy guys on this and update our docs...

No. The problems I was having were caused by the other problems (pps and
missing DP/HDMI port register writes). So in the next patch I just went
ahead and cleared the reset override bits. So I think we should just squash
these two patches and be happy with the result. I'll post a squashed
patch...

-- 
Ville Syrjälä
Intel OTC

[PATCH v2 15/40] drm/i915: Clear TX FIFO reset master override bits on chv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clear the override bits to make sure the hardware maanages
the TX FIFO reset master on its own.

v2: Squash with the earlier attempt at forcing the override bits

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
Note to maintainer: This supersedes both 14/40 and 15/40 of the original patches

 drivers/gpu/drm/i915/i915_reg.h   | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c   |  9 +++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |  9 +++++++++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e3b13a..1e0b0e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -787,6 +787,8 @@ enum punit_power_well {
 #define _VLV_PCS_DW0_CH1		0x8400
 #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
 #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
 #define _VLV_PCS01_DW0_CH0		0x200
@@ -863,8 +865,18 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW11_CH0		0x822c
 #define _VLV_PCS_DW11_CH1		0x842c
+#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
 
+#define _VLV_PCS01_DW11_CH0		0x022c
+#define _VLV_PCS23_DW11_CH0		0x042c
+#define _VLV_PCS01_DW11_CH1		0x262c
+#define _VLV_PCS23_DW11_CH1		0x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW12_CH0		0x8230
 #define _VLV_PCS_DW12_CH1		0x8430
 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 96e5dba..e7700df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2236,6 +2236,15 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* allow hardware to manage TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 63c577d..8449066 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1378,6 +1378,15 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpio_lock);
 
+	/* allow hardware to manage TX FIFO reset source */
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
+
+	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
+	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
+	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
+
 	/* Deassert soft data lane reset*/
 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
 	val |= CHV_PCS_REQ_SOFTRESET_EN;
-- 
1.8.5.5

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Re: [PATCH v2 28/40] drm/i915: Add cherryview_update_wm()

[Paulo Zanoni]

2014-08-01 9:36 GMT-03:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV has a third pipe so we need to compute the watermarks for its
> planes. Add cherryview_update_wm() to do just that.
>
> v2: Rebase on top of Imre's cxsr changes (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 81 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 80 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 69a099e..a8fc474 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1403,6 +1403,85 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
>                 intel_set_memory_cxsr(dev_priv, true);
>  }
>
> +static void cherryview_update_wm(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       static const int sr_latency_ns = 12000;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       int planea_wm, planeb_wm, planec_wm;
> +       int cursora_wm, cursorb_wm, cursorc_wm;
> +       int plane_sr, cursor_sr;
> +       int ignore_plane_sr, ignore_cursor_sr;
> +       unsigned int enabled = 0;
> +       bool cxsr_enabled;
> +
> +       vlv_update_drain_latency(dev);
> +
> +       if (g4x_compute_wm0(dev, PIPE_A,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planea_wm, &cursora_wm))
> +               enabled |= 1 << PIPE_A;
> +
> +       if (g4x_compute_wm0(dev, PIPE_B,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planeb_wm, &cursorb_wm))
> +               enabled |= 1 << PIPE_B;
> +
> +       if (g4x_compute_wm0(dev, PIPE_C,
> +                           &valleyview_wm_info, latency_ns,
> +                           &valleyview_cursor_wm_info, latency_ns,
> +                           &planec_wm, &cursorc_wm))
> +               enabled |= 1 << PIPE_C;
> +
> +       if (single_plane_enabled(enabled) &&
> +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> +                            sr_latency_ns,
> +                            &valleyview_wm_info,
> +                            &valleyview_cursor_wm_info,
> +                            &plane_sr, &ignore_cursor_sr) &&
> +           g4x_compute_srwm(dev, ffs(enabled) - 1,
> +                            2*sr_latency_ns,
> +                            &valleyview_wm_info,
> +                            &valleyview_cursor_wm_info,
> +                            &ignore_plane_sr, &cursor_sr)) {
> +               cxsr_enabled = true;
> +       } else {
> +               cxsr_enabled = false;
> +               intel_set_memory_cxsr(dev_priv, false);
> +               plane_sr = cursor_sr = 0;
> +       }
> +
> +       DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
> +                     "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
> +                     "SR: plane=%d, cursor=%d\n",
> +                     planea_wm, cursora_wm,
> +                     planeb_wm, cursorb_wm,
> +                     planec_wm, cursorc_wm,
> +                     plane_sr, cursor_sr);
> +
> +       I915_WRITE(DSPFW1,
> +                  (plane_sr << DSPFW_SR_SHIFT) |
> +                  (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> +                  (planeb_wm << DSPFW_PLANEB_SHIFT) |
> +                  (planea_wm << DSPFW_PLANEA_SHIFT));
> +       I915_WRITE(DSPFW2,
> +                  (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> +                  (cursora_wm << DSPFW_CURSORA_SHIFT));
> +       I915_WRITE(DSPFW3,
> +                  (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
> +                  (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> +       I915_WRITE(DSPFW9_CHV,
> +                  (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
> +                                             DSPFW_CURSORC_MASK)) |
> +                  (planec_wm << DSPFW_PLANEC_SHIFT) |
> +                  (cursorc_wm << DSPFW_CURSORC_SHIFT));
> +
> +       if (cxsr_enabled)
> +               intel_set_memory_cxsr(dev_priv, true);
> +}
> +
>  static void g4x_update_wm(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
> @@ -7170,7 +7249,7 @@ void intel_init_pm(struct drm_device *dev)
>                 else if (INTEL_INFO(dev)->gen == 8)
>                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
>         } else if (IS_CHERRYVIEW(dev)) {
> -               dev_priv->display.update_wm = valleyview_update_wm;
> +               dev_priv->display.update_wm = cherryview_update_wm;
>                 dev_priv->display.init_clock_gating =
>                         cherryview_init_clock_gating;
>         } else if (IS_VALLEYVIEW(dev)) {
> --
> 1.8.5.5
>



-- 
Paulo Zanoni
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