* [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135.
@ 2014-11-11 12:38 ` Hongzhou Yang
0 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Matthias Brugger
Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King,
Heiko St�bner, Pawel Moll, Ian Campbell, Hongzhou Yang,
Catalin Marinas, dandan.he, linux-kernel, alan.cheng,
Ashwin Chaugule, toby.liu, Sascha Hauer, Kumar Gala,
Grant Likely, Joe.C, eddie.huang, linux-arm-kernel
This is v3 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135.
It is based on Joe.C' basic device tree support.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296093.html
This driver include common and MT8135 part, other Mediatek SoCs will share the common part,
and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins.
Changes in v3:
- Rebase on 3.18-rc1.
- Follow '[RFC] pinctrl: Provide a generic device tree binding for per-pin pin controllers', modify mediatek,pins format,
add config setting for each pin, the reason is that each pin may have different config.
The RFC link: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296491.html
- Switch to use syscon regmap.
- Add CLR_ADDR() and SET_ADDR() macros.
- Add mtk_pconf_set_ies() and mtk_pconf_set_smt() functions to deal with input-enable and input-schmitt-enable.
- Rename mt_gpio_devdata to mtk_pinctrl_devdata.
- Rename all mt_prefix to mtk_prefix.
- Rename mt_pconf_pull_conf() to mtk_pconf_parse_conf, add mtk_pconf_set_pull_select() to deal with pull enable and pull up/down.
And we will add PIN_CONFIG_DRIVE_STRENGTH to mtk_pconf_parse_conf().
According to Linus' suggestion, make some following changes:
- Add port_shf, port_mask and port_align members to mtk_pinctrl_devdata struct.
- Use BIT(x) instead of 1 << (x).
- Remove mt_pctrl_write_reg() and mt_pctrl_read_reg().
- Remove mt_gpio_of_xlate().
- Use .set_mux() instead of .enable().
- Add some comments.
Hongzhou Yang (3):
ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +
arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++
arch/arm/boot/dts/mt8135.dtsi | 19 +
arch/arm/mach-mediatek/Kconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile | 5 +
drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++
include/dt-bindings/pinctrl/mt65xx.h | 23 +
13 files changed, 5020 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135.
@ 2014-11-11 12:38 ` Hongzhou Yang
0 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: linux-arm-kernel
This is v3 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135.
It is based on Joe.C' basic device tree support.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296093.html
This driver include common and MT8135 part, other Mediatek SoCs will share the common part,
and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins.
Changes in v3:
- Rebase on 3.18-rc1.
- Follow '[RFC] pinctrl: Provide a generic device tree binding for per-pin pin controllers', modify mediatek,pins format,
add config setting for each pin, the reason is that each pin may have different config.
The RFC link: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296491.html
- Switch to use syscon regmap.
- Add CLR_ADDR() and SET_ADDR() macros.
- Add mtk_pconf_set_ies() and mtk_pconf_set_smt() functions to deal with input-enable and input-schmitt-enable.
- Rename mt_gpio_devdata to mtk_pinctrl_devdata.
- Rename all mt_prefix to mtk_prefix.
- Rename mt_pconf_pull_conf() to mtk_pconf_parse_conf, add mtk_pconf_set_pull_select() to deal with pull enable and pull up/down.
And we will add PIN_CONFIG_DRIVE_STRENGTH to mtk_pconf_parse_conf().
According to Linus' suggestion, make some following changes:
- Add port_shf, port_mask and port_align members to mtk_pinctrl_devdata struct.
- Use BIT(x) instead of 1 << (x).
- Remove mt_pctrl_write_reg() and mt_pctrl_read_reg().
- Remove mt_gpio_of_xlate().
- Use .set_mux() instead of .enable().
- Add some comments.
Hongzhou Yang (3):
ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +
arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++
arch/arm/boot/dts/mt8135.dtsi | 19 +
arch/arm/mach-mediatek/Kconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile | 5 +
drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++
include/dt-bindings/pinctrl/mt65xx.h | 23 +
13 files changed, 5020 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
2014-11-11 12:38 ` Hongzhou Yang
@ 2014-11-11 12:38 ` Hongzhou Yang
-1 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Matthias Brugger
Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King,
Heiko St�bner, Pawel Moll, Ian Campbell, Hongzhou Yang,
Catalin Marinas, dandan.he, linux-kernel, alan.cheng,
Ashwin Chaugule, toby.liu, Sascha Hauer, Kumar Gala,
Grant Likely, Joe.C, eddie.huang, linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
arch/arm/mach-mediatek/Kconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile | 5 +
drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 ++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 +++++++++++++++++++++++++
include/dt-bindings/pinctrl/mt65xx.h | 23 +
10 files changed, 3574 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25fe6cf..cd57639 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -1,6 +1,7 @@
menuconfig ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
select ARM_GIC
+ select PINCTRL
select MTK_TIMER
help
Support for Mediatek MT65xx & MT81xx SoCs
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de..d15a56c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -213,6 +213,7 @@ source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
config PINCTRL_XWAY
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d3..af365c5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 0000000..bae4be6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK_COMMON
+ bool
+ select PINMUX
+ select GENERIC_PINCONF
+
+config PINCTRL_MT8135
+ def_bool MACH_MT8135
+ select PINCTRL_MTK_COMMON
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 0000000..8157dad
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
new file mode 100644
index 0000000..21ec1e6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8135.h"
+
+static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
+ .pins = mtk_pins_mt8135,
+ .npins = ARRAY_SIZE(mtk_pins_mt8135),
+ .dir_offset = 0x0000,
+ .ies_offset = 0x0100,
+ .pullen_offset = 0x0200,
+ .smt_offset = 0x0300,
+ .pullsel_offset = 0x0400,
+ .invser_offset = 0x0600,
+ .dout_offset = 0x0800,
+ .din_offset = 0x0A00,
+ .pinmux_offset = 0x0C00,
+ .type1_start = 34,
+ .type1_end = 149,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+};
+
+static int mt8135_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8135_pinctrl_data);
+}
+
+static int mt8135_pinctrl_remove(struct platform_device *pdev)
+{
+ return mtk_pctrl_remove(pdev);
+}
+
+
+static struct of_device_id mt8135_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt8135-pinctrl",
+ }, {
+ }
+};
+MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt8135_pinctrl_probe,
+ .remove = mt8135_pinctrl_remove,
+ .driver = {
+ .name = "mediatek-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = mt8135_pctrl_match,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+static void __exit mtk_pinctrl_exit(void)
+{
+ platform_driver_unregister(&mtk_pinctrl_driver);
+}
+
+module_init(mtk_pinctrl_init);
+module_exit(mtk_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
+MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
new file mode 100644
index 0000000..f4d1ec3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -0,0 +1,861 @@
+/*
+ * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "../pinconf.h"
+#include "pinctrl-mtk-common.h"
+
+#define PINMUX_MAX_VAL 8
+#define MAX_GPIO_MODE_PER_REG 5
+#define GPIO_MODE_BITS 3
+
+static const char * const mtk_gpio_functions[] = {
+ "func0", "func1", "func2", "func3",
+ "func4", "func5", "func6", "func7",
+};
+
+/*
+ * There are two base address for pull related configuration
+ * in mt8135, and different GPIO pins use different base address.
+ * When pin number greater than type1_start and less than type1_end,
+ * should use the second base address.
+ */
+static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
+ unsigned long pin)
+{
+ if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
+ return pctl->regmap2;
+ return pctl->regmap1;
+}
+
+static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
+{
+ /* Different SoC has different mask and port shift. */
+ return ((pin >> 4) & pctl->devdata->port_mask)
+ << pctl->devdata->port_shf;
+}
+
+static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset,
+ bool input)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & 0xf);
+
+ if (input)
+ /* Different SoC has different alignment offset. */
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+ else
+ reg_addr = SET_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+ return 0;
+}
+
+static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
+ bit = BIT(offset & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(reg_addr, pctl);
+ else
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+}
+
+static void mtk_pconf_set_ies(struct mtk_pinctrl *pctl, unsigned pin, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+
+ bit = BIT(pin & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->ies_offset, pctl);
+ else
+ reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->ies_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
+}
+
+static void mtk_pconf_set_smt(struct mtk_pinctrl *pctl, unsigned pin, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+
+ bit = BIT(pin & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->smt_offset, pctl);
+ else
+ reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->smt_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
+}
+
+static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
+ unsigned long pin, bool enable, bool isup, unsigned int arg)
+{
+ unsigned int bit;
+ unsigned int reg_pullen, reg_pullsel;
+
+ bit = BIT(pin & 0xf);
+ if (enable)
+ reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+ else
+ reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+
+ if (isup)
+ reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+ else
+ reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+ return 0;
+}
+
+static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
+ unsigned long pin, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mtk_pconf_set_ies(pctl, pin, arg);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ mtk_gpio_set(pctl->chip, pin, arg);
+ mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mtk_pconf_set_smt(pctl, pin, arg);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group,
+ unsigned long *config)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = pctl->groups[group].config;
+
+ return 0;
+}
+
+static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = &pctl->groups[group];
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ mtk_pconf_parse_conf(pctldev, g->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+
+ g->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops mtk_pconf_ops = {
+ .pin_config_group_get = mtk_pconf_group_get,
+ .pin_config_group_set = mtk_pconf_group_set,
+};
+
+static struct mtk_pinctrl_group *
+mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < pctl->ngroups; i++) {
+ struct mtk_pinctrl_group *grp = pctl->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
+ u32 pin_num, u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (pin->pin.number == pin_num) {
+ struct mtk_desc_function *func = pin->functions + fnum;
+
+ if (func->name)
+ return true;
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, u32 pin,
+ u32 fnum, struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps)
+{
+ bool ret;
+ struct mtk_pinctrl_group *grp;
+
+ if (*num_maps == *cnt_maps)
+ return -ENOSPC;
+
+ grp = mtk_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
+ unsigned long *configs, unsigned num_configs,
+ struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps)
+{
+ struct mtk_pinctrl_group *grp;
+ unsigned long *cfgs;
+
+ if (*num_maps == *cnt_maps)
+ return -ENOSPC;
+
+ cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+ GFP_KERNEL);
+ if (cfgs == NULL)
+ return -ENOMEM;
+
+ grp = mtk_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ (*map)[*num_maps].data.configs.group_or_pin = grp->name;
+ (*map)[*num_maps].data.configs.configs = cfgs;
+ (*map)[*num_maps].data.configs.num_configs = num_configs;
+ (*num_maps)++;
+
+ return 0;
+}
+
+static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map,
+ unsigned num_maps)
+{
+ int i;
+
+ for (i = 0; i < num_maps; i++) {
+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+ kfree(map[i].data.configs.configs);
+ }
+
+ kfree(map);
+}
+
+static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps, unsigned cnt)
+{
+ unsigned old_num = *cnt_maps;
+ unsigned new_num = *num_maps + cnt;
+ struct pinctrl_map *new_map;
+
+ if (old_num >= new_num)
+ return 0;
+
+ new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+ *map = new_map;
+ *cnt_maps = new_num;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned *num_maps, unsigned *cnt_maps)
+{
+ struct property *pins;
+ u32 pinfunc, pin, func;
+ int num_pins, num_funcs, maps_per_pin;
+ unsigned long *configs;
+ unsigned int num_configs;
+ bool has_config = 0;
+ int i, err;
+ unsigned cnt = 0;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ pins = of_find_property(node, "mediatek,pins", NULL);
+ if (!pins) {
+ dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
+ node->name);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
+ if (num_configs)
+ has_config = 1;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin)
+ return -EINVAL;
+
+ cnt = num_pins * maps_per_pin;
+
+ err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
+ if (err < 0)
+ goto fail;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "mediatek,pins",
+ i, &pinfunc);
+ if (err)
+ goto fail;
+
+ pin = MTK_GET_PIN_NO(pinfunc);
+ func = MTK_GET_PIN_FUNC(pinfunc);
+
+ if (pin >= pctl->devdata->npins ||
+ func >= ARRAY_SIZE(mtk_gpio_functions)) {
+ dev_err(pctl->dev, "invalid mediatek,pins value.\n");
+ err = -EINVAL;
+ goto fail;
+ }
+
+ err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, map,
+ cnt_maps, num_maps);
+ if (err < 0)
+ goto fail;
+
+ if (has_config) {
+ err = mtk_pctrl_dt_node_to_map_config(pctl, pin,
+ configs, num_configs, map, cnt_maps,
+ num_maps);
+ if (err < 0)
+ goto fail;
+ }
+ }
+
+ return 0;
+
+fail:
+ return err;
+}
+
+static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct device_node *np;
+ unsigned cnt_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ cnt_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
+ num_maps, &cnt_maps);
+ if (ret < 0) {
+ mtk_pctrl_dt_free_map(pctldev, *map, *num_maps);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned *)&pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops mtk_pctrl_ops = {
+ .dt_node_to_map = mtk_pctrl_dt_node_to_map,
+ .dt_free_map = mtk_pctrl_dt_free_map,
+ .get_groups_count = mtk_pctrl_get_groups_count,
+ .get_group_name = mtk_pctrl_get_group_name,
+ .get_group_pins = mtk_pctrl_get_group_pins,
+};
+
+static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mtk_gpio_functions);
+}
+
+static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ return mtk_gpio_functions[selector];
+}
+
+static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->grp_names;
+ *num_groups = pctl->ngroups;
+
+ return 0;
+}
+
+static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
+ unsigned long pin, unsigned long mode)
+{
+ unsigned int reg_addr;
+ unsigned char bit;
+ unsigned int val;
+ unsigned long flags;
+ unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
+ + pctl->devdata->pinmux_offset;
+
+ spin_lock_irqsave(&pctl->lock, flags);
+ regmap_read(pctl->regmap1, reg_addr, &val);
+ bit = pin % MAX_GPIO_MODE_PER_REG;
+ val &= ~(mask << (GPIO_MODE_BITS * bit));
+ val |= (mode << (GPIO_MODE_BITS * bit));
+ regmap_write(pctl->regmap1, reg_addr, val);
+ spin_unlock_irqrestore(&pctl->lock, flags);
+ return 0;
+}
+
+static struct mtk_desc_function *
+mtk_pctrl_desc_find_function_by_number(struct mtk_pinctrl *pctl,
+ const char *pin_name,
+ unsigned number)
+{
+ int i;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (!strcmp(pin->pin.name, pin_name)) {
+ struct mtk_desc_function *func = pin->functions;
+
+ return func + number;
+ }
+ }
+
+ return NULL;
+}
+
+static struct mtk_desc_function *
+mtk_pctrl_desc_find_irq_function_from_name(struct mtk_pinctrl *pctl,
+ const char *pin_name)
+{
+ int i, j;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (!strcmp(pin->pin.name, pin_name)) {
+ struct mtk_desc_function *func = pin->functions;
+
+ for (j = 0; j < PINMUX_MAX_VAL; j++) {
+ if (func->irqnum != MTK_NO_EINT_SUPPORT)
+ return func;
+
+ func++;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
+{
+ bool ret;
+ struct mtk_desc_function *desc;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = pctl->groups + group;
+
+ ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
+ if (!ret) {
+ dev_err(pctl->dev, "invaild function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ desc = mtk_pctrl_desc_find_function_by_number(pctl, g->name, function);
+ if (!desc)
+ return -EINVAL;
+ mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
+ return 0;
+}
+
+static const struct pinmux_ops mtk_pmx_ops = {
+ .get_functions_count = mtk_pmx_get_funcs_cnt,
+ .get_function_name = mtk_pmx_get_func_name,
+ .get_function_groups = mtk_pmx_get_func_groups,
+ .set_mux = mtk_pmx_set_mux,
+ .gpio_set_direction = mtk_pmx_gpio_set_direction,
+};
+
+static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int mtk_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int mtk_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ mtk_gpio_set(chip, offset, value);
+ return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & 0xf);
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !!(read_val & bit);
+}
+
+static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ if (mtk_gpio_get_direction(chip, offset))
+ reg_addr = mtk_get_port(pctl, offset) +
+ pctl->devdata->dout_offset;
+ else
+ reg_addr = mtk_get_port(pctl, offset) +
+ pctl->devdata->din_offset;
+
+ bit = BIT(offset & 0xf);
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !!(read_val & bit);
+}
+
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+ struct mtk_pinctrl_group *g = pctl->groups + offset;
+ struct mtk_desc_function *desc =
+ mtk_pctrl_desc_find_irq_function_from_name(
+ pctl, g->name);
+ if (!desc)
+ return -EINVAL;
+
+ return desc->irqnum;
+}
+
+static struct gpio_chip mtk_gpio_chip = {
+ .owner = THIS_MODULE,
+ .request = mtk_gpio_request,
+ .free = mtk_gpio_free,
+ .direction_input = mtk_gpio_direction_input,
+ .direction_output = mtk_gpio_direction_output,
+ .get = mtk_gpio_get,
+ .set = mtk_gpio_set,
+ .to_irq = mtk_gpio_to_irq,
+ .of_gpio_n_cells = 2,
+};
+
+static int mtk_pctrl_build_state(struct platform_device *pdev)
+{
+ struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
+ int i;
+
+ pctl->ngroups = pctl->devdata->npins;
+
+ /* Allocate groups */
+ pctl->groups = devm_kzalloc(&pdev->dev,
+ pctl->ngroups * sizeof(*pctl->groups),
+ GFP_KERNEL);
+ if (!pctl->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ pctl->grp_names = devm_kzalloc(&pdev->dev,
+ pctl->ngroups * sizeof(*pctl->grp_names),
+ GFP_KERNEL);
+ if (!pctl->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+ struct mtk_pinctrl_group *group = pctl->groups + i;
+ const char **func_grp;
+
+ group->name = pin->pin.name;
+ group->pin = pin->pin.number;
+
+ func_grp = pctl->grp_names;
+ while (*func_grp)
+ func_grp++;
+
+ *func_grp = pin->pin.name;
+ }
+
+ return 0;
+}
+
+static struct pinctrl_desc mtk_pctrl_desc = {
+ .confops = &mtk_pconf_ops,
+ .pctlops = &mtk_pctrl_ops,
+ .pmxops = &mtk_pmx_ops,
+};
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data)
+{
+ struct pinctrl_pin_desc *pins;
+ struct mtk_pinctrl *pctl;
+ struct device_node *np = pdev->dev.of_node, *node;
+ int i, ret;
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pctl);
+
+ spin_lock_init(&pctl->lock);
+
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
+ if (node) {
+ pctl->regmap1 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap1))
+ return PTR_ERR(pctl->regmap1);
+ }
+
+ /* Only 8135 has two base addr, other SoCs have only one. */
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
+ if (node) {
+ pctl->regmap2 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap2))
+ return PTR_ERR(pctl->regmap2);
+ }
+
+ pctl->devdata = data;
+ ret = mtk_pctrl_build_state(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "build state failed: %d\n", ret);
+ return -EINVAL;
+ }
+
+ pins = devm_kzalloc(&pdev->dev,
+ pctl->devdata->npins * sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++)
+ pins[i] = pctl->devdata->pins[i].pin;
+ mtk_pctrl_desc.name = dev_name(&pdev->dev);
+ mtk_pctrl_desc.owner = THIS_MODULE;
+ mtk_pctrl_desc.pins = pins;
+ mtk_pctrl_desc.npins = pctl->devdata->npins;
+ pctl->dev = &pdev->dev;
+ pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
+ if (!pctl->pctl_dev) {
+ dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
+ if (!pctl->chip) {
+ ret = -ENOMEM;
+ goto pctrl_error;
+ }
+
+ pctl->chip = &mtk_gpio_chip;
+ pctl->chip->ngpio = pctl->devdata->npins;
+ pctl->chip->label = dev_name(&pdev->dev);
+ pctl->chip->dev = &pdev->dev;
+ pctl->chip->base = 0;
+
+ ret = gpiochip_add(pctl->chip);
+ if (ret) {
+ ret = -EINVAL;
+ goto pctrl_error;
+ }
+
+ /* Register the GPIO to pin mappings. */
+ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
+ 0, 0, pctl->devdata->npins);
+ if (ret) {
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+ return 0;
+
+chip_error:
+ gpiochip_remove(pctl->chip);
+pctrl_error:
+ pinctrl_unregister(pctl->pctl_dev);
+ return ret;
+}
+
+int mtk_pctrl_remove(struct platform_device *pdev)
+{
+
+ struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(pctl->pctl_dev);
+ gpiochip_remove(pctl->chip);
+
+ return 0;
+}
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
+MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
new file mode 100644
index 0000000..7a254a3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_COMMON_H
+#define __PINCTRL_MTK_COMMON_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+
+#define MTK_NO_EINT_SUPPORT 255
+
+struct mtk_desc_function {
+ const char *name;
+ unsigned char muxval;
+ unsigned char irqnum;
+};
+
+struct mtk_desc_pin {
+ struct pinctrl_pin_desc pin;
+ const char *chip;
+ struct mtk_desc_function *functions;
+};
+
+#define MTK_PIN(_pin, _pad, _chip, ...) \
+ { \
+ .pin = _pin, \
+ .chip = _chip, \
+ .functions = (struct mtk_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define MTK_FUNCTION(_val, _name) \
+ { \
+ .name = _name, \
+ .muxval = _val, \
+ .irqnum = MTK_NO_EINT_SUPPORT, \
+ }
+
+#define MTK_FUNCTION_IRQ(_val, _name, _irq) \
+ { \
+ .name = _name, \
+ .muxval = _val, \
+ .irqnum = _irq, \
+ }
+
+#define SET_ADDR(x, y) (x + (y->devdata->port_align))
+#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1))
+
+struct mtk_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned pin;
+};
+
+/**
+ * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
+ * @pins: An array describing all pins the pin controller affects.
+
+ * @npins: The number of entries in @pins.
+ * @dir_offset: The direction register offset.
+ * @pullen_offset: The pull-up/pull-down enable register offset.
+ * @pinmux_offset: The pinmux register offset.
+ *
+ * @type1_start: Some chips have two base addresses for pull select register,
+ * that means some pins use the first address and others use the second. This
+ * member record the start of pin number to use the second address.
+ * @type1_end: The end of pin number to use the second address.
+ *
+ * @port_shf: The shift between two registers.
+ * @port_mask: The mask of register.
+ * @port_align: Provide clear register and set register step.
+ */
+struct mtk_pinctrl_devdata {
+ const struct mtk_desc_pin *pins;
+ unsigned int npins;
+ unsigned int dir_offset;
+ unsigned int ies_offset;
+ unsigned int smt_offset;
+ unsigned int pullen_offset;
+ unsigned int pullsel_offset;
+ unsigned int drv_offset;
+ unsigned int invser_offset;
+ unsigned int dout_offset;
+ unsigned int din_offset;
+ unsigned int pinmux_offset;
+ unsigned short type1_start;
+ unsigned short type1_end;
+ unsigned char port_shf;
+ unsigned char port_mask;
+ unsigned char port_align;
+};
+
+struct mtk_pinctrl {
+ struct regmap *regmap1;
+ struct regmap *regmap2;
+ struct device *dev;
+ struct gpio_chip *chip;
+ spinlock_t lock;
+ struct mtk_pinctrl_group *groups;
+ unsigned ngroups;
+ const char **grp_names;
+ struct pinctrl_dev *pctl_dev;
+ const struct mtk_pinctrl_devdata *devdata;
+};
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data);
+
+int mtk_pctrl_remove(struct platform_device *pdev);
+
+#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
new file mode 100644
index 0000000..9f9cee6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
@@ -0,0 +1,2460 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT8135_H
+#define __PINCTRL_MTK_MT8135_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <pinctrl-mtk-common.h>
+
+static const struct mtk_desc_pin mtk_pins_mt8135[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "MSDC0_DAT7"),
+ "D21", "mt8135",
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT49", 49),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "SPI1_MO"),
+ MTK_FUNCTION(7, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "MSDC0_DAT6"),
+ "D22", "mt8135",
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT48", 48),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "SPI1_CSN"),
+ MTK_FUNCTION(7, "NCLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "MSDC0_DAT5"),
+ "E22", "mt8135",
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT47", 47),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "SPI1_CLK"),
+ MTK_FUNCTION(7, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "MSDC0_DAT4"),
+ "F21", "mt8135",
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT46", 46),
+ MTK_FUNCTION(3, "A_FUNC_CK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "LSCE1B_2X"),
+ MTK_FUNCTION(7, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "MSDC0_CMD"),
+ "F20", "mt8135",
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT41", 41),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[0]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[0]"),
+ MTK_FUNCTION(6, "LRSTB_2X"),
+ MTK_FUNCTION(7, "NRNB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "MSDC0_CLK"),
+ "G18", "mt8135",
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT40", 40),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[1]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[1]"),
+ MTK_FUNCTION(6, "LPTE"),
+ MTK_FUNCTION(7, "NREB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "MSDC0_DAT3"),
+ "G21", "mt8135",
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT45", 45),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[2]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[2]"),
+ MTK_FUNCTION(6, "LSCE0B_2X"),
+ MTK_FUNCTION(7, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "MSDC0_DAT2"),
+ "E21", "mt8135",
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT44", 44),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[3]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[3]"),
+ MTK_FUNCTION(6, "LSA0_2X"),
+ MTK_FUNCTION(7, "NLD14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "MSDC0_DAT1"),
+ "E23", "mt8135",
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT43", 43),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[4]"),
+ MTK_FUNCTION(6, "LSCK_2X"),
+ MTK_FUNCTION(7, "NLD11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "MSDC0_DAT0"),
+ "F22", "mt8135",
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT42", 42),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[5]"),
+ MTK_FUNCTION(6, "LSDA_2X"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "NCEB0"),
+ "G20", "mt8135",
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION_IRQ(2, "EINT139", 139),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "NCEB1"),
+ "L17", "mt8135",
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION_IRQ(2, "EINT140", 140),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "TESTA_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "NRNB"),
+ "G19", "mt8135",
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION_IRQ(2, "EINT141", 141),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[4]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "NCLE"),
+ "J18", "mt8135",
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION_IRQ(2, "EINT142", 142),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[5]"),
+ MTK_FUNCTION(4, "CM2PDN_1X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "NALE"),
+ MTK_FUNCTION(7, "TESTA_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "NALE"),
+ "J19", "mt8135",
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "NALE"),
+ MTK_FUNCTION_IRQ(2, "EINT143", 143),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[6]"),
+ MTK_FUNCTION(4, "CM2MCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_RXD"),
+ MTK_FUNCTION(6, "NCLE"),
+ MTK_FUNCTION(7, "TESTA_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "NREB"),
+ "L18", "mt8135",
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION_IRQ(2, "EINT144", 144),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[7]"),
+ MTK_FUNCTION(4, "CM2RST_1X"),
+ MTK_FUNCTION(5, "IRDA_TXD"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "NWEB"),
+ "J20", "mt8135",
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "NWEB"),
+ MTK_FUNCTION_IRQ(2, "EINT145", 145),
+ MTK_FUNCTION(3, "A_FUNC_DIN[0]"),
+ MTK_FUNCTION(4, "CM2PCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_PDN"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "NLD0"),
+ "K21", "mt8135",
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "NLD0"),
+ MTK_FUNCTION_IRQ(2, "EINT146", 146),
+ MTK_FUNCTION(3, "A_FUNC_DIN[1]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[0]"),
+ MTK_FUNCTION(5, "I2SIN_CK"),
+ MTK_FUNCTION(6, "DAC_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "NLD1"),
+ "K22", "mt8135",
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "NLD1"),
+ MTK_FUNCTION_IRQ(2, "EINT147", 147),
+ MTK_FUNCTION(3, "A_FUNC_DIN[2]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[1]"),
+ MTK_FUNCTION(5, "I2SIN_WS"),
+ MTK_FUNCTION(6, "DAC_WS"),
+ MTK_FUNCTION(7, "TESTA_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "NLD2"),
+ "J21", "mt8135",
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "NLD2"),
+ MTK_FUNCTION_IRQ(2, "EINT148", 148),
+ MTK_FUNCTION(3, "A_FUNC_DIN[3]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[2]"),
+ MTK_FUNCTION(5, "I2SOUT_DAT"),
+ MTK_FUNCTION(6, "DAC_DAT_OUT"),
+ MTK_FUNCTION(7, "TESTA_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "NLD3"),
+ "J23", "mt8135",
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "NLD3"),
+ MTK_FUNCTION_IRQ(2, "EINT149", 149),
+ MTK_FUNCTION(3, "A_FUNC_DIN[4]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[3]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "NLD4"),
+ "J22", "mt8135",
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "NLD4"),
+ MTK_FUNCTION_IRQ(2, "EINT150", 150),
+ MTK_FUNCTION(3, "A_FUNC_DIN[5]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[4]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "NLD5"),
+ "H21", "mt8135",
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "NLD5"),
+ MTK_FUNCTION_IRQ(2, "EINT151", 151),
+ MTK_FUNCTION(3, "A_FUNC_DIN[6]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[5]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "NLD6"),
+ "H22", "mt8135",
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "NLD6"),
+ MTK_FUNCTION_IRQ(2, "EINT152", 152),
+ MTK_FUNCTION(3, "A_FUNC_DIN[7]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[6]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "NLD7"),
+ "H20", "mt8135",
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "NLD7"),
+ MTK_FUNCTION_IRQ(2, "EINT153", 153),
+ MTK_FUNCTION(3, "A_FUNC_DIN[8]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[7]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "NLD8"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "NLD8"),
+ MTK_FUNCTION_IRQ(2, "EINT154", 154),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_1X[8]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "NLD9"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "NLD9"),
+ MTK_FUNCTION_IRQ(2, "EINT155", 155),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_1X[9]"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "NLD10"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "NLD10"),
+ MTK_FUNCTION_IRQ(2, "EINT156", 156),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2VSYNC_1X"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "NLD11"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "NLD11"),
+ MTK_FUNCTION_IRQ(2, "EINT157", 157),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2HSYNC_1X"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "NLD12"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "NLD12"),
+ MTK_FUNCTION_IRQ(2, "EINT158", 158),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "NLD13"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "NLD13"),
+ MTK_FUNCTION_IRQ(2, "EINT159", 159),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "NLD14"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "NLD14"),
+ MTK_FUNCTION_IRQ(2, "EINT160", 160),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "NLD15"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "NLD15"),
+ MTK_FUNCTION_IRQ(2, "EINT161", 161),
+ MTK_FUNCTION(3, "DISP_PWM"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "MSDC0_RSTB"),
+ "G22", "mt8135",
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION_IRQ(2, "EINT50", 50),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "SPI1_MI"),
+ MTK_FUNCTION(7, "NLD10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "IDDIG"),
+ "N17", "mt8135",
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION_IRQ(2, "EINT34", 34),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "SCL3"),
+ "L19", "mt8135",
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION_IRQ(2, "EINT96", 96),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "SDA3"),
+ "L20", "mt8135",
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION_IRQ(2, "EINT97", 97),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "AUD_CLK_MOSI"),
+ "L21", "mt8135",
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "AUD_CLK"),
+ MTK_FUNCTION(2, "ADC_CK"),
+ MTK_FUNCTION(3, " HDMI_SDATA0"),
+ MTK_FUNCTION_IRQ(4, "EINT19", 19),
+ MTK_FUNCTION(5, "USB_TEST_IO[6]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "AUD_DAT_MOSI"),
+ "L23", "mt8135",
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(2, "ADC_WS"),
+ MTK_FUNCTION(3, "AUD_DAT_MISO"),
+ MTK_FUNCTION_IRQ(4, "EINT21", 21),
+ MTK_FUNCTION(5, "USB_TEST_IO[7]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "AUD_DAT_MISO"),
+ "L22", "mt8135",
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(2, "ADC_DAT_IN"),
+ MTK_FUNCTION(3, "AUD_DAT_MOSI"),
+ MTK_FUNCTION_IRQ(4, "EINT20", 20),
+ MTK_FUNCTION(5, "USB_TEST_IO[8]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "DAC_CLK"),
+ "P21", "mt8135",
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "DAC_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT22", 22),
+ MTK_FUNCTION(3, " HDMI_SDATA1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[9]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "DAC_WS"),
+ "N18", "mt8135",
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "DAC_WS"),
+ MTK_FUNCTION_IRQ(2, "EINT24", 24),
+ MTK_FUNCTION(3, " HDMI_SDATA2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[10]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "DAC_DAT_OUT"),
+ "N22", "mt8135",
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DAC_DAT_OUT"),
+ MTK_FUNCTION_IRQ(2, "EINT23", 23),
+ MTK_FUNCTION(3, " HDMI_SDATA3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[11]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
+ "M22", "mt8135",
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION_IRQ(2, "EINT29", 29),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
+ "P23", "mt8135",
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION_IRQ(2, "EINT28", 28),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
+ "M21", "mt8135",
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I"),
+ MTK_FUNCTION_IRQ(2, "EINT27", 27),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
+ "P22", "mt8135",
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I"),
+ MTK_FUNCTION_IRQ(2, "EINT26", 26),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "PWRAP_EVENT"),
+ "M23", "mt8135",
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "PWRAP_EVENT_IN"),
+ MTK_FUNCTION_IRQ(2, "EINT25", 25),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "RTC32K_CK"),
+ "N20", "mt8135",
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "RTC32K_CK"),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "WATCHDOG"),
+ "R22", "mt8135",
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "WATCHDOG"),
+ MTK_FUNCTION_IRQ(2, "EINT36", 36),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "SRCLKENA"),
+ "T22", "mt8135",
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SRCLKENA"),
+ MTK_FUNCTION_IRQ(2, "EINT38", 38),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "SRCVOLTEN"),
+ "T23", "mt8135",
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SRCVOLTEN"),
+ MTK_FUNCTION_IRQ(2, "EINT37", 37),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "EINT0"),
+ "T21", "mt8135",
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION_IRQ(1, "EINT0", 0),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, " SPDIF_OUT"),
+ MTK_FUNCTION(5, "USB_TEST_IO[12]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "URXD2"),
+ "R18", "mt8135",
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION_IRQ(2, "EINT83", 83),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, " HDMI_LRCK"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "UTXD2"),
+ "R17", "mt8135",
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION_IRQ(2, "EINT82", 82),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, " HDMI_BCK_OUT"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "UCTS2"),
+ "R20", "mt8135",
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION_IRQ(2, "EINT84", 84),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "URTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "URTS2"),
+ "R19", "mt8135",
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION_IRQ(2, "EINT85", 85),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "UCTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "JTCK"),
+ "V17", "mt8135",
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION_IRQ(2, "EINT188", 188),
+ MTK_FUNCTION(3, "DSP1_ICK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "JTDO"),
+ "T16", "mt8135",
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION_IRQ(2, "EINT190", 190),
+ MTK_FUNCTION(3, "DSP2_IMS"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "JTRST_B"),
+ "T19", "mt8135",
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "JTRST_B"),
+ MTK_FUNCTION_IRQ(2, "EINT0", 0),
+ MTK_FUNCTION(3, "DSP2_ICK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "JTDI"),
+ "T18", "mt8135",
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION_IRQ(2, "EINT189", 189),
+ MTK_FUNCTION(3, "DSP1_IMS"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "JRTCK"),
+ "T20", "mt8135",
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "JRTCK"),
+ MTK_FUNCTION_IRQ(2, "EINT187", 187),
+ MTK_FUNCTION(3, "DSP1_ID"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "JTMS"),
+ "T17", "mt8135",
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION_IRQ(2, "EINT191", 191),
+ MTK_FUNCTION(3, "DSP2_ID"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "MSDC1_INSI"),
+ "V18", "mt8135",
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MSDC1_INSI"),
+ MTK_FUNCTION_IRQ(2, "EINT57", 57),
+ MTK_FUNCTION(3, "SCL5"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "MSDC1_SDWPI"),
+ "W18", "mt8135",
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MSDC1_SDWPI"),
+ MTK_FUNCTION_IRQ(2, "EINT58", 58),
+ MTK_FUNCTION(3, "SDA5"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(5, "CLKM6"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "MSDC2_INSI"),
+ "U22", "mt8135",
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MSDC2_INSI"),
+ MTK_FUNCTION_IRQ(2, "EINT65", 65),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[27]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "MSDC2_SDWPI"),
+ "U21", "mt8135",
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MSDC2_SDWPI"),
+ MTK_FUNCTION_IRQ(2, "EINT66", 66),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[28]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "URXD4"),
+ "V23", "mt8135",
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "URXD4"),
+ MTK_FUNCTION_IRQ(2, "EINT89", 89),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "UTXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "UTXD4"),
+ "V22", "mt8135",
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "UTXD4"),
+ MTK_FUNCTION_IRQ(2, "EINT88", 88),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "URXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "URXD1"),
+ "W22", "mt8135",
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION_IRQ(2, "EINT79", 79),
+ MTK_FUNCTION(3, "URXD4"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "UTXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "UTXD1"),
+ "V21", "mt8135",
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION_IRQ(2, "EINT78", 78),
+ MTK_FUNCTION(3, "UTXD4"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "URXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "UCTS1"),
+ "V19", "mt8135",
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION_IRQ(2, "EINT80", 80),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, "URTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "URTS1"),
+ "V20", "mt8135",
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION_IRQ(2, "EINT81", 81),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "UCTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "PWM1"),
+ "W17", "mt8135",
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION_IRQ(2, "EINT73", 73),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "PWM2"),
+ "Y17", "mt8135",
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION_IRQ(2, "EINT74", 74),
+ MTK_FUNCTION(3, "DPI33_CK"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "URXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "PWM3"),
+ "Y19", "mt8135",
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION_IRQ(2, "EINT75", 75),
+ MTK_FUNCTION(3, "DPI33_D0"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "UTXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "PWM4"),
+ "W19", "mt8135",
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION_IRQ(2, "EINT76", 76),
+ MTK_FUNCTION(3, "DPI33_D1"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "MSDC2_DAT2"),
+ "W21", "mt8135",
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT63", 63),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_IMS"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DPI33_D6"),
+ MTK_FUNCTION(7, "TESTA_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "MSDC2_DAT3"),
+ "AA23", "mt8135",
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT64", 64),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_ID"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DPI33_D7"),
+ MTK_FUNCTION(7, "TESTA_OUT26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "MSDC2_CMD"),
+ "Y22", "mt8135",
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT60", 60),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_IMS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "DPI33_D3"),
+ MTK_FUNCTION(7, "TESTA_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "MSDC2_CLK"),
+ "AA22", "mt8135",
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT59", 59),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_ICK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "DPI33_D2"),
+ MTK_FUNCTION(7, "TESTA_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "MSDC2_DAT1"),
+ "Y21", "mt8135",
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT62", 62),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_ICK"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "DPI33_D5"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "MSDC2_DAT0"),
+ "AB22", "mt8135",
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT61", 61),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_ID"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "DPI33_D4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "MSDC1_DAT0"),
+ "AC19", "mt8135",
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT53", 53),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "MSDC1_DAT1"),
+ "AA19", "mt8135",
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT54", 54),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC1_CMD"),
+ "AA20", "mt8135",
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT52", 52),
+ MTK_FUNCTION(3, "SDA0"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC1_CLK"),
+ "AB19", "mt8135",
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT51", 51),
+ MTK_FUNCTION(3, "SCL0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC1_DAT2"),
+ "AA21", "mt8135",
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT55", 55),
+ MTK_FUNCTION(3, "SCL4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC1_DAT3"),
+ "AB20", "mt8135",
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT56", 56),
+ MTK_FUNCTION(3, "SDA4"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC4_DAT0"),
+ "AB8", "mt8135",
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC4_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT133", 133),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[9]"),
+ MTK_FUNCTION(7, "LPTE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC4_DAT1"),
+ "AB7", "mt8135",
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC4_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT134", 134),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "A_FUNC_DIN[10]"),
+ MTK_FUNCTION(7, "LRSTB_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "MSDC4_DAT5"),
+ "AA8", "mt8135",
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "MSDC4_DAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT136", 136),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[11]"),
+ MTK_FUNCTION(7, "SPI1_CSN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "MSDC4_DAT6"),
+ "AC4", "mt8135",
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "MSDC4_DAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT137", 137),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[12]"),
+ MTK_FUNCTION(7, "SPI1_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "MSDC4_DAT7"),
+ "AC6", "mt8135",
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "MSDC4_DAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT138", 138),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[13]"),
+ MTK_FUNCTION(7, "SPI1_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "MSDC4_DAT4"),
+ "AA7", "mt8135",
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "MSDC4_DAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT135", 135),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[14]"),
+ MTK_FUNCTION(7, "SPI1_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "MSDC4_DAT2"),
+ "AB6", "mt8135",
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "MSDC4_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT131", 131),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "CM2PDN_2X"),
+ MTK_FUNCTION(5, "DAC_WS"),
+ MTK_FUNCTION(6, "PCM1_WS"),
+ MTK_FUNCTION(7, "LSCE0B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "MSDC4_CLK"),
+ "AB5", "mt8135",
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "MSDC4_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT129", 129),
+ MTK_FUNCTION(3, "DPI1_CK_2X"),
+ MTK_FUNCTION(4, "CM2PCLK_2X"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "LSCK_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "MSDC4_DAT3"),
+ "Y8", "mt8135",
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "MSDC4_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT132", 132),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "CM2RST_2X"),
+ MTK_FUNCTION(5, "DAC_DAT_OUT"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "LSCE1B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "MSDC4_CMD"),
+ "AC3", "mt8135",
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "MSDC4_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT128", 128),
+ MTK_FUNCTION(3, "DPI1_DE_2X"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "LSDA_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "MSDC4_RSTB"),
+ "AB4", "mt8135",
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "MSDC4_RSTB"),
+ MTK_FUNCTION_IRQ(2, "EINT130", 130),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "CM2MCLK_2X"),
+ MTK_FUNCTION(5, "DAC_CK"),
+ MTK_FUNCTION(6, "PCM1_CK"),
+ MTK_FUNCTION(7, "LSA0_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "SDA0"),
+ "W9", "mt8135",
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION_IRQ(2, "EINT91", 91),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "SCL0"),
+ "W11", "mt8135",
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION_IRQ(2, "EINT90", 90),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "EINT10_AUXIN2"),
+ "AA3", "mt8135",
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION_IRQ(1, "EINT10", 10),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[16]"),
+ MTK_FUNCTION(6, "TESTB_OUT16"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "EINT11_AUXIN3"),
+ "AB2", "mt8135",
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION_IRQ(1, "EINT11", 11),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[17]"),
+ MTK_FUNCTION(6, "TESTB_OUT17"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "EINT16_AUXIN4"),
+ "AB3", "mt8135",
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION_IRQ(1, "EINT16", 16),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[18]"),
+ MTK_FUNCTION(6, "TESTB_OUT18"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "I2S_CLK"),
+ "W6", "mt8135",
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "I2SIN_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT10", 10),
+ MTK_FUNCTION(3, "DAC_CK"),
+ MTK_FUNCTION(4, "PCM1_CK"),
+ MTK_FUNCTION(5, "USB_TEST_IO[19]"),
+ MTK_FUNCTION(6, "TESTB_OUT19"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "I2S_WS"),
+ "AA6", "mt8135",
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "I2SIN_WS"),
+ MTK_FUNCTION_IRQ(2, "EINT13", 13),
+ MTK_FUNCTION(3, "DAC_WS"),
+ MTK_FUNCTION(4, "PCM1_WS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[20]"),
+ MTK_FUNCTION(6, "TESTB_OUT20"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "I2S_DATA_IN"),
+ "AA5", "mt8135",
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "I2SIN_DAT"),
+ MTK_FUNCTION_IRQ(2, "EINT11", 11),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[21]"),
+ MTK_FUNCTION(6, "TESTB_OUT22"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "I2S_DATA_OUT"),
+ "AA4", "mt8135",
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "I2SOUT_DAT"),
+ MTK_FUNCTION_IRQ(2, "EINT12", 12),
+ MTK_FUNCTION(3, "DAC_DAT_OUT"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[22]"),
+ MTK_FUNCTION(6, "TESTB_OUT23"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "EINT5"),
+ "W5", "mt8135",
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION_IRQ(1, "EINT5", 5),
+ MTK_FUNCTION(2, "PWM5"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "GPU_JTRSTB"),
+ MTK_FUNCTION(5, "USB_TEST_IO[23]"),
+ MTK_FUNCTION(6, "TESTB_OUT26"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "EINT6"),
+ "V5", "mt8135",
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION_IRQ(1, "EINT6", 6),
+ MTK_FUNCTION(2, "PWM6"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "GPU_JTMS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[24]"),
+ MTK_FUNCTION(6, "TESTB_OUT27"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "EINT7"),
+ "W3", "mt8135",
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION_IRQ(1, "EINT7", 7),
+ MTK_FUNCTION(2, "PWM7"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "GPU_JTDO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[25]"),
+ MTK_FUNCTION(6, "TESTB_OUT28"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "EINT8"),
+ "V6", "mt8135",
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION_IRQ(1, "EINT8", 8),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "GPU_JTDI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[26]"),
+ MTK_FUNCTION(6, "TESTB_OUT29"),
+ MTK_FUNCTION(7, "EXT_FRAME_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "EINT9"),
+ "W8", "mt8135",
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION_IRQ(1, "EINT9", 9),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "GPU_JTCK"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "TESTB_OUT30"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "LPCE1B"),
+ "W4", "mt8135",
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "LPCE1B"),
+ MTK_FUNCTION_IRQ(2, "EINT127", 127),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, "TESTB_OUT14"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "LPCE0B"),
+ "T5", "mt8135",
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "LPCE0B"),
+ MTK_FUNCTION_IRQ(2, "EINT126", 126),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, "TESTB_OUT15"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "DISP_PWM"),
+ "V4", "mt8135",
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION_IRQ(2, "EINT77", 77),
+ MTK_FUNCTION(3, "LSDI"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "EINT1"),
+ "T6", "mt8135",
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION_IRQ(1, "EINT1", 1),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[13]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "EINT2"),
+ "T4", "mt8135",
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION_IRQ(1, "EINT2", 2),
+ MTK_FUNCTION(2, "PWM3"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[14]"),
+ MTK_FUNCTION(6, "SRCLKENAI2"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "EINT3"),
+ "R4", "mt8135",
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION_IRQ(1, "EINT3", 3),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[15]"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "EXT_26M_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "EINT4"),
+ "R5", "mt8135",
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION_IRQ(1, "EINT4", 4),
+ MTK_FUNCTION(2, "PWM4"),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "DPIDE"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "DPI0_DE"),
+ MTK_FUNCTION_IRQ(2, "EINT100", 100),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "IRDA_TXD"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "DPICK"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "DPI0_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT101", 101),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "IRDA_PDN"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "DPIG4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "DPI0_G4"),
+ MTK_FUNCTION_IRQ(2, "EINT114", 114),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[0]"),
+ MTK_FUNCTION(5, "DSP2_ID"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "DPIG5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "DPI0_G5"),
+ MTK_FUNCTION_IRQ(2, "EINT115", 115),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[1]"),
+ MTK_FUNCTION(5, "DSP2_ICK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "DPIR3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "DPI0_R3"),
+ MTK_FUNCTION_IRQ(2, "EINT121", 121),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[7]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "DPIG1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "DPI0_G1"),
+ MTK_FUNCTION_IRQ(2, "EINT111", 111),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_ICK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "DPIVSYNC"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "DPI0_VSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT98", 98),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "DPIHSYNC"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "DPI0_HSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT99", 99),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "IRDA_RXD"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "DPIB0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "DPI0_B0"),
+ MTK_FUNCTION_IRQ(2, "EINT102", 102),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "SCL0"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "DPIB1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "DPI0_B1"),
+ MTK_FUNCTION_IRQ(2, "EINT103", 103),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SDA0"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "DPIB2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "DPI0_B2"),
+ MTK_FUNCTION_IRQ(2, "EINT104", 104),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "DPIB3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "DPI0_B3"),
+ MTK_FUNCTION_IRQ(2, "EINT105", 105),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "DPIB4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "DPI0_B4"),
+ MTK_FUNCTION_IRQ(2, "EINT106", 106),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "DPIB5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "DPI0_B5"),
+ MTK_FUNCTION_IRQ(2, "EINT107", 107),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "PWM5"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "DPIB6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "DPI0_B6"),
+ MTK_FUNCTION_IRQ(2, "EINT108", 108),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "PWM6"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "DPIB7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "DPI0_B7"),
+ MTK_FUNCTION_IRQ(2, "EINT109", 109),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "PWM7"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "DPIG0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "DPI0_G0"),
+ MTK_FUNCTION_IRQ(2, "EINT110", 110),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_ID"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "DPIG2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "DPI0_G2"),
+ MTK_FUNCTION_IRQ(2, "EINT112", 112),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_IMS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "DPIG3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "DPI0_G3"),
+ MTK_FUNCTION_IRQ(2, "EINT113", 113),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP2_IMS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "DPIG6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "DPI0_G6"),
+ MTK_FUNCTION_IRQ(2, "EINT116", 116),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[2]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "DPIG7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "DPI0_G7"),
+ MTK_FUNCTION_IRQ(2, "EINT117", 117),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[3]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "DPIR0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "DPI0_R0"),
+ MTK_FUNCTION_IRQ(2, "EINT118", 118),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[4]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "DPIR1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "DPI0_R1"),
+ MTK_FUNCTION_IRQ(2, "EINT119", 119),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[5]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "DPIR2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "DPI0_R2"),
+ MTK_FUNCTION_IRQ(2, "EINT120", 120),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[6]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "DPIR4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "DPI0_R4"),
+ MTK_FUNCTION_IRQ(2, "EINT122", 122),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[8]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "DPIR5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "DPI0_R5"),
+ MTK_FUNCTION_IRQ(2, "EINT123", 123),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[9]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "DPIR6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "DPI0_R6"),
+ MTK_FUNCTION_IRQ(2, "EINT124", 124),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2VSYNC_2X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "DPIR7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "DPI0_R7"),
+ MTK_FUNCTION_IRQ(2, "EINT125", 125),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2HSYNC_2X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
+ "AA2", "mt8135",
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT36", 36),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
+ "AA1", "mt8135",
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT35", 35),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
+ "Y2", "mt8135",
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT169", 169),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
+ "Y1", "mt8135",
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT168", 168),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
+ "W2", "mt8135",
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT163", 163),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
+ "W1", "mt8135",
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT162", 162),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
+ "V3", "mt8135",
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT167", 167),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
+ "V2", "mt8135",
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT166", 166),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
+ "U3", "mt8135",
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT165", 165),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
+ "U2", "mt8135",
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT164", 164),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "RDN3"),
+ "N5", "mt8135",
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT18", 18),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "RDP3"),
+ "N4", "mt8135",
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT30", 30),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "RDN2"),
+ "T2", "mt8135",
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT31", 31),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "RDP2"),
+ "T3", "mt8135",
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT32", 32),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "RCN"),
+ "P2", "mt8135",
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT33", 33),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "RCP"),
+ "P3", "mt8135",
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT39", 39),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "RDN1"),
+ "R3", "mt8135",
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "RDP1"),
+ "R2", "mt8135",
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "RDN0"),
+ "N3", "mt8135",
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "RDP0"),
+ "N2", "mt8135",
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "RDN1_A"),
+ "M4", "mt8135",
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "CMDAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT175", 175),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "RDP1_A"),
+ "M3", "mt8135",
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "CMDAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT174", 174),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "RCN_A"),
+ "L3", "mt8135",
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "CMDAT8"),
+ MTK_FUNCTION_IRQ(2, "EINT171", 171),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "RCP_A"),
+ "L2", "mt8135",
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "CMDAT9"),
+ MTK_FUNCTION_IRQ(2, "EINT170", 170),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "RDN0_A"),
+ "M2", "mt8135",
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "CMHSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT173", 173),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "RDP0_A"),
+ "M1", "mt8135",
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "CMVSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT172", 172),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "RDN1_B"),
+ "H2", "mt8135",
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "CMDAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT181", 181),
+ MTK_FUNCTION(3, "CMCSD2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "RDP1_B"),
+ "H1", "mt8135",
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "CMDAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT180", 180),
+ MTK_FUNCTION(3, "CMCSD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "RCN_B"),
+ "K3", "mt8135",
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "CMDAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT177", 177),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "RCP_B"),
+ "K2", "mt8135",
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "CMDAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT176", 176),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "RDN0_B"),
+ "J3", "mt8135",
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT179", 179),
+ MTK_FUNCTION(3, "CMCSD0"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "RDP0_B"),
+ "J2", "mt8135",
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT178", 178),
+ MTK_FUNCTION(3, "CMCSD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "CMPCLK"),
+ "K4", "mt8135",
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION_IRQ(2, "EINT182", 182),
+ MTK_FUNCTION(3, "CMCSK"),
+ MTK_FUNCTION(4, "CM2MCLK_4X"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"),
+ MTK_FUNCTION(6, "VENC_TEST_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "CMMCLK"),
+ "J5", "mt8135",
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION_IRQ(2, "EINT183", 183),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "CMRST"),
+ "J6", "mt8135",
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "CMRST"),
+ MTK_FUNCTION_IRQ(2, "EINT185", 185),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "CMPDN"),
+ "J4", "mt8135",
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "CMPDN"),
+ MTK_FUNCTION_IRQ(2, "EINT184", 184),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "CMFLASH"),
+ "G4", "mt8135",
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "CMFLASH"),
+ MTK_FUNCTION_IRQ(2, "EINT186", 186),
+ MTK_FUNCTION(3, "CM2MCLK_3X"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "MFG_TEST_CK_1"),
+ MTK_FUNCTION(7, "TESTA_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
+ "F5", "mt8135",
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT14", 14),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "PCM0_CK"),
+ MTK_FUNCTION(5, "DSP2_ICK"),
+ MTK_FUNCTION(6, "IMG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
+ "G6", "mt8135",
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT16", 16),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "PCM0_WS"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DISP_TEST_CK"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
+ "G3", "mt8135",
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_RX"),
+ MTK_FUNCTION_IRQ(2, "EINT15", 15),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, "PCM0_DI"),
+ MTK_FUNCTION(5, "DSP2_ID"),
+ MTK_FUNCTION(6, "MFG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
+ "G5", "mt8135",
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_TX"),
+ MTK_FUNCTION_IRQ(2, "EINT17", 17),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "PCM0_DO"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "VDEC_TEST_CK"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "SRCLKENAI"),
+ "K5", "mt8135",
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "SRCLKENAI"),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "URXD3"),
+ "C3", "mt8135",
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION_IRQ(2, "EINT87", 87),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUX_ST"),
+ MTK_FUNCTION(6, "PWM4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "UTXD3"),
+ "B2", "mt8135",
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION_IRQ(2, "EINT86", 86),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUX_CS_B"),
+ MTK_FUNCTION(6, "PWM3"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "SDA2"),
+ "G2", "mt8135",
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION_IRQ(2, "EINT95", 95),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "TS_AUX_PWDB"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "SCL2"),
+ "F4", "mt8135",
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION_IRQ(2, "EINT94", 94),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "TS_AUXADC_TEST_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "SDA1"),
+ "F2", "mt8135",
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION_IRQ(2, "EINT93", 93),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "SCL1"),
+ "F3", "mt8135",
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION_IRQ(2, "EINT92", 92),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "TS_AUX_DIN"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "MSDC3_DAT2"),
+ "E1", "mt8135",
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT71", 71),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_2"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "MSDC3_DAT3"),
+ "C2", "mt8135",
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT72", 72),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_3"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "MSDC3_CMD"),
+ "D2", "mt8135",
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "MSDC3_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT68", 68),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "MSDC3_CLK"),
+ "E2", "mt8135",
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "MSDC3_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT67", 67),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "MSDC3_DAT1"),
+ "D3", "mt8135",
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "MSDC3_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT70", 70),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "MSDC3_DAT0"),
+ "E3", "mt8135",
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "MSDC3_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT69", 69),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT8135_H */
diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h
new file mode 100644
index 0000000..4b5cefb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt65xx.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
+#define _DT_BINDINGS_PINCTRL_MT65XX_H
+
+#define MTK_PIN_NO(x) ((x) << 8)
+#define MTK_GET_PIN_NO(x) ((x) >> 8)
+#define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
+
+
+#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
@ 2014-11-11 12:38 ` Hongzhou Yang
0 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
arch/arm/mach-mediatek/Kconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 12 +
drivers/pinctrl/mediatek/Makefile | 5 +
drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 ++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 +++++++++++++++++++++++++
include/dt-bindings/pinctrl/mt65xx.h | 23 +
10 files changed, 3574 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25fe6cf..cd57639 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -1,6 +1,7 @@
menuconfig ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
select ARM_GIC
+ select PINCTRL
select MTK_TIMER
help
Support for Mediatek MT65xx & MT81xx SoCs
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6a66de..d15a56c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -213,6 +213,7 @@ source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
config PINCTRL_XWAY
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 51f52d3..af365c5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 0000000..bae4be6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK_COMMON
+ bool
+ select PINMUX
+ select GENERIC_PINCONF
+
+config PINCTRL_MT8135
+ def_bool MACH_MT8135
+ select PINCTRL_MTK_COMMON
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 0000000..8157dad
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
new file mode 100644
index 0000000..21ec1e6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8135.h"
+
+static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
+ .pins = mtk_pins_mt8135,
+ .npins = ARRAY_SIZE(mtk_pins_mt8135),
+ .dir_offset = 0x0000,
+ .ies_offset = 0x0100,
+ .pullen_offset = 0x0200,
+ .smt_offset = 0x0300,
+ .pullsel_offset = 0x0400,
+ .invser_offset = 0x0600,
+ .dout_offset = 0x0800,
+ .din_offset = 0x0A00,
+ .pinmux_offset = 0x0C00,
+ .type1_start = 34,
+ .type1_end = 149,
+ .port_shf = 4,
+ .port_mask = 0xf,
+ .port_align = 4,
+};
+
+static int mt8135_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_pctrl_init(pdev, &mt8135_pinctrl_data);
+}
+
+static int mt8135_pinctrl_remove(struct platform_device *pdev)
+{
+ return mtk_pctrl_remove(pdev);
+}
+
+
+static struct of_device_id mt8135_pctrl_match[] = {
+ {
+ .compatible = "mediatek,mt8135-pinctrl",
+ }, {
+ }
+};
+MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+ .probe = mt8135_pinctrl_probe,
+ .remove = mt8135_pinctrl_remove,
+ .driver = {
+ .name = "mediatek-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = mt8135_pctrl_match,
+ },
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+ return platform_driver_register(&mtk_pinctrl_driver);
+}
+
+static void __exit mtk_pinctrl_exit(void)
+{
+ platform_driver_unregister(&mtk_pinctrl_driver);
+}
+
+module_init(mtk_pinctrl_init);
+module_exit(mtk_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
+MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
new file mode 100644
index 0000000..f4d1ec3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -0,0 +1,861 @@
+/*
+ * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "../pinconf.h"
+#include "pinctrl-mtk-common.h"
+
+#define PINMUX_MAX_VAL 8
+#define MAX_GPIO_MODE_PER_REG 5
+#define GPIO_MODE_BITS 3
+
+static const char * const mtk_gpio_functions[] = {
+ "func0", "func1", "func2", "func3",
+ "func4", "func5", "func6", "func7",
+};
+
+/*
+ * There are two base address for pull related configuration
+ * in mt8135, and different GPIO pins use different base address.
+ * When pin number greater than type1_start and less than type1_end,
+ * should use the second base address.
+ */
+static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
+ unsigned long pin)
+{
+ if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
+ return pctl->regmap2;
+ return pctl->regmap1;
+}
+
+static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
+{
+ /* Different SoC has different mask and port shift. */
+ return ((pin >> 4) & pctl->devdata->port_mask)
+ << pctl->devdata->port_shf;
+}
+
+static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset,
+ bool input)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & 0xf);
+
+ if (input)
+ /* Different SoC has different alignment offset. */
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+ else
+ reg_addr = SET_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+ return 0;
+}
+
+static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
+ bit = BIT(offset & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(reg_addr, pctl);
+ else
+ reg_addr = CLR_ADDR(reg_addr, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
+}
+
+static void mtk_pconf_set_ies(struct mtk_pinctrl *pctl, unsigned pin, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+
+ bit = BIT(pin & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->ies_offset, pctl);
+ else
+ reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->ies_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
+}
+
+static void mtk_pconf_set_smt(struct mtk_pinctrl *pctl, unsigned pin, int value)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+
+ bit = BIT(pin & 0xf);
+
+ if (value)
+ reg_addr = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->smt_offset, pctl);
+ else
+ reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->smt_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
+}
+
+static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
+ unsigned long pin, bool enable, bool isup, unsigned int arg)
+{
+ unsigned int bit;
+ unsigned int reg_pullen, reg_pullsel;
+
+ bit = BIT(pin & 0xf);
+ if (enable)
+ reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+ else
+ reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset, pctl);
+
+ if (isup)
+ reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+ else
+ reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset, pctl);
+
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
+ regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
+ return 0;
+}
+
+static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
+ unsigned long pin, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mtk_pconf_set_ies(pctl, pin, arg);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ mtk_gpio_set(pctl->chip, pin, arg);
+ mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mtk_pconf_set_smt(pctl, pin, arg);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned group,
+ unsigned long *config)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = pctl->groups[group].config;
+
+ return 0;
+}
+
+static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = &pctl->groups[group];
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ mtk_pconf_parse_conf(pctldev, g->pin,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+
+ g->config = configs[i];
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops mtk_pconf_ops = {
+ .pin_config_group_get = mtk_pconf_group_get,
+ .pin_config_group_set = mtk_pconf_group_set,
+};
+
+static struct mtk_pinctrl_group *
+mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
+{
+ int i;
+
+ for (i = 0; i < pctl->ngroups; i++) {
+ struct mtk_pinctrl_group *grp = pctl->groups + i;
+
+ if (grp->pin == pin)
+ return grp;
+ }
+
+ return NULL;
+}
+
+static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
+ u32 pin_num, u32 fnum)
+{
+ int i;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (pin->pin.number == pin_num) {
+ struct mtk_desc_function *func = pin->functions + fnum;
+
+ if (func->name)
+ return true;
+
+ break;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, u32 pin,
+ u32 fnum, struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps)
+{
+ bool ret;
+ struct mtk_pinctrl_group *grp;
+
+ if (*num_maps == *cnt_maps)
+ return -ENOSPC;
+
+ grp = mtk_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)[*num_maps].data.mux.group = grp->name;
+
+ ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
+ if (!ret) {
+ dev_err(pctl->dev, "invalid function %d on pin %d .\n",
+ fnum, pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
+ (*num_maps)++;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
+ unsigned long *configs, unsigned num_configs,
+ struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps)
+{
+ struct mtk_pinctrl_group *grp;
+ unsigned long *cfgs;
+
+ if (*num_maps == *cnt_maps)
+ return -ENOSPC;
+
+ cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
+ GFP_KERNEL);
+ if (cfgs == NULL)
+ return -ENOMEM;
+
+ grp = mtk_pctrl_find_group_by_pin(pctl, pin);
+ if (!grp) {
+ dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
+ return -EINVAL;
+ }
+
+ (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ (*map)[*num_maps].data.configs.group_or_pin = grp->name;
+ (*map)[*num_maps].data.configs.configs = cfgs;
+ (*map)[*num_maps].data.configs.num_configs = num_configs;
+ (*num_maps)++;
+
+ return 0;
+}
+
+static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map,
+ unsigned num_maps)
+{
+ int i;
+
+ for (i = 0; i < num_maps; i++) {
+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+ kfree(map[i].data.configs.configs);
+ }
+
+ kfree(map);
+}
+
+static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
+ unsigned *num_maps, unsigned cnt)
+{
+ unsigned old_num = *cnt_maps;
+ unsigned new_num = *num_maps + cnt;
+ struct pinctrl_map *new_map;
+
+ if (old_num >= new_num)
+ return 0;
+
+ new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+ *map = new_map;
+ *cnt_maps = new_num;
+
+ return 0;
+}
+
+static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *node,
+ struct pinctrl_map **map,
+ unsigned *num_maps, unsigned *cnt_maps)
+{
+ struct property *pins;
+ u32 pinfunc, pin, func;
+ int num_pins, num_funcs, maps_per_pin;
+ unsigned long *configs;
+ unsigned int num_configs;
+ bool has_config = 0;
+ int i, err;
+ unsigned cnt = 0;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ pins = of_find_property(node, "mediatek,pins", NULL);
+ if (!pins) {
+ dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
+ node->name);
+ return -EINVAL;
+ }
+
+ err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
+ if (num_configs)
+ has_config = 1;
+
+ num_pins = pins->length / sizeof(u32);
+ num_funcs = num_pins;
+ maps_per_pin = 0;
+ if (num_funcs)
+ maps_per_pin++;
+ if (has_config && num_pins >= 1)
+ maps_per_pin++;
+
+ if (!num_pins || !maps_per_pin)
+ return -EINVAL;
+
+ cnt = num_pins * maps_per_pin;
+
+ err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
+ if (err < 0)
+ goto fail;
+
+ for (i = 0; i < num_pins; i++) {
+ err = of_property_read_u32_index(node, "mediatek,pins",
+ i, &pinfunc);
+ if (err)
+ goto fail;
+
+ pin = MTK_GET_PIN_NO(pinfunc);
+ func = MTK_GET_PIN_FUNC(pinfunc);
+
+ if (pin >= pctl->devdata->npins ||
+ func >= ARRAY_SIZE(mtk_gpio_functions)) {
+ dev_err(pctl->dev, "invalid mediatek,pins value.\n");
+ err = -EINVAL;
+ goto fail;
+ }
+
+ err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, map,
+ cnt_maps, num_maps);
+ if (err < 0)
+ goto fail;
+
+ if (has_config) {
+ err = mtk_pctrl_dt_node_to_map_config(pctl, pin,
+ configs, num_configs, map, cnt_maps,
+ num_maps);
+ if (err < 0)
+ goto fail;
+ }
+ }
+
+ return 0;
+
+fail:
+ return err;
+}
+
+static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct device_node *np;
+ unsigned cnt_maps;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+ cnt_maps = 0;
+
+ for_each_child_of_node(np_config, np) {
+ ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
+ num_maps, &cnt_maps);
+ if (ret < 0) {
+ mtk_pctrl_dt_free_map(pctldev, *map, *num_maps);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = (unsigned *)&pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops mtk_pctrl_ops = {
+ .dt_node_to_map = mtk_pctrl_dt_node_to_map,
+ .dt_free_map = mtk_pctrl_dt_free_map,
+ .get_groups_count = mtk_pctrl_get_groups_count,
+ .get_group_name = mtk_pctrl_get_group_name,
+ .get_group_pins = mtk_pctrl_get_group_pins,
+};
+
+static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mtk_gpio_functions);
+}
+
+static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ return mtk_gpio_functions[selector];
+}
+
+static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->grp_names;
+ *num_groups = pctl->ngroups;
+
+ return 0;
+}
+
+static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
+ unsigned long pin, unsigned long mode)
+{
+ unsigned int reg_addr;
+ unsigned char bit;
+ unsigned int val;
+ unsigned long flags;
+ unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
+ + pctl->devdata->pinmux_offset;
+
+ spin_lock_irqsave(&pctl->lock, flags);
+ regmap_read(pctl->regmap1, reg_addr, &val);
+ bit = pin % MAX_GPIO_MODE_PER_REG;
+ val &= ~(mask << (GPIO_MODE_BITS * bit));
+ val |= (mode << (GPIO_MODE_BITS * bit));
+ regmap_write(pctl->regmap1, reg_addr, val);
+ spin_unlock_irqrestore(&pctl->lock, flags);
+ return 0;
+}
+
+static struct mtk_desc_function *
+mtk_pctrl_desc_find_function_by_number(struct mtk_pinctrl *pctl,
+ const char *pin_name,
+ unsigned number)
+{
+ int i;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (!strcmp(pin->pin.name, pin_name)) {
+ struct mtk_desc_function *func = pin->functions;
+
+ return func + number;
+ }
+ }
+
+ return NULL;
+}
+
+static struct mtk_desc_function *
+mtk_pctrl_desc_find_irq_function_from_name(struct mtk_pinctrl *pctl,
+ const char *pin_name)
+{
+ int i, j;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+
+ if (!strcmp(pin->pin.name, pin_name)) {
+ struct mtk_desc_function *func = pin->functions;
+
+ for (j = 0; j < PINMUX_MAX_VAL; j++) {
+ if (func->irqnum != MTK_NO_EINT_SUPPORT)
+ return func;
+
+ func++;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned function,
+ unsigned group)
+{
+ bool ret;
+ struct mtk_desc_function *desc;
+ struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct mtk_pinctrl_group *g = pctl->groups + group;
+
+ ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
+ if (!ret) {
+ dev_err(pctl->dev, "invaild function %d on group %d .\n",
+ function, group);
+ return -EINVAL;
+ }
+
+ desc = mtk_pctrl_desc_find_function_by_number(pctl, g->name, function);
+ if (!desc)
+ return -EINVAL;
+ mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
+ return 0;
+}
+
+static const struct pinmux_ops mtk_pmx_ops = {
+ .get_functions_count = mtk_pmx_get_funcs_cnt,
+ .get_function_name = mtk_pmx_get_func_name,
+ .get_function_groups = mtk_pmx_get_func_groups,
+ .set_mux = mtk_pmx_set_mux,
+ .gpio_set_direction = mtk_pmx_gpio_set_direction,
+};
+
+static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int mtk_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int mtk_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ mtk_gpio_set(chip, offset, value);
+ return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
+ bit = BIT(offset & 0xf);
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !!(read_val & bit);
+}
+
+static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int reg_addr;
+ unsigned int bit;
+ unsigned int read_val = 0;
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+
+ if (mtk_gpio_get_direction(chip, offset))
+ reg_addr = mtk_get_port(pctl, offset) +
+ pctl->devdata->dout_offset;
+ else
+ reg_addr = mtk_get_port(pctl, offset) +
+ pctl->devdata->din_offset;
+
+ bit = BIT(offset & 0xf);
+ regmap_read(pctl->regmap1, reg_addr, &read_val);
+ return !!(read_val & bit);
+}
+
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
+ struct mtk_pinctrl_group *g = pctl->groups + offset;
+ struct mtk_desc_function *desc =
+ mtk_pctrl_desc_find_irq_function_from_name(
+ pctl, g->name);
+ if (!desc)
+ return -EINVAL;
+
+ return desc->irqnum;
+}
+
+static struct gpio_chip mtk_gpio_chip = {
+ .owner = THIS_MODULE,
+ .request = mtk_gpio_request,
+ .free = mtk_gpio_free,
+ .direction_input = mtk_gpio_direction_input,
+ .direction_output = mtk_gpio_direction_output,
+ .get = mtk_gpio_get,
+ .set = mtk_gpio_set,
+ .to_irq = mtk_gpio_to_irq,
+ .of_gpio_n_cells = 2,
+};
+
+static int mtk_pctrl_build_state(struct platform_device *pdev)
+{
+ struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
+ int i;
+
+ pctl->ngroups = pctl->devdata->npins;
+
+ /* Allocate groups */
+ pctl->groups = devm_kzalloc(&pdev->dev,
+ pctl->ngroups * sizeof(*pctl->groups),
+ GFP_KERNEL);
+ if (!pctl->groups)
+ return -ENOMEM;
+
+ /* We assume that one pin is one group, use pin name as group name. */
+ pctl->grp_names = devm_kzalloc(&pdev->dev,
+ pctl->ngroups * sizeof(*pctl->grp_names),
+ GFP_KERNEL);
+ if (!pctl->grp_names)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++) {
+ const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
+ struct mtk_pinctrl_group *group = pctl->groups + i;
+ const char **func_grp;
+
+ group->name = pin->pin.name;
+ group->pin = pin->pin.number;
+
+ func_grp = pctl->grp_names;
+ while (*func_grp)
+ func_grp++;
+
+ *func_grp = pin->pin.name;
+ }
+
+ return 0;
+}
+
+static struct pinctrl_desc mtk_pctrl_desc = {
+ .confops = &mtk_pconf_ops,
+ .pctlops = &mtk_pctrl_ops,
+ .pmxops = &mtk_pmx_ops,
+};
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data)
+{
+ struct pinctrl_pin_desc *pins;
+ struct mtk_pinctrl *pctl;
+ struct device_node *np = pdev->dev.of_node, *node;
+ int i, ret;
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pctl);
+
+ spin_lock_init(&pctl->lock);
+
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
+ if (node) {
+ pctl->regmap1 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap1))
+ return PTR_ERR(pctl->regmap1);
+ }
+
+ /* Only 8135 has two base addr, other SoCs have only one. */
+ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
+ if (node) {
+ pctl->regmap2 = syscon_node_to_regmap(node);
+ if (IS_ERR(pctl->regmap2))
+ return PTR_ERR(pctl->regmap2);
+ }
+
+ pctl->devdata = data;
+ ret = mtk_pctrl_build_state(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "build state failed: %d\n", ret);
+ return -EINVAL;
+ }
+
+ pins = devm_kzalloc(&pdev->dev,
+ pctl->devdata->npins * sizeof(*pins),
+ GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < pctl->devdata->npins; i++)
+ pins[i] = pctl->devdata->pins[i].pin;
+ mtk_pctrl_desc.name = dev_name(&pdev->dev);
+ mtk_pctrl_desc.owner = THIS_MODULE;
+ mtk_pctrl_desc.pins = pins;
+ mtk_pctrl_desc.npins = pctl->devdata->npins;
+ pctl->dev = &pdev->dev;
+ pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
+ if (!pctl->pctl_dev) {
+ dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
+ if (!pctl->chip) {
+ ret = -ENOMEM;
+ goto pctrl_error;
+ }
+
+ pctl->chip = &mtk_gpio_chip;
+ pctl->chip->ngpio = pctl->devdata->npins;
+ pctl->chip->label = dev_name(&pdev->dev);
+ pctl->chip->dev = &pdev->dev;
+ pctl->chip->base = 0;
+
+ ret = gpiochip_add(pctl->chip);
+ if (ret) {
+ ret = -EINVAL;
+ goto pctrl_error;
+ }
+
+ /* Register the GPIO to pin mappings. */
+ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
+ 0, 0, pctl->devdata->npins);
+ if (ret) {
+ ret = -EINVAL;
+ goto chip_error;
+ }
+
+ return 0;
+
+chip_error:
+ gpiochip_remove(pctl->chip);
+pctrl_error:
+ pinctrl_unregister(pctl->pctl_dev);
+ return ret;
+}
+
+int mtk_pctrl_remove(struct platform_device *pdev)
+{
+
+ struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(pctl->pctl_dev);
+ gpiochip_remove(pctl->chip);
+
+ return 0;
+}
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
+MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
new file mode 100644
index 0000000..7a254a3
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_COMMON_H
+#define __PINCTRL_MTK_COMMON_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+
+#define MTK_NO_EINT_SUPPORT 255
+
+struct mtk_desc_function {
+ const char *name;
+ unsigned char muxval;
+ unsigned char irqnum;
+};
+
+struct mtk_desc_pin {
+ struct pinctrl_pin_desc pin;
+ const char *chip;
+ struct mtk_desc_function *functions;
+};
+
+#define MTK_PIN(_pin, _pad, _chip, ...) \
+ { \
+ .pin = _pin, \
+ .chip = _chip, \
+ .functions = (struct mtk_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define MTK_FUNCTION(_val, _name) \
+ { \
+ .name = _name, \
+ .muxval = _val, \
+ .irqnum = MTK_NO_EINT_SUPPORT, \
+ }
+
+#define MTK_FUNCTION_IRQ(_val, _name, _irq) \
+ { \
+ .name = _name, \
+ .muxval = _val, \
+ .irqnum = _irq, \
+ }
+
+#define SET_ADDR(x, y) (x + (y->devdata->port_align))
+#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1))
+
+struct mtk_pinctrl_group {
+ const char *name;
+ unsigned long config;
+ unsigned pin;
+};
+
+/**
+ * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
+ * @pins: An array describing all pins the pin controller affects.
+
+ * @npins: The number of entries in @pins.
+ * @dir_offset: The direction register offset.
+ * @pullen_offset: The pull-up/pull-down enable register offset.
+ * @pinmux_offset: The pinmux register offset.
+ *
+ * @type1_start: Some chips have two base addresses for pull select register,
+ * that means some pins use the first address and others use the second. This
+ * member record the start of pin number to use the second address.
+ * @type1_end: The end of pin number to use the second address.
+ *
+ * @port_shf: The shift between two registers.
+ * @port_mask: The mask of register.
+ * @port_align: Provide clear register and set register step.
+ */
+struct mtk_pinctrl_devdata {
+ const struct mtk_desc_pin *pins;
+ unsigned int npins;
+ unsigned int dir_offset;
+ unsigned int ies_offset;
+ unsigned int smt_offset;
+ unsigned int pullen_offset;
+ unsigned int pullsel_offset;
+ unsigned int drv_offset;
+ unsigned int invser_offset;
+ unsigned int dout_offset;
+ unsigned int din_offset;
+ unsigned int pinmux_offset;
+ unsigned short type1_start;
+ unsigned short type1_end;
+ unsigned char port_shf;
+ unsigned char port_mask;
+ unsigned char port_align;
+};
+
+struct mtk_pinctrl {
+ struct regmap *regmap1;
+ struct regmap *regmap2;
+ struct device *dev;
+ struct gpio_chip *chip;
+ spinlock_t lock;
+ struct mtk_pinctrl_group *groups;
+ unsigned ngroups;
+ const char **grp_names;
+ struct pinctrl_dev *pctl_dev;
+ const struct mtk_pinctrl_devdata *devdata;
+};
+
+int mtk_pctrl_init(struct platform_device *pdev,
+ const struct mtk_pinctrl_devdata *data);
+
+int mtk_pctrl_remove(struct platform_device *pdev);
+
+#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
new file mode 100644
index 0000000..9f9cee6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
@@ -0,0 +1,2460 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PINCTRL_MTK_MT8135_H
+#define __PINCTRL_MTK_MT8135_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <pinctrl-mtk-common.h>
+
+static const struct mtk_desc_pin mtk_pins_mt8135[] = {
+ MTK_PIN(
+ PINCTRL_PIN(0, "MSDC0_DAT7"),
+ "D21", "mt8135",
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "MSDC0_DAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT49", 49),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "SPI1_MO"),
+ MTK_FUNCTION(7, "NALE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(1, "MSDC0_DAT6"),
+ "D22", "mt8135",
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "MSDC0_DAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT48", 48),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "SPI1_CSN"),
+ MTK_FUNCTION(7, "NCLE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(2, "MSDC0_DAT5"),
+ "E22", "mt8135",
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "MSDC0_DAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT47", 47),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "SPI1_CLK"),
+ MTK_FUNCTION(7, "NLD4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(3, "MSDC0_DAT4"),
+ "F21", "mt8135",
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "MSDC0_DAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT46", 46),
+ MTK_FUNCTION(3, "A_FUNC_CK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "LSCE1B_2X"),
+ MTK_FUNCTION(7, "NLD5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(4, "MSDC0_CMD"),
+ "F20", "mt8135",
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "MSDC0_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT41", 41),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[0]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[0]"),
+ MTK_FUNCTION(6, "LRSTB_2X"),
+ MTK_FUNCTION(7, "NRNB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(5, "MSDC0_CLK"),
+ "G18", "mt8135",
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "MSDC0_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT40", 40),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[1]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[1]"),
+ MTK_FUNCTION(6, "LPTE"),
+ MTK_FUNCTION(7, "NREB")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(6, "MSDC0_DAT3"),
+ "G21", "mt8135",
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "MSDC0_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT45", 45),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[2]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[2]"),
+ MTK_FUNCTION(6, "LSCE0B_2X"),
+ MTK_FUNCTION(7, "NLD7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(7, "MSDC0_DAT2"),
+ "E21", "mt8135",
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "MSDC0_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT44", 44),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[3]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[3]"),
+ MTK_FUNCTION(6, "LSA0_2X"),
+ MTK_FUNCTION(7, "NLD14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(8, "MSDC0_DAT1"),
+ "E23", "mt8135",
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "MSDC0_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT43", 43),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[4]"),
+ MTK_FUNCTION(6, "LSCK_2X"),
+ MTK_FUNCTION(7, "NLD11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(9, "MSDC0_DAT0"),
+ "F22", "mt8135",
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "MSDC0_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT42", 42),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[5]"),
+ MTK_FUNCTION(6, "LSDA_2X"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(10, "NCEB0"),
+ "G20", "mt8135",
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "NCEB0"),
+ MTK_FUNCTION_IRQ(2, "EINT139", 139),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(11, "NCEB1"),
+ "L17", "mt8135",
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "NCEB1"),
+ MTK_FUNCTION_IRQ(2, "EINT140", 140),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "USB_DRVVBUS"),
+ MTK_FUNCTION(7, "TESTA_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(12, "NRNB"),
+ "G19", "mt8135",
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "NRNB"),
+ MTK_FUNCTION_IRQ(2, "EINT141", 141),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[4]"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(13, "NCLE"),
+ "J18", "mt8135",
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "NCLE"),
+ MTK_FUNCTION_IRQ(2, "EINT142", 142),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[5]"),
+ MTK_FUNCTION(4, "CM2PDN_1X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "NALE"),
+ MTK_FUNCTION(7, "TESTA_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(14, "NALE"),
+ "J19", "mt8135",
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "NALE"),
+ MTK_FUNCTION_IRQ(2, "EINT143", 143),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[6]"),
+ MTK_FUNCTION(4, "CM2MCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_RXD"),
+ MTK_FUNCTION(6, "NCLE"),
+ MTK_FUNCTION(7, "TESTA_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(15, "NREB"),
+ "L18", "mt8135",
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "NREB"),
+ MTK_FUNCTION_IRQ(2, "EINT144", 144),
+ MTK_FUNCTION(3, "A_FUNC_DOUT[7]"),
+ MTK_FUNCTION(4, "CM2RST_1X"),
+ MTK_FUNCTION(5, "IRDA_TXD"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(16, "NWEB"),
+ "J20", "mt8135",
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "NWEB"),
+ MTK_FUNCTION_IRQ(2, "EINT145", 145),
+ MTK_FUNCTION(3, "A_FUNC_DIN[0]"),
+ MTK_FUNCTION(4, "CM2PCLK_1X"),
+ MTK_FUNCTION(5, "IRDA_PDN"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(17, "NLD0"),
+ "K21", "mt8135",
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "NLD0"),
+ MTK_FUNCTION_IRQ(2, "EINT146", 146),
+ MTK_FUNCTION(3, "A_FUNC_DIN[1]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[0]"),
+ MTK_FUNCTION(5, "I2SIN_CK"),
+ MTK_FUNCTION(6, "DAC_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(18, "NLD1"),
+ "K22", "mt8135",
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "NLD1"),
+ MTK_FUNCTION_IRQ(2, "EINT147", 147),
+ MTK_FUNCTION(3, "A_FUNC_DIN[2]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[1]"),
+ MTK_FUNCTION(5, "I2SIN_WS"),
+ MTK_FUNCTION(6, "DAC_WS"),
+ MTK_FUNCTION(7, "TESTA_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(19, "NLD2"),
+ "J21", "mt8135",
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "NLD2"),
+ MTK_FUNCTION_IRQ(2, "EINT148", 148),
+ MTK_FUNCTION(3, "A_FUNC_DIN[3]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[2]"),
+ MTK_FUNCTION(5, "I2SOUT_DAT"),
+ MTK_FUNCTION(6, "DAC_DAT_OUT"),
+ MTK_FUNCTION(7, "TESTA_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(20, "NLD3"),
+ "J23", "mt8135",
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "NLD3"),
+ MTK_FUNCTION_IRQ(2, "EINT149", 149),
+ MTK_FUNCTION(3, "A_FUNC_DIN[4]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[3]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT14")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(21, "NLD4"),
+ "J22", "mt8135",
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "NLD4"),
+ MTK_FUNCTION_IRQ(2, "EINT150", 150),
+ MTK_FUNCTION(3, "A_FUNC_DIN[5]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[4]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT15")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(22, "NLD5"),
+ "H21", "mt8135",
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "NLD5"),
+ MTK_FUNCTION_IRQ(2, "EINT151", 151),
+ MTK_FUNCTION(3, "A_FUNC_DIN[6]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[5]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT16")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(23, "NLD6"),
+ "H22", "mt8135",
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "NLD6"),
+ MTK_FUNCTION_IRQ(2, "EINT152", 152),
+ MTK_FUNCTION(3, "A_FUNC_DIN[7]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[6]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT17")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(24, "NLD7"),
+ "H20", "mt8135",
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "NLD7"),
+ MTK_FUNCTION_IRQ(2, "EINT153", 153),
+ MTK_FUNCTION(3, "A_FUNC_DIN[8]"),
+ MTK_FUNCTION(4, "CM2DAT_1X[7]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT18")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(25, "NLD8"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "NLD8"),
+ MTK_FUNCTION_IRQ(2, "EINT154", 154),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_1X[8]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(26, "NLD9"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "NLD9"),
+ MTK_FUNCTION_IRQ(2, "EINT155", 155),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_1X[9]"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(27, "NLD10"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "NLD10"),
+ MTK_FUNCTION_IRQ(2, "EINT156", 156),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2VSYNC_1X"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(28, "NLD11"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "NLD11"),
+ MTK_FUNCTION_IRQ(2, "EINT157", 157),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2HSYNC_1X"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(29, "NLD12"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "NLD12"),
+ MTK_FUNCTION_IRQ(2, "EINT158", 158),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(30, "NLD13"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "NLD13"),
+ MTK_FUNCTION_IRQ(2, "EINT159", 159),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(31, "NLD14"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "NLD14"),
+ MTK_FUNCTION_IRQ(2, "EINT160", 160),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(32, "NLD15"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "NLD15"),
+ MTK_FUNCTION_IRQ(2, "EINT161", 161),
+ MTK_FUNCTION(3, "DISP_PWM"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(33, "MSDC0_RSTB"),
+ "G22", "mt8135",
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "MSDC0_RSTB"),
+ MTK_FUNCTION_IRQ(2, "EINT50", 50),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "SPI1_MI"),
+ MTK_FUNCTION(7, "NLD10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(34, "IDDIG"),
+ "N17", "mt8135",
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION_IRQ(2, "EINT34", 34),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(35, "SCL3"),
+ "L19", "mt8135",
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION_IRQ(2, "EINT96", 96),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(36, "SDA3"),
+ "L20", "mt8135",
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION_IRQ(2, "EINT97", 97),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(37, "AUD_CLK_MOSI"),
+ "L21", "mt8135",
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "AUD_CLK"),
+ MTK_FUNCTION(2, "ADC_CK"),
+ MTK_FUNCTION(3, " HDMI_SDATA0"),
+ MTK_FUNCTION_IRQ(4, "EINT19", 19),
+ MTK_FUNCTION(5, "USB_TEST_IO[6]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT19")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(38, "AUD_DAT_MOSI"),
+ "L23", "mt8135",
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(2, "ADC_WS"),
+ MTK_FUNCTION(3, "AUD_DAT_MISO"),
+ MTK_FUNCTION_IRQ(4, "EINT21", 21),
+ MTK_FUNCTION(5, "USB_TEST_IO[7]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT20")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(39, "AUD_DAT_MISO"),
+ "L22", "mt8135",
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(2, "ADC_DAT_IN"),
+ MTK_FUNCTION(3, "AUD_DAT_MOSI"),
+ MTK_FUNCTION_IRQ(4, "EINT20", 20),
+ MTK_FUNCTION(5, "USB_TEST_IO[8]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(40, "DAC_CLK"),
+ "P21", "mt8135",
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "DAC_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT22", 22),
+ MTK_FUNCTION(3, " HDMI_SDATA1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[9]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT22")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(41, "DAC_WS"),
+ "N18", "mt8135",
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "DAC_WS"),
+ MTK_FUNCTION_IRQ(2, "EINT24", 24),
+ MTK_FUNCTION(3, " HDMI_SDATA2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[10]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT23")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(42, "DAC_DAT_OUT"),
+ "N22", "mt8135",
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DAC_DAT_OUT"),
+ MTK_FUNCTION_IRQ(2, "EINT23", 23),
+ MTK_FUNCTION(3, " HDMI_SDATA3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[11]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
+ "M22", "mt8135",
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "PWRAP_SPIDI"),
+ MTK_FUNCTION_IRQ(2, "EINT29", 29),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
+ "P23", "mt8135",
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "PWRAP_SPIDO"),
+ MTK_FUNCTION_IRQ(2, "EINT28", 28),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
+ "M21", "mt8135",
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "PWRAP_SPICS_B_I"),
+ MTK_FUNCTION_IRQ(2, "EINT27", 27),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
+ "P22", "mt8135",
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "PWRAP_SPICK_I"),
+ MTK_FUNCTION_IRQ(2, "EINT26", 26),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(47, "PWRAP_EVENT"),
+ "M23", "mt8135",
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "PWRAP_EVENT_IN"),
+ MTK_FUNCTION_IRQ(2, "EINT25", 25),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(48, "RTC32K_CK"),
+ "N20", "mt8135",
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "RTC32K_CK"),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(49, "WATCHDOG"),
+ "R22", "mt8135",
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "WATCHDOG"),
+ MTK_FUNCTION_IRQ(2, "EINT36", 36),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(50, "SRCLKENA"),
+ "T22", "mt8135",
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SRCLKENA"),
+ MTK_FUNCTION_IRQ(2, "EINT38", 38),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(51, "SRCVOLTEN"),
+ "T23", "mt8135",
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SRCVOLTEN"),
+ MTK_FUNCTION_IRQ(2, "EINT37", 37),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(52, "EINT0"),
+ "T21", "mt8135",
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION_IRQ(1, "EINT0", 0),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, " SPDIF_OUT"),
+ MTK_FUNCTION(5, "USB_TEST_IO[12]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(53, "URXD2"),
+ "R18", "mt8135",
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "URXD2"),
+ MTK_FUNCTION_IRQ(2, "EINT83", 83),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, " HDMI_LRCK"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "UTXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(54, "UTXD2"),
+ "R17", "mt8135",
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "UTXD2"),
+ MTK_FUNCTION_IRQ(2, "EINT82", 82),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, " HDMI_BCK_OUT"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "URXD2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(55, "UCTS2"),
+ "R20", "mt8135",
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "UCTS2"),
+ MTK_FUNCTION_IRQ(2, "EINT84", 84),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "URTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(56, "URTS2"),
+ "R19", "mt8135",
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "URTS2"),
+ MTK_FUNCTION_IRQ(2, "EINT85", 85),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "UCTS2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(57, "JTCK"),
+ "V17", "mt8135",
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "JTCK"),
+ MTK_FUNCTION_IRQ(2, "EINT188", 188),
+ MTK_FUNCTION(3, "DSP1_ICK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(58, "JTDO"),
+ "T16", "mt8135",
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "JTDO"),
+ MTK_FUNCTION_IRQ(2, "EINT190", 190),
+ MTK_FUNCTION(3, "DSP2_IMS"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(59, "JTRST_B"),
+ "T19", "mt8135",
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "JTRST_B"),
+ MTK_FUNCTION_IRQ(2, "EINT0", 0),
+ MTK_FUNCTION(3, "DSP2_ICK"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(60, "JTDI"),
+ "T18", "mt8135",
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "JTDI"),
+ MTK_FUNCTION_IRQ(2, "EINT189", 189),
+ MTK_FUNCTION(3, "DSP1_IMS"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(61, "JRTCK"),
+ "T20", "mt8135",
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "JRTCK"),
+ MTK_FUNCTION_IRQ(2, "EINT187", 187),
+ MTK_FUNCTION(3, "DSP1_ID"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(62, "JTMS"),
+ "T17", "mt8135",
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "JTMS"),
+ MTK_FUNCTION_IRQ(2, "EINT191", 191),
+ MTK_FUNCTION(3, "DSP2_ID"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(63, "MSDC1_INSI"),
+ "V18", "mt8135",
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "MSDC1_INSI"),
+ MTK_FUNCTION_IRQ(2, "EINT57", 57),
+ MTK_FUNCTION(3, "SCL5"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT6")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(64, "MSDC1_SDWPI"),
+ "W18", "mt8135",
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "MSDC1_SDWPI"),
+ MTK_FUNCTION_IRQ(2, "EINT58", 58),
+ MTK_FUNCTION(3, "SDA5"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(5, "CLKM6"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT7")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(65, "MSDC2_INSI"),
+ "U22", "mt8135",
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "MSDC2_INSI"),
+ MTK_FUNCTION_IRQ(2, "EINT65", 65),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[27]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(66, "MSDC2_SDWPI"),
+ "U21", "mt8135",
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "MSDC2_SDWPI"),
+ MTK_FUNCTION_IRQ(2, "EINT66", 66),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[28]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(67, "URXD4"),
+ "V23", "mt8135",
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "URXD4"),
+ MTK_FUNCTION_IRQ(2, "EINT89", 89),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "UTXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT10")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(68, "UTXD4"),
+ "V22", "mt8135",
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "UTXD4"),
+ MTK_FUNCTION_IRQ(2, "EINT88", 88),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "URXD4"),
+ MTK_FUNCTION(7, "TESTB_OUT11")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(69, "URXD1"),
+ "W22", "mt8135",
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION_IRQ(2, "EINT79", 79),
+ MTK_FUNCTION(3, "URXD4"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "UTXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT24")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(70, "UTXD1"),
+ "V21", "mt8135",
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION_IRQ(2, "EINT78", 78),
+ MTK_FUNCTION(3, "UTXD4"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "URXD1"),
+ MTK_FUNCTION(7, "TESTB_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(71, "UCTS1"),
+ "V19", "mt8135",
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "UCTS1"),
+ MTK_FUNCTION_IRQ(2, "EINT80", 80),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, "URTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(72, "URTS1"),
+ "V20", "mt8135",
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "URTS1"),
+ MTK_FUNCTION_IRQ(2, "EINT81", 81),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "UCTS1"),
+ MTK_FUNCTION(7, "TESTB_OUT21")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(73, "PWM1"),
+ "W17", "mt8135",
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION_IRQ(2, "EINT73", 73),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT8")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(74, "PWM2"),
+ "Y17", "mt8135",
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION_IRQ(2, "EINT74", 74),
+ MTK_FUNCTION(3, "DPI33_CK"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "URXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT9")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(75, "PWM3"),
+ "Y19", "mt8135",
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "PWM3"),
+ MTK_FUNCTION_IRQ(2, "EINT75", 75),
+ MTK_FUNCTION(3, "DPI33_D0"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "UTXD2"),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT12")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(76, "PWM4"),
+ "W19", "mt8135",
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "PWM4"),
+ MTK_FUNCTION_IRQ(2, "EINT76", 76),
+ MTK_FUNCTION(3, "DPI33_D1"),
+ MTK_FUNCTION(4, "PWM7"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DISP_PWM"),
+ MTK_FUNCTION(7, "TESTB_OUT13")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(77, "MSDC2_DAT2"),
+ "W21", "mt8135",
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC2_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT63", 63),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_IMS"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DPI33_D6"),
+ MTK_FUNCTION(7, "TESTA_OUT25")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(78, "MSDC2_DAT3"),
+ "AA23", "mt8135",
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC2_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT64", 64),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_ID"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DPI33_D7"),
+ MTK_FUNCTION(7, "TESTA_OUT26")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(79, "MSDC2_CMD"),
+ "Y22", "mt8135",
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "MSDC2_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT60", 60),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_IMS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "DPI33_D3"),
+ MTK_FUNCTION(7, "TESTA_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(80, "MSDC2_CLK"),
+ "AA22", "mt8135",
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "MSDC2_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT59", 59),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_ICK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "DPI33_D2"),
+ MTK_FUNCTION(7, "TESTA_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(81, "MSDC2_DAT1"),
+ "Y21", "mt8135",
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "MSDC2_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT62", 62),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP2_ICK"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "DPI33_D5"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(82, "MSDC2_DAT0"),
+ "AB22", "mt8135",
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "MSDC2_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT61", 61),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "DSP1_ID"),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "DPI33_D4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(83, "MSDC1_DAT0"),
+ "AC19", "mt8135",
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT53", 53),
+ MTK_FUNCTION(3, "SCL1"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT2")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(84, "MSDC1_DAT1"),
+ "AA19", "mt8135",
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT54", 54),
+ MTK_FUNCTION(3, "SDA1"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(85, "MSDC1_CMD"),
+ "AA20", "mt8135",
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT52", 52),
+ MTK_FUNCTION(3, "SDA0"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT1")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(86, "MSDC1_CLK"),
+ "AB19", "mt8135",
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT51", 51),
+ MTK_FUNCTION(3, "SCL0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT0")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(87, "MSDC1_DAT2"),
+ "AA21", "mt8135",
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT55", 55),
+ MTK_FUNCTION(3, "SCL4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT4")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(88, "MSDC1_DAT3"),
+ "AB20", "mt8135",
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT56", 56),
+ MTK_FUNCTION(3, "SDA4"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTB_OUT5")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(89, "MSDC4_DAT0"),
+ "AB8", "mt8135",
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC4_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT133", 133),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[9]"),
+ MTK_FUNCTION(7, "LPTE")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(90, "MSDC4_DAT1"),
+ "AB7", "mt8135",
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "MSDC4_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT134", 134),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "A_FUNC_DIN[10]"),
+ MTK_FUNCTION(7, "LRSTB_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(91, "MSDC4_DAT5"),
+ "AA8", "mt8135",
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "MSDC4_DAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT136", 136),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[11]"),
+ MTK_FUNCTION(7, "SPI1_CSN")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(92, "MSDC4_DAT6"),
+ "AC4", "mt8135",
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "MSDC4_DAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT137", 137),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[12]"),
+ MTK_FUNCTION(7, "SPI1_MO")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(93, "MSDC4_DAT7"),
+ "AC6", "mt8135",
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "MSDC4_DAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT138", 138),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[13]"),
+ MTK_FUNCTION(7, "SPI1_MI")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(94, "MSDC4_DAT4"),
+ "AA7", "mt8135",
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "MSDC4_DAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT135", 135),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, "A_FUNC_DIN[14]"),
+ MTK_FUNCTION(7, "SPI1_CLK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(95, "MSDC4_DAT2"),
+ "AB6", "mt8135",
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "MSDC4_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT131", 131),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "CM2PDN_2X"),
+ MTK_FUNCTION(5, "DAC_WS"),
+ MTK_FUNCTION(6, "PCM1_WS"),
+ MTK_FUNCTION(7, "LSCE0B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(96, "MSDC4_CLK"),
+ "AB5", "mt8135",
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "MSDC4_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT129", 129),
+ MTK_FUNCTION(3, "DPI1_CK_2X"),
+ MTK_FUNCTION(4, "CM2PCLK_2X"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, "PCM1_DI"),
+ MTK_FUNCTION(7, "LSCK_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(97, "MSDC4_DAT3"),
+ "Y8", "mt8135",
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "MSDC4_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT132", 132),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "CM2RST_2X"),
+ MTK_FUNCTION(5, "DAC_DAT_OUT"),
+ MTK_FUNCTION(6, "PCM1_DO"),
+ MTK_FUNCTION(7, "LSCE1B_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(98, "MSDC4_CMD"),
+ "AC3", "mt8135",
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "MSDC4_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT128", 128),
+ MTK_FUNCTION(3, "DPI1_DE_2X"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "LSDA_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(99, "MSDC4_RSTB"),
+ "AB4", "mt8135",
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "MSDC4_RSTB"),
+ MTK_FUNCTION_IRQ(2, "EINT130", 130),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "CM2MCLK_2X"),
+ MTK_FUNCTION(5, "DAC_CK"),
+ MTK_FUNCTION(6, "PCM1_CK"),
+ MTK_FUNCTION(7, "LSA0_1X")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(100, "SDA0"),
+ "W9", "mt8135",
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION_IRQ(2, "EINT91", 91),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[15]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(101, "SCL0"),
+ "W11", "mt8135",
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION_IRQ(2, "EINT90", 90),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[16]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(102, "EINT10_AUXIN2"),
+ "AA3", "mt8135",
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION_IRQ(1, "EINT10", 10),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[16]"),
+ MTK_FUNCTION(6, "TESTB_OUT16"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[17]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(103, "EINT11_AUXIN3"),
+ "AB2", "mt8135",
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION_IRQ(1, "EINT11", 11),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[17]"),
+ MTK_FUNCTION(6, "TESTB_OUT17"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[18]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(104, "EINT16_AUXIN4"),
+ "AB3", "mt8135",
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION_IRQ(1, "EINT16", 16),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[18]"),
+ MTK_FUNCTION(6, "TESTB_OUT18"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[19]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(105, "I2S_CLK"),
+ "W6", "mt8135",
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "I2SIN_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT10", 10),
+ MTK_FUNCTION(3, "DAC_CK"),
+ MTK_FUNCTION(4, "PCM1_CK"),
+ MTK_FUNCTION(5, "USB_TEST_IO[19]"),
+ MTK_FUNCTION(6, "TESTB_OUT19"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[20]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(106, "I2S_WS"),
+ "AA6", "mt8135",
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "I2SIN_WS"),
+ MTK_FUNCTION_IRQ(2, "EINT13", 13),
+ MTK_FUNCTION(3, "DAC_WS"),
+ MTK_FUNCTION(4, "PCM1_WS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[20]"),
+ MTK_FUNCTION(6, "TESTB_OUT20"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[21]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(107, "I2S_DATA_IN"),
+ "AA5", "mt8135",
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "I2SIN_DAT"),
+ MTK_FUNCTION_IRQ(2, "EINT11", 11),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[21]"),
+ MTK_FUNCTION(6, "TESTB_OUT22"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[22]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(108, "I2S_DATA_OUT"),
+ "AA4", "mt8135",
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "I2SOUT_DAT"),
+ MTK_FUNCTION_IRQ(2, "EINT12", 12),
+ MTK_FUNCTION(3, "DAC_DAT_OUT"),
+ MTK_FUNCTION(4, "PCM1_DO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[22]"),
+ MTK_FUNCTION(6, "TESTB_OUT23"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[23]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(109, "EINT5"),
+ "W5", "mt8135",
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION_IRQ(1, "EINT5", 5),
+ MTK_FUNCTION(2, "PWM5"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "GPU_JTRSTB"),
+ MTK_FUNCTION(5, "USB_TEST_IO[23]"),
+ MTK_FUNCTION(6, "TESTB_OUT26"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[24]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(110, "EINT6"),
+ "V5", "mt8135",
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION_IRQ(1, "EINT6", 6),
+ MTK_FUNCTION(2, "PWM6"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "GPU_JTMS"),
+ MTK_FUNCTION(5, "USB_TEST_IO[24]"),
+ MTK_FUNCTION(6, "TESTB_OUT27"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[25]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(111, "EINT7"),
+ "W3", "mt8135",
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION_IRQ(1, "EINT7", 7),
+ MTK_FUNCTION(2, "PWM7"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "GPU_JTDO"),
+ MTK_FUNCTION(5, "USB_TEST_IO[25]"),
+ MTK_FUNCTION(6, "TESTB_OUT28"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[26]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(112, "EINT8"),
+ "V6", "mt8135",
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION_IRQ(1, "EINT8", 8),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "GPU_JTDI"),
+ MTK_FUNCTION(5, "USB_TEST_IO[26]"),
+ MTK_FUNCTION(6, "TESTB_OUT29"),
+ MTK_FUNCTION(7, "EXT_FRAME_SYNC")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(113, "EINT9"),
+ "W8", "mt8135",
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION_IRQ(1, "EINT9", 9),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "GPU_JTCK"),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, "TESTB_OUT30"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[27]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(114, "LPCE1B"),
+ "W4", "mt8135",
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "LPCE1B"),
+ MTK_FUNCTION_IRQ(2, "EINT127", 127),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, "TESTB_OUT14"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[28]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(115, "LPCE0B"),
+ "T5", "mt8135",
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "LPCE0B"),
+ MTK_FUNCTION_IRQ(2, "EINT126", 126),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, "TESTB_OUT15"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[29]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(116, "DISP_PWM"),
+ "V4", "mt8135",
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION_IRQ(2, "EINT77", 77),
+ MTK_FUNCTION(3, "LSDI"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "PWM3")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(117, "EINT1"),
+ "T6", "mt8135",
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION_IRQ(1, "EINT1", 1),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[13]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(118, "EINT2"),
+ "T4", "mt8135",
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION_IRQ(1, "EINT2", 2),
+ MTK_FUNCTION(2, "PWM3"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[14]"),
+ MTK_FUNCTION(6, "SRCLKENAI2"),
+ MTK_FUNCTION(7, "A_FUNC_DIN[30]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(119, "EINT3"),
+ "R4", "mt8135",
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION_IRQ(1, "EINT3", 3),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_TEST_IO[15]"),
+ MTK_FUNCTION(6, "SRCLKENAI1"),
+ MTK_FUNCTION(7, "EXT_26M_CK")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(120, "EINT4"),
+ "R5", "mt8135",
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION_IRQ(1, "EINT4", 4),
+ MTK_FUNCTION(2, "PWM4"),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "USB_DRVVBUS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "A_FUNC_DIN[31]")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(121, "DPIDE"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "DPI0_DE"),
+ MTK_FUNCTION_IRQ(2, "EINT100", 100),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "DAC_DAT_OUT"),
+ MTK_FUNCTION(5, "PCM1_DO"),
+ MTK_FUNCTION(6, "IRDA_TXD"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(122, "DPICK"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "DPI0_CK"),
+ MTK_FUNCTION_IRQ(2, "EINT101", 101),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "PCM1_DI"),
+ MTK_FUNCTION(6, "IRDA_PDN"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(123, "DPIG4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "DPI0_G4"),
+ MTK_FUNCTION_IRQ(2, "EINT114", 114),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[0]"),
+ MTK_FUNCTION(5, "DSP2_ID"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(124, "DPIG5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "DPI0_G5"),
+ MTK_FUNCTION_IRQ(2, "EINT115", 115),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[1]"),
+ MTK_FUNCTION(5, "DSP2_ICK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(125, "DPIR3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "DPI0_R3"),
+ MTK_FUNCTION_IRQ(2, "EINT121", 121),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[7]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(126, "DPIG1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "DPI0_G1"),
+ MTK_FUNCTION_IRQ(2, "EINT111", 111),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_ICK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(127, "DPIVSYNC"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "DPI0_VSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT98", 98),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "DAC_CK"),
+ MTK_FUNCTION(5, "PCM1_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(128, "DPIHSYNC"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "DPI0_HSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT99", 99),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "DAC_WS"),
+ MTK_FUNCTION(5, "PCM1_WS"),
+ MTK_FUNCTION(6, "IRDA_RXD"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(129, "DPIB0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "DPI0_B0"),
+ MTK_FUNCTION_IRQ(2, "EINT102", 102),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "SCL0"),
+ MTK_FUNCTION(5, "DISP_PWM"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(130, "DPIB1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "DPI0_B1"),
+ MTK_FUNCTION_IRQ(2, "EINT103", 103),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SDA0"),
+ MTK_FUNCTION(5, "PWM1"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(131, "DPIB2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "DPI0_B2"),
+ MTK_FUNCTION_IRQ(2, "EINT104", 104),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "SCL1"),
+ MTK_FUNCTION(5, "PWM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(132, "DPIB3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "DPI0_B3"),
+ MTK_FUNCTION_IRQ(2, "EINT105", 105),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "SDA1"),
+ MTK_FUNCTION(5, "PWM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(133, "DPIB4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "DPI0_B4"),
+ MTK_FUNCTION_IRQ(2, "EINT106", 106),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "SCL2"),
+ MTK_FUNCTION(5, "PWM4"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(134, "DPIB5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "DPI0_B5"),
+ MTK_FUNCTION_IRQ(2, "EINT107", 107),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "SDA2"),
+ MTK_FUNCTION(5, "PWM5"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(135, "DPIB6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "DPI0_B6"),
+ MTK_FUNCTION_IRQ(2, "EINT108", 108),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "SCL3"),
+ MTK_FUNCTION(5, "PWM6"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(136, "DPIB7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "DPI0_B7"),
+ MTK_FUNCTION_IRQ(2, "EINT109", 109),
+ MTK_FUNCTION(3, "CLKM6"),
+ MTK_FUNCTION(4, "SDA3"),
+ MTK_FUNCTION(5, "PWM7"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(137, "DPIG0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "DPI0_G0"),
+ MTK_FUNCTION_IRQ(2, "EINT110", 110),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_ID"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(138, "DPIG2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "DPI0_G2"),
+ MTK_FUNCTION_IRQ(2, "EINT112", 112),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP1_IMS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(139, "DPIG3"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "DPI0_G3"),
+ MTK_FUNCTION_IRQ(2, "EINT113", 113),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "DSP2_IMS"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(140, "DPIG6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "DPI0_G6"),
+ MTK_FUNCTION_IRQ(2, "EINT116", 116),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[2]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(141, "DPIG7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "DPI0_G7"),
+ MTK_FUNCTION_IRQ(2, "EINT117", 117),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[3]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(142, "DPIR0"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "DPI0_R0"),
+ MTK_FUNCTION_IRQ(2, "EINT118", 118),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[4]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(143, "DPIR1"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "DPI0_R1"),
+ MTK_FUNCTION_IRQ(2, "EINT119", 119),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[5]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(144, "DPIR2"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "DPI0_R2"),
+ MTK_FUNCTION_IRQ(2, "EINT120", 120),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[6]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(145, "DPIR4"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "DPI0_R4"),
+ MTK_FUNCTION_IRQ(2, "EINT122", 122),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[8]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(146, "DPIR5"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "DPI0_R5"),
+ MTK_FUNCTION_IRQ(2, "EINT123", 123),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2DAT_2X[9]"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(147, "DPIR6"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "DPI0_R6"),
+ MTK_FUNCTION_IRQ(2, "EINT124", 124),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2VSYNC_2X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(148, "DPIR7"),
+ NULL, "mt8135",
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "DPI0_R7"),
+ MTK_FUNCTION_IRQ(2, "EINT125", 125),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, "CM2HSYNC_2X"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
+ "AA2", "mt8135",
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT36", 36),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
+ "AA1", "mt8135",
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT35", 35),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
+ "Y2", "mt8135",
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT169", 169),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
+ "Y1", "mt8135",
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT168", 168),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
+ "W2", "mt8135",
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT163", 163),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
+ "W1", "mt8135",
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT162", 162),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
+ "V3", "mt8135",
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT167", 167),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
+ "V2", "mt8135",
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT166", 166),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
+ "U3", "mt8135",
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT165", 165),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
+ "U2", "mt8135",
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT164", 164),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(159, "RDN3"),
+ "N5", "mt8135",
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT18", 18),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(160, "RDP3"),
+ "N4", "mt8135",
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT30", 30),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(161, "RDN2"),
+ "T2", "mt8135",
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT31", 31),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(162, "RDP2"),
+ "T3", "mt8135",
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT32", 32),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(163, "RCN"),
+ "P2", "mt8135",
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT33", 33),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(164, "RCP"),
+ "P3", "mt8135",
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION_IRQ(2, "EINT39", 39),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(165, "RDN1"),
+ "R3", "mt8135",
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(166, "RDP1"),
+ "R2", "mt8135",
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(167, "RDN0"),
+ "N3", "mt8135",
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(168, "RDP0"),
+ "N2", "mt8135",
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, NULL),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(169, "RDN1_A"),
+ "M4", "mt8135",
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "CMDAT6"),
+ MTK_FUNCTION_IRQ(2, "EINT175", 175),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(170, "RDP1_A"),
+ "M3", "mt8135",
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "CMDAT7"),
+ MTK_FUNCTION_IRQ(2, "EINT174", 174),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(171, "RCN_A"),
+ "L3", "mt8135",
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "CMDAT8"),
+ MTK_FUNCTION_IRQ(2, "EINT171", 171),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(172, "RCP_A"),
+ "L2", "mt8135",
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "CMDAT9"),
+ MTK_FUNCTION_IRQ(2, "EINT170", 170),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(173, "RDN0_A"),
+ "M2", "mt8135",
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "CMHSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT173", 173),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(174, "RDP0_A"),
+ "M1", "mt8135",
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "CMVSYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT172", 172),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(175, "RDN1_B"),
+ "H2", "mt8135",
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "CMDAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT181", 181),
+ MTK_FUNCTION(3, "CMCSD2"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(176, "RDP1_B"),
+ "H1", "mt8135",
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "CMDAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT180", 180),
+ MTK_FUNCTION(3, "CMCSD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(177, "RCN_B"),
+ "K3", "mt8135",
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "CMDAT4"),
+ MTK_FUNCTION_IRQ(2, "EINT177", 177),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(178, "RCP_B"),
+ "K2", "mt8135",
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "CMDAT5"),
+ MTK_FUNCTION_IRQ(2, "EINT176", 176),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(179, "RDN0_B"),
+ "J3", "mt8135",
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "CMDAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT179", 179),
+ MTK_FUNCTION(3, "CMCSD0"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(180, "RDP0_B"),
+ "J2", "mt8135",
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "CMDAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT178", 178),
+ MTK_FUNCTION(3, "CMCSD1"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(181, "CMPCLK"),
+ "K4", "mt8135",
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "CMPCLK"),
+ MTK_FUNCTION_IRQ(2, "EINT182", 182),
+ MTK_FUNCTION(3, "CMCSK"),
+ MTK_FUNCTION(4, "CM2MCLK_4X"),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"),
+ MTK_FUNCTION(6, "VENC_TEST_CK"),
+ MTK_FUNCTION(7, "TESTA_OUT27")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(182, "CMMCLK"),
+ "J5", "mt8135",
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "CMMCLK"),
+ MTK_FUNCTION_IRQ(2, "EINT183", 183),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT28")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(183, "CMRST"),
+ "J6", "mt8135",
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "CMRST"),
+ MTK_FUNCTION_IRQ(2, "EINT185", 185),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT30")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(184, "CMPDN"),
+ "J4", "mt8135",
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "CMPDN"),
+ MTK_FUNCTION_IRQ(2, "EINT184", 184),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, "TESTA_OUT29")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(185, "CMFLASH"),
+ "G4", "mt8135",
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "CMFLASH"),
+ MTK_FUNCTION_IRQ(2, "EINT186", 186),
+ MTK_FUNCTION(3, "CM2MCLK_3X"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "MFG_TEST_CK_1"),
+ MTK_FUNCTION(7, "TESTA_OUT31")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
+ "F5", "mt8135",
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT14", 14),
+ MTK_FUNCTION(3, "I2SIN_CK"),
+ MTK_FUNCTION(4, "PCM0_CK"),
+ MTK_FUNCTION(5, "DSP2_ICK"),
+ MTK_FUNCTION(6, "IMG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SCL")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
+ "G6", "mt8135",
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"),
+ MTK_FUNCTION_IRQ(2, "EINT16", 16),
+ MTK_FUNCTION(3, "I2SIN_WS"),
+ MTK_FUNCTION(4, "PCM0_WS"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "DISP_TEST_CK"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
+ "G3", "mt8135",
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_RX"),
+ MTK_FUNCTION_IRQ(2, "EINT15", 15),
+ MTK_FUNCTION(3, "I2SIN_DAT"),
+ MTK_FUNCTION(4, "PCM0_DI"),
+ MTK_FUNCTION(5, "DSP2_ID"),
+ MTK_FUNCTION(6, "MFG_TEST_CK"),
+ MTK_FUNCTION(7, "USB_SDA")
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
+ "G5", "mt8135",
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "MRG_I2S_PCM_TX"),
+ MTK_FUNCTION_IRQ(2, "EINT17", 17),
+ MTK_FUNCTION(3, "I2SOUT_DAT"),
+ MTK_FUNCTION(4, "PCM0_DO"),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, "VDEC_TEST_CK"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(190, "SRCLKENAI"),
+ "K5", "mt8135",
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "SRCLKENAI"),
+ MTK_FUNCTION(2, NULL),
+ MTK_FUNCTION(3, NULL),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, NULL),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(191, "URXD3"),
+ "C3", "mt8135",
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "URXD3"),
+ MTK_FUNCTION_IRQ(2, "EINT87", 87),
+ MTK_FUNCTION(3, "UTXD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUX_ST"),
+ MTK_FUNCTION(6, "PWM4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(192, "UTXD3"),
+ "B2", "mt8135",
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "UTXD3"),
+ MTK_FUNCTION_IRQ(2, "EINT86", 86),
+ MTK_FUNCTION(3, "URXD3"),
+ MTK_FUNCTION(4, NULL),
+ MTK_FUNCTION(5, "TS_AUX_CS_B"),
+ MTK_FUNCTION(6, "PWM3"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(193, "SDA2"),
+ "G2", "mt8135",
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION_IRQ(2, "EINT95", 95),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "TS_AUX_PWDB"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(194, "SCL2"),
+ "F4", "mt8135",
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION_IRQ(2, "EINT94", 94),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "TS_AUXADC_TEST_CK"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(195, "SDA1"),
+ "F2", "mt8135",
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION_IRQ(2, "EINT93", 93),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(196, "SCL1"),
+ "F3", "mt8135",
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION_IRQ(2, "EINT92", 92),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "TS_AUX_DIN"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(197, "MSDC3_DAT2"),
+ "E1", "mt8135",
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "MSDC3_DAT2"),
+ MTK_FUNCTION_IRQ(2, "EINT71", 71),
+ MTK_FUNCTION(3, "SCL6"),
+ MTK_FUNCTION(4, "PWM5"),
+ MTK_FUNCTION(5, "CLKM4"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_2"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(198, "MSDC3_DAT3"),
+ "C2", "mt8135",
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "MSDC3_DAT3"),
+ MTK_FUNCTION_IRQ(2, "EINT72", 72),
+ MTK_FUNCTION(3, "SDA6"),
+ MTK_FUNCTION(4, "PWM6"),
+ MTK_FUNCTION(5, "CLKM5"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_3"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(199, "MSDC3_CMD"),
+ "D2", "mt8135",
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "MSDC3_CMD"),
+ MTK_FUNCTION_IRQ(2, "EINT68", 68),
+ MTK_FUNCTION(3, "SDA2"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(5, "CLKM1"),
+ MTK_FUNCTION(6, "MFG_TEST_CK_4"),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(200, "MSDC3_CLK"),
+ "E2", "mt8135",
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "MSDC3_CLK"),
+ MTK_FUNCTION_IRQ(2, "EINT67", 67),
+ MTK_FUNCTION(3, "SCL2"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(201, "MSDC3_DAT1"),
+ "D3", "mt8135",
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "MSDC3_DAT1"),
+ MTK_FUNCTION_IRQ(2, "EINT70", 70),
+ MTK_FUNCTION(3, "SDA3"),
+ MTK_FUNCTION(4, "PWM4"),
+ MTK_FUNCTION(5, "CLKM3"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+ MTK_PIN(
+ PINCTRL_PIN(202, "MSDC3_DAT0"),
+ "E3", "mt8135",
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "MSDC3_DAT0"),
+ MTK_FUNCTION_IRQ(2, "EINT69", 69),
+ MTK_FUNCTION(3, "SCL3"),
+ MTK_FUNCTION(4, "PWM3"),
+ MTK_FUNCTION(5, "CLKM2"),
+ MTK_FUNCTION(6, NULL),
+ MTK_FUNCTION(7, NULL)
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT8135_H */
diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h
new file mode 100644
index 0000000..4b5cefb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt65xx.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
+#define _DT_BINDINGS_PINCTRL_MT65XX_H
+
+#define MTK_PIN_NO(x) ((x) << 8)
+#define MTK_GET_PIN_NO(x) ((x) >> 8)
+#define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
+
+
+#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2014-11-11 12:38 ` Hongzhou Yang
@ 2014-11-11 12:38 ` Hongzhou Yang
-1 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Matthias Brugger
Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King,
Heiko St�bner, Pawel Moll, Ian Campbell, Hongzhou Yang,
Catalin Marinas, dandan.he, linux-kernel, alan.cheng,
Ashwin Chaugule, toby.liu, Sascha Hauer, Kumar Gala,
Grant Likely, Joe.C, eddie.huang, linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
Add devicetree bindings for Mediatek SoC pinctrl driver.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +++++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
new file mode 100644
index 0000000..70f35b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -0,0 +1,123 @@
+* Mediatek MT65XX Pin Controller
+
+The Mediatek's Pin controller is used to control GPIO pins.
+
+Required properties:
+- compatible: value should be either of the following.
+ (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
+- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ Eg: <&pio 6 0>
+ <[phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [flags]>
+
+ Values for gpio specifier:
+ - Pin number: is a value between 0 to 202.
+ - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
+ Only the following flags are supported:
+ 0 - GPIO_ACTIVE_HIGH
+ 1 - GPIO_ACTIVE_LOW
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+A pinctrl node should contain at least one subnodes representing the
+pinctrl groups available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive strngth, input enable/disable and input schmitt.
+
+Required subnode-properties:
+
+- mediatek,pins: 2 integers array, represents gpio pinmux number and config
+ setting. The format as following
+
+ node {
+ mediatek,pins = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+ The PIN_NUMBER_PINMUX is combination of GPIO number and pinmux, it can
+ use macros which already defind in boot/dts/mt8135-pinfunc.h directly.
+ The GENERIC_PINCONFIG is the generic pinconfig options to use, bias-disable,
+ bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
+ input-schmitt-enable and input-schmitt-disable are valid.
+
+Examples:
+
+#include "mt8135-pinfunc.h"
+
+...
+{
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ syscfg_pctl_b: syscfg_pctl_b@1020C020 {
+ compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
+ reg = <0 0x1020C020 0 0x1000>;
+ };
+
+ pinctrl@01c20800 {
+ compatible = "mediatek,mt8135-pinctrl";
+ mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ i2c0_pins_a: i2c0@0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
+ <MT8135_PIN_101_SCL0__FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins {
+ mediatek,pins = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
+ <MT8135_PIN_196_SCL1__FUNC_SCL1>;
+ bias-pull-up = <55>;
+ };
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
+ bias-pull-down;
+ };
+
+ pins2 {
+ mediatek,pins = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
+ bias-pull-up;
+ };
+ };
+
+ i2c3_pins_a: i2c3@0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
+ <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
+ bias-pull-up = <55>;
+ };
+
+ pins2 {
+ mediatek,pins = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
+ <MT8135_PIN_36_SDA3__FUNC_SDA3>;
+ output-low;
+ bias-pull-up = <55>;
+ };
+
+ pins3 {
+ mediatek,pins = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
+ <MT8135_PIN_60_JTDI__FUNC_JTDI>;
+ drive-strength = <32>;
+ };
+ };
+
+ ...
+ }
+};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-11 12:38 ` Hongzhou Yang
0 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
Add devicetree bindings for Mediatek SoC pinctrl driver.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +++++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
new file mode 100644
index 0000000..70f35b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -0,0 +1,123 @@
+* Mediatek MT65XX Pin Controller
+
+The Mediatek's Pin controller is used to control GPIO pins.
+
+Required properties:
+- compatible: value should be either of the following.
+ (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
+- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ Eg: <&pio 6 0>
+ <[phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [flags]>
+
+ Values for gpio specifier:
+ - Pin number: is a value between 0 to 202.
+ - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
+ Only the following flags are supported:
+ 0 - GPIO_ACTIVE_HIGH
+ 1 - GPIO_ACTIVE_LOW
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+A pinctrl node should contain at least one subnodes representing the
+pinctrl groups available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive strngth, input enable/disable and input schmitt.
+
+Required subnode-properties:
+
+- mediatek,pins: 2 integers array, represents gpio pinmux number and config
+ setting. The format as following
+
+ node {
+ mediatek,pins = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+ The PIN_NUMBER_PINMUX is combination of GPIO number and pinmux, it can
+ use macros which already defind in boot/dts/mt8135-pinfunc.h directly.
+ The GENERIC_PINCONFIG is the generic pinconfig options to use, bias-disable,
+ bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
+ input-schmitt-enable and input-schmitt-disable are valid.
+
+Examples:
+
+#include "mt8135-pinfunc.h"
+
+...
+{
+ syscfg_pctl_a: syscfg_pctl_a at 10005000 {
+ compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ syscfg_pctl_b: syscfg_pctl_b at 1020C020 {
+ compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
+ reg = <0 0x1020C020 0 0x1000>;
+ };
+
+ pinctrl at 01c20800 {
+ compatible = "mediatek,mt8135-pinctrl";
+ mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ i2c0_pins_a: i2c0 at 0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
+ <MT8135_PIN_101_SCL0__FUNC_SCL0>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1 at 0 {
+ pins {
+ mediatek,pins = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
+ <MT8135_PIN_196_SCL1__FUNC_SCL1>;
+ bias-pull-up = <55>;
+ };
+ };
+
+ i2c2_pins_a: i2c2 at 0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
+ bias-pull-down;
+ };
+
+ pins2 {
+ mediatek,pins = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
+ bias-pull-up;
+ };
+ };
+
+ i2c3_pins_a: i2c3 at 0 {
+ pins1 {
+ mediatek,pins = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
+ <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
+ bias-pull-up = <55>;
+ };
+
+ pins2 {
+ mediatek,pins = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
+ <MT8135_PIN_36_SDA3__FUNC_SDA3>;
+ output-low;
+ bias-pull-up = <55>;
+ };
+
+ pins3 {
+ mediatek,pins = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
+ <MT8135_PIN_60_JTDI__FUNC_JTDI>;
+ drive-strength = <32>;
+ };
+ };
+
+ ...
+ }
+};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v3 3/3] ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
2014-11-11 12:38 ` Hongzhou Yang
@ 2014-11-11 12:38 ` Hongzhou Yang
-1 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: Rob Herring, Linus Walleij, Matthias Brugger
Cc: Mark Rutland, devicetree, Vladimir Murzin, Russell King,
Heiko St�bner, Pawel Moll, Ian Campbell, Hongzhou Yang,
Catalin Marinas, dandan.he, linux-kernel, alan.cheng,
Ashwin Chaugule, toby.liu, Sascha Hauer, Kumar Gala,
Grant Likely, Joe.C, eddie.huang, linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
Add pinctrl and GPIO node to mt8135.dtsi.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
arch/arm/boot/dts/mt8135-pinfunc.h | 1304 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt8135.dtsi | 19 +
2 files changed, 1323 insertions(+)
create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h
new file mode 100644
index 0000000..06269d1
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-pinfunc.h
@@ -0,0 +1,1304 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT8135_PINFUNC_H
+#define __DTS_MT8135_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7)
+
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7)
+
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7)
+
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7)
+
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7)
+
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7)
+
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7)
+
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7)
+
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7)
+
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6)
+
+#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1)
+#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2)
+#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7)
+
+#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1)
+#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2)
+#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6)
+#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7)
+
+#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1)
+#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2)
+#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3)
+#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7)
+
+#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1)
+#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2)
+#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3)
+#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4)
+#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6)
+#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7)
+
+#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1)
+#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2)
+#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3)
+#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4)
+#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5)
+#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6)
+#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7)
+
+#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1)
+#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2)
+#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3)
+#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4)
+#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5)
+#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7)
+
+#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1)
+#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2)
+#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3)
+#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4)
+#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5)
+#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7)
+
+#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1)
+#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2)
+#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3)
+#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4)
+#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5)
+#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6)
+#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7)
+
+#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1)
+#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2)
+#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3)
+#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4)
+#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5)
+#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6)
+#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7)
+
+#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1)
+#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2)
+#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3)
+#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4)
+#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5)
+#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6)
+#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7)
+
+#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1)
+#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2)
+#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3)
+#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4)
+#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7)
+
+#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1)
+#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2)
+#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3)
+#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4)
+#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7)
+
+#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1)
+#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2)
+#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3)
+#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4)
+#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7)
+
+#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1)
+#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2)
+#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3)
+#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4)
+#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7)
+
+#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1)
+#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2)
+#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3)
+#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4)
+#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7)
+
+#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1)
+#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2)
+#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4)
+
+#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1)
+#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2)
+#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4)
+#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5)
+
+#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1)
+#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2)
+#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4)
+#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5)
+
+#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1)
+#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2)
+#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4)
+#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5)
+
+#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1)
+#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2)
+#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3)
+#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4)
+#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5)
+
+#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1)
+#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2)
+#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3)
+#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4)
+#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5)
+
+#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1)
+#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2)
+#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3)
+#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4)
+#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5)
+
+#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1)
+#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2)
+#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3)
+#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4)
+#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5)
+
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7)
+
+#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1)
+#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2)
+
+#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1)
+#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2)
+#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3)
+#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4)
+
+#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1)
+#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2)
+
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7)
+
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7)
+
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7)
+
+#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1)
+#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2)
+#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3)
+#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5)
+#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7)
+
+#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1)
+#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2)
+#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3)
+#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5)
+#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7)
+
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7)
+
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2)
+
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2)
+
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2)
+
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2)
+
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7)
+
+#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1)
+
+#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1)
+#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2)
+
+#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1)
+#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2)
+
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2)
+
+#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1)
+#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2)
+#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3)
+#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4)
+#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5)
+#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7)
+
+#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1)
+#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2)
+#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4)
+#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5)
+#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7)
+
+#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1)
+#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2)
+#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4)
+#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5)
+#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7)
+
+#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1)
+#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2)
+#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5)
+#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7)
+
+#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1)
+#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2)
+#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5)
+#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7)
+
+#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1)
+#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2)
+#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3)
+
+#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1)
+#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2)
+#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3)
+
+#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1)
+#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2)
+#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3)
+
+#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1)
+#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2)
+#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3)
+
+#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1)
+#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2)
+#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3)
+
+#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1)
+#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2)
+#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3)
+
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_EINT57 (MTK_PIN_NO(63) | 2)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7)
+
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7)
+
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_EINT65 (MTK_PIN_NO(65) | 2)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7)
+
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5)
+
+#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1)
+#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2)
+#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3)
+#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6)
+#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7)
+
+#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1)
+#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3)
+#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6)
+#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7)
+
+#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1)
+#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2)
+#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3)
+#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6)
+#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7)
+
+#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1)
+#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3)
+#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6)
+#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7)
+
+#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1)
+#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2)
+#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5)
+#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6)
+#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7)
+
+#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1)
+#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2)
+#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5)
+#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6)
+#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7)
+
+#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1)
+#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2)
+#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5)
+#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6)
+#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7)
+
+#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1)
+#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2)
+#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3)
+#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4)
+#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5)
+#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6)
+#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7)
+
+#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1)
+#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2)
+#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3)
+#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4)
+#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5)
+#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6)
+#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7)
+
+#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1)
+#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2)
+#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3)
+#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4)
+#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6)
+#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7)
+
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7)
+
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7)
+
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7)
+
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7)
+
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6)
+
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6)
+
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7)
+
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7)
+
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7)
+
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7)
+
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7)
+
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7)
+
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7)
+
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7)
+
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7)
+
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7)
+
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7)
+
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7)
+
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7)
+
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7)
+
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7)
+
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7)
+
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7)
+
+#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
+#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2)
+#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3)
+#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4)
+#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7)
+
+#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1)
+#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2)
+#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3)
+#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4)
+#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7)
+
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7)
+
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7)
+
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7)
+
+#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1)
+#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2)
+#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3)
+#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4)
+#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5)
+#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6)
+#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7)
+
+#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1)
+#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2)
+#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3)
+#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4)
+#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5)
+#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6)
+#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7)
+
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7)
+
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7)
+
+#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1)
+#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2)
+#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3)
+#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4)
+#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5)
+#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6)
+#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7)
+
+#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1)
+#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2)
+#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3)
+#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4)
+#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5)
+#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6)
+#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7)
+
+#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1)
+#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2)
+#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3)
+#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4)
+#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5)
+#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6)
+#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7)
+
+#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1)
+#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2)
+#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3)
+#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4)
+#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5)
+#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6)
+#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7)
+
+#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1)
+#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4)
+#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5)
+#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6)
+#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7)
+
+#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1)
+#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2)
+#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5)
+#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6)
+#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7)
+
+#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1)
+#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2)
+#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5)
+#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6)
+#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7)
+
+#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1)
+#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2)
+#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7)
+
+#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1)
+#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2)
+#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3)
+#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5)
+#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7)
+
+#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1)
+#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2)
+#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3)
+#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5)
+#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6)
+#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7)
+
+#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1)
+#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5)
+#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6)
+#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7)
+
+#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1)
+#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2)
+#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5)
+#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7)
+
+#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1)
+#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2)
+#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3)
+#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4)
+#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5)
+#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6)
+
+#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1)
+#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2)
+#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3)
+#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5)
+#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6)
+
+#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1)
+#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2)
+#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4)
+#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5)
+
+#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1)
+#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2)
+#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4)
+#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5)
+
+#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1)
+#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2)
+#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4)
+
+#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1)
+#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2)
+#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5)
+
+#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5)
+
+#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6)
+
+#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1)
+#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2)
+#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4)
+#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5)
+
+#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1)
+#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2)
+#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3)
+#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4)
+#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5)
+
+#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1)
+#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2)
+#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3)
+#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4)
+#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5)
+
+#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1)
+#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2)
+#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3)
+#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4)
+#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5)
+
+#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1)
+#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2)
+#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3)
+#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4)
+#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5)
+
+#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1)
+#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2)
+#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3)
+#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4)
+#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5)
+
+#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1)
+#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2)
+#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3)
+#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4)
+#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5)
+
+#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1)
+#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2)
+#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3)
+#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4)
+#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5)
+
+#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1)
+#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2)
+#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5)
+
+#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1)
+#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2)
+#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5)
+
+#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1)
+#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2)
+#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5)
+
+#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1)
+#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2)
+#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4)
+
+#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1)
+#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2)
+#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4)
+
+#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1)
+#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2)
+#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4)
+
+#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1)
+#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2)
+#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4)
+
+#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1)
+#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2)
+#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4)
+
+#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1)
+#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2)
+#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4)
+
+#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1)
+#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2)
+#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4)
+
+#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1)
+#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2)
+#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4)
+
+#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1)
+#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2)
+#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4)
+
+#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2)
+
+#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2)
+
+#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2)
+
+#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2)
+
+#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2)
+
+#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2)
+
+#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2)
+
+#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2)
+
+#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2)
+
+#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2)
+
+#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2)
+
+#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2)
+
+#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2)
+
+#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2)
+
+#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2)
+
+#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2)
+
+#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+
+#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+
+#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+
+#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+
+#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1)
+#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2)
+
+#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1)
+#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2)
+
+#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1)
+#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2)
+
+#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1)
+#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2)
+
+#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1)
+#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2)
+
+#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1)
+#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2)
+
+#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1)
+#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3)
+
+#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1)
+#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3)
+
+#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1)
+#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2)
+
+#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1)
+#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2)
+
+#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1)
+#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3)
+
+#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1)
+#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3)
+
+#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1)
+#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3)
+#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4)
+#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5)
+#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6)
+#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7)
+
+#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1)
+#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2)
+#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5)
+#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7)
+
+#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1)
+#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2)
+#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5)
+#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7)
+
+#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1)
+#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2)
+#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5)
+#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7)
+
+#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1)
+#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2)
+#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3)
+#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6)
+#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7)
+
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7)
+
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6)
+
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7)
+
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6)
+
+#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1)
+
+#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1)
+#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2)
+#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3)
+#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5)
+#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6)
+
+#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1)
+#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2)
+#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3)
+#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5)
+#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6)
+
+#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1)
+#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2)
+#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3)
+#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4)
+#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5)
+
+#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1)
+#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2)
+#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3)
+#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4)
+#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5)
+
+#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1)
+#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2)
+#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3)
+#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4)
+#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5)
+
+#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1)
+#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2)
+#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3)
+#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4)
+#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5)
+
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6)
+
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6)
+
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6)
+
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5)
+
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5)
+
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5)
+
+#endif /* __DTS_MT8135_PINFUNC_H */
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..1362626 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
+#include "mt8135-pinfunc.h"
/ {
compatible = "mediatek,mt8135";
@@ -94,6 +95,16 @@
compatible = "simple-bus";
ranges;
+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ syscfg_pctl_b: syscfg_pctl_b@1020C020 {
+ compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
+ reg = <0 0x1020C020 0 0x1000>;
+ };
+
timer: timer@10008000 {
compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
@@ -111,5 +122,13 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8135-pinctrl";
+ mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
};
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v3 3/3] ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
@ 2014-11-11 12:38 ` Hongzhou Yang
0 siblings, 0 replies; 59+ messages in thread
From: Hongzhou Yang @ 2014-11-11 12:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Hongzhou Yang <hongzhou.yang@mediatek.com>
Add pinctrl and GPIO node to mt8135.dtsi.
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
---
arch/arm/boot/dts/mt8135-pinfunc.h | 1304 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt8135.dtsi | 19 +
2 files changed, 1323 insertions(+)
create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
diff --git a/arch/arm/boot/dts/mt8135-pinfunc.h b/arch/arm/boot/dts/mt8135-pinfunc.h
new file mode 100644
index 0000000..06269d1
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-pinfunc.h
@@ -0,0 +1,1304 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT8135_PINFUNC_H
+#define __DTS_MT8135_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7)
+
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7)
+
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7)
+
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7)
+
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7)
+
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7)
+
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7)
+
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7)
+
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7)
+
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6)
+
+#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1)
+#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2)
+#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7)
+
+#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1)
+#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2)
+#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6)
+#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7)
+
+#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1)
+#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2)
+#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3)
+#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7)
+
+#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1)
+#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2)
+#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3)
+#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4)
+#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6)
+#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7)
+
+#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1)
+#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2)
+#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3)
+#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4)
+#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5)
+#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6)
+#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7)
+
+#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1)
+#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2)
+#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3)
+#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4)
+#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5)
+#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7)
+
+#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1)
+#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2)
+#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3)
+#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4)
+#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5)
+#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7)
+
+#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1)
+#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2)
+#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3)
+#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4)
+#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5)
+#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6)
+#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7)
+
+#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1)
+#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2)
+#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3)
+#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4)
+#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5)
+#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6)
+#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7)
+
+#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1)
+#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2)
+#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3)
+#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4)
+#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5)
+#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6)
+#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7)
+
+#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1)
+#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2)
+#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3)
+#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4)
+#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7)
+
+#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1)
+#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2)
+#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3)
+#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4)
+#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7)
+
+#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1)
+#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2)
+#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3)
+#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4)
+#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7)
+
+#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1)
+#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2)
+#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3)
+#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4)
+#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7)
+
+#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1)
+#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2)
+#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3)
+#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4)
+#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7)
+
+#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1)
+#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2)
+#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4)
+
+#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1)
+#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2)
+#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4)
+#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5)
+
+#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1)
+#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2)
+#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4)
+#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5)
+
+#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1)
+#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2)
+#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4)
+#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5)
+
+#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1)
+#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2)
+#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3)
+#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4)
+#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5)
+
+#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1)
+#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2)
+#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3)
+#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4)
+#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5)
+
+#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1)
+#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2)
+#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3)
+#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4)
+#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5)
+
+#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1)
+#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2)
+#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3)
+#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4)
+#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5)
+
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7)
+
+#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1)
+#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2)
+
+#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1)
+#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2)
+#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3)
+#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4)
+
+#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1)
+#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2)
+
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7)
+
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7)
+
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7)
+
+#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1)
+#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2)
+#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3)
+#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5)
+#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7)
+
+#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1)
+#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2)
+#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3)
+#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5)
+#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7)
+
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7)
+
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2)
+
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2)
+
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2)
+
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2)
+
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7)
+
+#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1)
+
+#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1)
+#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2)
+
+#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1)
+#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2)
+
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2)
+
+#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1)
+#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2)
+#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3)
+#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4)
+#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5)
+#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7)
+
+#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1)
+#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2)
+#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4)
+#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5)
+#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7)
+
+#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1)
+#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2)
+#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4)
+#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5)
+#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7)
+
+#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1)
+#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2)
+#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5)
+#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7)
+
+#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1)
+#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2)
+#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5)
+#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7)
+
+#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1)
+#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2)
+#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3)
+
+#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1)
+#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2)
+#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3)
+
+#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1)
+#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2)
+#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3)
+
+#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1)
+#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2)
+#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3)
+
+#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1)
+#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2)
+#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3)
+
+#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1)
+#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2)
+#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3)
+
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_EINT57 (MTK_PIN_NO(63) | 2)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7)
+
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7)
+
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_EINT65 (MTK_PIN_NO(65) | 2)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7)
+
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5)
+
+#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1)
+#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2)
+#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3)
+#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6)
+#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7)
+
+#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1)
+#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3)
+#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6)
+#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7)
+
+#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1)
+#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2)
+#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3)
+#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6)
+#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7)
+
+#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1)
+#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3)
+#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6)
+#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7)
+
+#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1)
+#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2)
+#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5)
+#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6)
+#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7)
+
+#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1)
+#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2)
+#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5)
+#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6)
+#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7)
+
+#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1)
+#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2)
+#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5)
+#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6)
+#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7)
+
+#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1)
+#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2)
+#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3)
+#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4)
+#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5)
+#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6)
+#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7)
+
+#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1)
+#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2)
+#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3)
+#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4)
+#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5)
+#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6)
+#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7)
+
+#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1)
+#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2)
+#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3)
+#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4)
+#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6)
+#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7)
+
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7)
+
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7)
+
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7)
+
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7)
+
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6)
+
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6)
+
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7)
+
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7)
+
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7)
+
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7)
+
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7)
+
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7)
+
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7)
+
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7)
+
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7)
+
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7)
+
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7)
+
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7)
+
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7)
+
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7)
+
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7)
+
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7)
+
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7)
+
+#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
+#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2)
+#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3)
+#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4)
+#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7)
+
+#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1)
+#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2)
+#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3)
+#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4)
+#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7)
+
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7)
+
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7)
+
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7)
+
+#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1)
+#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2)
+#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3)
+#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4)
+#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5)
+#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6)
+#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7)
+
+#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1)
+#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2)
+#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3)
+#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4)
+#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5)
+#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6)
+#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7)
+
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7)
+
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7)
+
+#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1)
+#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2)
+#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3)
+#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4)
+#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5)
+#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6)
+#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7)
+
+#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1)
+#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2)
+#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3)
+#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4)
+#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5)
+#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6)
+#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7)
+
+#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1)
+#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2)
+#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3)
+#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4)
+#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5)
+#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6)
+#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7)
+
+#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1)
+#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2)
+#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3)
+#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4)
+#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5)
+#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6)
+#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7)
+
+#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1)
+#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4)
+#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5)
+#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6)
+#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7)
+
+#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1)
+#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2)
+#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5)
+#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6)
+#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7)
+
+#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1)
+#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2)
+#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5)
+#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6)
+#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7)
+
+#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1)
+#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2)
+#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7)
+
+#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1)
+#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2)
+#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3)
+#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5)
+#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7)
+
+#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1)
+#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2)
+#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3)
+#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5)
+#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6)
+#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7)
+
+#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1)
+#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5)
+#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6)
+#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7)
+
+#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1)
+#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2)
+#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5)
+#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7)
+
+#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1)
+#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2)
+#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3)
+#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4)
+#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5)
+#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6)
+
+#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1)
+#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2)
+#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3)
+#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5)
+#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6)
+
+#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1)
+#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2)
+#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4)
+#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5)
+
+#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1)
+#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2)
+#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4)
+#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5)
+
+#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1)
+#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2)
+#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4)
+
+#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1)
+#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2)
+#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5)
+
+#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5)
+
+#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6)
+
+#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1)
+#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2)
+#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4)
+#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5)
+
+#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1)
+#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2)
+#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3)
+#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4)
+#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5)
+
+#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1)
+#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2)
+#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3)
+#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4)
+#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5)
+
+#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1)
+#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2)
+#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3)
+#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4)
+#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5)
+
+#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1)
+#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2)
+#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3)
+#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4)
+#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5)
+
+#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1)
+#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2)
+#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3)
+#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4)
+#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5)
+
+#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1)
+#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2)
+#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3)
+#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4)
+#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5)
+
+#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1)
+#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2)
+#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3)
+#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4)
+#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5)
+
+#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1)
+#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2)
+#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5)
+
+#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1)
+#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2)
+#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5)
+
+#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1)
+#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2)
+#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5)
+
+#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1)
+#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2)
+#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4)
+
+#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1)
+#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2)
+#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4)
+
+#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1)
+#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2)
+#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4)
+
+#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1)
+#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2)
+#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4)
+
+#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1)
+#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2)
+#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4)
+
+#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1)
+#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2)
+#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4)
+
+#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1)
+#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2)
+#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4)
+
+#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1)
+#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2)
+#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4)
+
+#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1)
+#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2)
+#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4)
+
+#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2)
+
+#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2)
+
+#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2)
+
+#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2)
+
+#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2)
+
+#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2)
+
+#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2)
+
+#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2)
+
+#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2)
+
+#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2)
+
+#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2)
+
+#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2)
+
+#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2)
+
+#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2)
+
+#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2)
+
+#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2)
+
+#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+
+#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+
+#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+
+#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+
+#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1)
+#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2)
+
+#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1)
+#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2)
+
+#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1)
+#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2)
+
+#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1)
+#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2)
+
+#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1)
+#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2)
+
+#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1)
+#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2)
+
+#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1)
+#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3)
+
+#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1)
+#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3)
+
+#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1)
+#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2)
+
+#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1)
+#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2)
+
+#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1)
+#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3)
+
+#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1)
+#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3)
+
+#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1)
+#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3)
+#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4)
+#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5)
+#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6)
+#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7)
+
+#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1)
+#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2)
+#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5)
+#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7)
+
+#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1)
+#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2)
+#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5)
+#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7)
+
+#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1)
+#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2)
+#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5)
+#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7)
+
+#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1)
+#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2)
+#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3)
+#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6)
+#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7)
+
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7)
+
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6)
+
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7)
+
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6)
+
+#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1)
+
+#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1)
+#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2)
+#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3)
+#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5)
+#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6)
+
+#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1)
+#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2)
+#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3)
+#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5)
+#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6)
+
+#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1)
+#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2)
+#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3)
+#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4)
+#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5)
+
+#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1)
+#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2)
+#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3)
+#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4)
+#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5)
+
+#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1)
+#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2)
+#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3)
+#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4)
+#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5)
+
+#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1)
+#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2)
+#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3)
+#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4)
+#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5)
+
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6)
+
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6)
+
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6)
+
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5)
+
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5)
+
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5)
+
+#endif /* __DTS_MT8135_PINFUNC_H */
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..1362626 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
+#include "mt8135-pinfunc.h"
/ {
compatible = "mediatek,mt8135";
@@ -94,6 +95,16 @@
compatible = "simple-bus";
ranges;
+ syscfg_pctl_a: syscfg_pctl_a at 10005000 {
+ compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ syscfg_pctl_b: syscfg_pctl_b at 1020C020 {
+ compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
+ reg = <0 0x1020C020 0 0x1000>;
+ };
+
timer: timer at 10008000 {
compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
@@ -111,5 +122,13 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ pio: pinctrl at 10005000 {
+ compatible = "mediatek,mt8135-pinctrl";
+ mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
};
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135.
2014-11-11 12:38 ` Hongzhou Yang
@ 2014-11-18 16:24 ` Sascha Hauer
-1 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-11-18 16:24 UTC (permalink / raw)
To: Linus Walleij
Cc: Hongzhou Yang, Rob Herring, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko St�bner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, eddie.huang, dandan.he, alan.cheng, toby.liu
Hi Linus,
Is this driver generally ok? It basically implements the binding
suggested as RFC (except that mediatek,pins should only be pins).
Are you Ok with this approach? Anything else missing?
Sascha
On Tue, Nov 11, 2014 at 08:38:52PM +0800, Hongzhou Yang wrote:
> This is v3 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135.
> It is based on Joe.C' basic device tree support.
> See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296093.html
>
> This driver include common and MT8135 part, other Mediatek SoCs will share the common part,
> and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins.
>
> Changes in v3:
> - Rebase on 3.18-rc1.
> - Follow '[RFC] pinctrl: Provide a generic device tree binding for per-pin pin controllers', modify mediatek,pins format,
> add config setting for each pin, the reason is that each pin may have different config.
> The RFC link: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296491.html
> - Switch to use syscon regmap.
> - Add CLR_ADDR() and SET_ADDR() macros.
> - Add mtk_pconf_set_ies() and mtk_pconf_set_smt() functions to deal with input-enable and input-schmitt-enable.
> - Rename mt_gpio_devdata to mtk_pinctrl_devdata.
> - Rename all mt_prefix to mtk_prefix.
> - Rename mt_pconf_pull_conf() to mtk_pconf_parse_conf, add mtk_pconf_set_pull_select() to deal with pull enable and pull up/down.
> And we will add PIN_CONFIG_DRIVE_STRENGTH to mtk_pconf_parse_conf().
>
> According to Linus' suggestion, make some following changes:
> - Add port_shf, port_mask and port_align members to mtk_pinctrl_devdata struct.
> - Use BIT(x) instead of 1 << (x).
> - Remove mt_pctrl_write_reg() and mt_pctrl_read_reg().
> - Remove mt_gpio_of_xlate().
> - Use .set_mux() instead of .enable().
> - Add some comments.
>
> Hongzhou Yang (3):
> ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
> dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
> ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
>
> .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +
> arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++
> arch/arm/boot/dts/mt8135.dtsi | 19 +
> arch/arm/mach-mediatek/Kconfig | 1 +
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/mediatek/Kconfig | 12 +
> drivers/pinctrl/mediatek/Makefile | 5 +
> drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
> drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++
> drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 +
> drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++
> include/dt-bindings/pinctrl/mt65xx.h | 23 +
> 13 files changed, 5020 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
> create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
> create mode 100644 drivers/pinctrl/mediatek/Kconfig
> create mode 100644 drivers/pinctrl/mediatek/Makefile
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
> create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
>
> --
> 1.8.1.1.dirty
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135.
@ 2014-11-18 16:24 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-11-18 16:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
Is this driver generally ok? It basically implements the binding
suggested as RFC (except that mediatek,pins should only be pins).
Are you Ok with this approach? Anything else missing?
Sascha
On Tue, Nov 11, 2014 at 08:38:52PM +0800, Hongzhou Yang wrote:
> This is v3 of add Mediatek SoC Pinctrl/GPIO drvier for MT8135.
> It is based on Joe.C' basic device tree support.
> See http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296093.html
>
> This driver include common and MT8135 part, other Mediatek SoCs will share the common part,
> and MT8135 part only support MT8135. MT8135 has GPIO controller, it includes 203 pins.
>
> Changes in v3:
> - Rebase on 3.18-rc1.
> - Follow '[RFC] pinctrl: Provide a generic device tree binding for per-pin pin controllers', modify mediatek,pins format,
> add config setting for each pin, the reason is that each pin may have different config.
> The RFC link: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296491.html
> - Switch to use syscon regmap.
> - Add CLR_ADDR() and SET_ADDR() macros.
> - Add mtk_pconf_set_ies() and mtk_pconf_set_smt() functions to deal with input-enable and input-schmitt-enable.
> - Rename mt_gpio_devdata to mtk_pinctrl_devdata.
> - Rename all mt_prefix to mtk_prefix.
> - Rename mt_pconf_pull_conf() to mtk_pconf_parse_conf, add mtk_pconf_set_pull_select() to deal with pull enable and pull up/down.
> And we will add PIN_CONFIG_DRIVE_STRENGTH to mtk_pconf_parse_conf().
>
> According to Linus' suggestion, make some following changes:
> - Add port_shf, port_mask and port_align members to mtk_pinctrl_devdata struct.
> - Use BIT(x) instead of 1 << (x).
> - Remove mt_pctrl_write_reg() and mt_pctrl_read_reg().
> - Remove mt_gpio_of_xlate().
> - Use .set_mux() instead of .enable().
> - Add some comments.
>
> Hongzhou Yang (3):
> ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
> dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
> ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135.
>
> .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 123 +
> arch/arm/boot/dts/mt8135-pinfunc.h | 1304 +++++++++++
> arch/arm/boot/dts/mt8135.dtsi | 19 +
> arch/arm/mach-mediatek/Kconfig | 1 +
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/mediatek/Kconfig | 12 +
> drivers/pinctrl/mediatek/Makefile | 5 +
> drivers/pinctrl/mediatek/pinctrl-mt8135.c | 87 +
> drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 861 +++++++
> drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 123 +
> drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h | 2460 ++++++++++++++++++++
> include/dt-bindings/pinctrl/mt65xx.h | 23 +
> 13 files changed, 5020 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
> create mode 100644 arch/arm/boot/dts/mt8135-pinfunc.h
> create mode 100644 drivers/pinctrl/mediatek/Kconfig
> create mode 100644 drivers/pinctrl/mediatek/Makefile
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8135.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
> create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
>
> --
> 1.8.1.1.dirty
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 8:44 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 8:44 UTC (permalink / raw)
To: Hongzhou Yang
Cc: Rob Herring, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang@mediatek.com> wrote:
> +* Mediatek MT65XX Pin Controller
> +
> +The Mediatek's Pin controller is used to control GPIO pins.
It's not GPIO pins, since they are not always general purpose. It's just
pins. Say "control SoC pins".
> +Required properties:
> +- compatible: value should be either of the following.
> + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> +- gpio-controller : Marks the device node as a gpio controller.
> +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> + binding is used, the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> +
> + Eg: <&pio 6 0>
> + <[phandle of the gpio controller node]
> + [pin number within the gpio controller]
It's not a pin number really, it is a GPIO offset. But incidentally it's
the same as the pin number. (This is OK...)
> +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> + setting. The format as following
> +
> + node {
> + mediatek,pins = <PIN_NUMBER_PINMUX>;
> + GENERIC_PINCONFIG;
> + };
As suggested by Sacha, use just "pins" and define the binding as a patch
to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
that is generic for multiplexing, so we get some order here.
I want you however to put pin multiplexing and pin configuration into
different nodes if possible. I don't like combines muxing and config
nodes. If necessary tag the node with something.
In the end we can also move the parsing functions to the pinctrl core, as
long as the bindings are correct (possibly as a refactoring later).
> + i2c0_pins_a: i2c0@0 {
> + pins1 {
> + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> + bias-disable;
> + };
> + };
I would split it up.
i2c0_pins_a: i2c0@0 {
pins1 {
pins = <MT8135_PIN_100_SDA0>;
function = <MT8135_PIN_100_FUNC_SDA0>;
};
pins2 {
pins = <MT8135_PIN_100_SDA0>;
bias-disable;
};
};
One node for the multiplexing, one node for the config. This is the
pattern used by most drivers, so I want to have this structure.
It is also easy to tell one node from the other: if it contains "function"
we know it's a multiplexing node, if it doesn't, it's a config node.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 8:44 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 8:44 UTC (permalink / raw)
To: Hongzhou Yang
Cc: Rob Herring, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w,
alan.cheng-NuS5LvNUpcJWk0Htik3J/w,
toby.liu-NuS5LvNUpcJWk0Htik3J/w
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> +* Mediatek MT65XX Pin Controller
> +
> +The Mediatek's Pin controller is used to control GPIO pins.
It's not GPIO pins, since they are not always general purpose. It's just
pins. Say "control SoC pins".
> +Required properties:
> +- compatible: value should be either of the following.
> + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> +- gpio-controller : Marks the device node as a gpio controller.
> +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> + binding is used, the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> +
> + Eg: <&pio 6 0>
> + <[phandle of the gpio controller node]
> + [pin number within the gpio controller]
It's not a pin number really, it is a GPIO offset. But incidentally it's
the same as the pin number. (This is OK...)
> +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> + setting. The format as following
> +
> + node {
> + mediatek,pins = <PIN_NUMBER_PINMUX>;
> + GENERIC_PINCONFIG;
> + };
As suggested by Sacha, use just "pins" and define the binding as a patch
to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
that is generic for multiplexing, so we get some order here.
I want you however to put pin multiplexing and pin configuration into
different nodes if possible. I don't like combines muxing and config
nodes. If necessary tag the node with something.
In the end we can also move the parsing functions to the pinctrl core, as
long as the bindings are correct (possibly as a refactoring later).
> + i2c0_pins_a: i2c0@0 {
> + pins1 {
> + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> + bias-disable;
> + };
> + };
I would split it up.
i2c0_pins_a: i2c0@0 {
pins1 {
pins = <MT8135_PIN_100_SDA0>;
function = <MT8135_PIN_100_FUNC_SDA0>;
};
pins2 {
pins = <MT8135_PIN_100_SDA0>;
bias-disable;
};
};
One node for the multiplexing, one node for the config. This is the
pattern used by most drivers, so I want to have this structure.
It is also easy to tell one node from the other: if it contains "function"
we know it's a multiplexing node, if it doesn't, it's a config node.
Yours,
Linus Walleij
--
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 8:44 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 8:44 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang@mediatek.com> wrote:
> +* Mediatek MT65XX Pin Controller
> +
> +The Mediatek's Pin controller is used to control GPIO pins.
It's not GPIO pins, since they are not always general purpose. It's just
pins. Say "control SoC pins".
> +Required properties:
> +- compatible: value should be either of the following.
> + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> +- gpio-controller : Marks the device node as a gpio controller.
> +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> + binding is used, the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> +
> + Eg: <&pio 6 0>
> + <[phandle of the gpio controller node]
> + [pin number within the gpio controller]
It's not a pin number really, it is a GPIO offset. But incidentally it's
the same as the pin number. (This is OK...)
> +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> + setting. The format as following
> +
> + node {
> + mediatek,pins = <PIN_NUMBER_PINMUX>;
> + GENERIC_PINCONFIG;
> + };
As suggested by Sacha, use just "pins" and define the binding as a patch
to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
that is generic for multiplexing, so we get some order here.
I want you however to put pin multiplexing and pin configuration into
different nodes if possible. I don't like combines muxing and config
nodes. If necessary tag the node with something.
In the end we can also move the parsing functions to the pinctrl core, as
long as the bindings are correct (possibly as a refactoring later).
> + i2c0_pins_a: i2c0 at 0 {
> + pins1 {
> + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> + bias-disable;
> + };
> + };
I would split it up.
i2c0_pins_a: i2c0 at 0 {
pins1 {
pins = <MT8135_PIN_100_SDA0>;
function = <MT8135_PIN_100_FUNC_SDA0>;
};
pins2 {
pins = <MT8135_PIN_100_SDA0>;
bias-disable;
};
};
One node for the multiplexing, one node for the config. This is the
pattern used by most drivers, so I want to have this structure.
It is also easy to tell one node from the other: if it contains "function"
we know it's a multiplexing node, if it doesn't, it's a config node.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
@ 2014-11-27 9:14 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 9:14 UTC (permalink / raw)
To: Hongzhou Yang
Cc: Rob Herring, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang@mediatek.com> wrote:
> From: Hongzhou Yang <hongzhou.yang@mediatek.com>
>
> The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
>
> The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
>
> This driver include common driver and mt8135 part.
> The common driver include the pinctrl driver and GPIO driver.
> The mt8135 part contain its special device data.
>
> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
(...)
> menuconfig ARCH_MEDIATEK
> bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> select ARM_GIC
> + select PINCTRL
Should it not also select PINCTRL_MTK8135 for the right SoC?
(...)
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -0,0 +1,12 @@
> +if ARCH_MEDIATEK
> +
> +config PINCTRL_MTK_COMMON
> + bool
> + select PINMUX
> + select GENERIC_PINCONF
This is also a GPIO driver but it fails to select GPIOLIB,
OF_GPIO and also possibly GPIOLIB_IRQCHIP.
(...)
> +static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
> + unsigned long *configs, unsigned num_configs,
> + struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps)
> +{
> + struct mtk_pinctrl_group *grp;
> + unsigned long *cfgs;
> +
> + if (*num_maps == *cnt_maps)
> + return -ENOSPC;
> +
> + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
> + GFP_KERNEL);
> + if (cfgs == NULL)
> + return -ENOMEM;
> +
> + grp = mtk_pctrl_find_group_by_pin(pctl, pin);
> + if (!grp) {
> + dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
> + return -EINVAL;
> + }
> +
> + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
> + (*map)[*num_maps].data.configs.group_or_pin = grp->name;
> + (*map)[*num_maps].data.configs.configs = cfgs;
> + (*map)[*num_maps].data.configs.num_configs = num_configs;
> + (*num_maps)++;
> +
> + return 0;
> +}
Can't this use pinctrl_utils_add_map_configs()?
> +static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map,
> + unsigned num_maps)
> +{
> + int i;
> +
> + for (i = 0; i < num_maps; i++) {
> + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
> + kfree(map[i].data.configs.configs);
> + }
> +
> + kfree(map);
> +}
Use pinctrl_utils_dt_free_map() instead.
> +static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps, unsigned cnt)
> +{
> + unsigned old_num = *cnt_maps;
> + unsigned new_num = *num_maps + cnt;
> + struct pinctrl_map *new_map;
> +
> + if (old_num >= new_num)
> + return 0;
> +
> + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
> + if (!new_map)
> + return -ENOMEM;
> +
> + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
> +
> + *map = new_map;
> + *cnt_maps = new_num;
> +
> + return 0;
> +}
Use pinctrl_utils_reserve_map() instead.
> +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> + struct device_node *node,
> + struct pinctrl_map **map,
> + unsigned *num_maps, unsigned *cnt_maps)
> +{
> + struct property *pins;
> + u32 pinfunc, pin, func;
> + int num_pins, num_funcs, maps_per_pin;
> + unsigned long *configs;
> + unsigned int num_configs;
> + bool has_config = 0;
> + int i, err;
> + unsigned cnt = 0;
> + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
> +
> + pins = of_find_property(node, "mediatek,pins", NULL);
> + if (!pins) {
> + dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
> + node->name);
> + return -EINVAL;
> + }
> +
> + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
> + if (num_configs)
> + has_config = 1;
I'd prefer we first identify if it's a config or mux subnode, then go on to
parse it as mux or config. See comments on patch 2/3.
> +
> + num_pins = pins->length / sizeof(u32);
> + num_funcs = num_pins;
> + maps_per_pin = 0;
> + if (num_funcs)
> + maps_per_pin++;
> + if (has_config && num_pins >= 1)
> + maps_per_pin++;
> +
> + if (!num_pins || !maps_per_pin)
> + return -EINVAL;
> +
> + cnt = num_pins * maps_per_pin;
> +
> + err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
> + if (err < 0)
> + goto fail;
> +
> + for (i = 0; i < num_pins; i++) {
> + err = of_property_read_u32_index(node, "mediatek,pins",
> + i, &pinfunc);
As mentioned use just "pins" and let's figure out how to handle
this in a generic way.
> +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
> +{
> + return pinctrl_request_gpio(chip->base + offset);
> +}
> +
> +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
> +{
> + pinctrl_free_gpio(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_input(struct gpio_chip *chip,
> + unsigned offset)
> +{
> + return pinctrl_gpio_direction_input(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_output(struct gpio_chip *chip,
> + unsigned offset, int value)
> +{
> + mtk_gpio_set(chip, offset, value);
> + return pinctrl_gpio_direction_output(chip->base + offset);
> +}
This is kinda nice!
> +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> +{
> + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> + struct mtk_pinctrl_group *g = pctl->groups + offset;
> + struct mtk_desc_function *desc =
> + mtk_pctrl_desc_find_irq_function_from_name(
> + pctl, g->name);
> + if (!desc)
> + return -EINVAL;
> +
> + return desc->irqnum;
> +}
I don't quite get this still. Does this mean every single GPIO line
potentially has it's own unique IRQ line?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
@ 2014-11-27 9:14 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 9:14 UTC (permalink / raw)
To: Hongzhou Yang
Cc: Rob Herring, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w,
alan.cheng-NuS5LvNUpcJWk0Htik3J/w,
toby.liu-NuS5LvNUpcJWk0Htik3J/w
()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> From: Hongzhou Yang <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
>
> The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
>
> This driver include common driver and mt8135 part.
> The common driver include the pinctrl driver and GPIO driver.
> The mt8135 part contain its special device data.
>
> Signed-off-by: Hongzhou Yang <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
(...)
> menuconfig ARCH_MEDIATEK
> bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> select ARM_GIC
> + select PINCTRL
Should it not also select PINCTRL_MTK8135 for the right SoC?
(...)
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -0,0 +1,12 @@
> +if ARCH_MEDIATEK
> +
> +config PINCTRL_MTK_COMMON
> + bool
> + select PINMUX
> + select GENERIC_PINCONF
This is also a GPIO driver but it fails to select GPIOLIB,
OF_GPIO and also possibly GPIOLIB_IRQCHIP.
(...)
> +static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
> + unsigned long *configs, unsigned num_configs,
> + struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps)
> +{
> + struct mtk_pinctrl_group *grp;
> + unsigned long *cfgs;
> +
> + if (*num_maps == *cnt_maps)
> + return -ENOSPC;
> +
> + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
> + GFP_KERNEL);
> + if (cfgs == NULL)
> + return -ENOMEM;
> +
> + grp = mtk_pctrl_find_group_by_pin(pctl, pin);
> + if (!grp) {
> + dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
> + return -EINVAL;
> + }
> +
> + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
> + (*map)[*num_maps].data.configs.group_or_pin = grp->name;
> + (*map)[*num_maps].data.configs.configs = cfgs;
> + (*map)[*num_maps].data.configs.num_configs = num_configs;
> + (*num_maps)++;
> +
> + return 0;
> +}
Can't this use pinctrl_utils_add_map_configs()?
> +static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map,
> + unsigned num_maps)
> +{
> + int i;
> +
> + for (i = 0; i < num_maps; i++) {
> + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
> + kfree(map[i].data.configs.configs);
> + }
> +
> + kfree(map);
> +}
Use pinctrl_utils_dt_free_map() instead.
> +static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps, unsigned cnt)
> +{
> + unsigned old_num = *cnt_maps;
> + unsigned new_num = *num_maps + cnt;
> + struct pinctrl_map *new_map;
> +
> + if (old_num >= new_num)
> + return 0;
> +
> + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
> + if (!new_map)
> + return -ENOMEM;
> +
> + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
> +
> + *map = new_map;
> + *cnt_maps = new_num;
> +
> + return 0;
> +}
Use pinctrl_utils_reserve_map() instead.
> +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> + struct device_node *node,
> + struct pinctrl_map **map,
> + unsigned *num_maps, unsigned *cnt_maps)
> +{
> + struct property *pins;
> + u32 pinfunc, pin, func;
> + int num_pins, num_funcs, maps_per_pin;
> + unsigned long *configs;
> + unsigned int num_configs;
> + bool has_config = 0;
> + int i, err;
> + unsigned cnt = 0;
> + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
> +
> + pins = of_find_property(node, "mediatek,pins", NULL);
> + if (!pins) {
> + dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
> + node->name);
> + return -EINVAL;
> + }
> +
> + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
> + if (num_configs)
> + has_config = 1;
I'd prefer we first identify if it's a config or mux subnode, then go on to
parse it as mux or config. See comments on patch 2/3.
> +
> + num_pins = pins->length / sizeof(u32);
> + num_funcs = num_pins;
> + maps_per_pin = 0;
> + if (num_funcs)
> + maps_per_pin++;
> + if (has_config && num_pins >= 1)
> + maps_per_pin++;
> +
> + if (!num_pins || !maps_per_pin)
> + return -EINVAL;
> +
> + cnt = num_pins * maps_per_pin;
> +
> + err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
> + if (err < 0)
> + goto fail;
> +
> + for (i = 0; i < num_pins; i++) {
> + err = of_property_read_u32_index(node, "mediatek,pins",
> + i, &pinfunc);
As mentioned use just "pins" and let's figure out how to handle
this in a generic way.
> +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
> +{
> + return pinctrl_request_gpio(chip->base + offset);
> +}
> +
> +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
> +{
> + pinctrl_free_gpio(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_input(struct gpio_chip *chip,
> + unsigned offset)
> +{
> + return pinctrl_gpio_direction_input(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_output(struct gpio_chip *chip,
> + unsigned offset, int value)
> +{
> + mtk_gpio_set(chip, offset, value);
> + return pinctrl_gpio_direction_output(chip->base + offset);
> +}
This is kinda nice!
> +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> +{
> + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> + struct mtk_pinctrl_group *g = pctl->groups + offset;
> + struct mtk_desc_function *desc =
> + mtk_pctrl_desc_find_irq_function_from_name(
> + pctl, g->name);
> + if (!desc)
> + return -EINVAL;
> +
> + return desc->irqnum;
> +}
I don't quite get this still. Does this mean every single GPIO line
potentially has it's own unique IRQ line?
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
@ 2014-11-27 9:14 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-27 9:14 UTC (permalink / raw)
To: linux-arm-kernel
()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
<hongzhou.yang@mediatek.com> wrote:
> From: Hongzhou Yang <hongzhou.yang@mediatek.com>
>
> The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
>
> The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
>
> This driver include common driver and mt8135 part.
> The common driver include the pinctrl driver and GPIO driver.
> The mt8135 part contain its special device data.
>
> Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
(...)
> menuconfig ARCH_MEDIATEK
> bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> select ARM_GIC
> + select PINCTRL
Should it not also select PINCTRL_MTK8135 for the right SoC?
(...)
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -0,0 +1,12 @@
> +if ARCH_MEDIATEK
> +
> +config PINCTRL_MTK_COMMON
> + bool
> + select PINMUX
> + select GENERIC_PINCONF
This is also a GPIO driver but it fails to select GPIOLIB,
OF_GPIO and also possibly GPIOLIB_IRQCHIP.
(...)
> +static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
> + unsigned long *configs, unsigned num_configs,
> + struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps)
> +{
> + struct mtk_pinctrl_group *grp;
> + unsigned long *cfgs;
> +
> + if (*num_maps == *cnt_maps)
> + return -ENOSPC;
> +
> + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
> + GFP_KERNEL);
> + if (cfgs == NULL)
> + return -ENOMEM;
> +
> + grp = mtk_pctrl_find_group_by_pin(pctl, pin);
> + if (!grp) {
> + dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
> + return -EINVAL;
> + }
> +
> + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
> + (*map)[*num_maps].data.configs.group_or_pin = grp->name;
> + (*map)[*num_maps].data.configs.configs = cfgs;
> + (*map)[*num_maps].data.configs.num_configs = num_configs;
> + (*num_maps)++;
> +
> + return 0;
> +}
Can't this use pinctrl_utils_add_map_configs()?
> +static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map,
> + unsigned num_maps)
> +{
> + int i;
> +
> + for (i = 0; i < num_maps; i++) {
> + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
> + kfree(map[i].data.configs.configs);
> + }
> +
> + kfree(map);
> +}
Use pinctrl_utils_dt_free_map() instead.
> +static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
> + unsigned *num_maps, unsigned cnt)
> +{
> + unsigned old_num = *cnt_maps;
> + unsigned new_num = *num_maps + cnt;
> + struct pinctrl_map *new_map;
> +
> + if (old_num >= new_num)
> + return 0;
> +
> + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
> + if (!new_map)
> + return -ENOMEM;
> +
> + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
> +
> + *map = new_map;
> + *cnt_maps = new_num;
> +
> + return 0;
> +}
Use pinctrl_utils_reserve_map() instead.
> +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> + struct device_node *node,
> + struct pinctrl_map **map,
> + unsigned *num_maps, unsigned *cnt_maps)
> +{
> + struct property *pins;
> + u32 pinfunc, pin, func;
> + int num_pins, num_funcs, maps_per_pin;
> + unsigned long *configs;
> + unsigned int num_configs;
> + bool has_config = 0;
> + int i, err;
> + unsigned cnt = 0;
> + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
> +
> + pins = of_find_property(node, "mediatek,pins", NULL);
> + if (!pins) {
> + dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
> + node->name);
> + return -EINVAL;
> + }
> +
> + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
> + if (num_configs)
> + has_config = 1;
I'd prefer we first identify if it's a config or mux subnode, then go on to
parse it as mux or config. See comments on patch 2/3.
> +
> + num_pins = pins->length / sizeof(u32);
> + num_funcs = num_pins;
> + maps_per_pin = 0;
> + if (num_funcs)
> + maps_per_pin++;
> + if (has_config && num_pins >= 1)
> + maps_per_pin++;
> +
> + if (!num_pins || !maps_per_pin)
> + return -EINVAL;
> +
> + cnt = num_pins * maps_per_pin;
> +
> + err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
> + if (err < 0)
> + goto fail;
> +
> + for (i = 0; i < num_pins; i++) {
> + err = of_property_read_u32_index(node, "mediatek,pins",
> + i, &pinfunc);
As mentioned use just "pins" and let's figure out how to handle
this in a generic way.
> +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
> +{
> + return pinctrl_request_gpio(chip->base + offset);
> +}
> +
> +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
> +{
> + pinctrl_free_gpio(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_input(struct gpio_chip *chip,
> + unsigned offset)
> +{
> + return pinctrl_gpio_direction_input(chip->base + offset);
> +}
> +
> +static int mtk_gpio_direction_output(struct gpio_chip *chip,
> + unsigned offset, int value)
> +{
> + mtk_gpio_set(chip, offset, value);
> + return pinctrl_gpio_direction_output(chip->base + offset);
> +}
This is kinda nice!
> +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> +{
> + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> + struct mtk_pinctrl_group *g = pctl->groups + offset;
> + struct mtk_desc_function *desc =
> + mtk_pctrl_desc_find_irq_function_from_name(
> + pctl, g->name);
> + if (!desc)
> + return -EINVAL;
> +
> + return desc->irqnum;
> +}
I don't quite get this still. Does this mean every single GPIO line
potentially has it's own unique IRQ line?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 10:18 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-11-27 10:18 UTC (permalink / raw)
To: Linus Walleij
Cc: Hongzhou Yang, Rob Herring, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > +* Mediatek MT65XX Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control GPIO pins.
>
> It's not GPIO pins, since they are not always general purpose. It's just
> pins. Say "control SoC pins".
>
> > +Required properties:
> > +- compatible: value should be either of the following.
> > + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> > +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [pin number within the gpio controller]
>
> It's not a pin number really, it is a GPIO offset. But incidentally it's
> the same as the pin number. (This is OK...)
>
> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> > + setting. The format as following
> > +
> > + node {
> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
>
> As suggested by Sacha, use just "pins" and define the binding as a patch
> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> that is generic for multiplexing, so we get some order here.
>
> I want you however to put pin multiplexing and pin configuration into
> different nodes if possible. I don't like combines muxing and config
> nodes. If necessary tag the node with something.
Why? I think the properties can live happily together, even when the
parsing functions go to the pinctrl core.
> In the end we can also move the parsing functions to the pinctrl core, as
> long as the bindings are correct (possibly as a refactoring later).
>
> > + i2c0_pins_a: i2c0@0 {
> > + pins1 {
> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > + bias-disable;
> > + };
> > + };
>
> I would split it up.
>
> i2c0_pins_a: i2c0@0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0>;
> function = <MT8135_PIN_100_FUNC_SDA0>;
> };
The reason to put this in a single define was to make writing the device
trees less error prone. When you have two arrays you must correlate the
entries.
> pins2 {
> pins = <MT8135_PIN_100_SDA0>;
> bias-disable;
> };
Here we repeat what we've already written above just to add the pinctrl.
Let's have a look at a real world example, here a eMMC controller node
from the i.MX6 riotboard converted to generic pinconf, first your
suggestion, then mine:
emmc_pins: emmc@0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_CLK
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7>;
function = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_CLK__SD3_CLK
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
pins3 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7
>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
};
emmc_pins: emmc@0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK__SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
};
So this is not even half as big. Also it provides less opportunities for
introducing bugs like: Do all pins have a valid configuration setting?
Do the pins/function arrays have both the same number of entries and do
the entries in both arrays match?
>
> One node for the multiplexing, one node for the config. This is the
> pattern used by most drivers, so I want to have this structure.
>
> It is also easy to tell one node from the other: if it contains "function"
> we know it's a multiplexing node, if it doesn't, it's a config node.
So when merging these together a node is always multiplexing and
configuration. But do we really win anything if both are separated? When
both are separated you still need an array of pins in the nodes to
tell which pins this node is for. If this array also contains the
mux information then this won't hurt. You can still ignore it.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 10:18 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-11-27 10:18 UTC (permalink / raw)
To: Linus Walleij
Cc: Hongzhou Yang, Rob Herring, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
>
> > +* Mediatek MT65XX Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control GPIO pins.
>
> It's not GPIO pins, since they are not always general purpose. It's just
> pins. Say "control SoC pins".
>
> > +Required properties:
> > +- compatible: value should be either of the following.
> > + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> > +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [pin number within the gpio controller]
>
> It's not a pin number really, it is a GPIO offset. But incidentally it's
> the same as the pin number. (This is OK...)
>
> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> > + setting. The format as following
> > +
> > + node {
> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
>
> As suggested by Sacha, use just "pins" and define the binding as a patch
> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> that is generic for multiplexing, so we get some order here.
>
> I want you however to put pin multiplexing and pin configuration into
> different nodes if possible. I don't like combines muxing and config
> nodes. If necessary tag the node with something.
Why? I think the properties can live happily together, even when the
parsing functions go to the pinctrl core.
> In the end we can also move the parsing functions to the pinctrl core, as
> long as the bindings are correct (possibly as a refactoring later).
>
> > + i2c0_pins_a: i2c0@0 {
> > + pins1 {
> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > + bias-disable;
> > + };
> > + };
>
> I would split it up.
>
> i2c0_pins_a: i2c0@0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0>;
> function = <MT8135_PIN_100_FUNC_SDA0>;
> };
The reason to put this in a single define was to make writing the device
trees less error prone. When you have two arrays you must correlate the
entries.
> pins2 {
> pins = <MT8135_PIN_100_SDA0>;
> bias-disable;
> };
Here we repeat what we've already written above just to add the pinctrl.
Let's have a look at a real world example, here a eMMC controller node
from the i.MX6 riotboard converted to generic pinconf, first your
suggestion, then mine:
emmc_pins: emmc@0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_CLK
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7>;
function = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_CLK__SD3_CLK
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
pins3 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7
>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
};
emmc_pins: emmc@0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK__SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
};
So this is not even half as big. Also it provides less opportunities for
introducing bugs like: Do all pins have a valid configuration setting?
Do the pins/function arrays have both the same number of entries and do
the entries in both arrays match?
>
> One node for the multiplexing, one node for the config. This is the
> pattern used by most drivers, so I want to have this structure.
>
> It is also easy to tell one node from the other: if it contains "function"
> we know it's a multiplexing node, if it doesn't, it's a config node.
So when merging these together a node is always multiplexing and
configuration. But do we really win anything if both are separated? When
both are separated you still need an array of pins in the nodes to
tell which pins this node is for. If this array also contains the
mux information then this won't hurt. You can still ignore it.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-27 10:18 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-11-27 10:18 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > +* Mediatek MT65XX Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control GPIO pins.
>
> It's not GPIO pins, since they are not always general purpose. It's just
> pins. Say "control SoC pins".
>
> > +Required properties:
> > +- compatible: value should be either of the following.
> > + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> > +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [pin number within the gpio controller]
>
> It's not a pin number really, it is a GPIO offset. But incidentally it's
> the same as the pin number. (This is OK...)
>
> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> > + setting. The format as following
> > +
> > + node {
> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
>
> As suggested by Sacha, use just "pins" and define the binding as a patch
> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> that is generic for multiplexing, so we get some order here.
>
> I want you however to put pin multiplexing and pin configuration into
> different nodes if possible. I don't like combines muxing and config
> nodes. If necessary tag the node with something.
Why? I think the properties can live happily together, even when the
parsing functions go to the pinctrl core.
> In the end we can also move the parsing functions to the pinctrl core, as
> long as the bindings are correct (possibly as a refactoring later).
>
> > + i2c0_pins_a: i2c0 at 0 {
> > + pins1 {
> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > + bias-disable;
> > + };
> > + };
>
> I would split it up.
>
> i2c0_pins_a: i2c0 at 0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0>;
> function = <MT8135_PIN_100_FUNC_SDA0>;
> };
The reason to put this in a single define was to make writing the device
trees less error prone. When you have two arrays you must correlate the
entries.
> pins2 {
> pins = <MT8135_PIN_100_SDA0>;
> bias-disable;
> };
Here we repeat what we've already written above just to add the pinctrl.
Let's have a look at a real world example, here a eMMC controller node
from the i.MX6 riotboard converted to generic pinconf, first your
suggestion, then mine:
emmc_pins: emmc at 0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_CLK
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7>;
function = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_CLK__SD3_CLK
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
pins3 {
pins = <MX6QDL_PAD_SD3_CMD
MX6QDL_PAD_SD3_DAT0
MX6QDL_PAD_SD3_DAT1
MX6QDL_PAD_SD3_DAT2
MX6QDL_PAD_SD3_DAT3
MX6QDL_PAD_SD3_DAT4
MX6QDL_PAD_SD3_DAT5
MX6QDL_PAD_SD3_DAT6
MX6QDL_PAD_SD3_DAT7
>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
};
emmc_pins: emmc at 0 {
pins1 {
pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD
MX6QDL_PAD_SD3_DAT0__SD3_DATA0
MX6QDL_PAD_SD3_DAT1__SD3_DATA1
MX6QDL_PAD_SD3_DAT2__SD3_DATA2
MX6QDL_PAD_SD3_DAT3__SD3_DATA3
MX6QDL_PAD_SD3_DAT4__SD3_DATA4
MX6QDL_PAD_SD3_DAT5__SD3_DATA5
MX6QDL_PAD_SD3_DAT6__SD3_DATA6
MX6QDL_PAD_SD3_DAT7__SD3_DATA7>;
drive-strength = <87>; /* in OHM */
bias-pull-up = <47000>;
};
pins2 {
pins = <MX6QDL_PAD_SD3_CLK__SD3_CLK>;
drive-strength = <87>; /* in OHM */
};
};
So this is not even half as big. Also it provides less opportunities for
introducing bugs like: Do all pins have a valid configuration setting?
Do the pins/function arrays have both the same number of entries and do
the entries in both arrays match?
>
> One node for the multiplexing, one node for the config. This is the
> pattern used by most drivers, so I want to have this structure.
>
> It is also easy to tell one node from the other: if it contains "function"
> we know it's a multiplexing node, if it doesn't, it's a config node.
So when merging these together a node is always multiplexing and
configuration. But do we really win anything if both are separated? When
both are separated you still need an array of pins in the nodes to
tell which pins this node is for. If this array also contains the
mux information then this won't hurt. You can still ignore it.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2014-11-27 8:44 ` Linus Walleij
@ 2014-11-28 4:19 ` hongzhou yang
-1 siblings, 0 replies; 59+ messages in thread
From: hongzhou yang @ 2014-11-28 4:19 UTC (permalink / raw)
To: Linus Walleij
Cc: Mark Rutland, Ashwin Chaugule, Vladimir Murzin, Russell King,
Heiko Stübner, Pawel Moll, Ian Campbell, Catalin Marinas,
dandan.he, linux-kernel, alan.cheng, Grant Likely, devicetree,
Rob Herring, toby.liu, Sascha Hauer, Kumar Gala,
Matthias Brugger, Joe.C, huang eddie, linux-arm-kernel
On Thu, 2014-11-27 at 09:44 +0100, Linus Walleij wrote:
> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > +* Mediatek MT65XX Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control GPIO pins.
>
> It's not GPIO pins, since they are not always general purpose. It's just
> pins. Say "control SoC pins".
Ok, I'll modify it, thanks.
> > +Required properties:
> > +- compatible: value should be either of the following.
> > + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> > +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [pin number within the gpio controller]
>
> It's not a pin number really, it is a GPIO offset. But incidentally it's
> the same as the pin number. (This is OK...)
Yes, you're right, I will modify it. Thanks.
> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> > + setting. The format as following
> > +
> > + node {
> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
>
> As suggested by Sacha, use just "pins" and define the binding as a patch
> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> that is generic for multiplexing, so we get some order here.
>
> I want you however to put pin multiplexing and pin configuration into
> different nodes if possible. I don't like combines muxing and config
> nodes. If necessary tag the node with something.
>
> In the end we can also move the parsing functions to the pinctrl core, as
> long as the bindings are correct (possibly as a refactoring later).
>
> > + i2c0_pins_a: i2c0@0 {
> > + pins1 {
> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > + bias-disable;
> > + };
> > + };
>
> I would split it up.
>
> i2c0_pins_a: i2c0@0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0>;
> function = <MT8135_PIN_100_FUNC_SDA0>;
> };
> pins2 {
> pins = <MT8135_PIN_100_SDA0>;
> bias-disable;
> };
> };
>
> One node for the multiplexing, one node for the config. This is the
> pattern used by most drivers, so I want to have this structure.
>
> It is also easy to tell one node from the other: if it contains "function"
> we know it's a multiplexing node, if it doesn't, it's a config node.
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-28 4:19 ` hongzhou yang
0 siblings, 0 replies; 59+ messages in thread
From: hongzhou yang @ 2014-11-28 4:19 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2014-11-27 at 09:44 +0100, Linus Walleij wrote:
> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > +* Mediatek MT65XX Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control GPIO pins.
>
> It's not GPIO pins, since they are not always general purpose. It's just
> pins. Say "control SoC pins".
Ok, I'll modify it, thanks.
> > +Required properties:
> > +- compatible: value should be either of the following.
> > + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
> > +- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [pin number within the gpio controller]
>
> It's not a pin number really, it is a GPIO offset. But incidentally it's
> the same as the pin number. (This is OK...)
Yes, you're right, I will modify it. Thanks.
> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> > + setting. The format as following
> > +
> > + node {
> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
>
> As suggested by Sacha, use just "pins" and define the binding as a patch
> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> that is generic for multiplexing, so we get some order here.
>
> I want you however to put pin multiplexing and pin configuration into
> different nodes if possible. I don't like combines muxing and config
> nodes. If necessary tag the node with something.
>
> In the end we can also move the parsing functions to the pinctrl core, as
> long as the bindings are correct (possibly as a refactoring later).
>
> > + i2c0_pins_a: i2c0 at 0 {
> > + pins1 {
> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > + bias-disable;
> > + };
> > + };
>
> I would split it up.
>
> i2c0_pins_a: i2c0 at 0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0>;
> function = <MT8135_PIN_100_FUNC_SDA0>;
> };
> pins2 {
> pins = <MT8135_PIN_100_SDA0>;
> bias-disable;
> };
> };
>
> One node for the multiplexing, one node for the config. This is the
> pattern used by most drivers, so I want to have this structure.
>
> It is also easy to tell one node from the other: if it contains "function"
> we know it's a multiplexing node, if it doesn't, it's a config node.
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
2014-11-27 9:14 ` Linus Walleij
@ 2014-11-28 5:06 ` hongzhou yang
-1 siblings, 0 replies; 59+ messages in thread
From: hongzhou yang @ 2014-11-28 5:06 UTC (permalink / raw)
To: Linus Walleij
Cc: Mark Rutland, Ashwin Chaugule, Vladimir Murzin, Russell King,
Heiko Stübner, Pawel Moll, Ian Campbell, Catalin Marinas,
dandan.he, linux-kernel, alan.cheng, Grant Likely, devicetree,
Rob Herring, toby.liu, Sascha Hauer, Kumar Gala,
Matthias Brugger, Joe.C, huang eddie, linux-arm-kernel
On Thu, 2014-11-27 at 10:14 +0100, Linus Walleij wrote:
> ()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > From: Hongzhou Yang <hongzhou.yang@mediatek.com>
> >
> > The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
> >
> > The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
> >
> > This driver include common driver and mt8135 part.
> > The common driver include the pinctrl driver and GPIO driver.
> > The mt8135 part contain its special device data.
> >
> > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
> (...)
> > menuconfig ARCH_MEDIATEK
> > bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> > select ARM_GIC
> > + select PINCTRL
>
> Should it not also select PINCTRL_MTK8135 for the right SoC?
Ok, I will add it in next version.Thanks.
> (...)
> > +++ b/drivers/pinctrl/mediatek/Kconfig
> > @@ -0,0 +1,12 @@
> > +if ARCH_MEDIATEK
> > +
> > +config PINCTRL_MTK_COMMON
> > + bool
> > + select PINMUX
> > + select GENERIC_PINCONF
>
> This is also a GPIO driver but it fails to select GPIOLIB,
> OF_GPIO and also possibly GPIOLIB_IRQCHIP.
Ok, I will add it in next version. Thanks.
> (...)
> > +static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
> > + unsigned long *configs, unsigned num_configs,
> > + struct pinctrl_map **map, unsigned *cnt_maps,
> > + unsigned *num_maps)
> > +{
> > + struct mtk_pinctrl_group *grp;
> > + unsigned long *cfgs;
> > +
> > + if (*num_maps == *cnt_maps)
> > + return -ENOSPC;
> > +
> > + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
> > + GFP_KERNEL);
> > + if (cfgs == NULL)
> > + return -ENOMEM;
> > +
> > + grp = mtk_pctrl_find_group_by_pin(pctl, pin);
> > + if (!grp) {
> > + dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
> > + return -EINVAL;
> > + }
> > +
> > + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
> > + (*map)[*num_maps].data.configs.group_or_pin = grp->name;
> > + (*map)[*num_maps].data.configs.configs = cfgs;
> > + (*map)[*num_maps].data.configs.num_configs = num_configs;
> > + (*num_maps)++;
> > +
> > + return 0;
> > +}
>
> Can't this use pinctrl_utils_add_map_configs()?
Yes, it can use it, I will use it, thanks.
> > +static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> > + struct pinctrl_map *map,
> > + unsigned num_maps)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < num_maps; i++) {
> > + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
> > + kfree(map[i].data.configs.configs);
> > + }
> > +
> > + kfree(map);
> > +}
>
> Use pinctrl_utils_dt_free_map() instead.
Ok, thanks.
> > +static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
> > + unsigned *num_maps, unsigned cnt)
> > +{
> > + unsigned old_num = *cnt_maps;
> > + unsigned new_num = *num_maps + cnt;
> > + struct pinctrl_map *new_map;
> > +
> > + if (old_num >= new_num)
> > + return 0;
> > +
> > + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
> > + if (!new_map)
> > + return -ENOMEM;
> > +
> > + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
> > +
> > + *map = new_map;
> > + *cnt_maps = new_num;
> > +
> > + return 0;
> > +}
>
> Use pinctrl_utils_reserve_map() instead.
Ok, thanks.
> > +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> > + struct device_node *node,
> > + struct pinctrl_map **map,
> > + unsigned *num_maps, unsigned *cnt_maps)
> > +{
> > + struct property *pins;
> > + u32 pinfunc, pin, func;
> > + int num_pins, num_funcs, maps_per_pin;
> > + unsigned long *configs;
> > + unsigned int num_configs;
> > + bool has_config = 0;
> > + int i, err;
> > + unsigned cnt = 0;
> > + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + pins = of_find_property(node, "mediatek,pins", NULL);
> > + if (!pins) {
> > + dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
> > + node->name);
> > + return -EINVAL;
> > + }
> > +
> > + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
> > + if (num_configs)
> > + has_config = 1;
>
> I'd prefer we first identify if it's a config or mux subnode, then go on to
> parse it as mux or config. See comments on patch 2/3.
I think this need more discuss, thanks.
> > +
> > + num_pins = pins->length / sizeof(u32);
> > + num_funcs = num_pins;
> > + maps_per_pin = 0;
> > + if (num_funcs)
> > + maps_per_pin++;
> > + if (has_config && num_pins >= 1)
> > + maps_per_pin++;
> > +
> > + if (!num_pins || !maps_per_pin)
> > + return -EINVAL;
> > +
> > + cnt = num_pins * maps_per_pin;
> > +
> > + err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
> > + if (err < 0)
> > + goto fail;
> > +
> > + for (i = 0; i < num_pins; i++) {
> > + err = of_property_read_u32_index(node, "mediatek,pins",
> > + i, &pinfunc);
>
> As mentioned use just "pins" and let's figure out how to handle
> this in a generic way.
Ok, I will modify it, thanks.
> > +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
> > +{
> > + return pinctrl_request_gpio(chip->base + offset);
> > +}
> > +
> > +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
> > +{
> > + pinctrl_free_gpio(chip->base + offset);
> > +}
> > +
> > +static int mtk_gpio_direction_input(struct gpio_chip *chip,
> > + unsigned offset)
> > +{
> > + return pinctrl_gpio_direction_input(chip->base + offset);
> > +}
> > +
> > +static int mtk_gpio_direction_output(struct gpio_chip *chip,
> > + unsigned offset, int value)
> > +{
> > + mtk_gpio_set(chip, offset, value);
> > + return pinctrl_gpio_direction_output(chip->base + offset);
> > +}
>
> This is kinda nice!
>
> > +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> > +{
> > + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> > + struct mtk_pinctrl_group *g = pctl->groups + offset;
> > + struct mtk_desc_function *desc =
> > + mtk_pctrl_desc_find_irq_function_from_name(
> > + pctl, g->name);
> > + if (!desc)
> > + return -EINVAL;
> > +
> > + return desc->irqnum;
> > +}
>
> I don't quite get this still. Does this mean every single GPIO line
> potentially has it's own unique IRQ line?
For this question, we will add irq support in another patch, then we can
explain it, thanks.
Regards,
Hongzhou
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135.
@ 2014-11-28 5:06 ` hongzhou yang
0 siblings, 0 replies; 59+ messages in thread
From: hongzhou yang @ 2014-11-28 5:06 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2014-11-27 at 10:14 +0100, Linus Walleij wrote:
> ()On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> <hongzhou.yang@mediatek.com> wrote:
>
> > From: Hongzhou Yang <hongzhou.yang@mediatek.com>
> >
> > The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.
> >
> > The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.
> >
> > This driver include common driver and mt8135 part.
> > The common driver include the pinctrl driver and GPIO driver.
> > The mt8135 part contain its special device data.
> >
> > Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
> (...)
> > menuconfig ARCH_MEDIATEK
> > bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
> > select ARM_GIC
> > + select PINCTRL
>
> Should it not also select PINCTRL_MTK8135 for the right SoC?
Ok, I will add it in next version.Thanks.
> (...)
> > +++ b/drivers/pinctrl/mediatek/Kconfig
> > @@ -0,0 +1,12 @@
> > +if ARCH_MEDIATEK
> > +
> > +config PINCTRL_MTK_COMMON
> > + bool
> > + select PINMUX
> > + select GENERIC_PINCONF
>
> This is also a GPIO driver but it fails to select GPIOLIB,
> OF_GPIO and also possibly GPIOLIB_IRQCHIP.
Ok, I will add it in next version. Thanks.
> (...)
> > +static int mtk_pctrl_dt_node_to_map_config(struct mtk_pinctrl *pctl, u32 pin,
> > + unsigned long *configs, unsigned num_configs,
> > + struct pinctrl_map **map, unsigned *cnt_maps,
> > + unsigned *num_maps)
> > +{
> > + struct mtk_pinctrl_group *grp;
> > + unsigned long *cfgs;
> > +
> > + if (*num_maps == *cnt_maps)
> > + return -ENOSPC;
> > +
> > + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
> > + GFP_KERNEL);
> > + if (cfgs == NULL)
> > + return -ENOMEM;
> > +
> > + grp = mtk_pctrl_find_group_by_pin(pctl, pin);
> > + if (!grp) {
> > + dev_err(pctl->dev, "unable to match pin %d to group\n", pin);
> > + return -EINVAL;
> > + }
> > +
> > + (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
> > + (*map)[*num_maps].data.configs.group_or_pin = grp->name;
> > + (*map)[*num_maps].data.configs.configs = cfgs;
> > + (*map)[*num_maps].data.configs.num_configs = num_configs;
> > + (*num_maps)++;
> > +
> > + return 0;
> > +}
>
> Can't this use pinctrl_utils_add_map_configs()?
Yes, it can use it, I will use it, thanks.
> > +static void mtk_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
> > + struct pinctrl_map *map,
> > + unsigned num_maps)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < num_maps; i++) {
> > + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
> > + kfree(map[i].data.configs.configs);
> > + }
> > +
> > + kfree(map);
> > +}
>
> Use pinctrl_utils_dt_free_map() instead.
Ok, thanks.
> > +static int mtk_dt_cnt_map(struct pinctrl_map **map, unsigned *cnt_maps,
> > + unsigned *num_maps, unsigned cnt)
> > +{
> > + unsigned old_num = *cnt_maps;
> > + unsigned new_num = *num_maps + cnt;
> > + struct pinctrl_map *new_map;
> > +
> > + if (old_num >= new_num)
> > + return 0;
> > +
> > + new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
> > + if (!new_map)
> > + return -ENOMEM;
> > +
> > + memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
> > +
> > + *map = new_map;
> > + *cnt_maps = new_num;
> > +
> > + return 0;
> > +}
>
> Use pinctrl_utils_reserve_map() instead.
Ok, thanks.
> > +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> > + struct device_node *node,
> > + struct pinctrl_map **map,
> > + unsigned *num_maps, unsigned *cnt_maps)
> > +{
> > + struct property *pins;
> > + u32 pinfunc, pin, func;
> > + int num_pins, num_funcs, maps_per_pin;
> > + unsigned long *configs;
> > + unsigned int num_configs;
> > + bool has_config = 0;
> > + int i, err;
> > + unsigned cnt = 0;
> > + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + pins = of_find_property(node, "mediatek,pins", NULL);
> > + if (!pins) {
> > + dev_err(pctl->dev, "missing mediatek,pins property in node %s .\n",
> > + node->name);
> > + return -EINVAL;
> > + }
> > +
> > + err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
> > + if (num_configs)
> > + has_config = 1;
>
> I'd prefer we first identify if it's a config or mux subnode, then go on to
> parse it as mux or config. See comments on patch 2/3.
I think this need more discuss, thanks.
> > +
> > + num_pins = pins->length / sizeof(u32);
> > + num_funcs = num_pins;
> > + maps_per_pin = 0;
> > + if (num_funcs)
> > + maps_per_pin++;
> > + if (has_config && num_pins >= 1)
> > + maps_per_pin++;
> > +
> > + if (!num_pins || !maps_per_pin)
> > + return -EINVAL;
> > +
> > + cnt = num_pins * maps_per_pin;
> > +
> > + err = mtk_dt_cnt_map(map, cnt_maps, num_maps, cnt);
> > + if (err < 0)
> > + goto fail;
> > +
> > + for (i = 0; i < num_pins; i++) {
> > + err = of_property_read_u32_index(node, "mediatek,pins",
> > + i, &pinfunc);
>
> As mentioned use just "pins" and let's figure out how to handle
> this in a generic way.
Ok, I will modify it, thanks.
> > +static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
> > +{
> > + return pinctrl_request_gpio(chip->base + offset);
> > +}
> > +
> > +static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
> > +{
> > + pinctrl_free_gpio(chip->base + offset);
> > +}
> > +
> > +static int mtk_gpio_direction_input(struct gpio_chip *chip,
> > + unsigned offset)
> > +{
> > + return pinctrl_gpio_direction_input(chip->base + offset);
> > +}
> > +
> > +static int mtk_gpio_direction_output(struct gpio_chip *chip,
> > + unsigned offset, int value)
> > +{
> > + mtk_gpio_set(chip, offset, value);
> > + return pinctrl_gpio_direction_output(chip->base + offset);
> > +}
>
> This is kinda nice!
>
> > +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> > +{
> > + struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
> > + struct mtk_pinctrl_group *g = pctl->groups + offset;
> > + struct mtk_desc_function *desc =
> > + mtk_pctrl_desc_find_irq_function_from_name(
> > + pctl, g->name);
> > + if (!desc)
> > + return -EINVAL;
> > +
> > + return desc->irqnum;
> > +}
>
> I don't quite get this still. Does this mean every single GPIO line
> potentially has it's own unique IRQ line?
For this question, we will add irq support in another patch, then we can
explain it, thanks.
Regards,
Hongzhou
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-28 16:12 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-28 16:12 UTC (permalink / raw)
To: Sascha Hauer, Rob Herring
Cc: Hongzhou Yang, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> <hongzhou.yang@mediatek.com> wrote:
>> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
>> > + setting. The format as following
>> > +
>> > + node {
>> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> > + GENERIC_PINCONFIG;
>> > + };
>>
>> As suggested by Sacha, use just "pins" and define the binding as a patch
>> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> that is generic for multiplexing, so we get some order here.
>>
>> I want you however to put pin multiplexing and pin configuration into
>> different nodes if possible. I don't like combines muxing and config
>> nodes. If necessary tag the node with something.
>
> Why? I think the properties can live happily together, even when the
> parsing functions go to the pinctrl core.
I'm worried about the semantic ambiguity between the pins = <...>;
property on different pin controllers, whether they are based on
function+group or per-pin. It's not even up to me to decide,
this is for the DT binding people.
In this case:
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
Each element is a 32bit unsigned where the lower and higher
16 bits have different meanings.
In some other pin controller (using generic bindings and
already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
gpio39 {
gpio39_default_mode: gpio39_default {
default_mux {
function = "gpio";
groups = "gpio39_a_1";
};
default_cfg {
pins = "GPIO39_E16";
input-enable;
bias-pull-down;
};
};
};
Can we get away with using the same core parser with this
as well, here the nodes are split and using strings to identify
pins, not 32bit numbers.
I am worried about semantic coexistance...
>> > + i2c0_pins_a: i2c0@0 {
>> > + pins1 {
>> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>> > + bias-disable;
>> > + };
>> > + };
>>
>> I would split it up.
>>
>> i2c0_pins_a: i2c0@0 {
>> pins1 {
>> pins = <MT8135_PIN_100_SDA0>;
>> function = <MT8135_PIN_100_FUNC_SDA0>;
>> };
>
> The reason to put this in a single define was to make writing the device
> trees less error prone. When you have two arrays you must correlate the
> entries.
I see the upside. I'm just worried about ambiguity when comparing
different device trees to each other, because they should be about
readability and understanding, not confusing...
>> One node for the multiplexing, one node for the config. This is the
>> pattern used by most drivers, so I want to have this structure.
>>
>> It is also easy to tell one node from the other: if it contains "function"
>> we know it's a multiplexing node, if it doesn't, it's a config node.
>
> So when merging these together a node is always multiplexing and
> configuration. But do we really win anything if both are separated? When
> both are separated you still need an array of pins in the nodes to
> tell which pins this node is for. If this array also contains the
> mux information then this won't hurt. You can still ignore it.
Well we definately have to support the case with split config and
muxing nodes at least. I am very worried that we would get into
ambguities where that is not possible.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-28 16:12 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-28 16:12 UTC (permalink / raw)
To: Sascha Hauer, Rob Herring
Cc: Hongzhou Yang, Matthias Brugger, Sascha Hauer, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w,
alan.cheng-NuS5LvNUpcJWk0Htik3J/w, toby.liu
On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
>> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
>> > + setting. The format as following
>> > +
>> > + node {
>> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> > + GENERIC_PINCONFIG;
>> > + };
>>
>> As suggested by Sacha, use just "pins" and define the binding as a patch
>> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> that is generic for multiplexing, so we get some order here.
>>
>> I want you however to put pin multiplexing and pin configuration into
>> different nodes if possible. I don't like combines muxing and config
>> nodes. If necessary tag the node with something.
>
> Why? I think the properties can live happily together, even when the
> parsing functions go to the pinctrl core.
I'm worried about the semantic ambiguity between the pins = <...>;
property on different pin controllers, whether they are based on
function+group or per-pin. It's not even up to me to decide,
this is for the DT binding people.
In this case:
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
Each element is a 32bit unsigned where the lower and higher
16 bits have different meanings.
In some other pin controller (using generic bindings and
already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
gpio39 {
gpio39_default_mode: gpio39_default {
default_mux {
function = "gpio";
groups = "gpio39_a_1";
};
default_cfg {
pins = "GPIO39_E16";
input-enable;
bias-pull-down;
};
};
};
Can we get away with using the same core parser with this
as well, here the nodes are split and using strings to identify
pins, not 32bit numbers.
I am worried about semantic coexistance...
>> > + i2c0_pins_a: i2c0@0 {
>> > + pins1 {
>> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>> > + bias-disable;
>> > + };
>> > + };
>>
>> I would split it up.
>>
>> i2c0_pins_a: i2c0@0 {
>> pins1 {
>> pins = <MT8135_PIN_100_SDA0>;
>> function = <MT8135_PIN_100_FUNC_SDA0>;
>> };
>
> The reason to put this in a single define was to make writing the device
> trees less error prone. When you have two arrays you must correlate the
> entries.
I see the upside. I'm just worried about ambiguity when comparing
different device trees to each other, because they should be about
readability and understanding, not confusing...
>> One node for the multiplexing, one node for the config. This is the
>> pattern used by most drivers, so I want to have this structure.
>>
>> It is also easy to tell one node from the other: if it contains "function"
>> we know it's a multiplexing node, if it doesn't, it's a config node.
>
> So when merging these together a node is always multiplexing and
> configuration. But do we really win anything if both are separated? When
> both are separated you still need an array of pins in the nodes to
> tell which pins this node is for. If this array also contains the
> mux information then this won't hurt. You can still ignore it.
Well we definately have to support the case with split config and
muxing nodes at least. I am very worried that we would get into
ambguities where that is not possible.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-11-28 16:12 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2014-11-28 16:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> <hongzhou.yang@mediatek.com> wrote:
>> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
>> > + setting. The format as following
>> > +
>> > + node {
>> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> > + GENERIC_PINCONFIG;
>> > + };
>>
>> As suggested by Sacha, use just "pins" and define the binding as a patch
>> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> that is generic for multiplexing, so we get some order here.
>>
>> I want you however to put pin multiplexing and pin configuration into
>> different nodes if possible. I don't like combines muxing and config
>> nodes. If necessary tag the node with something.
>
> Why? I think the properties can live happily together, even when the
> parsing functions go to the pinctrl core.
I'm worried about the semantic ambiguity between the pins = <...>;
property on different pin controllers, whether they are based on
function+group or per-pin. It's not even up to me to decide,
this is for the DT binding people.
In this case:
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
Each element is a 32bit unsigned where the lower and higher
16 bits have different meanings.
In some other pin controller (using generic bindings and
already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
gpio39 {
gpio39_default_mode: gpio39_default {
default_mux {
function = "gpio";
groups = "gpio39_a_1";
};
default_cfg {
pins = "GPIO39_E16";
input-enable;
bias-pull-down;
};
};
};
Can we get away with using the same core parser with this
as well, here the nodes are split and using strings to identify
pins, not 32bit numbers.
I am worried about semantic coexistance...
>> > + i2c0_pins_a: i2c0 at 0 {
>> > + pins1 {
>> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>> > + bias-disable;
>> > + };
>> > + };
>>
>> I would split it up.
>>
>> i2c0_pins_a: i2c0 at 0 {
>> pins1 {
>> pins = <MT8135_PIN_100_SDA0>;
>> function = <MT8135_PIN_100_FUNC_SDA0>;
>> };
>
> The reason to put this in a single define was to make writing the device
> trees less error prone. When you have two arrays you must correlate the
> entries.
I see the upside. I'm just worried about ambiguity when comparing
different device trees to each other, because they should be about
readability and understanding, not confusing...
>> One node for the multiplexing, one node for the config. This is the
>> pattern used by most drivers, so I want to have this structure.
>>
>> It is also easy to tell one node from the other: if it contains "function"
>> we know it's a multiplexing node, if it doesn't, it's a config node.
>
> So when merging these together a node is always multiplexing and
> configuration. But do we really win anything if both are separated? When
> both are separated you still need an array of pins in the nodes to
> tell which pins this node is for. If this array also contains the
> mux information then this won't hurt. You can still ignore it.
Well we definately have to support the case with split config and
muxing nodes at least. I am very worried that we would get into
ambguities where that is not possible.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-12-02 13:55 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-12-02 13:55 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
Hi Linus,
On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> >> <hongzhou.yang@mediatek.com> wrote:
>
> >> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> >> > + setting. The format as following
> >> > +
> >> > + node {
> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> >> > + GENERIC_PINCONFIG;
> >> > + };
> >>
> >> As suggested by Sacha, use just "pins" and define the binding as a patch
> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> >> that is generic for multiplexing, so we get some order here.
> >>
> >> I want you however to put pin multiplexing and pin configuration into
> >> different nodes if possible. I don't like combines muxing and config
> >> nodes. If necessary tag the node with something.
> >
> > Why? I think the properties can live happily together, even when the
> > parsing functions go to the pinctrl core.
>
> I'm worried about the semantic ambiguity between the pins = <...>;
> property on different pin controllers, whether they are based on
> function+group or per-pin. It's not even up to me to decide,
> this is for the DT binding people.
>
> In this case:
>
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>
> Each element is a 32bit unsigned where the lower and higher
> 16 bits have different meanings.
>
> In some other pin controller (using generic bindings and
> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>
> gpio39 {
> gpio39_default_mode: gpio39_default {
> default_mux {
> function = "gpio";
> groups = "gpio39_a_1";
> };
> default_cfg {
> pins = "GPIO39_E16";
> input-enable;
> bias-pull-down;
> };
> };
> };
>
> Can we get away with using the same core parser with this
> as well, here the nodes are split and using strings to identify
> pins, not 32bit numbers.
>
> I am worried about semantic coexistance...
We could rename the property from 'pins' to 'pinmux' for this variant of
the binding. Then a parser would know that this property is about pins
and muxing.
>
> >> > + i2c0_pins_a: i2c0@0 {
> >> > + pins1 {
> >> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> >> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> >> > + bias-disable;
> >> > + };
> >> > + };
> >>
> >> I would split it up.
> >>
> >> i2c0_pins_a: i2c0@0 {
> >> pins1 {
> >> pins = <MT8135_PIN_100_SDA0>;
> >> function = <MT8135_PIN_100_FUNC_SDA0>;
> >> };
> >
> > The reason to put this in a single define was to make writing the device
> > trees less error prone. When you have two arrays you must correlate the
> > entries.
>
> I see the upside. I'm just worried about ambiguity when comparing
> different device trees to each other, because they should be about
> readability and understanding, not confusing...
Sorry, given the currently existing devicetrees I don't buy that
readability argument. Let's look into the snowball example, here ssp0:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
ste,function = "ssp0";
ste,pins = "ssp0_a_1";
};
snowball_cfg1 {
ste,pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
ste,pins = "GPIO145_C13"; /* RXD */
ste,config = <&in_pd>;
};
snowball_cfg3 {
ste,pins =
"GPIO146_D13", /* TXD */
"GPIO143_D12"; /* CLK */
ste,config = <&out_lo>;
};
};
For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
nowhere. Only the sourcecode shows that this (totally made up) string
means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
DB8500_PIN_D13 shall be muxed. The corresponding ste,function property
has the value "ssp0" which again is not documented. The following config
nodes reference the same pins under a different name: "GPIO144_B13",
"GPIO145_C13", "GPIO146_D13" and "GPIO143_D12". Again, these strings are
completely undocumented and only the sourcecode shows which strings can
be used for the ste,pins property. Not only that no documentation shows
which strings are allowed, there's also no documentation which describes
which combination of strings for the different properties make sense.
The use of ## for concatenating defines in the driver makes the whole
stuff even harder to understand. It even took me quite a while to
realize that the binding requires me to configure the muxes in groups,
but the config as individual pins. So no, the current devicetrees are
not about readability.
Rewrite this to:
#define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
#define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
#define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
#define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
and we get:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_cfg1 {
pinmux = <GPIO144_B13_SSP0_FRM>;
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
pinmux = <GPIO145_C13_SSP0_RXD>;
ste,config = <&in_pd>;
};
snowball_cfg3 {
pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
ste,config = <&out_lo>;
};
};
And the documentation we need is: "For the pinmux property pick macros
from dt-bindings/.../xy.h"
>
> >> One node for the multiplexing, one node for the config. This is the
> >> pattern used by most drivers, so I want to have this structure.
> >>
> >> It is also easy to tell one node from the other: if it contains "function"
> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >
> > So when merging these together a node is always multiplexing and
> > configuration. But do we really win anything if both are separated? When
> > both are separated you still need an array of pins in the nodes to
> > tell which pins this node is for. If this array also contains the
> > mux information then this won't hurt. You can still ignore it.
>
> Well we definately have to support the case with split config and
> muxing nodes at least. I am very worried that we would get into
> ambguities where that is not possible.
Sure we have as we cannot change existing bindings, but I cannot see
any ambiguities. In the end it's the SoC specific driver which decides
over the binding. Of course we do ourselves a favor when all use a
similar binding and use common code to parse it, but when everything
else fails we can still make a SoC specific parser. Nobody wants that
of course, we are all lazy ;)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-12-02 13:55 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-12-02 13:55 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
Hi Linus,
On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> >> <hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
>
> >> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> >> > + setting. The format as following
> >> > +
> >> > + node {
> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> >> > + GENERIC_PINCONFIG;
> >> > + };
> >>
> >> As suggested by Sacha, use just "pins" and define the binding as a patch
> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> >> that is generic for multiplexing, so we get some order here.
> >>
> >> I want you however to put pin multiplexing and pin configuration into
> >> different nodes if possible. I don't like combines muxing and config
> >> nodes. If necessary tag the node with something.
> >
> > Why? I think the properties can live happily together, even when the
> > parsing functions go to the pinctrl core.
>
> I'm worried about the semantic ambiguity between the pins = <...>;
> property on different pin controllers, whether they are based on
> function+group or per-pin. It's not even up to me to decide,
> this is for the DT binding people.
>
> In this case:
>
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>
> Each element is a 32bit unsigned where the lower and higher
> 16 bits have different meanings.
>
> In some other pin controller (using generic bindings and
> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>
> gpio39 {
> gpio39_default_mode: gpio39_default {
> default_mux {
> function = "gpio";
> groups = "gpio39_a_1";
> };
> default_cfg {
> pins = "GPIO39_E16";
> input-enable;
> bias-pull-down;
> };
> };
> };
>
> Can we get away with using the same core parser with this
> as well, here the nodes are split and using strings to identify
> pins, not 32bit numbers.
>
> I am worried about semantic coexistance...
We could rename the property from 'pins' to 'pinmux' for this variant of
the binding. Then a parser would know that this property is about pins
and muxing.
>
> >> > + i2c0_pins_a: i2c0@0 {
> >> > + pins1 {
> >> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> >> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> >> > + bias-disable;
> >> > + };
> >> > + };
> >>
> >> I would split it up.
> >>
> >> i2c0_pins_a: i2c0@0 {
> >> pins1 {
> >> pins = <MT8135_PIN_100_SDA0>;
> >> function = <MT8135_PIN_100_FUNC_SDA0>;
> >> };
> >
> > The reason to put this in a single define was to make writing the device
> > trees less error prone. When you have two arrays you must correlate the
> > entries.
>
> I see the upside. I'm just worried about ambiguity when comparing
> different device trees to each other, because they should be about
> readability and understanding, not confusing...
Sorry, given the currently existing devicetrees I don't buy that
readability argument. Let's look into the snowball example, here ssp0:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
ste,function = "ssp0";
ste,pins = "ssp0_a_1";
};
snowball_cfg1 {
ste,pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
ste,pins = "GPIO145_C13"; /* RXD */
ste,config = <&in_pd>;
};
snowball_cfg3 {
ste,pins =
"GPIO146_D13", /* TXD */
"GPIO143_D12"; /* CLK */
ste,config = <&out_lo>;
};
};
For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
nowhere. Only the sourcecode shows that this (totally made up) string
means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
DB8500_PIN_D13 shall be muxed. The corresponding ste,function property
has the value "ssp0" which again is not documented. The following config
nodes reference the same pins under a different name: "GPIO144_B13",
"GPIO145_C13", "GPIO146_D13" and "GPIO143_D12". Again, these strings are
completely undocumented and only the sourcecode shows which strings can
be used for the ste,pins property. Not only that no documentation shows
which strings are allowed, there's also no documentation which describes
which combination of strings for the different properties make sense.
The use of ## for concatenating defines in the driver makes the whole
stuff even harder to understand. It even took me quite a while to
realize that the binding requires me to configure the muxes in groups,
but the config as individual pins. So no, the current devicetrees are
not about readability.
Rewrite this to:
#define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
#define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
#define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
#define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
and we get:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_cfg1 {
pinmux = <GPIO144_B13_SSP0_FRM>;
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
pinmux = <GPIO145_C13_SSP0_RXD>;
ste,config = <&in_pd>;
};
snowball_cfg3 {
pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
ste,config = <&out_lo>;
};
};
And the documentation we need is: "For the pinmux property pick macros
from dt-bindings/.../xy.h"
>
> >> One node for the multiplexing, one node for the config. This is the
> >> pattern used by most drivers, so I want to have this structure.
> >>
> >> It is also easy to tell one node from the other: if it contains "function"
> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >
> > So when merging these together a node is always multiplexing and
> > configuration. But do we really win anything if both are separated? When
> > both are separated you still need an array of pins in the nodes to
> > tell which pins this node is for. If this array also contains the
> > mux information then this won't hurt. You can still ignore it.
>
> Well we definately have to support the case with split config and
> muxing nodes at least. I am very worried that we would get into
> ambguities where that is not possible.
Sure we have as we cannot change existing bindings, but I cannot see
any ambiguities. In the end it's the SoC specific driver which decides
over the binding. Of course we do ourselves a favor when all use a
similar binding and use common code to parse it, but when everything
else fails we can still make a SoC specific parser. Nobody wants that
of course, we are all lazy ;)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2014-12-02 13:55 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2014-12-02 13:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
> >> <hongzhou.yang@mediatek.com> wrote:
>
> >> > +- mediatek,pins: 2 integers array, represents gpio pinmux number and config
> >> > + setting. The format as following
> >> > +
> >> > + node {
> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
> >> > + GENERIC_PINCONFIG;
> >> > + };
> >>
> >> As suggested by Sacha, use just "pins" and define the binding as a patch
> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> >> that is generic for multiplexing, so we get some order here.
> >>
> >> I want you however to put pin multiplexing and pin configuration into
> >> different nodes if possible. I don't like combines muxing and config
> >> nodes. If necessary tag the node with something.
> >
> > Why? I think the properties can live happily together, even when the
> > parsing functions go to the pinctrl core.
>
> I'm worried about the semantic ambiguity between the pins = <...>;
> property on different pin controllers, whether they are based on
> function+group or per-pin. It's not even up to me to decide,
> this is for the DT binding people.
>
> In this case:
>
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>
> Each element is a 32bit unsigned where the lower and higher
> 16 bits have different meanings.
>
> In some other pin controller (using generic bindings and
> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>
> gpio39 {
> gpio39_default_mode: gpio39_default {
> default_mux {
> function = "gpio";
> groups = "gpio39_a_1";
> };
> default_cfg {
> pins = "GPIO39_E16";
> input-enable;
> bias-pull-down;
> };
> };
> };
>
> Can we get away with using the same core parser with this
> as well, here the nodes are split and using strings to identify
> pins, not 32bit numbers.
>
> I am worried about semantic coexistance...
We could rename the property from 'pins' to 'pinmux' for this variant of
the binding. Then a parser would know that this property is about pins
and muxing.
>
> >> > + i2c0_pins_a: i2c0 at 0 {
> >> > + pins1 {
> >> > + mediatek,pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> >> > + <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> >> > + bias-disable;
> >> > + };
> >> > + };
> >>
> >> I would split it up.
> >>
> >> i2c0_pins_a: i2c0 at 0 {
> >> pins1 {
> >> pins = <MT8135_PIN_100_SDA0>;
> >> function = <MT8135_PIN_100_FUNC_SDA0>;
> >> };
> >
> > The reason to put this in a single define was to make writing the device
> > trees less error prone. When you have two arrays you must correlate the
> > entries.
>
> I see the upside. I'm just worried about ambiguity when comparing
> different device trees to each other, because they should be about
> readability and understanding, not confusing...
Sorry, given the currently existing devicetrees I don't buy that
readability argument. Let's look into the snowball example, here ssp0:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
ste,function = "ssp0";
ste,pins = "ssp0_a_1";
};
snowball_cfg1 {
ste,pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
ste,pins = "GPIO145_C13"; /* RXD */
ste,config = <&in_pd>;
};
snowball_cfg3 {
ste,pins =
"GPIO146_D13", /* TXD */
"GPIO143_D12"; /* CLK */
ste,config = <&out_lo>;
};
};
For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
nowhere. Only the sourcecode shows that this (totally made up) string
means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
DB8500_PIN_D13 shall be muxed. The corresponding ste,function property
has the value "ssp0" which again is not documented. The following config
nodes reference the same pins under a different name: "GPIO144_B13",
"GPIO145_C13", "GPIO146_D13" and "GPIO143_D12". Again, these strings are
completely undocumented and only the sourcecode shows which strings can
be used for the ste,pins property. Not only that no documentation shows
which strings are allowed, there's also no documentation which describes
which combination of strings for the different properties make sense.
The use of ## for concatenating defines in the driver makes the whole
stuff even harder to understand. It even took me quite a while to
realize that the binding requires me to configure the muxes in groups,
but the config as individual pins. So no, the current devicetrees are
not about readability.
Rewrite this to:
#define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
#define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
#define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
#define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
and we get:
ssp0_snowball_mode: ssp0_snowball_default {
snowball_cfg1 {
pinmux = <GPIO144_B13_SSP0_FRM>;
ste,config = <&gpio_out_hi>;
};
snowball_cfg2 {
pinmux = <GPIO145_C13_SSP0_RXD>;
ste,config = <&in_pd>;
};
snowball_cfg3 {
pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
ste,config = <&out_lo>;
};
};
And the documentation we need is: "For the pinmux property pick macros
from dt-bindings/.../xy.h"
>
> >> One node for the multiplexing, one node for the config. This is the
> >> pattern used by most drivers, so I want to have this structure.
> >>
> >> It is also easy to tell one node from the other: if it contains "function"
> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >
> > So when merging these together a node is always multiplexing and
> > configuration. But do we really win anything if both are separated? When
> > both are separated you still need an array of pins in the nodes to
> > tell which pins this node is for. If this array also contains the
> > mux information then this won't hurt. You can still ignore it.
>
> Well we definately have to support the case with split config and
> muxing nodes at least. I am very worried that we would get into
> ambguities where that is not possible.
Sure we have as we cannot change existing bindings, but I cannot see
any ambiguities. In the end it's the SoC specific driver which decides
over the binding. Of course we do ourselves a favor when all use a
similar binding and use common code to parse it, but when everything
else fails we can still make a SoC specific parser. Nobody wants that
of course, we are all lazy ;)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2014-12-02 13:55 ` Sascha Hauer
(?)
@ 2015-01-10 21:33 ` Linus Walleij
-1 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-10 21:33 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
Sorry for taking eternities to get back on this, I ran into a merge window
and some christmas. I do hope we can resolve this in the current
development cycle so we can get this support in.
> On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
>> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> >> <hongzhou.yang@mediatek.com> wrote:
>> >> > + node {
>> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> >> > + GENERIC_PINCONFIG;
>> >> > + };
>> >>
>> >> As suggested by Sacha, use just "pins" and define the binding as a patch
>> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> >> that is generic for multiplexing, so we get some order here.
>> >>
>> >> I want you however to put pin multiplexing and pin configuration into
>> >> different nodes if possible. I don't like combines muxing and config
>> >> nodes. If necessary tag the node with something.
>> >
>> > Why? I think the properties can live happily together, even when the
>> > parsing functions go to the pinctrl core.
>>
>> I'm worried about the semantic ambiguity between the pins = <...>;
>> property on different pin controllers, whether they are based on
>> function+group or per-pin. It's not even up to me to decide,
>> this is for the DT binding people.
>>
>> In this case:
>>
>> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>>
>> Each element is a 32bit unsigned where the lower and higher
>> 16 bits have different meanings.
>>
>> In some other pin controller (using generic bindings and
>> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>>
>> gpio39 {
>> gpio39_default_mode: gpio39_default {
>> default_mux {
>> function = "gpio";
>> groups = "gpio39_a_1";
>> };
>> default_cfg {
>> pins = "GPIO39_E16";
>> input-enable;
>> bias-pull-down;
>> };
>> };
>> };
>>
>> Can we get away with using the same core parser with this
>> as well, here the nodes are split and using strings to identify
>> pins, not 32bit numbers.
>>
>> I am worried about semantic coexistance...
>
> We could rename the property from 'pins' to 'pinmux' for this variant of
> the binding. Then a parser would know that this property is about pins
> and muxing.
OK sounds like a viable compromise.
I am mostly worried that none of the fine device tree people say
anything about this stuff we're discussing here, maybe absolutely
nobody else understands...
>> >> i2c0_pins_a: i2c0@0 {
>> >> pins1 {
>> >> pins = <MT8135_PIN_100_SDA0>;
>> >> function = <MT8135_PIN_100_FUNC_SDA0>;
>> >> };
>> >
>> > The reason to put this in a single define was to make writing the device
>> > trees less error prone. When you have two arrays you must correlate the
>> > entries.
>>
>> I see the upside. I'm just worried about ambiguity when comparing
>> different device trees to each other, because they should be about
>> readability and understanding, not confusing...
>
> Sorry, given the currently existing devicetrees I don't buy that
> readability argument. Let's look into the snowball example, here ssp0:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_mux {
> ste,function = "ssp0";
> ste,pins = "ssp0_a_1";
> };
> snowball_cfg1 {
> ste,pins = "GPIO144_B13"; /* FRM */
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> ste,pins = "GPIO145_C13"; /* RXD */
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> ste,pins =
> "GPIO146_D13", /* TXD */
> "GPIO143_D12"; /* CLK */
> ste,config = <&out_lo>;
> };
> };
I agree the ste,pins is not a good example, it is insane to have
something group and pins mixed, and that is why
I migrated it in the last merge window, notably the pin multiplex thing
so it now looks like this:
ssp0 {
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
function = "ssp0";
groups = "ssp0_a_1";
};
snowball_cfg1 {
pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
(...)
I'm sorry about not migrating the ste,config part to
generic bindings yet :( that is next.
> For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> nowhere.
Is this a bug report about the documentation? I don't see how
that is relevant to the overall design.
> Only the sourcecode shows that this (totally made up) string
> means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> DB8500_PIN_D13 shall be muxed.
So this pins and pins ambiguity (which has nothing to do with the
generic bindings BTW) is now fixed up somewhat. The first thing is
a group, the pins are pin names.
> The corresponding ste,function property
> has the value "ssp0" which again is not documented. The following config
> nodes reference the same pins under a different name: "GPIO144_B13",
> "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
Yes, because it references individual pins, not groups. Config
is per-pin, multiplexing is per-group in the Nomadik case.
(Some hardware and drivers are different.)
> Again, these strings are
> completely undocumented and only the sourcecode shows which strings can
> be used for the ste,pins property. Not only that no documentation shows
> which strings are allowed, there's also no documentation which describes
> which combination of strings for the different properties make sense.
OK again a documentation bug report I guess, if you want to I can
add this to the documentation (there are indeed some pin control
drivers that list these groups and functions). This documentation was
not written by me, but I can sure fix it up if that makes you happier.
> The use of ## for concatenating defines in the driver makes the whole
> stuff even harder to understand. It even took me quite a while to
> realize that the binding requires me to configure the muxes in groups,
> but the config as individual pins.
The hardware is such that muxes are in groups and pin config per-pin.
We cannot augment reality, just describe it in an as structured way
as possible.
To add to the complexity, some pin controllers mux things in groups,
some per-pin (like freescale I think?) some controllers even do config
of things like pull-up across groups of pins rather than individually.
> So no, the current devicetrees are
> not about readability.
Is this an argument that goes away if I fix the documentation?
> #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
>
> and we get:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_cfg1 {
> pinmux = <GPIO144_B13_SSP0_FRM>;
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> pinmux = <GPIO145_C13_SSP0_RXD>;
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> ste,config = <&out_lo>;
> };
> };
But this gives the false impression that pins can be muxed
individually, and it makes it possible to write device trees that
attempt to do so, while in practice it will not perform on the
hardware.
>> >> One node for the multiplexing, one node for the config. This is the
>> >> pattern used by most drivers, so I want to have this structure.
>> >>
>> >> It is also easy to tell one node from the other: if it contains "function"
>> >> we know it's a multiplexing node, if it doesn't, it's a config node.
>> >
>> > So when merging these together a node is always multiplexing and
>> > configuration. But do we really win anything if both are separated? When
>> > both are separated you still need an array of pins in the nodes to
>> > tell which pins this node is for. If this array also contains the
>> > mux information then this won't hurt. You can still ignore it.
>>
>> Well we definately have to support the case with split config and
>> muxing nodes at least. I am very worried that we would get into
>> ambguities where that is not possible.
>
> Sure we have as we cannot change existing bindings,
For Nomadik I did, because there are no deployed systems suffering
from it. I just had to use some board I had to make some kind of
example. I would encourage any other system not deployed in the
masses with flashed-in device trees to do the same as this is
still somewhat in a flux.
I am worried that there is something in your reasoning that sort of
assumes all pin controllers mux pins one-by-one and not in groups.
How do we make it impossible to write a device tree that also
make hardware that do groupwise config viable without ambiguities?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-10 21:33 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-10 21:33 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he
On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
Sorry for taking eternities to get back on this, I ran into a merge window
and some christmas. I do hope we can resolve this in the current
development cycle so we can get this support in.
> On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
>> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> >> <hongzhou.yang@mediatek.com> wrote:
>> >> > + node {
>> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> >> > + GENERIC_PINCONFIG;
>> >> > + };
>> >>
>> >> As suggested by Sacha, use just "pins" and define the binding as a patch
>> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> >> that is generic for multiplexing, so we get some order here.
>> >>
>> >> I want you however to put pin multiplexing and pin configuration into
>> >> different nodes if possible. I don't like combines muxing and config
>> >> nodes. If necessary tag the node with something.
>> >
>> > Why? I think the properties can live happily together, even when the
>> > parsing functions go to the pinctrl core.
>>
>> I'm worried about the semantic ambiguity between the pins = <...>;
>> property on different pin controllers, whether they are based on
>> function+group or per-pin. It's not even up to me to decide,
>> this is for the DT binding people.
>>
>> In this case:
>>
>> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>>
>> Each element is a 32bit unsigned where the lower and higher
>> 16 bits have different meanings.
>>
>> In some other pin controller (using generic bindings and
>> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>>
>> gpio39 {
>> gpio39_default_mode: gpio39_default {
>> default_mux {
>> function = "gpio";
>> groups = "gpio39_a_1";
>> };
>> default_cfg {
>> pins = "GPIO39_E16";
>> input-enable;
>> bias-pull-down;
>> };
>> };
>> };
>>
>> Can we get away with using the same core parser with this
>> as well, here the nodes are split and using strings to identify
>> pins, not 32bit numbers.
>>
>> I am worried about semantic coexistance...
>
> We could rename the property from 'pins' to 'pinmux' for this variant of
> the binding. Then a parser would know that this property is about pins
> and muxing.
OK sounds like a viable compromise.
I am mostly worried that none of the fine device tree people say
anything about this stuff we're discussing here, maybe absolutely
nobody else understands...
>> >> i2c0_pins_a: i2c0@0 {
>> >> pins1 {
>> >> pins = <MT8135_PIN_100_SDA0>;
>> >> function = <MT8135_PIN_100_FUNC_SDA0>;
>> >> };
>> >
>> > The reason to put this in a single define was to make writing the device
>> > trees less error prone. When you have two arrays you must correlate the
>> > entries.
>>
>> I see the upside. I'm just worried about ambiguity when comparing
>> different device trees to each other, because they should be about
>> readability and understanding, not confusing...
>
> Sorry, given the currently existing devicetrees I don't buy that
> readability argument. Let's look into the snowball example, here ssp0:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_mux {
> ste,function = "ssp0";
> ste,pins = "ssp0_a_1";
> };
> snowball_cfg1 {
> ste,pins = "GPIO144_B13"; /* FRM */
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> ste,pins = "GPIO145_C13"; /* RXD */
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> ste,pins =
> "GPIO146_D13", /* TXD */
> "GPIO143_D12"; /* CLK */
> ste,config = <&out_lo>;
> };
> };
I agree the ste,pins is not a good example, it is insane to have
something group and pins mixed, and that is why
I migrated it in the last merge window, notably the pin multiplex thing
so it now looks like this:
ssp0 {
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
function = "ssp0";
groups = "ssp0_a_1";
};
snowball_cfg1 {
pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
(...)
I'm sorry about not migrating the ste,config part to
generic bindings yet :( that is next.
> For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> nowhere.
Is this a bug report about the documentation? I don't see how
that is relevant to the overall design.
> Only the sourcecode shows that this (totally made up) string
> means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> DB8500_PIN_D13 shall be muxed.
So this pins and pins ambiguity (which has nothing to do with the
generic bindings BTW) is now fixed up somewhat. The first thing is
a group, the pins are pin names.
> The corresponding ste,function property
> has the value "ssp0" which again is not documented. The following config
> nodes reference the same pins under a different name: "GPIO144_B13",
> "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
Yes, because it references individual pins, not groups. Config
is per-pin, multiplexing is per-group in the Nomadik case.
(Some hardware and drivers are different.)
> Again, these strings are
> completely undocumented and only the sourcecode shows which strings can
> be used for the ste,pins property. Not only that no documentation shows
> which strings are allowed, there's also no documentation which describes
> which combination of strings for the different properties make sense.
OK again a documentation bug report I guess, if you want to I can
add this to the documentation (there are indeed some pin control
drivers that list these groups and functions). This documentation was
not written by me, but I can sure fix it up if that makes you happier.
> The use of ## for concatenating defines in the driver makes the whole
> stuff even harder to understand. It even took me quite a while to
> realize that the binding requires me to configure the muxes in groups,
> but the config as individual pins.
The hardware is such that muxes are in groups and pin config per-pin.
We cannot augment reality, just describe it in an as structured way
as possible.
To add to the complexity, some pin controllers mux things in groups,
some per-pin (like freescale I think?) some controllers even do config
of things like pull-up across groups of pins rather than individually.
> So no, the current devicetrees are
> not about readability.
Is this an argument that goes away if I fix the documentation?
> #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
>
> and we get:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_cfg1 {
> pinmux = <GPIO144_B13_SSP0_FRM>;
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> pinmux = <GPIO145_C13_SSP0_RXD>;
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> ste,config = <&out_lo>;
> };
> };
But this gives the false impression that pins can be muxed
individually, and it makes it possible to write device trees that
attempt to do so, while in practice it will not perform on the
hardware.
>> >> One node for the multiplexing, one node for the config. This is the
>> >> pattern used by most drivers, so I want to have this structure.
>> >>
>> >> It is also easy to tell one node from the other: if it contains "function"
>> >> we know it's a multiplexing node, if it doesn't, it's a config node.
>> >
>> > So when merging these together a node is always multiplexing and
>> > configuration. But do we really win anything if both are separated? When
>> > both are separated you still need an array of pins in the nodes to
>> > tell which pins this node is for. If this array also contains the
>> > mux information then this won't hurt. You can still ignore it.
>>
>> Well we definately have to support the case with split config and
>> muxing nodes at least. I am very worried that we would get into
>> ambguities where that is not possible.
>
> Sure we have as we cannot change existing bindings,
For Nomadik I did, because there are no deployed systems suffering
from it. I just had to use some board I had to make some kind of
example. I would encourage any other system not deployed in the
masses with flashed-in device trees to do the same as this is
still somewhat in a flux.
I am worried that there is something in your reasoning that sort of
assumes all pin controllers mux pins one-by-one and not in groups.
How do we make it impossible to write a device tree that also
make hardware that do groupwise config viable without ambiguities?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-10 21:33 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-10 21:33 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
Sorry for taking eternities to get back on this, I ran into a merge window
and some christmas. I do hope we can resolve this in the current
development cycle so we can get this support in.
> On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
>> On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
>> >> On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
>> >> <hongzhou.yang@mediatek.com> wrote:
>> >> > + node {
>> >> > + mediatek,pins = <PIN_NUMBER_PINMUX>;
>> >> > + GENERIC_PINCONFIG;
>> >> > + };
>> >>
>> >> As suggested by Sacha, use just "pins" and define the binding as a patch
>> >> to Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> >> that is generic for multiplexing, so we get some order here.
>> >>
>> >> I want you however to put pin multiplexing and pin configuration into
>> >> different nodes if possible. I don't like combines muxing and config
>> >> nodes. If necessary tag the node with something.
>> >
>> > Why? I think the properties can live happily together, even when the
>> > parsing functions go to the pinctrl core.
>>
>> I'm worried about the semantic ambiguity between the pins = <...>;
>> property on different pin controllers, whether they are based on
>> function+group or per-pin. It's not even up to me to decide,
>> this is for the DT binding people.
>>
>> In this case:
>>
>> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
>> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
>>
>> Each element is a 32bit unsigned where the lower and higher
>> 16 bits have different meanings.
>>
>> In some other pin controller (using generic bindings and
>> already merged! arch/arm/boot/dts/ste-href-ab8500.dtsi):
>>
>> gpio39 {
>> gpio39_default_mode: gpio39_default {
>> default_mux {
>> function = "gpio";
>> groups = "gpio39_a_1";
>> };
>> default_cfg {
>> pins = "GPIO39_E16";
>> input-enable;
>> bias-pull-down;
>> };
>> };
>> };
>>
>> Can we get away with using the same core parser with this
>> as well, here the nodes are split and using strings to identify
>> pins, not 32bit numbers.
>>
>> I am worried about semantic coexistance...
>
> We could rename the property from 'pins' to 'pinmux' for this variant of
> the binding. Then a parser would know that this property is about pins
> and muxing.
OK sounds like a viable compromise.
I am mostly worried that none of the fine device tree people say
anything about this stuff we're discussing here, maybe absolutely
nobody else understands...
>> >> i2c0_pins_a: i2c0 at 0 {
>> >> pins1 {
>> >> pins = <MT8135_PIN_100_SDA0>;
>> >> function = <MT8135_PIN_100_FUNC_SDA0>;
>> >> };
>> >
>> > The reason to put this in a single define was to make writing the device
>> > trees less error prone. When you have two arrays you must correlate the
>> > entries.
>>
>> I see the upside. I'm just worried about ambiguity when comparing
>> different device trees to each other, because they should be about
>> readability and understanding, not confusing...
>
> Sorry, given the currently existing devicetrees I don't buy that
> readability argument. Let's look into the snowball example, here ssp0:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_mux {
> ste,function = "ssp0";
> ste,pins = "ssp0_a_1";
> };
> snowball_cfg1 {
> ste,pins = "GPIO144_B13"; /* FRM */
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> ste,pins = "GPIO145_C13"; /* RXD */
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> ste,pins =
> "GPIO146_D13", /* TXD */
> "GPIO143_D12"; /* CLK */
> ste,config = <&out_lo>;
> };
> };
I agree the ste,pins is not a good example, it is insane to have
something group and pins mixed, and that is why
I migrated it in the last merge window, notably the pin multiplex thing
so it now looks like this:
ssp0 {
ssp0_snowball_mode: ssp0_snowball_default {
snowball_mux {
function = "ssp0";
groups = "ssp0_a_1";
};
snowball_cfg1 {
pins = "GPIO144_B13"; /* FRM */
ste,config = <&gpio_out_hi>;
};
(...)
I'm sorry about not migrating the ste,config part to
generic bindings yet :( that is next.
> For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> nowhere.
Is this a bug report about the documentation? I don't see how
that is relevant to the overall design.
> Only the sourcecode shows that this (totally made up) string
> means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> DB8500_PIN_D13 shall be muxed.
So this pins and pins ambiguity (which has nothing to do with the
generic bindings BTW) is now fixed up somewhat. The first thing is
a group, the pins are pin names.
> The corresponding ste,function property
> has the value "ssp0" which again is not documented. The following config
> nodes reference the same pins under a different name: "GPIO144_B13",
> "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
Yes, because it references individual pins, not groups. Config
is per-pin, multiplexing is per-group in the Nomadik case.
(Some hardware and drivers are different.)
> Again, these strings are
> completely undocumented and only the sourcecode shows which strings can
> be used for the ste,pins property. Not only that no documentation shows
> which strings are allowed, there's also no documentation which describes
> which combination of strings for the different properties make sense.
OK again a documentation bug report I guess, if you want to I can
add this to the documentation (there are indeed some pin control
drivers that list these groups and functions). This documentation was
not written by me, but I can sure fix it up if that makes you happier.
> The use of ## for concatenating defines in the driver makes the whole
> stuff even harder to understand. It even took me quite a while to
> realize that the binding requires me to configure the muxes in groups,
> but the config as individual pins.
The hardware is such that muxes are in groups and pin config per-pin.
We cannot augment reality, just describe it in an as structured way
as possible.
To add to the complexity, some pin controllers mux things in groups,
some per-pin (like freescale I think?) some controllers even do config
of things like pull-up across groups of pins rather than individually.
> So no, the current devicetrees are
> not about readability.
Is this an argument that goes away if I fix the documentation?
> #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
>
> and we get:
>
> ssp0_snowball_mode: ssp0_snowball_default {
> snowball_cfg1 {
> pinmux = <GPIO144_B13_SSP0_FRM>;
> ste,config = <&gpio_out_hi>;
> };
> snowball_cfg2 {
> pinmux = <GPIO145_C13_SSP0_RXD>;
> ste,config = <&in_pd>;
> };
> snowball_cfg3 {
> pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> ste,config = <&out_lo>;
> };
> };
But this gives the false impression that pins can be muxed
individually, and it makes it possible to write device trees that
attempt to do so, while in practice it will not perform on the
hardware.
>> >> One node for the multiplexing, one node for the config. This is the
>> >> pattern used by most drivers, so I want to have this structure.
>> >>
>> >> It is also easy to tell one node from the other: if it contains "function"
>> >> we know it's a multiplexing node, if it doesn't, it's a config node.
>> >
>> > So when merging these together a node is always multiplexing and
>> > configuration. But do we really win anything if both are separated? When
>> > both are separated you still need an array of pins in the nodes to
>> > tell which pins this node is for. If this array also contains the
>> > mux information then this won't hurt. You can still ignore it.
>>
>> Well we definately have to support the case with split config and
>> muxing nodes at least. I am very worried that we would get into
>> ambguities where that is not possible.
>
> Sure we have as we cannot change existing bindings,
For Nomadik I did, because there are no deployed systems suffering
from it. I just had to use some board I had to make some kind of
example. I would encourage any other system not deployed in the
masses with flashed-in device trees to do the same as this is
still somewhat in a flux.
I am worried that there is something in your reasoning that sort of
assumes all pin controllers mux pins one-by-one and not in groups.
How do we make it impossible to write a device tree that also
make hardware that do groupwise config viable without ambiguities?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2015-01-10 21:33 ` Linus Walleij
(?)
@ 2015-01-12 12:22 ` Sascha Hauer
-1 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-12 12:22 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
Hi Linus,
On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Sorry for taking eternities to get back on this, I ran into a merge window
> and some christmas. I do hope we can resolve this in the current
> development cycle so we can get this support in.
No problem, I'm sure there are nicer things to do than discussing about
this topic ;)
I also hope we get this from the table soon.
> >>
> >> I am worried about semantic coexistance...
> >
> > We could rename the property from 'pins' to 'pinmux' for this variant of
> > the binding. Then a parser would know that this property is about pins
> > and muxing.
>
> OK sounds like a viable compromise.
Ok, will change this.
> I'm sorry about not migrating the ste,config part to
> generic bindings yet :( that is next.
>
> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> > nowhere.
>
> Is this a bug report about the documentation? I don't see how
> that is relevant to the overall design.
The best documentation is one that is not needed. I mandate to use
defines with combinations of pin with mux setting to reduce the
necessary documentation to: "Pick one (many) of these and you're done".
So my criticism here is not mainly that there is no documentation but
that the necessary documention would be very voluminous. Normally it
must cover all possible combinations of pin/mux settings. If you add
this you can equally well add it to defines instead, which makes it
impossible to write inconsistent device trees and makes it easier to
understand what's happening.
>
> > Only the sourcecode shows that this (totally made up) string
> > means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> > DB8500_PIN_D13 shall be muxed.
>
> So this pins and pins ambiguity (which has nothing to do with the
> generic bindings BTW) is now fixed up somewhat. The first thing is
> a group, the pins are pin names.
>
> > The corresponding ste,function property
> > has the value "ssp0" which again is not documented. The following config
> > nodes reference the same pins under a different name: "GPIO144_B13",
> > "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
>
> Yes, because it references individual pins, not groups. Config
> is per-pin, multiplexing is per-group in the Nomadik case.
> (Some hardware and drivers are different.)
>
> > Again, these strings are
> > completely undocumented and only the sourcecode shows which strings can
> > be used for the ste,pins property. Not only that no documentation shows
> > which strings are allowed, there's also no documentation which describes
> > which combination of strings for the different properties make sense.
>
> OK again a documentation bug report I guess, if you want to I can
> add this to the documentation (there are indeed some pin control
> drivers that list these groups and functions). This documentation was
> not written by me, but I can sure fix it up if that makes you happier.
>
> > The use of ## for concatenating defines in the driver makes the whole
> > stuff even harder to understand. It even took me quite a while to
> > realize that the binding requires me to configure the muxes in groups,
> > but the config as individual pins.
>
> The hardware is such that muxes are in groups and pin config per-pin.
> We cannot augment reality, just describe it in an as structured way
> as possible.
>
> To add to the complexity, some pin controllers mux things in groups,
> some per-pin (like freescale I think?) some controllers even do config
> of things like pull-up across groups of pins rather than individually.
>
> > So no, the current devicetrees are
> > not about readability.
>
> Is this an argument that goes away if I fix the documentation?
>
> > #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> > #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> > #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> > #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
> >
> > and we get:
> >
> > ssp0_snowball_mode: ssp0_snowball_default {
> > snowball_cfg1 {
> > pinmux = <GPIO144_B13_SSP0_FRM>;
> > ste,config = <&gpio_out_hi>;
> > };
> > snowball_cfg2 {
> > pinmux = <GPIO145_C13_SSP0_RXD>;
> > ste,config = <&in_pd>;
> > };
> > snowball_cfg3 {
> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> > ste,config = <&out_lo>;
> > };
> > };
>
> But this gives the false impression that pins can be muxed
> individually, and it makes it possible to write device trees that
> attempt to do so, while in practice it will not perform on the
> hardware.
If I understand the driver correctly on snowball (ab8500, right?) the
pins can be muxed individually. If you say that does not perform on the
hardware, that's something different. If a board designer decides to use
a pin northeast on the BGA and a pin southwest together for a single
I2C bus, then I as a device tree writer have no other choice but to
support this case, no matter if it's ideal or not. What's written in the
devicetree is dictated by the board designers, not the devicetree
writers.
I don't think board designers will create such a hardware just because
the Linux driver supports this. More likely they will create such a
hardware even though Linux does not support it ;)
>
> >> >> One node for the multiplexing, one node for the config. This is the
> >> >> pattern used by most drivers, so I want to have this structure.
> >> >>
> >> >> It is also easy to tell one node from the other: if it contains "function"
> >> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >> >
> >> > So when merging these together a node is always multiplexing and
> >> > configuration. But do we really win anything if both are separated? When
> >> > both are separated you still need an array of pins in the nodes to
> >> > tell which pins this node is for. If this array also contains the
> >> > mux information then this won't hurt. You can still ignore it.
> >>
> >> Well we definately have to support the case with split config and
> >> muxing nodes at least. I am very worried that we would get into
> >> ambguities where that is not possible.
> >
> > Sure we have as we cannot change existing bindings,
>
> For Nomadik I did, because there are no deployed systems suffering
> from it. I just had to use some board I had to make some kind of
> example. I would encourage any other system not deployed in the
> masses with flashed-in device trees to do the same as this is
> still somewhat in a flux.
In certain cases it may make sense to break existing device trees, I
just wanted to express that with any kind of generic binding I don't
want to enforce breaking existing bindings.
>
> I am worried that there is something in your reasoning that sort of
> assumes all pin controllers mux pins one-by-one and not in groups.
> How do we make it impossible to write a device tree that also
> make hardware that do groupwise config viable without ambiguities?
Sorry, I don't understand this sentence. What do you mean here?
The bindings I suggested are for individual pin based controllers
only. I know there are group based controllers, but I don't want to
change their bindings. I believe there is no single binding that is
good for both types of controllers.
I think we must face it that individual pin based controllers are
different from group based controllers. That's the main difference
between different pin controllers and I think there are good reasons
to reflect that in the device tree.
You often talk about ambiguities. Could you give an example what
ambiguities you mean? I can't think of a situation where the device tree
is ambiguous. I can only think of a common device tree parser that
misinterpretes the device tree, but that would be a problem in the
implementation, not with the binding.
Note that the way we combine pin/mux in a single define is not new,
the i.MX pin controller uses this already and so far I'm not aware of
any problems this makes. I wouldn't integrate the pinconf settings
in the same define again though, but for this part we have the generic
pinconf bindings.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-12 12:22 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-12 12:22 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he
Hi Linus,
On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Sorry for taking eternities to get back on this, I ran into a merge window
> and some christmas. I do hope we can resolve this in the current
> development cycle so we can get this support in.
No problem, I'm sure there are nicer things to do than discussing about
this topic ;)
I also hope we get this from the table soon.
> >>
> >> I am worried about semantic coexistance...
> >
> > We could rename the property from 'pins' to 'pinmux' for this variant of
> > the binding. Then a parser would know that this property is about pins
> > and muxing.
>
> OK sounds like a viable compromise.
Ok, will change this.
> I'm sorry about not migrating the ste,config part to
> generic bindings yet :( that is next.
>
> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> > nowhere.
>
> Is this a bug report about the documentation? I don't see how
> that is relevant to the overall design.
The best documentation is one that is not needed. I mandate to use
defines with combinations of pin with mux setting to reduce the
necessary documentation to: "Pick one (many) of these and you're done".
So my criticism here is not mainly that there is no documentation but
that the necessary documention would be very voluminous. Normally it
must cover all possible combinations of pin/mux settings. If you add
this you can equally well add it to defines instead, which makes it
impossible to write inconsistent device trees and makes it easier to
understand what's happening.
>
> > Only the sourcecode shows that this (totally made up) string
> > means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> > DB8500_PIN_D13 shall be muxed.
>
> So this pins and pins ambiguity (which has nothing to do with the
> generic bindings BTW) is now fixed up somewhat. The first thing is
> a group, the pins are pin names.
>
> > The corresponding ste,function property
> > has the value "ssp0" which again is not documented. The following config
> > nodes reference the same pins under a different name: "GPIO144_B13",
> > "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
>
> Yes, because it references individual pins, not groups. Config
> is per-pin, multiplexing is per-group in the Nomadik case.
> (Some hardware and drivers are different.)
>
> > Again, these strings are
> > completely undocumented and only the sourcecode shows which strings can
> > be used for the ste,pins property. Not only that no documentation shows
> > which strings are allowed, there's also no documentation which describes
> > which combination of strings for the different properties make sense.
>
> OK again a documentation bug report I guess, if you want to I can
> add this to the documentation (there are indeed some pin control
> drivers that list these groups and functions). This documentation was
> not written by me, but I can sure fix it up if that makes you happier.
>
> > The use of ## for concatenating defines in the driver makes the whole
> > stuff even harder to understand. It even took me quite a while to
> > realize that the binding requires me to configure the muxes in groups,
> > but the config as individual pins.
>
> The hardware is such that muxes are in groups and pin config per-pin.
> We cannot augment reality, just describe it in an as structured way
> as possible.
>
> To add to the complexity, some pin controllers mux things in groups,
> some per-pin (like freescale I think?) some controllers even do config
> of things like pull-up across groups of pins rather than individually.
>
> > So no, the current devicetrees are
> > not about readability.
>
> Is this an argument that goes away if I fix the documentation?
>
> > #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> > #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> > #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> > #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
> >
> > and we get:
> >
> > ssp0_snowball_mode: ssp0_snowball_default {
> > snowball_cfg1 {
> > pinmux = <GPIO144_B13_SSP0_FRM>;
> > ste,config = <&gpio_out_hi>;
> > };
> > snowball_cfg2 {
> > pinmux = <GPIO145_C13_SSP0_RXD>;
> > ste,config = <&in_pd>;
> > };
> > snowball_cfg3 {
> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> > ste,config = <&out_lo>;
> > };
> > };
>
> But this gives the false impression that pins can be muxed
> individually, and it makes it possible to write device trees that
> attempt to do so, while in practice it will not perform on the
> hardware.
If I understand the driver correctly on snowball (ab8500, right?) the
pins can be muxed individually. If you say that does not perform on the
hardware, that's something different. If a board designer decides to use
a pin northeast on the BGA and a pin southwest together for a single
I2C bus, then I as a device tree writer have no other choice but to
support this case, no matter if it's ideal or not. What's written in the
devicetree is dictated by the board designers, not the devicetree
writers.
I don't think board designers will create such a hardware just because
the Linux driver supports this. More likely they will create such a
hardware even though Linux does not support it ;)
>
> >> >> One node for the multiplexing, one node for the config. This is the
> >> >> pattern used by most drivers, so I want to have this structure.
> >> >>
> >> >> It is also easy to tell one node from the other: if it contains "function"
> >> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >> >
> >> > So when merging these together a node is always multiplexing and
> >> > configuration. But do we really win anything if both are separated? When
> >> > both are separated you still need an array of pins in the nodes to
> >> > tell which pins this node is for. If this array also contains the
> >> > mux information then this won't hurt. You can still ignore it.
> >>
> >> Well we definately have to support the case with split config and
> >> muxing nodes at least. I am very worried that we would get into
> >> ambguities where that is not possible.
> >
> > Sure we have as we cannot change existing bindings,
>
> For Nomadik I did, because there are no deployed systems suffering
> from it. I just had to use some board I had to make some kind of
> example. I would encourage any other system not deployed in the
> masses with flashed-in device trees to do the same as this is
> still somewhat in a flux.
In certain cases it may make sense to break existing device trees, I
just wanted to express that with any kind of generic binding I don't
want to enforce breaking existing bindings.
>
> I am worried that there is something in your reasoning that sort of
> assumes all pin controllers mux pins one-by-one and not in groups.
> How do we make it impossible to write a device tree that also
> make hardware that do groupwise config viable without ambiguities?
Sorry, I don't understand this sentence. What do you mean here?
The bindings I suggested are for individual pin based controllers
only. I know there are group based controllers, but I don't want to
change their bindings. I believe there is no single binding that is
good for both types of controllers.
I think we must face it that individual pin based controllers are
different from group based controllers. That's the main difference
between different pin controllers and I think there are good reasons
to reflect that in the device tree.
You often talk about ambiguities. Could you give an example what
ambiguities you mean? I can't think of a situation where the device tree
is ambiguous. I can only think of a common device tree parser that
misinterpretes the device tree, but that would be a problem in the
implementation, not with the binding.
Note that the way we combine pin/mux in a single define is not new,
the i.MX pin controller uses this already and so far I'm not aware of
any problems this makes. I wouldn't integrate the pinconf settings
in the same define again though, but for this part we have the generic
pinconf bindings.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-12 12:22 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-12 12:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Sorry for taking eternities to get back on this, I ran into a merge window
> and some christmas. I do hope we can resolve this in the current
> development cycle so we can get this support in.
No problem, I'm sure there are nicer things to do than discussing about
this topic ;)
I also hope we get this from the table soon.
> >>
> >> I am worried about semantic coexistance...
> >
> > We could rename the property from 'pins' to 'pinmux' for this variant of
> > the binding. Then a parser would know that this property is about pins
> > and muxing.
>
> OK sounds like a viable compromise.
Ok, will change this.
> I'm sorry about not migrating the ste,config part to
> generic bindings yet :( that is next.
>
> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
> > nowhere.
>
> Is this a bug report about the documentation? I don't see how
> that is relevant to the overall design.
The best documentation is one that is not needed. I mandate to use
defines with combinations of pin with mux setting to reduce the
necessary documentation to: "Pick one (many) of these and you're done".
So my criticism here is not mainly that there is no documentation but
that the necessary documention would be very voluminous. Normally it
must cover all possible combinations of pin/mux settings. If you add
this you can equally well add it to defines instead, which makes it
impossible to write inconsistent device trees and makes it easier to
understand what's happening.
>
> > Only the sourcecode shows that this (totally made up) string
> > means that the pins DB8500_PIN_D12, DB8500_PIN_B13, DB8500_PIN_C13 and
> > DB8500_PIN_D13 shall be muxed.
>
> So this pins and pins ambiguity (which has nothing to do with the
> generic bindings BTW) is now fixed up somewhat. The first thing is
> a group, the pins are pin names.
>
> > The corresponding ste,function property
> > has the value "ssp0" which again is not documented. The following config
> > nodes reference the same pins under a different name: "GPIO144_B13",
> > "GPIO145_C13", "GPIO146_D13" and "GPIO143_D12".
>
> Yes, because it references individual pins, not groups. Config
> is per-pin, multiplexing is per-group in the Nomadik case.
> (Some hardware and drivers are different.)
>
> > Again, these strings are
> > completely undocumented and only the sourcecode shows which strings can
> > be used for the ste,pins property. Not only that no documentation shows
> > which strings are allowed, there's also no documentation which describes
> > which combination of strings for the different properties make sense.
>
> OK again a documentation bug report I guess, if you want to I can
> add this to the documentation (there are indeed some pin control
> drivers that list these groups and functions). This documentation was
> not written by me, but I can sure fix it up if that makes you happier.
>
> > The use of ## for concatenating defines in the driver makes the whole
> > stuff even harder to understand. It even took me quite a while to
> > realize that the binding requires me to configure the muxes in groups,
> > but the config as individual pins.
>
> The hardware is such that muxes are in groups and pin config per-pin.
> We cannot augment reality, just describe it in an as structured way
> as possible.
>
> To add to the complexity, some pin controllers mux things in groups,
> some per-pin (like freescale I think?) some controllers even do config
> of things like pull-up across groups of pins rather than individually.
>
> > So no, the current devicetrees are
> > not about readability.
>
> Is this an argument that goes away if I fix the documentation?
>
> > #define GPIO143_D12_SSP0_CLK PINMUX_PIN(143, 1)
> > #define GPIO144_B13_SSP0_FRM PINMUX_PIN(144, 1)
> > #define GPIO145_C13_SSP0_RXD PINMUX_PIN(145, 1)
> > #define GPIO146_D13_SSP0_TXD PINMUX_PIN(146, 1)
> >
> > and we get:
> >
> > ssp0_snowball_mode: ssp0_snowball_default {
> > snowball_cfg1 {
> > pinmux = <GPIO144_B13_SSP0_FRM>;
> > ste,config = <&gpio_out_hi>;
> > };
> > snowball_cfg2 {
> > pinmux = <GPIO145_C13_SSP0_RXD>;
> > ste,config = <&in_pd>;
> > };
> > snowball_cfg3 {
> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
> > ste,config = <&out_lo>;
> > };
> > };
>
> But this gives the false impression that pins can be muxed
> individually, and it makes it possible to write device trees that
> attempt to do so, while in practice it will not perform on the
> hardware.
If I understand the driver correctly on snowball (ab8500, right?) the
pins can be muxed individually. If you say that does not perform on the
hardware, that's something different. If a board designer decides to use
a pin northeast on the BGA and a pin southwest together for a single
I2C bus, then I as a device tree writer have no other choice but to
support this case, no matter if it's ideal or not. What's written in the
devicetree is dictated by the board designers, not the devicetree
writers.
I don't think board designers will create such a hardware just because
the Linux driver supports this. More likely they will create such a
hardware even though Linux does not support it ;)
>
> >> >> One node for the multiplexing, one node for the config. This is the
> >> >> pattern used by most drivers, so I want to have this structure.
> >> >>
> >> >> It is also easy to tell one node from the other: if it contains "function"
> >> >> we know it's a multiplexing node, if it doesn't, it's a config node.
> >> >
> >> > So when merging these together a node is always multiplexing and
> >> > configuration. But do we really win anything if both are separated? When
> >> > both are separated you still need an array of pins in the nodes to
> >> > tell which pins this node is for. If this array also contains the
> >> > mux information then this won't hurt. You can still ignore it.
> >>
> >> Well we definately have to support the case with split config and
> >> muxing nodes at least. I am very worried that we would get into
> >> ambguities where that is not possible.
> >
> > Sure we have as we cannot change existing bindings,
>
> For Nomadik I did, because there are no deployed systems suffering
> from it. I just had to use some board I had to make some kind of
> example. I would encourage any other system not deployed in the
> masses with flashed-in device trees to do the same as this is
> still somewhat in a flux.
In certain cases it may make sense to break existing device trees, I
just wanted to express that with any kind of generic binding I don't
want to enforce breaking existing bindings.
>
> I am worried that there is something in your reasoning that sort of
> assumes all pin controllers mux pins one-by-one and not in groups.
> How do we make it impossible to write a device tree that also
> make hardware that do groupwise config viable without ambiguities?
Sorry, I don't understand this sentence. What do you mean here?
The bindings I suggested are for individual pin based controllers
only. I know there are group based controllers, but I don't want to
change their bindings. I believe there is no single binding that is
good for both types of controllers.
I think we must face it that individual pin based controllers are
different from group based controllers. That's the main difference
between different pin controllers and I think there are good reasons
to reflect that in the device tree.
You often talk about ambiguities. Could you give an example what
ambiguities you mean? I can't think of a situation where the device tree
is ambiguous. I can only think of a common device tree parser that
misinterpretes the device tree, but that would be a problem in the
implementation, not with the binding.
Note that the way we combine pin/mux in a single define is not new,
the i.MX pin controller uses this already and so far I'm not aware of
any problems this makes. I wouldn't integrate the pinconf settings
in the same define again though, but for this part we have the generic
pinconf bindings.
Sascha
--
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 10:05 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-13 10:05 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Mon, Jan 12, 2015 at 1:22 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
>> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
>> > nowhere.
>>
>> Is this a bug report about the documentation? I don't see how
>> that is relevant to the overall design.
>
> The best documentation is one that is not needed. I mandate to use
> defines with combinations of pin with mux setting to reduce the
> necessary documentation to: "Pick one (many) of these and you're done".
> So my criticism here is not mainly that there is no documentation but
> that the necessary documention would be very voluminous.
I don't know. I have since we discussed merged the long
overdue zynq driver that use this generic function+group mechanism.
The docs look like so:
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
(...)
Required properties for pinmux nodes are:
- groups: A list of pinmux groups.
- function: The name of a pinmux function to activate for the specified set
of groups.
Required properties for configuration nodes:
One of:
- pins: a list of pin names
- groups: A list of pinmux groups.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
groups, function
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
low-power-disable, low-power-enable
Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
respectively.
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp -
uart0_10_grp,
uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp -
i2c1_10_grp,
ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
Valid values for pins are:
MIO0 - MIO53
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
(...)
Example:
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
> Normally it
> must cover all possible combinations of pin/mux settings.
I think it's fairly intuitive to combine function uart1 with
group uart1_10_grp without documenting that this is a
valid combination. For complex stuff it may be complex,
but that is the nature of the complex hardware I think.
>> > ssp0_snowball_mode: ssp0_snowball_default {
>> > snowball_cfg1 {
>> > pinmux = <GPIO144_B13_SSP0_FRM>;
>> > ste,config = <&gpio_out_hi>;
>> > };
>> > snowball_cfg2 {
>> > pinmux = <GPIO145_C13_SSP0_RXD>;
>> > ste,config = <&in_pd>;
>> > };
>> > snowball_cfg3 {
>> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
>> > ste,config = <&out_lo>;
>> > };
>> > };
>>
>> But this gives the false impression that pins can be muxed
>> individually, and it makes it possible to write device trees that
>> attempt to do so, while in practice it will not perform on the
>> hardware.
>
> If I understand the driver correctly on snowball (ab8500, right?)
No that is drivers/pinctrl/nomadik/pinctrl-nomadik.c
and the db8500 subdriver pinctrl-nomadik-db8500.c
> the
> pins can be muxed individually.
Nope. They have individual registers per-pin, but if you try to
mux them in certain ways you will screw up the hardware or
even cause damage.
They also have to be reconfigured in batch in order to avoid
glitches on the lines, causing spurious IRQs & stuff.
So the driver has to restrict this by enforcing a groups concept
which is there in the hardware, but which is not visible in
the register map.
We have another driver under review, the Broadcom Cygnus.
This one configures a whole patch of pins with a single
register write and thus even reflects the non-one-register-per-pin
layout of the hardware in the register map.
http://marc.info/?l=linux-kernel&m=142113721817137&w=2
>> I am worried that there is something in your reasoning that sort of
>> assumes all pin controllers mux pins one-by-one and not in groups.
>> How do we make it impossible to write a device tree that also
>> make hardware that do groupwise config viable without ambiguities?
>
> Sorry, I don't understand this sentence. What do you mean here?
>
> The bindings I suggested are for individual pin based controllers
> only. I know there are group based controllers, but I don't want to
> change their bindings. I believe there is no single binding that is
> good for both types of controllers.
>
> I think we must face it that individual pin based controllers are
> different from group based controllers. That's the main difference
> between different pin controllers and I think there are good reasons
> to reflect that in the device tree.
OK let's work on a binding for this usecase.
> You often talk about ambiguities. Could you give an example what
> ambiguities you mean?
What happened was this pins = ; arguments were sometimes
strings and sometimes integers, that becomes strange to handle
in code, ambiguous.
I'm fuzzily referring to the concept of things being named the
same way in different device trees, yet lacking commonality,
confusing a human reader that they may be the same thing,
even if it is possible to write schemas and parsers handling
it unambigously, so not ambiguity in the formal logic sense.
If i later want to refactor the code around this to a central
parser I cannot do so because it would lead to formal ambiguities
and is non-doable.
> Note that the way we combine pin/mux in a single define is not new,
> the i.MX pin controller uses this already and so far I'm not aware of
> any problems this makes.
Yeah we never had time to sit down and come up with proper
generic pin control bindings, we went with custom bindings
partly because of general disagreements, partly because I
was new to device tree and honestly had no idea of how
to skin this cat.
Now that we get to formalize generic bindings for DT and
ACPI and whatever alike, I prefer if we make both groupwise
and per-pin pin controllers as strict and well defined as
possible.
One minor problem I have with using an integer for mux config
is that it assumes something about how many pins, configs etc
that may exist on such a system. This should be stated
explicitly in the bindings atleast so we know what restrictions
we build into them. String-based function+group matching has
no such restrictions.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 10:05 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-13 10:05 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
On Mon, Jan 12, 2015 at 1:22 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
>> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
>> > nowhere.
>>
>> Is this a bug report about the documentation? I don't see how
>> that is relevant to the overall design.
>
> The best documentation is one that is not needed. I mandate to use
> defines with combinations of pin with mux setting to reduce the
> necessary documentation to: "Pick one (many) of these and you're done".
> So my criticism here is not mainly that there is no documentation but
> that the necessary documention would be very voluminous.
I don't know. I have since we discussed merged the long
overdue zynq driver that use this generic function+group mechanism.
The docs look like so:
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
(...)
Required properties for pinmux nodes are:
- groups: A list of pinmux groups.
- function: The name of a pinmux function to activate for the specified set
of groups.
Required properties for configuration nodes:
One of:
- pins: a list of pin names
- groups: A list of pinmux groups.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
groups, function
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
low-power-disable, low-power-enable
Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
respectively.
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp -
uart0_10_grp,
uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp -
i2c1_10_grp,
ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
Valid values for pins are:
MIO0 - MIO53
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
(...)
Example:
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
> Normally it
> must cover all possible combinations of pin/mux settings.
I think it's fairly intuitive to combine function uart1 with
group uart1_10_grp without documenting that this is a
valid combination. For complex stuff it may be complex,
but that is the nature of the complex hardware I think.
>> > ssp0_snowball_mode: ssp0_snowball_default {
>> > snowball_cfg1 {
>> > pinmux = <GPIO144_B13_SSP0_FRM>;
>> > ste,config = <&gpio_out_hi>;
>> > };
>> > snowball_cfg2 {
>> > pinmux = <GPIO145_C13_SSP0_RXD>;
>> > ste,config = <&in_pd>;
>> > };
>> > snowball_cfg3 {
>> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
>> > ste,config = <&out_lo>;
>> > };
>> > };
>>
>> But this gives the false impression that pins can be muxed
>> individually, and it makes it possible to write device trees that
>> attempt to do so, while in practice it will not perform on the
>> hardware.
>
> If I understand the driver correctly on snowball (ab8500, right?)
No that is drivers/pinctrl/nomadik/pinctrl-nomadik.c
and the db8500 subdriver pinctrl-nomadik-db8500.c
> the
> pins can be muxed individually.
Nope. They have individual registers per-pin, but if you try to
mux them in certain ways you will screw up the hardware or
even cause damage.
They also have to be reconfigured in batch in order to avoid
glitches on the lines, causing spurious IRQs & stuff.
So the driver has to restrict this by enforcing a groups concept
which is there in the hardware, but which is not visible in
the register map.
We have another driver under review, the Broadcom Cygnus.
This one configures a whole patch of pins with a single
register write and thus even reflects the non-one-register-per-pin
layout of the hardware in the register map.
http://marc.info/?l=linux-kernel&m=142113721817137&w=2
>> I am worried that there is something in your reasoning that sort of
>> assumes all pin controllers mux pins one-by-one and not in groups.
>> How do we make it impossible to write a device tree that also
>> make hardware that do groupwise config viable without ambiguities?
>
> Sorry, I don't understand this sentence. What do you mean here?
>
> The bindings I suggested are for individual pin based controllers
> only. I know there are group based controllers, but I don't want to
> change their bindings. I believe there is no single binding that is
> good for both types of controllers.
>
> I think we must face it that individual pin based controllers are
> different from group based controllers. That's the main difference
> between different pin controllers and I think there are good reasons
> to reflect that in the device tree.
OK let's work on a binding for this usecase.
> You often talk about ambiguities. Could you give an example what
> ambiguities you mean?
What happened was this pins = ; arguments were sometimes
strings and sometimes integers, that becomes strange to handle
in code, ambiguous.
I'm fuzzily referring to the concept of things being named the
same way in different device trees, yet lacking commonality,
confusing a human reader that they may be the same thing,
even if it is possible to write schemas and parsers handling
it unambigously, so not ambiguity in the formal logic sense.
If i later want to refactor the code around this to a central
parser I cannot do so because it would lead to formal ambiguities
and is non-doable.
> Note that the way we combine pin/mux in a single define is not new,
> the i.MX pin controller uses this already and so far I'm not aware of
> any problems this makes.
Yeah we never had time to sit down and come up with proper
generic pin control bindings, we went with custom bindings
partly because of general disagreements, partly because I
was new to device tree and honestly had no idea of how
to skin this cat.
Now that we get to formalize generic bindings for DT and
ACPI and whatever alike, I prefer if we make both groupwise
and per-pin pin controllers as strict and well defined as
possible.
One minor problem I have with using an integer for mux config
is that it assumes something about how many pins, configs etc
that may exist on such a system. This should be stated
explicitly in the bindings atleast so we know what restrictions
we build into them. String-based function+group matching has
no such restrictions.
Yours,
Linus Walleij
--
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 10:05 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-13 10:05 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 12, 2015 at 1:22 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, Jan 10, 2015 at 10:33:46PM +0100, Linus Walleij wrote:
>> On Tue, Dec 2, 2014 at 2:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > For the SSP0 it needs the string "ssp0_a_1" which is documented exactly
>> > nowhere.
>>
>> Is this a bug report about the documentation? I don't see how
>> that is relevant to the overall design.
>
> The best documentation is one that is not needed. I mandate to use
> defines with combinations of pin with mux setting to reduce the
> necessary documentation to: "Pick one (many) of these and you're done".
> So my criticism here is not mainly that there is no documentation but
> that the necessary documention would be very voluminous.
I don't know. I have since we discussed merged the long
overdue zynq driver that use this generic function+group mechanism.
The docs look like so:
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
(...)
Required properties for pinmux nodes are:
- groups: A list of pinmux groups.
- function: The name of a pinmux function to activate for the specified set
of groups.
Required properties for configuration nodes:
One of:
- pins: a list of pin names
- groups: A list of pinmux groups.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
groups, function
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
low-power-disable, low-power-enable
Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
respectively.
Valid values for groups are:
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp -
uart0_10_grp,
uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp -
i2c1_10_grp,
ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
Valid values for pins are:
MIO0 - MIO53
Valid values for function are:
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
(...)
Example:
pinctrl0: pinctrl at 700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
};
> Normally it
> must cover all possible combinations of pin/mux settings.
I think it's fairly intuitive to combine function uart1 with
group uart1_10_grp without documenting that this is a
valid combination. For complex stuff it may be complex,
but that is the nature of the complex hardware I think.
>> > ssp0_snowball_mode: ssp0_snowball_default {
>> > snowball_cfg1 {
>> > pinmux = <GPIO144_B13_SSP0_FRM>;
>> > ste,config = <&gpio_out_hi>;
>> > };
>> > snowball_cfg2 {
>> > pinmux = <GPIO145_C13_SSP0_RXD>;
>> > ste,config = <&in_pd>;
>> > };
>> > snowball_cfg3 {
>> > pinmux = <GPIO143_D12_SSP0_CLK GPIO146_D13_SSP0_TXD>;
>> > ste,config = <&out_lo>;
>> > };
>> > };
>>
>> But this gives the false impression that pins can be muxed
>> individually, and it makes it possible to write device trees that
>> attempt to do so, while in practice it will not perform on the
>> hardware.
>
> If I understand the driver correctly on snowball (ab8500, right?)
No that is drivers/pinctrl/nomadik/pinctrl-nomadik.c
and the db8500 subdriver pinctrl-nomadik-db8500.c
> the
> pins can be muxed individually.
Nope. They have individual registers per-pin, but if you try to
mux them in certain ways you will screw up the hardware or
even cause damage.
They also have to be reconfigured in batch in order to avoid
glitches on the lines, causing spurious IRQs & stuff.
So the driver has to restrict this by enforcing a groups concept
which is there in the hardware, but which is not visible in
the register map.
We have another driver under review, the Broadcom Cygnus.
This one configures a whole patch of pins with a single
register write and thus even reflects the non-one-register-per-pin
layout of the hardware in the register map.
http://marc.info/?l=linux-kernel&m=142113721817137&w=2
>> I am worried that there is something in your reasoning that sort of
>> assumes all pin controllers mux pins one-by-one and not in groups.
>> How do we make it impossible to write a device tree that also
>> make hardware that do groupwise config viable without ambiguities?
>
> Sorry, I don't understand this sentence. What do you mean here?
>
> The bindings I suggested are for individual pin based controllers
> only. I know there are group based controllers, but I don't want to
> change their bindings. I believe there is no single binding that is
> good for both types of controllers.
>
> I think we must face it that individual pin based controllers are
> different from group based controllers. That's the main difference
> between different pin controllers and I think there are good reasons
> to reflect that in the device tree.
OK let's work on a binding for this usecase.
> You often talk about ambiguities. Could you give an example what
> ambiguities you mean?
What happened was this pins = ; arguments were sometimes
strings and sometimes integers, that becomes strange to handle
in code, ambiguous.
I'm fuzzily referring to the concept of things being named the
same way in different device trees, yet lacking commonality,
confusing a human reader that they may be the same thing,
even if it is possible to write schemas and parsers handling
it unambigously, so not ambiguity in the formal logic sense.
If i later want to refactor the code around this to a central
parser I cannot do so because it would lead to formal ambiguities
and is non-doable.
> Note that the way we combine pin/mux in a single define is not new,
> the i.MX pin controller uses this already and so far I'm not aware of
> any problems this makes.
Yeah we never had time to sit down and come up with proper
generic pin control bindings, we went with custom bindings
partly because of general disagreements, partly because I
was new to device tree and honestly had no idea of how
to skin this cat.
Now that we get to formalize generic bindings for DT and
ACPI and whatever alike, I prefer if we make both groupwise
and per-pin pin controllers as strict and well defined as
possible.
One minor problem I have with using an integer for mux config
is that it assumes something about how many pins, configs etc
that may exist on such a system. This should be stated
explicitly in the bindings atleast so we know what restrictions
we build into them. String-based function+group matching has
no such restrictions.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 16:16 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-13 16:16 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >> I am worried that there is something in your reasoning that sort of
> >> assumes all pin controllers mux pins one-by-one and not in groups.
> >> How do we make it impossible to write a device tree that also
> >> make hardware that do groupwise config viable without ambiguities?
> >
> > Sorry, I don't understand this sentence. What do you mean here?
> >
> > The bindings I suggested are for individual pin based controllers
> > only. I know there are group based controllers, but I don't want to
> > change their bindings. I believe there is no single binding that is
> > good for both types of controllers.
> >
> > I think we must face it that individual pin based controllers are
> > different from group based controllers. That's the main difference
> > between different pin controllers and I think there are good reasons
> > to reflect that in the device tree.
>
> OK let's work on a binding for this usecase.
Okay.
>
> > You often talk about ambiguities. Could you give an example what
> > ambiguities you mean?
>
> What happened was this pins = ; arguments were sometimes
> strings and sometimes integers, that becomes strange to handle
> in code, ambiguous.
I see. I like naming it 'pinmux' because that's what it is: pins and
mux settings. A plain 'pinno' suggests that it contains only pin mubers,
without mux setting. How about 'pin-no-mux'? We also could add an
explicit "pins-are-numbered" property instead of distinguishing this
by property names.
>
> I'm fuzzily referring to the concept of things being named the
> same way in different device trees, yet lacking commonality,
> confusing a human reader that they may be the same thing,
> even if it is possible to write schemas and parsers handling
> it unambigously, so not ambiguity in the formal logic sense.
>
> If i later want to refactor the code around this to a central
> parser I cannot do so because it would lead to formal ambiguities
> and is non-doable.
There could be a flag in the pinctroller struct indicating whether the
properties are to be interpreted as strings or as numbers.
>
> > Note that the way we combine pin/mux in a single define is not new,
> > the i.MX pin controller uses this already and so far I'm not aware of
> > any problems this makes.
>
> Yeah we never had time to sit down and come up with proper
> generic pin control bindings, we went with custom bindings
> partly because of general disagreements, partly because I
> was new to device tree and honestly had no idea of how
> to skin this cat.
>
> Now that we get to formalize generic bindings for DT and
> ACPI and whatever alike, I prefer if we make both groupwise
> and per-pin pin controllers as strict and well defined as
> possible.
>
> One minor problem I have with using an integer for mux config
> is that it assumes something about how many pins, configs etc
> that may exist on such a system. This should be stated
> explicitly in the bindings atleast so we know what restrictions
> we build into them. String-based function+group matching has
> no such restrictions.
No problem, that can be documented. Normally the defines should be used
anyway, not the plain pin numbers.
BTW one thing I really like about integers is the pure binary size. In
barebox I also parse the pinmux settings from the device tree. The
drivers using string matching are multiple times bigger due to the
string tables:
-rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
-rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 16:16 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-13 16:16 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >> I am worried that there is something in your reasoning that sort of
> >> assumes all pin controllers mux pins one-by-one and not in groups.
> >> How do we make it impossible to write a device tree that also
> >> make hardware that do groupwise config viable without ambiguities?
> >
> > Sorry, I don't understand this sentence. What do you mean here?
> >
> > The bindings I suggested are for individual pin based controllers
> > only. I know there are group based controllers, but I don't want to
> > change their bindings. I believe there is no single binding that is
> > good for both types of controllers.
> >
> > I think we must face it that individual pin based controllers are
> > different from group based controllers. That's the main difference
> > between different pin controllers and I think there are good reasons
> > to reflect that in the device tree.
>
> OK let's work on a binding for this usecase.
Okay.
>
> > You often talk about ambiguities. Could you give an example what
> > ambiguities you mean?
>
> What happened was this pins = ; arguments were sometimes
> strings and sometimes integers, that becomes strange to handle
> in code, ambiguous.
I see. I like naming it 'pinmux' because that's what it is: pins and
mux settings. A plain 'pinno' suggests that it contains only pin mubers,
without mux setting. How about 'pin-no-mux'? We also could add an
explicit "pins-are-numbered" property instead of distinguishing this
by property names.
>
> I'm fuzzily referring to the concept of things being named the
> same way in different device trees, yet lacking commonality,
> confusing a human reader that they may be the same thing,
> even if it is possible to write schemas and parsers handling
> it unambigously, so not ambiguity in the formal logic sense.
>
> If i later want to refactor the code around this to a central
> parser I cannot do so because it would lead to formal ambiguities
> and is non-doable.
There could be a flag in the pinctroller struct indicating whether the
properties are to be interpreted as strings or as numbers.
>
> > Note that the way we combine pin/mux in a single define is not new,
> > the i.MX pin controller uses this already and so far I'm not aware of
> > any problems this makes.
>
> Yeah we never had time to sit down and come up with proper
> generic pin control bindings, we went with custom bindings
> partly because of general disagreements, partly because I
> was new to device tree and honestly had no idea of how
> to skin this cat.
>
> Now that we get to formalize generic bindings for DT and
> ACPI and whatever alike, I prefer if we make both groupwise
> and per-pin pin controllers as strict and well defined as
> possible.
>
> One minor problem I have with using an integer for mux config
> is that it assumes something about how many pins, configs etc
> that may exist on such a system. This should be stated
> explicitly in the bindings atleast so we know what restrictions
> we build into them. String-based function+group matching has
> no such restrictions.
No problem, that can be documented. Normally the defines should be used
anyway, not the plain pin numbers.
BTW one thing I really like about integers is the pure binary size. In
barebox I also parse the pinmux settings from the device tree. The
drivers using string matching are multiple times bigger due to the
string tables:
-rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
-rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 16:16 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-13 16:16 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >> I am worried that there is something in your reasoning that sort of
> >> assumes all pin controllers mux pins one-by-one and not in groups.
> >> How do we make it impossible to write a device tree that also
> >> make hardware that do groupwise config viable without ambiguities?
> >
> > Sorry, I don't understand this sentence. What do you mean here?
> >
> > The bindings I suggested are for individual pin based controllers
> > only. I know there are group based controllers, but I don't want to
> > change their bindings. I believe there is no single binding that is
> > good for both types of controllers.
> >
> > I think we must face it that individual pin based controllers are
> > different from group based controllers. That's the main difference
> > between different pin controllers and I think there are good reasons
> > to reflect that in the device tree.
>
> OK let's work on a binding for this usecase.
Okay.
>
> > You often talk about ambiguities. Could you give an example what
> > ambiguities you mean?
>
> What happened was this pins = ; arguments were sometimes
> strings and sometimes integers, that becomes strange to handle
> in code, ambiguous.
I see. I like naming it 'pinmux' because that's what it is: pins and
mux settings. A plain 'pinno' suggests that it contains only pin mubers,
without mux setting. How about 'pin-no-mux'? We also could add an
explicit "pins-are-numbered" property instead of distinguishing this
by property names.
>
> I'm fuzzily referring to the concept of things being named the
> same way in different device trees, yet lacking commonality,
> confusing a human reader that they may be the same thing,
> even if it is possible to write schemas and parsers handling
> it unambigously, so not ambiguity in the formal logic sense.
>
> If i later want to refactor the code around this to a central
> parser I cannot do so because it would lead to formal ambiguities
> and is non-doable.
There could be a flag in the pinctroller struct indicating whether the
properties are to be interpreted as strings or as numbers.
>
> > Note that the way we combine pin/mux in a single define is not new,
> > the i.MX pin controller uses this already and so far I'm not aware of
> > any problems this makes.
>
> Yeah we never had time to sit down and come up with proper
> generic pin control bindings, we went with custom bindings
> partly because of general disagreements, partly because I
> was new to device tree and honestly had no idea of how
> to skin this cat.
>
> Now that we get to formalize generic bindings for DT and
> ACPI and whatever alike, I prefer if we make both groupwise
> and per-pin pin controllers as strict and well defined as
> possible.
>
> One minor problem I have with using an integer for mux config
> is that it assumes something about how many pins, configs etc
> that may exist on such a system. This should be stated
> explicitly in the bindings atleast so we know what restrictions
> we build into them. String-based function+group matching has
> no such restrictions.
No problem, that can be documented. Normally the defines should be used
anyway, not the plain pin numbers.
BTW one thing I really like about integers is the pure binary size. In
barebox I also parse the pinmux settings from the device tree. The
drivers using string matching are multiple times bigger due to the
string tables:
-rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
-rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2015-01-13 16:16 ` Sascha Hauer
(?)
@ 2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
-1 siblings, 0 replies; 59+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2015-01-13 16:24 UTC (permalink / raw)
To: Sascha Hauer
Cc: Jean-Christophe PLAGNIOL-VILLARD, Linus Walleij, Mark Rutland,
Heiko Stübner, Catalin Marinas, alan.cheng, Russell King,
Hongzhou Yang, toby.liu, Grant Likely, Joe.C, devicetree,
Vladimir Murzin, Pawel Moll, Ian Campbell, Rob Herring,
Matthias Brugger, dandan.he, huang eddie, linux-arm-kernel,
linux-kernel, Ashwin Chaugule, Sascha Hauer, Kumar Gala
> On Jan 14, 2015, at 12:16 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>>> I am worried that there is something in your reasoning that sort of
>>>> assumes all pin controllers mux pins one-by-one and not in groups.
>>>> How do we make it impossible to write a device tree that also
>>>> make hardware that do groupwise config viable without ambiguities?
>>>
>>> Sorry, I don't understand this sentence. What do you mean here?
>>>
>>> The bindings I suggested are for individual pin based controllers
>>> only. I know there are group based controllers, but I don't want to
>>> change their bindings. I believe there is no single binding that is
>>> good for both types of controllers.
>>>
>>> I think we must face it that individual pin based controllers are
>>> different from group based controllers. That's the main difference
>>> between different pin controllers and I think there are good reasons
>>> to reflect that in the device tree.
>>
>> OK let's work on a binding for this usecase.
>
> Okay.
>
>>
>>> You often talk about ambiguities. Could you give an example what
>>> ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
>
>>
>> I'm fuzzily referring to the concept of things being named the
>> same way in different device trees, yet lacking commonality,
>> confusing a human reader that they may be the same thing,
>> even if it is possible to write schemas and parsers handling
>> it unambigously, so not ambiguity in the formal logic sense.
>>
>> If i later want to refactor the code around this to a central
>> parser I cannot do so because it would lead to formal ambiguities
>> and is non-doable.
>
> There could be a flag in the pinctroller struct indicating whether the
> properties are to be interpreted as strings or as numbers.
>
>>
>>> Note that the way we combine pin/mux in a single define is not new,
>>> the i.MX pin controller uses this already and so far I'm not aware of
>>> any problems this makes.
>>
>> Yeah we never had time to sit down and come up with proper
>> generic pin control bindings, we went with custom bindings
>> partly because of general disagreements, partly because I
>> was new to device tree and honestly had no idea of how
>> to skin this cat.
>>
>> Now that we get to formalize generic bindings for DT and
>> ACPI and whatever alike, I prefer if we make both groupwise
>> and per-pin pin controllers as strict and well defined as
>> possible.
>>
>> One minor problem I have with using an integer for mux config
>> is that it assumes something about how many pins, configs etc
>> that may exist on such a system. This should be stated
>> explicitly in the bindings atleast so we know what restrictions
>> we build into them. String-based function+group matching has
>> no such restrictions.
>
> No problem, that can be documented. Normally the defines should be used
> anyway, not the plain pin numbers.
>
> BTW one thing I really like about integers is the pure binary size. In
> barebox I also parse the pinmux settings from the device tree. The
> drivers using string matching are multiple times bigger due to the
> string tables:
>
> -rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
> -rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Agreed with Sascha that’s why I chose integer for at91 too
if you want string just use define instead to make it more readable
Best Regards,
J.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 59+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2015-01-13 16:24 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mark Rutland, Heiko Stübner, Catalin Marinas, Linus Walleij,
alan.cheng, Russell King, Hongzhou Yang, toby.liu, Grant Likely,
Joe.C, Jean-Christophe PLAGNIOL-VILLARD, devicetree,
Vladimir Murzin, Pawel Moll, Ian Campbell, Rob Herring,
Matthias Brugger, dandan.he, huang eddie, linux-arm-kernel
> On Jan 14, 2015, at 12:16 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>>> I am worried that there is something in your reasoning that sort of
>>>> assumes all pin controllers mux pins one-by-one and not in groups.
>>>> How do we make it impossible to write a device tree that also
>>>> make hardware that do groupwise config viable without ambiguities?
>>>
>>> Sorry, I don't understand this sentence. What do you mean here?
>>>
>>> The bindings I suggested are for individual pin based controllers
>>> only. I know there are group based controllers, but I don't want to
>>> change their bindings. I believe there is no single binding that is
>>> good for both types of controllers.
>>>
>>> I think we must face it that individual pin based controllers are
>>> different from group based controllers. That's the main difference
>>> between different pin controllers and I think there are good reasons
>>> to reflect that in the device tree.
>>
>> OK let's work on a binding for this usecase.
>
> Okay.
>
>>
>>> You often talk about ambiguities. Could you give an example what
>>> ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
>
>>
>> I'm fuzzily referring to the concept of things being named the
>> same way in different device trees, yet lacking commonality,
>> confusing a human reader that they may be the same thing,
>> even if it is possible to write schemas and parsers handling
>> it unambigously, so not ambiguity in the formal logic sense.
>>
>> If i later want to refactor the code around this to a central
>> parser I cannot do so because it would lead to formal ambiguities
>> and is non-doable.
>
> There could be a flag in the pinctroller struct indicating whether the
> properties are to be interpreted as strings or as numbers.
>
>>
>>> Note that the way we combine pin/mux in a single define is not new,
>>> the i.MX pin controller uses this already and so far I'm not aware of
>>> any problems this makes.
>>
>> Yeah we never had time to sit down and come up with proper
>> generic pin control bindings, we went with custom bindings
>> partly because of general disagreements, partly because I
>> was new to device tree and honestly had no idea of how
>> to skin this cat.
>>
>> Now that we get to formalize generic bindings for DT and
>> ACPI and whatever alike, I prefer if we make both groupwise
>> and per-pin pin controllers as strict and well defined as
>> possible.
>>
>> One minor problem I have with using an integer for mux config
>> is that it assumes something about how many pins, configs etc
>> that may exist on such a system. This should be stated
>> explicitly in the bindings atleast so we know what restrictions
>> we build into them. String-based function+group matching has
>> no such restrictions.
>
> No problem, that can be documented. Normally the defines should be used
> anyway, not the plain pin numbers.
>
> BTW one thing I really like about integers is the pure binary size. In
> barebox I also parse the pinmux settings from the device tree. The
> drivers using string matching are multiple times bigger due to the
> string tables:
>
> -rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
> -rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Agreed with Sascha that’s why I chose integer for at91 too
if you want string just use define instead to make it more readable
Best Regards,
J.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 59+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2015-01-13 16:24 UTC (permalink / raw)
To: linux-arm-kernel
> On Jan 14, 2015, at 12:16 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>>> I am worried that there is something in your reasoning that sort of
>>>> assumes all pin controllers mux pins one-by-one and not in groups.
>>>> How do we make it impossible to write a device tree that also
>>>> make hardware that do groupwise config viable without ambiguities?
>>>
>>> Sorry, I don't understand this sentence. What do you mean here?
>>>
>>> The bindings I suggested are for individual pin based controllers
>>> only. I know there are group based controllers, but I don't want to
>>> change their bindings. I believe there is no single binding that is
>>> good for both types of controllers.
>>>
>>> I think we must face it that individual pin based controllers are
>>> different from group based controllers. That's the main difference
>>> between different pin controllers and I think there are good reasons
>>> to reflect that in the device tree.
>>
>> OK let's work on a binding for this usecase.
>
> Okay.
>
>>
>>> You often talk about ambiguities. Could you give an example what
>>> ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
>
>>
>> I'm fuzzily referring to the concept of things being named the
>> same way in different device trees, yet lacking commonality,
>> confusing a human reader that they may be the same thing,
>> even if it is possible to write schemas and parsers handling
>> it unambigously, so not ambiguity in the formal logic sense.
>>
>> If i later want to refactor the code around this to a central
>> parser I cannot do so because it would lead to formal ambiguities
>> and is non-doable.
>
> There could be a flag in the pinctroller struct indicating whether the
> properties are to be interpreted as strings or as numbers.
>
>>
>>> Note that the way we combine pin/mux in a single define is not new,
>>> the i.MX pin controller uses this already and so far I'm not aware of
>>> any problems this makes.
>>
>> Yeah we never had time to sit down and come up with proper
>> generic pin control bindings, we went with custom bindings
>> partly because of general disagreements, partly because I
>> was new to device tree and honestly had no idea of how
>> to skin this cat.
>>
>> Now that we get to formalize generic bindings for DT and
>> ACPI and whatever alike, I prefer if we make both groupwise
>> and per-pin pin controllers as strict and well defined as
>> possible.
>>
>> One minor problem I have with using an integer for mux config
>> is that it assumes something about how many pins, configs etc
>> that may exist on such a system. This should be stated
>> explicitly in the bindings atleast so we know what restrictions
>> we build into them. String-based function+group matching has
>> no such restrictions.
>
> No problem, that can be documented. Normally the defines should be used
> anyway, not the plain pin numbers.
>
> BTW one thing I really like about integers is the pure binary size. In
> barebox I also parse the pinmux settings from the device tree. The
> drivers using string matching are multiple times bigger due to the
> string tables:
>
> -rw-r--r-- 1 sha ptx 5436 Jan 13 15:00 imx-iomux-v3.o
> -rw-r--r-- 1 sha ptx 42060 Jan 13 15:00 pinctrl-tegra30.o
Agreed with Sascha that?s why I chose integer for at91 too
if you want string just use define instead to make it more readable
Best Regards,
J.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-16 9:53 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-16 9:53 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>> > You often talk about ambiguities. Could you give an example what
>> > ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
I kind of like this "pins-are-numbered" thing.
The other property for the pin, whether pinmux or pin-no-mux or
pin-num-and-mux etc is no such big deal, as long as it's
consistent and documented with the generic bindings.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-16 9:53 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-16 9:53 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Hongzhou Yang, Matthias Brugger, Sascha Hauer,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Russell King,
Grant Likely, Joe.C, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>> > You often talk about ambiguities. Could you give an example what
>> > ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
I kind of like this "pins-are-numbered" thing.
The other property for the pin, whether pinmux or pin-no-mux or
pin-num-and-mux etc is no such big deal, as long as it's
consistent and documented with the generic bindings.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-16 9:53 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-16 9:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>> > You often talk about ambiguities. Could you give an example what
>> > ambiguities you mean?
>>
>> What happened was this pins = ; arguments were sometimes
>> strings and sometimes integers, that becomes strange to handle
>> in code, ambiguous.
>
> I see. I like naming it 'pinmux' because that's what it is: pins and
> mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> without mux setting. How about 'pin-no-mux'? We also could add an
> explicit "pins-are-numbered" property instead of distinguishing this
> by property names.
I kind of like this "pins-are-numbered" thing.
The other property for the pin, whether pinmux or pin-no-mux or
pin-num-and-mux etc is no such big deal, as long as it's
consistent and documented with the generic bindings.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2015-01-16 9:53 ` Linus Walleij
(?)
@ 2015-01-16 10:23 ` Yingjoe Chen
-1 siblings, 0 replies; 59+ messages in thread
From: Yingjoe Chen @ 2015-01-16 10:23 UTC (permalink / raw)
To: Linus Walleij
Cc: Sascha Hauer, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>
> >> > You often talk about ambiguities. Could you give an example what
> >> > ambiguities you mean?
> >>
> >> What happened was this pins = ; arguments were sometimes
> >> strings and sometimes integers, that becomes strange to handle
> >> in code, ambiguous.
> >
> > I see. I like naming it 'pinmux' because that's what it is: pins and
> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> > without mux setting. How about 'pin-no-mux'? We also could add an
> > explicit "pins-are-numbered" property instead of distinguishing this
> > by property names.
>
> I kind of like this "pins-are-numbered" thing.
>
> The other property for the pin, whether pinmux or pin-no-mux or
> pin-num-and-mux etc is no such big deal, as long as it's
> consistent and documented with the generic bindings.
Hi Linus,
To make sure I understand it correct, you think something like this is
OK?
pinctrl@01c20800 {
compatible = "mediatek,mt8135-pinctrl";
[...]
pins-are-numbered;
i2c0_pins_a: i2c0@0 {
pins1 {
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
[....]
}
Joe.C
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-16 10:23 ` Yingjoe Chen
0 siblings, 0 replies; 59+ messages in thread
From: Yingjoe Chen @ 2015-01-16 10:23 UTC (permalink / raw)
To: Linus Walleij
Cc: Sascha Hauer, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he
On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>
> >> > You often talk about ambiguities. Could you give an example what
> >> > ambiguities you mean?
> >>
> >> What happened was this pins = ; arguments were sometimes
> >> strings and sometimes integers, that becomes strange to handle
> >> in code, ambiguous.
> >
> > I see. I like naming it 'pinmux' because that's what it is: pins and
> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> > without mux setting. How about 'pin-no-mux'? We also could add an
> > explicit "pins-are-numbered" property instead of distinguishing this
> > by property names.
>
> I kind of like this "pins-are-numbered" thing.
>
> The other property for the pin, whether pinmux or pin-no-mux or
> pin-num-and-mux etc is no such big deal, as long as it's
> consistent and documented with the generic bindings.
Hi Linus,
To make sure I understand it correct, you think something like this is
OK?
pinctrl@01c20800 {
compatible = "mediatek,mt8135-pinctrl";
[...]
pins-are-numbered;
i2c0_pins_a: i2c0@0 {
pins1 {
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
[....]
}
Joe.C
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-16 10:23 ` Yingjoe Chen
0 siblings, 0 replies; 59+ messages in thread
From: Yingjoe Chen @ 2015-01-16 10:23 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>
> >> > You often talk about ambiguities. Could you give an example what
> >> > ambiguities you mean?
> >>
> >> What happened was this pins = ; arguments were sometimes
> >> strings and sometimes integers, that becomes strange to handle
> >> in code, ambiguous.
> >
> > I see. I like naming it 'pinmux' because that's what it is: pins and
> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> > without mux setting. How about 'pin-no-mux'? We also could add an
> > explicit "pins-are-numbered" property instead of distinguishing this
> > by property names.
>
> I kind of like this "pins-are-numbered" thing.
>
> The other property for the pin, whether pinmux or pin-no-mux or
> pin-num-and-mux etc is no such big deal, as long as it's
> consistent and documented with the generic bindings.
Hi Linus,
To make sure I understand it correct, you think something like this is
OK?
pinctrl at 01c20800 {
compatible = "mediatek,mt8135-pinctrl";
[...]
pins-are-numbered;
i2c0_pins_a: i2c0 at 0 {
pins1 {
pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
[....]
}
Joe.C
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2015-01-16 10:23 ` Yingjoe Chen
(?)
@ 2015-01-20 9:45 ` Linus Walleij
-1 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-20 9:45 UTC (permalink / raw)
To: Yingjoe Chen
Cc: Sascha Hauer, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
<yingjoe.chen@mediatek.com> wrote:
> On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
>> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>
>> >> > You often talk about ambiguities. Could you give an example what
>> >> > ambiguities you mean?
>> >>
>> >> What happened was this pins = ; arguments were sometimes
>> >> strings and sometimes integers, that becomes strange to handle
>> >> in code, ambiguous.
>> >
>> > I see. I like naming it 'pinmux' because that's what it is: pins and
>> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
>> > without mux setting. How about 'pin-no-mux'? We also could add an
>> > explicit "pins-are-numbered" property instead of distinguishing this
>> > by property names.
>>
>> I kind of like this "pins-are-numbered" thing.
>>
>> The other property for the pin, whether pinmux or pin-no-mux or
>> pin-num-and-mux etc is no such big deal, as long as it's
>> consistent and documented with the generic bindings.
>
> Hi Linus,
>
> To make sure I understand it correct, you think something like this is
> OK?
>
> pinctrl@01c20800 {
> compatible = "mediatek,mt8135-pinctrl";
> [...]
> pins-are-numbered;
>
> i2c0_pins_a: i2c0@0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> bias-disable;
> };
> };
As discussed with Sascha Hauer it is ambigous to use "pins" for
a numerical value indicating both a mux setting and a pin. Sascha
suggests using "pinmux" and adding this as a secondary generic
binding for this type of pin controllers that use numbers and #defines
to set up bindings.
We should still move these parsing functions to the core.
See this discussion earlier in this thread:
http://marc.info/?l=linux-kernel&m=142116581226500&w=2
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-20 9:45 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-20 9:45 UTC (permalink / raw)
To: Yingjoe Chen
Cc: Sascha Hauer, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he-NuS5LvNUpcJWk0Htik3J/w
On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
<yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
>> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
>> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>
>> >> > You often talk about ambiguities. Could you give an example what
>> >> > ambiguities you mean?
>> >>
>> >> What happened was this pins = ; arguments were sometimes
>> >> strings and sometimes integers, that becomes strange to handle
>> >> in code, ambiguous.
>> >
>> > I see. I like naming it 'pinmux' because that's what it is: pins and
>> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
>> > without mux setting. How about 'pin-no-mux'? We also could add an
>> > explicit "pins-are-numbered" property instead of distinguishing this
>> > by property names.
>>
>> I kind of like this "pins-are-numbered" thing.
>>
>> The other property for the pin, whether pinmux or pin-no-mux or
>> pin-num-and-mux etc is no such big deal, as long as it's
>> consistent and documented with the generic bindings.
>
> Hi Linus,
>
> To make sure I understand it correct, you think something like this is
> OK?
>
> pinctrl@01c20800 {
> compatible = "mediatek,mt8135-pinctrl";
> [...]
> pins-are-numbered;
>
> i2c0_pins_a: i2c0@0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> bias-disable;
> };
> };
As discussed with Sascha Hauer it is ambigous to use "pins" for
a numerical value indicating both a mux setting and a pin. Sascha
suggests using "pinmux" and adding this as a secondary generic
binding for this type of pin controllers that use numbers and #defines
to set up bindings.
We should still move these parsing functions to the core.
See this discussion earlier in this thread:
http://marc.info/?l=linux-kernel&m=142116581226500&w=2
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-20 9:45 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-20 9:45 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
<yingjoe.chen@mediatek.com> wrote:
> On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
>> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
>>
>> >> > You often talk about ambiguities. Could you give an example what
>> >> > ambiguities you mean?
>> >>
>> >> What happened was this pins = ; arguments were sometimes
>> >> strings and sometimes integers, that becomes strange to handle
>> >> in code, ambiguous.
>> >
>> > I see. I like naming it 'pinmux' because that's what it is: pins and
>> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
>> > without mux setting. How about 'pin-no-mux'? We also could add an
>> > explicit "pins-are-numbered" property instead of distinguishing this
>> > by property names.
>>
>> I kind of like this "pins-are-numbered" thing.
>>
>> The other property for the pin, whether pinmux or pin-no-mux or
>> pin-num-and-mux etc is no such big deal, as long as it's
>> consistent and documented with the generic bindings.
>
> Hi Linus,
>
> To make sure I understand it correct, you think something like this is
> OK?
>
> pinctrl at 01c20800 {
> compatible = "mediatek,mt8135-pinctrl";
> [...]
> pins-are-numbered;
>
> i2c0_pins_a: i2c0 at 0 {
> pins1 {
> pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> bias-disable;
> };
> };
As discussed with Sascha Hauer it is ambigous to use "pins" for
a numerical value indicating both a mux setting and a pin. Sascha
suggests using "pinmux" and adding this as a secondary generic
binding for this type of pin controllers that use numbers and #defines
to set up bindings.
We should still move these parsing functions to the core.
See this discussion earlier in this thread:
http://marc.info/?l=linux-kernel&m=142116581226500&w=2
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-26 15:57 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-26 15:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Yingjoe Chen, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
Hi Linus,
On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
> On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
> <yingjoe.chen@mediatek.com> wrote:
> > On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> >> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >>
> >> >> > You often talk about ambiguities. Could you give an example what
> >> >> > ambiguities you mean?
> >> >>
> >> >> What happened was this pins = ; arguments were sometimes
> >> >> strings and sometimes integers, that becomes strange to handle
> >> >> in code, ambiguous.
> >> >
> >> > I see. I like naming it 'pinmux' because that's what it is: pins and
> >> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> >> > without mux setting. How about 'pin-no-mux'? We also could add an
> >> > explicit "pins-are-numbered" property instead of distinguishing this
> >> > by property names.
> >>
> >> I kind of like this "pins-are-numbered" thing.
> >>
> >> The other property for the pin, whether pinmux or pin-no-mux or
> >> pin-num-and-mux etc is no such big deal, as long as it's
> >> consistent and documented with the generic bindings.
> >
> > Hi Linus,
> >
> > To make sure I understand it correct, you think something like this is
> > OK?
> >
> > pinctrl@01c20800 {
> > compatible = "mediatek,mt8135-pinctrl";
> > [...]
> > pins-are-numbered;
> >
> > i2c0_pins_a: i2c0@0 {
> > pins1 {
> > pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > bias-disable;
> > };
> > };
>
> As discussed with Sascha Hauer it is ambigous to use "pins" for
> a numerical value indicating both a mux setting and a pin. Sascha
> suggests using "pinmux" and adding this as a secondary generic
> binding for this type of pin controllers that use numbers and #defines
> to set up bindings.
>
> We should still move these parsing functions to the core.
I tried that for the last few days and failed.
Part of the problem is that the core lacks the data structures to put
the information in. There is
struct pinctrl_map_mux {
const char *group;
const char *function;
};
but its meaning is SoC specific. Some SoCs combine the pins found in a
dt subnode to one group (i.MX, rockchip, at91) while others make an
individual group from each single pin (Tegra, others?). Also the
function string is SoC specific. Some SoCs just define functions like
"alt1".."altn" which are valid for all groups, others define different
function names for each group.
Another thing is that the binding gives us numbers, but struct
pinctrl_map_mux expects strings, so the numbers would have to be
converted to strings. This is crude since the contents of struct
pinctrl_map_mux are converted from strings back to numbers later from
the pinctrl core with the help of the driver. So we would have to
translate the numbers from the bindings to strings just to convert them
back to numbers before passing them to the driver later.
Given that the best I can come up with is something like:
int pinctrl_parse_pinmux(struct device_node *np, int index,
unsigned int *pinno, unsigned int *funcno)
{
u32 val;
int ret;
ret = of_property_read_u32_index(np, "pinmux", index, &val);
if (ret)
return ret;
*pinno = val >> 8
*funcno = val & 0xff;
return 0;
}
Is that what you expect from a common parser?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-26 15:57 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-26 15:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Yingjoe Chen, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, huang eddie,
dandan.he
Hi Linus,
On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
> On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
> <yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> > On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> >> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> >> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >>
> >> >> > You often talk about ambiguities. Could you give an example what
> >> >> > ambiguities you mean?
> >> >>
> >> >> What happened was this pins = ; arguments were sometimes
> >> >> strings and sometimes integers, that becomes strange to handle
> >> >> in code, ambiguous.
> >> >
> >> > I see. I like naming it 'pinmux' because that's what it is: pins and
> >> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> >> > without mux setting. How about 'pin-no-mux'? We also could add an
> >> > explicit "pins-are-numbered" property instead of distinguishing this
> >> > by property names.
> >>
> >> I kind of like this "pins-are-numbered" thing.
> >>
> >> The other property for the pin, whether pinmux or pin-no-mux or
> >> pin-num-and-mux etc is no such big deal, as long as it's
> >> consistent and documented with the generic bindings.
> >
> > Hi Linus,
> >
> > To make sure I understand it correct, you think something like this is
> > OK?
> >
> > pinctrl@01c20800 {
> > compatible = "mediatek,mt8135-pinctrl";
> > [...]
> > pins-are-numbered;
> >
> > i2c0_pins_a: i2c0@0 {
> > pins1 {
> > pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > bias-disable;
> > };
> > };
>
> As discussed with Sascha Hauer it is ambigous to use "pins" for
> a numerical value indicating both a mux setting and a pin. Sascha
> suggests using "pinmux" and adding this as a secondary generic
> binding for this type of pin controllers that use numbers and #defines
> to set up bindings.
>
> We should still move these parsing functions to the core.
I tried that for the last few days and failed.
Part of the problem is that the core lacks the data structures to put
the information in. There is
struct pinctrl_map_mux {
const char *group;
const char *function;
};
but its meaning is SoC specific. Some SoCs combine the pins found in a
dt subnode to one group (i.MX, rockchip, at91) while others make an
individual group from each single pin (Tegra, others?). Also the
function string is SoC specific. Some SoCs just define functions like
"alt1".."altn" which are valid for all groups, others define different
function names for each group.
Another thing is that the binding gives us numbers, but struct
pinctrl_map_mux expects strings, so the numbers would have to be
converted to strings. This is crude since the contents of struct
pinctrl_map_mux are converted from strings back to numbers later from
the pinctrl core with the help of the driver. So we would have to
translate the numbers from the bindings to strings just to convert them
back to numbers before passing them to the driver later.
Given that the best I can come up with is something like:
int pinctrl_parse_pinmux(struct device_node *np, int index,
unsigned int *pinno, unsigned int *funcno)
{
u32 val;
int ret;
ret = of_property_read_u32_index(np, "pinmux", index, &val);
if (ret)
return ret;
*pinno = val >> 8
*funcno = val & 0xff;
return 0;
}
Is that what you expect from a common parser?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-26 15:57 ` Sascha Hauer
0 siblings, 0 replies; 59+ messages in thread
From: Sascha Hauer @ 2015-01-26 15:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
> On Fri, Jan 16, 2015 at 11:23 AM, Yingjoe Chen
> <yingjoe.chen@mediatek.com> wrote:
> > On Fri, 2015-01-16 at 10:53 +0100, Linus Walleij wrote:
> >> On Tue, Jan 13, 2015 at 5:16 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >> > On Tue, Jan 13, 2015 at 11:05:22AM +0100, Linus Walleij wrote:
> >>
> >> >> > You often talk about ambiguities. Could you give an example what
> >> >> > ambiguities you mean?
> >> >>
> >> >> What happened was this pins = ; arguments were sometimes
> >> >> strings and sometimes integers, that becomes strange to handle
> >> >> in code, ambiguous.
> >> >
> >> > I see. I like naming it 'pinmux' because that's what it is: pins and
> >> > mux settings. A plain 'pinno' suggests that it contains only pin mubers,
> >> > without mux setting. How about 'pin-no-mux'? We also could add an
> >> > explicit "pins-are-numbered" property instead of distinguishing this
> >> > by property names.
> >>
> >> I kind of like this "pins-are-numbered" thing.
> >>
> >> The other property for the pin, whether pinmux or pin-no-mux or
> >> pin-num-and-mux etc is no such big deal, as long as it's
> >> consistent and documented with the generic bindings.
> >
> > Hi Linus,
> >
> > To make sure I understand it correct, you think something like this is
> > OK?
> >
> > pinctrl at 01c20800 {
> > compatible = "mediatek,mt8135-pinctrl";
> > [...]
> > pins-are-numbered;
> >
> > i2c0_pins_a: i2c0 at 0 {
> > pins1 {
> > pins = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
> > <MT8135_PIN_101_SCL0__FUNC_SCL0>;
> > bias-disable;
> > };
> > };
>
> As discussed with Sascha Hauer it is ambigous to use "pins" for
> a numerical value indicating both a mux setting and a pin. Sascha
> suggests using "pinmux" and adding this as a secondary generic
> binding for this type of pin controllers that use numbers and #defines
> to set up bindings.
>
> We should still move these parsing functions to the core.
I tried that for the last few days and failed.
Part of the problem is that the core lacks the data structures to put
the information in. There is
struct pinctrl_map_mux {
const char *group;
const char *function;
};
but its meaning is SoC specific. Some SoCs combine the pins found in a
dt subnode to one group (i.MX, rockchip, at91) while others make an
individual group from each single pin (Tegra, others?). Also the
function string is SoC specific. Some SoCs just define functions like
"alt1".."altn" which are valid for all groups, others define different
function names for each group.
Another thing is that the binding gives us numbers, but struct
pinctrl_map_mux expects strings, so the numbers would have to be
converted to strings. This is crude since the contents of struct
pinctrl_map_mux are converted from strings back to numbers later from
the pinctrl core with the help of the driver. So we would have to
translate the numbers from the bindings to strings just to convert them
back to numbers before passing them to the driver later.
Given that the best I can come up with is something like:
int pinctrl_parse_pinmux(struct device_node *np, int index,
unsigned int *pinno, unsigned int *funcno)
{
u32 val;
int ret;
ret = of_property_read_u32_index(np, "pinmux", index, &val);
if (ret)
return ret;
*pinno = val >> 8
*funcno = val & 0xff;
return 0;
}
Is that what you expect from a common parser?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
2015-01-26 15:57 ` Sascha Hauer
(?)
@ 2015-01-27 14:07 ` Linus Walleij
-1 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-27 14:07 UTC (permalink / raw)
To: Sascha Hauer
Cc: Yingjoe Chen, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he, alan.cheng, toby.liu
On Mon, Jan 26, 2015 at 4:57 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
>> As discussed with Sascha Hauer it is ambigous to use "pins" for
>> a numerical value indicating both a mux setting and a pin. Sascha
>> suggests using "pinmux" and adding this as a secondary generic
>> binding for this type of pin controllers that use numbers and #defines
>> to set up bindings.
>>
>> We should still move these parsing functions to the core.
>
> I tried that for the last few days and failed.
>
> Part of the problem is that the core lacks the data structures to put
> the information in. There is
>
> struct pinctrl_map_mux {
> const char *group;
> const char *function;
> };
>
> but its meaning is SoC specific. Some SoCs combine the pins found in a
> dt subnode to one group (i.MX, rockchip, at91) while others make an
> individual group from each single pin (Tegra, others?). Also the
> function string is SoC specific. Some SoCs just define functions like
> "alt1".."altn" which are valid for all groups, others define different
> function names for each group.
>
> Another thing is that the binding gives us numbers, but struct
> pinctrl_map_mux expects strings, so the numbers would have to be
> converted to strings. This is crude since the contents of struct
> pinctrl_map_mux are converted from strings back to numbers later from
> the pinctrl core with the help of the driver. So we would have to
> translate the numbers from the bindings to strings just to convert them
> back to numbers before passing them to the driver later.
So can we use a union?
struct pinctrl_map_mux {
union group {
const char *groupstr;
u16 groupno;
};
union function {
const char *functionstr;
u16 funcno;
};
};
The augment the code to reference foo->group.groupstr or
foo->group.groupno etc depending on runpath.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-27 14:07 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-27 14:07 UTC (permalink / raw)
To: Sascha Hauer
Cc: Yingjoe Chen, Rob Herring, Hongzhou Yang, Matthias Brugger,
Sascha Hauer, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Russell King, Grant Likely, Heiko Stübner, Catalin Marinas,
Vladimir Murzin, Ashwin Chaugule, devicetree, linux-kernel,
linux-arm-kernel, huang eddie, dandan.he
On Mon, Jan 26, 2015 at 4:57 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
>> As discussed with Sascha Hauer it is ambigous to use "pins" for
>> a numerical value indicating both a mux setting and a pin. Sascha
>> suggests using "pinmux" and adding this as a secondary generic
>> binding for this type of pin controllers that use numbers and #defines
>> to set up bindings.
>>
>> We should still move these parsing functions to the core.
>
> I tried that for the last few days and failed.
>
> Part of the problem is that the core lacks the data structures to put
> the information in. There is
>
> struct pinctrl_map_mux {
> const char *group;
> const char *function;
> };
>
> but its meaning is SoC specific. Some SoCs combine the pins found in a
> dt subnode to one group (i.MX, rockchip, at91) while others make an
> individual group from each single pin (Tegra, others?). Also the
> function string is SoC specific. Some SoCs just define functions like
> "alt1".."altn" which are valid for all groups, others define different
> function names for each group.
>
> Another thing is that the binding gives us numbers, but struct
> pinctrl_map_mux expects strings, so the numbers would have to be
> converted to strings. This is crude since the contents of struct
> pinctrl_map_mux are converted from strings back to numbers later from
> the pinctrl core with the help of the driver. So we would have to
> translate the numbers from the bindings to strings just to convert them
> back to numbers before passing them to the driver later.
So can we use a union?
struct pinctrl_map_mux {
union group {
const char *groupstr;
u16 groupno;
};
union function {
const char *functionstr;
u16 funcno;
};
};
The augment the code to reference foo->group.groupstr or
foo->group.groupno etc depending on runpath.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx.
@ 2015-01-27 14:07 ` Linus Walleij
0 siblings, 0 replies; 59+ messages in thread
From: Linus Walleij @ 2015-01-27 14:07 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 26, 2015 at 4:57 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Tue, Jan 20, 2015 at 10:45:09AM +0100, Linus Walleij wrote:
>> As discussed with Sascha Hauer it is ambigous to use "pins" for
>> a numerical value indicating both a mux setting and a pin. Sascha
>> suggests using "pinmux" and adding this as a secondary generic
>> binding for this type of pin controllers that use numbers and #defines
>> to set up bindings.
>>
>> We should still move these parsing functions to the core.
>
> I tried that for the last few days and failed.
>
> Part of the problem is that the core lacks the data structures to put
> the information in. There is
>
> struct pinctrl_map_mux {
> const char *group;
> const char *function;
> };
>
> but its meaning is SoC specific. Some SoCs combine the pins found in a
> dt subnode to one group (i.MX, rockchip, at91) while others make an
> individual group from each single pin (Tegra, others?). Also the
> function string is SoC specific. Some SoCs just define functions like
> "alt1".."altn" which are valid for all groups, others define different
> function names for each group.
>
> Another thing is that the binding gives us numbers, but struct
> pinctrl_map_mux expects strings, so the numbers would have to be
> converted to strings. This is crude since the contents of struct
> pinctrl_map_mux are converted from strings back to numbers later from
> the pinctrl core with the help of the driver. So we would have to
> translate the numbers from the bindings to strings just to convert them
> back to numbers before passing them to the driver later.
So can we use a union?
struct pinctrl_map_mux {
union group {
const char *groupstr;
u16 groupno;
};
union function {
const char *functionstr;
u16 funcno;
};
};
The augment the code to reference foo->group.groupstr or
foo->group.groupno etc depending on runpath.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 59+ messages in thread
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2014-11-11 12:38 [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Hongzhou Yang
2014-11-11 12:38 ` Hongzhou Yang
2014-11-11 12:38 ` [PATCH v3 1/3] ARM: mediatek: Add Pinctrl/GPIO driver for mt8135 Hongzhou Yang
2014-11-11 12:38 ` Hongzhou Yang
2014-11-27 9:14 ` Linus Walleij
2014-11-27 9:14 ` Linus Walleij
2014-11-27 9:14 ` Linus Walleij
2014-11-28 5:06 ` hongzhou yang
2014-11-28 5:06 ` hongzhou yang
2014-11-11 12:38 ` [PATCH v3 2/3] dt-bindings: Add pinctrl bindings for mt65xx/mt81xx Hongzhou Yang
2014-11-11 12:38 ` Hongzhou Yang
2014-11-27 8:44 ` Linus Walleij
2014-11-27 8:44 ` Linus Walleij
2014-11-27 8:44 ` Linus Walleij
2014-11-27 10:18 ` Sascha Hauer
2014-11-27 10:18 ` Sascha Hauer
2014-11-27 10:18 ` Sascha Hauer
2014-11-28 16:12 ` Linus Walleij
2014-11-28 16:12 ` Linus Walleij
2014-11-28 16:12 ` Linus Walleij
2014-12-02 13:55 ` Sascha Hauer
2014-12-02 13:55 ` Sascha Hauer
2014-12-02 13:55 ` Sascha Hauer
2015-01-10 21:33 ` Linus Walleij
2015-01-10 21:33 ` Linus Walleij
2015-01-10 21:33 ` Linus Walleij
2015-01-12 12:22 ` Sascha Hauer
2015-01-12 12:22 ` Sascha Hauer
2015-01-12 12:22 ` Sascha Hauer
2015-01-13 10:05 ` Linus Walleij
2015-01-13 10:05 ` Linus Walleij
2015-01-13 10:05 ` Linus Walleij
2015-01-13 16:16 ` Sascha Hauer
2015-01-13 16:16 ` Sascha Hauer
2015-01-13 16:16 ` Sascha Hauer
2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
2015-01-13 16:24 ` Jean-Christophe PLAGNIOL-VILLARD
2015-01-16 9:53 ` Linus Walleij
2015-01-16 9:53 ` Linus Walleij
2015-01-16 9:53 ` Linus Walleij
2015-01-16 10:23 ` Yingjoe Chen
2015-01-16 10:23 ` Yingjoe Chen
2015-01-16 10:23 ` Yingjoe Chen
2015-01-20 9:45 ` Linus Walleij
2015-01-20 9:45 ` Linus Walleij
2015-01-20 9:45 ` Linus Walleij
2015-01-26 15:57 ` Sascha Hauer
2015-01-26 15:57 ` Sascha Hauer
2015-01-26 15:57 ` Sascha Hauer
2015-01-27 14:07 ` Linus Walleij
2015-01-27 14:07 ` Linus Walleij
2015-01-27 14:07 ` Linus Walleij
2014-11-28 4:19 ` hongzhou yang
2014-11-28 4:19 ` hongzhou yang
2014-11-11 12:38 ` [PATCH v3 3/3] ARM: dts: mt8135: Add pinctrl/GPIO node for mt8135 Hongzhou Yang
2014-11-11 12:38 ` Hongzhou Yang
2014-11-18 16:24 ` [PATCH v3 0/3] Add Mediatek SoC Pinctrl/GPIO driver for MT8135 Sascha Hauer
2014-11-18 16:24 ` Sascha Hauer
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