All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits
@ 2015-05-14 14:41 Damien Lespiau
  2015-05-15  8:57 ` Jani Nikula
  2015-05-15  9:09 ` Chris Wilson
  0 siblings, 2 replies; 4+ messages in thread
From: Damien Lespiau @ 2015-05-14 14:41 UTC (permalink / raw)
  To: intel-gfx

gem_bad_blit.c: In function ‘bad_blit’:
gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
   OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 tests/gem_bad_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
index 593167c..366b182 100644
--- a/tests/gem_bad_blit.c
+++ b/tests/gem_bad_blit.c
@@ -60,7 +60,7 @@
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 
-#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
+#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */
 
 static void
 bad_blit(drm_intel_bo *src_bo, uint32_t devid)
-- 
2.1.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits
  2015-05-14 14:41 [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits Damien Lespiau
@ 2015-05-15  8:57 ` Jani Nikula
  2015-05-15  9:09 ` Chris Wilson
  1 sibling, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2015-05-15  8:57 UTC (permalink / raw)
  To: Damien Lespiau, intel-gfx

On Thu, 14 May 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> gem_bad_blit.c: In function ‘bad_blit’:
> gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
>    OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  tests/gem_bad_blit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
> index 593167c..366b182 100644
> --- a/tests/gem_bad_blit.c
> +++ b/tests/gem_bad_blit.c
> @@ -60,7 +60,7 @@
>  static drm_intel_bufmgr *bufmgr;
>  struct intel_batchbuffer *batch;
>  
> -#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
> +#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */

Why not three pairs of braces? Or... *gasp* just one? ;)

Jani.

>  
>  static void
>  bad_blit(drm_intel_bo *src_bo, uint32_t devid)
> -- 
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits
  2015-05-14 14:41 [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits Damien Lespiau
  2015-05-15  8:57 ` Jani Nikula
@ 2015-05-15  9:09 ` Chris Wilson
  2015-05-18  8:10   ` Daniel Vetter
  1 sibling, 1 reply; 4+ messages in thread
From: Chris Wilson @ 2015-05-15  9:09 UTC (permalink / raw)
  To: Damien Lespiau; +Cc: intel-gfx

On Thu, May 14, 2015 at 03:41:54PM +0100, Damien Lespiau wrote:
> gem_bad_blit.c: In function ‘bad_blit’:
> gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
>    OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  tests/gem_bad_blit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
> index 593167c..366b182 100644
> --- a/tests/gem_bad_blit.c
> +++ b/tests/gem_bad_blit.c
> @@ -60,7 +60,7 @@
>  static drm_intel_bufmgr *bufmgr;
>  struct intel_batchbuffer *batch;
>  
> -#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
> +#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */

Hmm, that comment and this test do not make sense. It has not been a bad
blit since g33.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits
  2015-05-15  9:09 ` Chris Wilson
@ 2015-05-18  8:10   ` Daniel Vetter
  0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2015-05-18  8:10 UTC (permalink / raw)
  To: Chris Wilson, Damien Lespiau, intel-gfx

On Fri, May 15, 2015 at 10:09:34AM +0100, Chris Wilson wrote:
> On Thu, May 14, 2015 at 03:41:54PM +0100, Damien Lespiau wrote:
> > gem_bad_blit.c: In function ‘bad_blit’:
> > gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
> >    OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > ---
> >  tests/gem_bad_blit.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
> > index 593167c..366b182 100644
> > --- a/tests/gem_bad_blit.c
> > +++ b/tests/gem_bad_blit.c
> > @@ -60,7 +60,7 @@
> >  static drm_intel_bufmgr *bufmgr;
> >  struct intel_batchbuffer *batch;
> >  
> > -#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
> > +#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */
> 
> Hmm, that comment and this test do not make sense. It has not been a bad
> blit since g33.

Yeah, I guess time to git rm gem_bad_blt. We have the hangman now to
exercise the reset/hang detection manchinery.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-05-18  8:08 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-14 14:41 [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits Damien Lespiau
2015-05-15  8:57 ` Jani Nikula
2015-05-15  9:09 ` Chris Wilson
2015-05-18  8:10   ` Daniel Vetter

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.