From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org, blogic@openwrt.org, cernekee@gmail.com,
jon.fraser@broadcom.com, pgynther@google.com,
paul.burton@imgtec.com, ddaney.cavm@gmail.com,
Florian Fainelli <f.fainelli@gmail.com>
Subject: [PATCH 2/6] MIPS: BMIPS: Add early CPU initialization code
Date: Tue, 9 Feb 2016 12:55:50 -0800 [thread overview]
Message-ID: <1455051354-6225-3-git-send-email-f.fainelli@gmail.com> (raw)
In-Reply-To: <1455051354-6225-1-git-send-email-f.fainelli@gmail.com>
Port the stblinux-3.3 code to perform a bunch of CPU-specific initialization,
make it compatible with run-time detection of the CPU, and unroll the
brcmstb-specific macros: BDEV_RB(), BDEV_UNSET.
The "pref 30" disabling is done as a quirk. This is a preliminary change to
allow the use of the "rotr" instruction gated by cpu_has_rixi.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/bmips/setup.c | 1 +
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 87 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 9c8f15daf5e9..de31559f6f72 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -127,6 +127,7 @@ static const struct bmips_quirk bmips_quirk_list[] = {
void __init prom_init(void)
{
+ bmips_cpu_setup();
register_bmips_smp_ops();
}
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 6d25ad33ec78..a92aee7b977a 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -88,6 +88,7 @@ extern unsigned long bmips_tp1_irqs;
extern void bmips_ebase_setup(void);
extern asmlinkage void plat_wired_tlb_setup(void);
+extern void bmips_cpu_setup(void);
static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
{
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 78cf8c2f1de0..6835cb13ea9e 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -565,3 +565,90 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
* once the wired entries are present.
*/
}
+
+void __init bmips_cpu_setup(void)
+{
+ void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
+ u32 __maybe_unused cfg;
+
+ switch (current_cpu_type()) {
+ case CPU_BMIPS3300:
+ /* Set BIU to async mode */
+ set_c0_brcm_bus_pll(BIT(22));
+ __sync();
+
+ /* put the BIU back in sync mode */
+ clear_c0_brcm_bus_pll(BIT(22));
+
+ /* clear BHTD to enable branch history table */
+ clear_c0_brcm_reset(BIT(16));
+
+ /* Flush and enable RAC */
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG);
+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
+
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG);
+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
+
+ cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
+ __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
+ __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
+ break;
+
+ case CPU_BMIPS4380:
+ /* CBG workaround for early BMIPS4380 CPUs */
+ switch (read_c0_prid()) {
+ case 0x2a040:
+ case 0x2a042:
+ case 0x2a044:
+ case 0x2a060:
+ cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
+ __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
+ __raw_readl(cbr + BMIPS_L2_CONFIG);
+ }
+
+ /* clear BHTD to enable branch history table */
+ clear_c0_brcm_config_0(BIT(21));
+
+ /* XI/ROTR enable */
+ set_c0_brcm_config_0(BIT(23));
+ set_c0_brcm_cmt_ctrl(BIT(15));
+ break;
+
+ case CPU_BMIPS5000:
+ /* enable RDHWR, BRDHWR */
+ set_c0_brcm_config(BIT(17) | BIT(21));
+
+ /* Disable JTB */
+ __asm__ __volatile__(
+ " .set noreorder\n"
+ " li $8, 0x5a455048\n"
+ " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
+ " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
+ " li $9, 0x00008000\n"
+ " or $8, $8, $9\n"
+ " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
+ " sync\n"
+ " li $8, 0x0\n"
+ " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
+ " .set reorder\n"
+ : : : "$8", "$9");
+
+ /* XI enable */
+ set_c0_brcm_config(BIT(27));
+
+ /* enable MIPS32R2 ROR instruction for XI TLB handlers */
+ __asm__ __volatile__(
+ " li $8, 0x5a455048\n"
+ " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
+ " nop; nop; nop\n"
+ " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
+ " lui $9, 0x0100\n"
+ " or $8, $9\n"
+ " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
+ : : : "$8", "$9");
+ break;
+ }
+}
--
2.1.0
next prev parent reply other threads:[~2016-02-09 20:56 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 20:55 [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
2016-02-09 20:55 ` [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs Florian Fainelli
2016-02-09 21:01 ` Florian Fainelli
2016-02-09 23:42 ` Petri Gynther
2016-02-09 23:45 ` Florian Fainelli
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 22:40 ` Florian Fainelli
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-10 0:04 ` Florian Fainelli
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 9:20 ` Ralf Baechle
2016-02-10 9:22 ` Ralf Baechle
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-09 20:55 ` Florian Fainelli [this message]
2016-02-09 20:55 ` [PATCH 3/6] MIPS: Allow RIXI to be used on non-R2 or R6 cores Florian Fainelli
2016-02-09 20:55 ` [PATCH 4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe Florian Fainelli
2016-02-09 20:55 ` [PATCH 5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI Florian Fainelli
2016-02-09 20:55 ` [PATCH 6/6] MIPS: Expose current_cpu_data.options through debugfs Florian Fainelli
2016-02-10 10:46 ` Ralf Baechle
2016-02-11 1:58 ` Florian Fainelli
2016-03-29 1:38 ` [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
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