From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org, blogic@openwrt.org, cernekee@gmail.com,
jon.fraser@broadcom.com, pgynther@google.com,
paul.burton@imgtec.com, ddaney.cavm@gmail.com
Subject: Re: [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs
Date: Tue, 9 Feb 2016 13:01:53 -0800 [thread overview]
Message-ID: <56BA53C1.3080004@gmail.com> (raw)
In-Reply-To: <1455051354-6225-2-git-send-email-f.fainelli@gmail.com>
On 09/02/16 12:55, Florian Fainelli wrote:
> Disable pref 30 by utilizing the standard quirk method and matching the
> affected SoCs: 7344, 7436, 7425.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> arch/mips/bmips/setup.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
> index 35535284b39e..9c8f15daf5e9 100644
> --- a/arch/mips/bmips/setup.c
> +++ b/arch/mips/bmips/setup.c
> @@ -100,12 +100,28 @@ static void bcm6368_quirks(void)
> bcm63xx_fixup_cpu1();
> }
>
> +static void bmips5000_pref30_quirk(void)
> +{
> + __asm__ __volatile__(
> + " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
> + " lui $9, 0x0100\n"
> + " or $8, $9\n"
> + /* disable "pref 30" on buggy CPUs */
> + " lui $9, 0x0800\n"
> + " or $8, $9\n"
> + " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
> + : : : "$8", "$9");
We are missing an additional load here to $8, I will respin this patch,
but would appreciate feedback on the other patches of the series so I
can address everything at once. Thanks!
> +}
> +
> static const struct bmips_quirk bmips_quirk_list[] = {
> { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
> { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
> { "brcm,bcm6328", &bcm6328_quirks },
> { "brcm,bcm6368", &bcm6368_quirks },
> { "brcm,bcm63168", &bcm6368_quirks },
> + { "brcm,bcm7344", &bmips5000_pref30_quirk },
> + { "brcm,bcm7346", &bmips5000_pref30_quirk },
> + { "brcm,bcm7425", &bmips5000_pref30_quirk },
> { },
> };
>
>
--
Florian
next prev parent reply other threads:[~2016-02-09 21:03 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 20:55 [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
2016-02-09 20:55 ` [PATCH 1/6] MIPS: BMIPS: Disable pref 30 for buggy CPUs Florian Fainelli
2016-02-09 21:01 ` Florian Fainelli [this message]
2016-02-09 23:42 ` Petri Gynther
2016-02-09 23:45 ` Florian Fainelli
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 21:19 ` Maciej W. Rozycki
2016-02-09 22:40 ` Florian Fainelli
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-09 23:52 ` Maciej W. Rozycki
2016-02-10 0:04 ` Florian Fainelli
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 0:54 ` Maciej W. Rozycki
2016-02-10 9:20 ` Ralf Baechle
2016-02-10 9:22 ` Ralf Baechle
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-10 14:20 ` Maciej W. Rozycki
2016-02-09 20:55 ` [PATCH 2/6] MIPS: BMIPS: Add early CPU initialization code Florian Fainelli
2016-02-09 20:55 ` [PATCH 3/6] MIPS: Allow RIXI to be used on non-R2 or R6 cores Florian Fainelli
2016-02-09 20:55 ` [PATCH 4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe Florian Fainelli
2016-02-09 20:55 ` [PATCH 5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI Florian Fainelli
2016-02-09 20:55 ` [PATCH 6/6] MIPS: Expose current_cpu_data.options through debugfs Florian Fainelli
2016-02-10 10:46 ` Ralf Baechle
2016-02-11 1:58 ` Florian Fainelli
2016-03-29 1:38 ` [PATCH 0/6] MIPS: BMIPS: RIXI and workarounds support Florian Fainelli
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