From: Mathieu Poirier <mathieu.poirier@linaro.org> To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com Cc: linux-kernel@vger.kernel.org Subject: [PATCH V4 13/18] coresight: tmc: make sysFS and Perf mode mutually exclusive Date: Tue, 26 Apr 2016 16:10:29 -0600 [thread overview] Message-ID: <1461708634-6327-14-git-send-email-mathieu.poirier@linaro.org> (raw) In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 60 +++++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 62 +++++++++++++++++++++++-- 2 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index b5e5e6ac67eb..b11c52be54a9 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -111,7 +111,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev, u32 mode) { int ret = 0; bool used = false; @@ -185,6 +185,54 @@ out: return ret; } +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, u32 mode) +{ + int ret = 0; + long val; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* This shouldn't be happening */ + if (WARN_ON(mode != CS_MODE_PERF)) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + ret = -EINVAL; + goto out; + } + + val = local_xchg(&drvdata->mode, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETB/ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + ret = -EINVAL; + goto out; + } + + tmc_etb_enable_hw(drvdata); +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return ret; +} + +static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etf_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etf_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + static void tmc_disable_etf_sink(struct coresight_device *csdev) { long val; @@ -267,6 +315,7 @@ const struct coresight_ops tmc_etf_cs_ops = { int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) { + long val; enum tmc_mode mode; int ret = 0; unsigned long flags; @@ -290,6 +339,13 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; } + val = local_read(&drvdata->mode); + /* Don't interfere if operated from Perf */ + if (val == CS_MODE_PERF) { + ret = -EINVAL; + goto out; + } + /* If drvdata::buf is NULL the trace data has been read already */ if (drvdata->buf == NULL) { ret = -EINVAL; @@ -297,7 +353,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (local_read(&drvdata->mode) == CS_MODE_SYSFS) + if (val == CS_MODE_SYSFS) tmc_etb_disable_hw(drvdata); drvdata->reading = true; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 7208584d0da7..847d1b5f2c13 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -87,7 +87,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode) { int ret = 0; bool used = false; @@ -165,6 +165,54 @@ out: return ret; } +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode) +{ + int ret = 0; + long val; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* This shouldn't be happening */ + if (WARN_ON(mode != CS_MODE_PERF)) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + ret = -EINVAL; + goto out; + } + + val = local_xchg(&drvdata->mode, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + ret = -EINVAL; + goto out; + } + + tmc_etr_enable_hw(drvdata); +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return ret; +} + +static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etr_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etr_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + static void tmc_disable_etr_sink(struct coresight_device *csdev) { long val; @@ -199,6 +247,7 @@ const struct coresight_ops tmc_etr_cs_ops = { int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret = 0; + long val; unsigned long flags; /* config types are set a boot time and never change */ @@ -211,6 +260,13 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) goto out; } + val = local_read(&drvdata->mode); + /* Don't interfere if operated from Perf */ + if (val == CS_MODE_PERF) { + ret = -EINVAL; + goto out; + } + /* If drvdata::buf is NULL the trace data has been read already */ if (drvdata->buf == NULL) { ret = -EINVAL; @@ -218,14 +274,14 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (local_read(&drvdata->mode) == CS_MODE_SYSFS) + if (val == CS_MODE_SYSFS) tmc_etr_disable_hw(drvdata); drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); - return 0; + return ret; } int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) -- 2.5.0
WARNING: multiple messages have this Message-ID (diff)
From: mathieu.poirier@linaro.org (Mathieu Poirier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V4 13/18] coresight: tmc: make sysFS and Perf mode mutually exclusive Date: Tue, 26 Apr 2016 16:10:29 -0600 [thread overview] Message-ID: <1461708634-6327-14-git-send-email-mathieu.poirier@linaro.org> (raw) In-Reply-To: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 60 +++++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 62 +++++++++++++++++++++++-- 2 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index b5e5e6ac67eb..b11c52be54a9 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -111,7 +111,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev, u32 mode) { int ret = 0; bool used = false; @@ -185,6 +185,54 @@ out: return ret; } +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, u32 mode) +{ + int ret = 0; + long val; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* This shouldn't be happening */ + if (WARN_ON(mode != CS_MODE_PERF)) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + ret = -EINVAL; + goto out; + } + + val = local_xchg(&drvdata->mode, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETB/ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + ret = -EINVAL; + goto out; + } + + tmc_etb_enable_hw(drvdata); +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return ret; +} + +static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etf_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etf_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + static void tmc_disable_etf_sink(struct coresight_device *csdev) { long val; @@ -267,6 +315,7 @@ const struct coresight_ops tmc_etf_cs_ops = { int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) { + long val; enum tmc_mode mode; int ret = 0; unsigned long flags; @@ -290,6 +339,13 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; } + val = local_read(&drvdata->mode); + /* Don't interfere if operated from Perf */ + if (val == CS_MODE_PERF) { + ret = -EINVAL; + goto out; + } + /* If drvdata::buf is NULL the trace data has been read already */ if (drvdata->buf == NULL) { ret = -EINVAL; @@ -297,7 +353,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (local_read(&drvdata->mode) == CS_MODE_SYSFS) + if (val == CS_MODE_SYSFS) tmc_etb_disable_hw(drvdata); drvdata->reading = true; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 7208584d0da7..847d1b5f2c13 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -87,7 +87,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode) { int ret = 0; bool used = false; @@ -165,6 +165,54 @@ out: return ret; } +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode) +{ + int ret = 0; + long val; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* This shouldn't be happening */ + if (WARN_ON(mode != CS_MODE_PERF)) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + ret = -EINVAL; + goto out; + } + + val = local_xchg(&drvdata->mode, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + ret = -EINVAL; + goto out; + } + + tmc_etr_enable_hw(drvdata); +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return ret; +} + +static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etr_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etr_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + static void tmc_disable_etr_sink(struct coresight_device *csdev) { long val; @@ -199,6 +247,7 @@ const struct coresight_ops tmc_etr_cs_ops = { int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret = 0; + long val; unsigned long flags; /* config types are set a boot time and never change */ @@ -211,6 +260,13 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) goto out; } + val = local_read(&drvdata->mode); + /* Don't interfere if operated from Perf */ + if (val == CS_MODE_PERF) { + ret = -EINVAL; + goto out; + } + /* If drvdata::buf is NULL the trace data has been read already */ if (drvdata->buf == NULL) { ret = -EINVAL; @@ -218,14 +274,14 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (local_read(&drvdata->mode) == CS_MODE_SYSFS) + if (val == CS_MODE_SYSFS) tmc_etr_disable_hw(drvdata); drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); - return 0; + return ret; } int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) -- 2.5.0
next prev parent reply other threads:[~2016-04-26 22:11 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-04-26 22:10 [PATCH V4 00/18] coresight: tmc: make driver usable by Perf Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 01/18] coresight: tmc: modifying naming convention Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 02/18] coresight: tmc: waiting for TMCReady bit before programming Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 03/18] coresight: tmc: re-implementing tmc_read_prepare/unprepare() functions Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 04/18] coresight: tmc: clearly define number of transfers per burst Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 05/18] coresight: tmc: introducing new header file Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 06/18] coresight: tmc: cleaning up " Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 07/18] coresight: tmc: splitting driver in ETB/ETF and ETR components Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 08/18] coresight: tmc: making prepare/unprepare functions generic Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 09/18] coresight: tmc: allocating memory when needed Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 10/18] coresight: tmc: getting rid of multiple read access Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 8:54 ` Suzuki K Poulose 2016-04-27 8:54 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 11/18] coresight: tmc: adding mode of operation for link/sinks Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 9:07 ` Suzuki K Poulose 2016-04-27 9:07 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 12/18] coresight: tmc: dump system memory content only when needed Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 9:08 ` Suzuki K Poulose 2016-04-27 9:08 ` Suzuki K Poulose 2016-04-26 22:10 ` Mathieu Poirier [this message] 2016-04-26 22:10 ` [PATCH V4 13/18] coresight: tmc: make sysFS and Perf mode mutually exclusive Mathieu Poirier 2016-04-27 9:10 ` Suzuki K Poulose 2016-04-27 9:10 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 14/18] coresight: tmc: keep track of memory width Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 9:17 ` Suzuki K Poulose 2016-04-27 9:17 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 15/18] coresight: moving struct cs_buffers to header file Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 9:11 ` Suzuki K Poulose 2016-04-27 9:11 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-27 11:21 ` Suzuki K Poulose 2016-04-27 11:21 ` Suzuki K Poulose 2016-04-27 17:22 ` Mathieu Poirier 2016-04-27 17:22 ` Mathieu Poirier 2016-04-27 17:25 ` Suzuki K Poulose 2016-04-27 17:25 ` Suzuki K Poulose 2016-04-26 22:10 ` [PATCH V4 17/18] coresight: tmc: implementing TMC-ETR " Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier 2016-04-26 22:10 ` [PATCH V4 18/18] coresight: configuring ETF in FIFO mode when acting as link Mathieu Poirier 2016-04-26 22:10 ` Mathieu Poirier
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