[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

Fabio, please add your changes on-top-of this series.

Compared to previous series, this series
- Removed 'Fabio' patch changes.
- Droped DM_I2C and DM_PMIC, since power driver need to chage dm
- Added phy-reset-gpio support for fec_mxc driver
- Added Linux merge tag details on dts patches

Changes for v6:
- rebase on u-boot-imx/master
- Droped DM_I2C and DM_PMIC changes
- Added phy-reset-gpio support for fec_mxc driver
- Added Linux merge tag details on dts patches
- Removed 'Fabio' patch changes.

Changes for v6:
- rebase on u-boot-imx/master
- Fixed comments from 'Fabio' in v5
- Droped file/directory rename changes patches
- Droped dm_gpio changes on board

Changes for v5:
- rebase on master
- removed SPL support for i.MX6DL SabreSD
- Add board_fit_config_name_match for SPL to fetch board dts
- Add imx6qdl_sabresd_spl_defconfig for common SPL support

Changes for v4:
- rebase on master
- Rename imx6[dl|q]_sabresd_spl_defconfig to imx6[dl|q]_sabresd_spl_defconfig
- Update README
- Move CONFIG_FEC_MXC to configs/mx6[dl|q|qp]sabreauto_defconfigs
- Add dts support for non-spl based defconfigs

Changes for v3:
- rebase on master
- Added patch 'ARM: i.MX6: sabresd: Cleanup board code'
- Added patch 'ARM: i.MX6DL: sabresd: Move DCD reginit on SPL'

Changes for v2:
- rebase on master
- Added new-patches.

Jagan Teki (17):
  ARM: i.MX6: sabresd: Remove SPL_I2C_SUPPORT
  ARM: dts: i.MX6: Add imx6qdl-sabresd.dtsi
  ARM: dts: i.MX6: Add imx6q-sabresd.dts
  ARM: dts: i.MX6: Add imx6dl-sabresd.dts
  ARM: dts: i.MX6: Add imx6qp.dtsi
  ARM: dts: i.MX6: Add imx6qp-sabresd.dts
  sabresd: i.MX6Q: Add initial dts support
  sabresd: i.MX6QP: Add initial dts support
  SabreSD: i.MX6DL: Add initial dts support
  SabreSD: Move CONFIG_SYS_I2C_MXC to defconfigs
  SabreSD: Enable CONFIG_DM_REGULATOR
  SabreSD: Enable DM_USB
  i.MX6: Sabre: Move CONFIG_FEC_MXC to defconfigs
  net: fec_mxc: Add 'phy-reset-gpios' support
  i.MX6: SabreSD: Enable DM_ETH
  i.MX6: sabresd: Drop checkboard
  i.MX6: SabreSD: Cleanup board code

 arch/arm/cpu/armv7/mx6/Kconfig          |  15 +-
 arch/arm/dts/Makefile                   |   3 +
 arch/arm/dts/imx6dl-sabresd.dts         |  17 +
 arch/arm/dts/imx6q-sabresd.dts          |  25 +
 arch/arm/dts/imx6qdl-sabresd.dtsi       | 626 ++++++++++++++++++++++++
 arch/arm/dts/imx6qp-sabresd.dts         |  93 ++++
 arch/arm/dts/imx6qp.dtsi                | 149 ++++++
 board/freescale/mx6sabresd/Makefile     |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 834 ++++----------------------------
 board/freescale/mx6sabresd/spl.c        | 517 ++++++++++++++++++++
 configs/mx6dlsabreauto_defconfig        |   2 +
 configs/mx6qpsabreauto_defconfig        |   2 +
 configs/mx6qsabreauto_defconfig         |   2 +
 configs/mx6sabresd_spl_defconfig        |   7 +-
 drivers/net/fec_mxc.c                   |  64 ++-
 drivers/net/fec_mxc.h                   |   8 +
 include/configs/mx6sabre_common.h       |   3 +-
 include/configs/mx6sabresd.h            |  21 +-
 include/netdev.h                        |   5 +
 19 files changed, 1638 insertions(+), 756 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
 create mode 100644 arch/arm/dts/imx6q-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
 create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
 create mode 100644 arch/arm/dts/imx6qp.dtsi
 create mode 100644 board/freescale/mx6sabresd/spl.c

-- 
1.9.1

[U-Boot] [PATCH v7 01/17] ARM: i.MX6: sabresd: Remove SPL_I2C_SUPPORT

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

I2C support not needed for SPL build, hence removed the
CONFIG_SPL_I2C_SUPPORT from mx6sabresd_spl_defconfig

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 configs/mx6sabresd_spl_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 0e0edef..2bfacb9 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -16,7 +16,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SPL=y
 CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-- 
1.9.1

[U-Boot] [PATCH v7 02/17] ARM: dts: i.MX6: Add imx6qdl-sabresd.dtsi

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Retrive imx6qdl-sabresd.dtsi from Linux with last commit
"ARM: dts: imx6qdl-sabresd: Set LDO regulator supply"
(sha1: c23568dbbda110a5c79c6537cc81ed7af5444b64)

Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/imx6qdl-sabresd.dtsi | 626 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 626 insertions(+)
 create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi

diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
new file mode 100644
index 0000000..58055ce
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -0,0 +1,626 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg_vbus: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 22 0>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_usb_h1_vbus: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_h1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 29 0>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_audio: regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "wm8962-supply";
+			gpio = <&gpio4 10 0>;
+			enable-active-high;
+		};
+
+		reg_pcie: regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie_reg>;
+			regulator-name = "MPCIE_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 19 0>;
+			regulator-always-on;
+			enable-active-high;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		power {
+			label = "Power Button";
+			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_POWER>;
+		};
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx6q-sabresd-wm8962",
+			   "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		ssi-controller = <&ssi2>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+		mux-int-port = <2>;
+		mux-ext-port = <3>;
+	};
+
+	backlight_lvds: backlight-lvds {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+		status = "okay";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		red {
+			gpios = <&gpio1 2 0>;
+			default-state = "on";
+		};
+	};
+
+	panel {
+		compatible = "hannstar,hsd100pxn1";
+		backlight = <&backlight_lvds>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio4 9 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 0>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	codec: wm8962 at 1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		DCVDD-supply = <&reg_audio>;
+		DBVDD-supply = <&reg_audio>;
+		AVDD-supply = <&reg_audio>;
+		CPVDD-supply = <&reg_audio>;
+		MICVDD-supply = <&reg_audio>;
+		PLLVDD-supply = <&reg_audio>;
+		SPKVDD1-supply = <&reg_audio>;
+		SPKVDD2-supply = <&reg_audio>;
+		gpio-cfg = <
+			0x0000 /* 0:Default */
+			0x0000 /* 1:Default */
+			0x0013 /* 2:FN_DMICCLK */
+			0x0000 /* 3:Default */
+			0x8014 /* 4:FN_DMICCDAT */
+			0x0000 /* 5:Default */
+		>;
+       };
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100 at 08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	egalax_ts at 04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <7 2>;
+		wakeup-gpios = <&gpio6 7 0>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6qdl-sabresd {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
+				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
+				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+			>;
+		};
+
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			>;
+		};
+
+		pinctrl_ecspi1: ecspi1grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
+				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
+				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
+				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
+				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
+				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+			>;
+		};
+
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
+			>;
+		};
+
+		pinctrl_pcie_reg: pciereggrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
+			>;
+		};
+
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+			>;
+		};
+
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc4: usdhc4grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
+				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
+				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
+				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
+				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
+				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
+				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
+				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
+				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
+			>;
+		};
+	};
+
+	gpio_leds {
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+			>;
+		};
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		port at 4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&reg_arm {
+       vin-supply = <&sw1a_reg>;
+};
+
+&reg_pu {
+       vin-supply = <&sw1c_reg>;
+};
+
+&reg_soc {
+       vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&ssi2 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	status = "okay";
+};
+
+&wdog1 {
+	status = "disabled";
+};
+
+&wdog2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
-- 
1.9.1

[U-Boot] [PATCH v7 03/17] ARM: dts: i.MX6: Add imx6q-sabresd.dts

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Retrive imx6q-sabresd.dts from Linux with last commit
"ARM: dtsi: enable ahci sata on imx6q platforms"
(sha1: 0fb1f804269e549b556b475c8655bc862c220622)

Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/Makefile          |  1 +
 arch/arm/dts/imx6q-sabresd.dts | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/dts/imx6q-sabresd.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e2c2584..1ae14c4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -339,6 +339,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-rqs.dtb \
 	imx6q-logicpd.dtb \
+	imx6q-sabresd.dtb \
 	imx6sx-sabreauto.dtb \
 	imx6ul-geam-kit.dtb \
 	imx6ul-isiot-emmc.dtb \
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
new file mode 100644
index 0000000..9cbdfe7
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Smart Device Board";
+	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};
-- 
1.9.1

[U-Boot] [PATCH v7 04/17] ARM: dts: i.MX6: Add imx6dl-sabresd.dts

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Retrive imx6dl-sabresd.dts from Linux with last commit
"ARM: dts: imx: share pad macro names between imx6q and imx6dl"
(sha1: c56009b2f6134e5943a03cf26e4d7fce9745d56b)

Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/Makefile           |  1 +
 arch/arm/dts/imx6dl-sabresd.dts | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl-sabresd.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1ae14c4..a5a5e74 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -336,6 +336,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 	imx6sll-evk.dtb \
 	imx6dl-icore.dtb \
 	imx6dl-icore-rqs.dtb \
+	imx6dl-sabresd.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-rqs.dtb \
 	imx6q-logicpd.dtb \
diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts
new file mode 100644
index 0000000..1e45f2f
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabresd.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+};
-- 
1.9.1

[U-Boot] [PATCH v7 05/17] ARM: dts: i.MX6: Add imx6qp.dtsi

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Retrive imx6qp.dtsi from Linux with last commit
"ARM: dts: imx6qp: add PRG nodes and hook up to IPUs"
(sha1: 54458dac349f72dd9a4fd816619bde0bab40841d)

Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/imx6qp.dtsi | 149 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 149 insertions(+)
 create mode 100644 arch/arm/dts/imx6qp.dtsi

diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
new file mode 100644
index 0000000..59453f2
--- /dev/null
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+	soc {
+		ocram2: sram at 00940000 {
+			compatible = "mmio-sram";
+			reg = <0x00940000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocram3: sram at 00960000 {
+			compatible = "mmio-sram";
+			reg = <0x00960000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		aips-bus at 02100000 {
+			pre1: pre at 21c8000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021c8000 0x1000>;
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE0>;
+				clock-names = "axi";
+				fsl,iram = <&ocram2>;
+			};
+
+			pre2: pre at 21c9000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021c9000 0x1000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE1>;
+				clock-names = "axi";
+				fsl,iram = <&ocram2>;
+			};
+
+			pre3: pre at 21ca000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021ca000 0x1000>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE2>;
+				clock-names = "axi";
+				fsl,iram = <&ocram3>;
+			};
+
+			pre4: pre at 21cb000 {
+				compatible = "fsl,imx6qp-pre";
+				reg = <0x021cb000 0x1000>;
+				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clks IMX6QDL_CLK_PRE3>;
+				clock-names = "axi";
+				fsl,iram = <&ocram3>;
+			};
+
+			prg1: prg at 21cc000 {
+				compatible = "fsl,imx6qp-prg";
+				reg = <0x021cc000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
+					 <&clks IMX6QDL_CLK_PRG0_AXI>;
+				clock-names = "ipg", "axi";
+				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+			};
+
+			prg2: prg at 21cd000 {
+				compatible = "fsl,imx6qp-prg";
+				reg = <0x021cd000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
+					 <&clks IMX6QDL_CLK_PRG1_AXI>;
+				clock-names = "ipg", "axi";
+				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
+			};
+		};
+	};
+};
+
+&fec {
+	/delete-property/interrupts-extended;
+	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
+		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ipu1 {
+	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	fsl,prg = <&prg1>;
+};
+
+&ipu2 {
+	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	fsl,prg = <&prg2>;
+};
+
+&ldb {
+	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
+	clock-names = "di0_pll", "di1_pll",
+		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+		      "di0", "di1";
+};
+
+&mmdc0 {
+	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+};
+
+&pcie {
+	compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+};
-- 
1.9.1

[U-Boot] [PATCH v7 06/17] ARM: dts: i.MX6: Add imx6qp-sabresd.dts

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Retrive imx6qp-sabresd.dts from Linux with last commit
"ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply"
(sha1: 448548174caaa04ffe9da4da9326052eb8791a9b)

Sync with Linux commit 4879b7ae("Merge tag 'dmaengine-4.12-rc1'").

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/Makefile           |  1 +
 arch/arm/dts/imx6qp-sabresd.dts | 93 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 arch/arm/dts/imx6qp-sabresd.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5a5e74..9a0d65b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -341,6 +341,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 	imx6q-icore-rqs.dtb \
 	imx6q-logicpd.dtb \
 	imx6q-sabresd.dtb \
+	imx6qp-sabresd.dtb \
 	imx6sx-sabreauto.dtb \
 	imx6ul-geam-kit.dtb \
 	imx6ul-isiot-emmc.dtb \
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
new file mode 100644
index 0000000..a8a5004
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+};
+
+&reg_arm {
+	vin-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+	imx6qdl-sabresd {
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+	};
+};
+
+&pcie {
+	status = "disabled";
+};
-- 
1.9.1

[U-Boot] [PATCH v7 07/17] sabresd: i.MX6Q: Add initial dts support

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Add initial devicetree support for i.MX6 Quad Sabresd board.

(1) Added config options
    CONFIG_OF_CONTROL=y
    CONFIG_DM_GPIO=y
    CONFIG_DM_MMC=y
    CONFIG_BLK is not set
    CONFIG_DM_MMC_OPS is not set
    CONFIG_PINCTRL=y
    CONFIG_PINCTRL_IMX6=y
(2) Moved spl code to board/freescale/mx6sabresd/spl.c
(3) Removed U-Boot proper board_mmc_init code, since mmc
    support through dtb
(4) DM_GPIO and GM_MMC are undef for SPL, till SPL_OF_CONTROL
    support.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig          |   9 +-
 board/freescale/mx6sabresd/Makefile     |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 523 --------------------------------
 board/freescale/mx6sabresd/spl.c        | 501 ++++++++++++++++++++++++++++++
 configs/mx6sabresd_spl_defconfig        |   3 +
 include/configs/mx6sabresd.h            |   5 +-
 6 files changed, 516 insertions(+), 526 deletions(-)
 create mode 100644 board/freescale/mx6sabresd/spl.c

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 0ff9045..0497fe0 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -210,11 +210,16 @@ config TARGET_MX6QSABREAUTO
 
 config TARGET_MX6SABRESD
 	bool "mx6sabresd"
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
-	select SUPPORT_SPL
+	select OF_CONTROL
 	select DM
+	select DM_GPIO
+	select DM_MMC
 	select DM_THERMAL
-	select BOARD_EARLY_INIT_F
+	select PINCTRL
+	select PINCTRL_IMX6
+	select SUPPORT_SPL
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile
index cfca2ef..3ae32ab 100644
--- a/board/freescale/mx6sabresd/Makefile
+++ b/board/freescale/mx6sabresd/Makefile
@@ -7,3 +7,4 @@
 #
 
 obj-y  := mx6sabresd.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index f4a5d9c..7af263d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -16,8 +16,6 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/video.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -36,10 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
@@ -56,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
 
-#define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -100,47 +92,6 @@ static void setup_iomux_enet(void)
 	udelay(100);
 }
 
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
 static iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -253,121 +204,6 @@ static void setup_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart1_pads);
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
-
-int board_mmc_get_env_dev(int devno)
-{
-	return devno - 1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = 1; /* eMMC/uSDHC4 is always present */
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
-	int ret;
-	int i;
-
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    SD2
-	 * mmc1                    SD3
-	 * mmc2                    eMMC
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			SETUP_IOMUX_PADS(usdhc2_pads);
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 1:
-			SETUP_IOMUX_PADS(usdhc3_pads);
-			gpio_direction_input(USDHC3_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 2:
-			SETUP_IOMUX_PADS(usdhc4_pads);
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-#else
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned reg = readl(&psrc->sbmr1) >> 11;
-	/*
-	 * Upon reading BOOT_CFG register the following map is done:
-	 * Bit 11 and 12 of BOOT_CFG register can determine the current
-	 * mmc port
-	 * 0x1                  SD1
-	 * 0x2                  SD2
-	 * 0x3                  SD4
-	 */
-
-	switch (reg & 0x3) {
-	case 0x1:
-		SETUP_IOMUX_PADS(usdhc2_pads);
-		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	case 0x2:
-		SETUP_IOMUX_PADS(usdhc3_pads);
-		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	case 0x3:
-		SETUP_IOMUX_PADS(usdhc4_pads);
-		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	}
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
@@ -718,362 +554,3 @@ int checkboard(void)
 	puts("Board: MX6-SabreSD\n");
 	return 0;
 }
-
-#ifdef CONFIG_SPL_BUILD
-#include <asm/arch/mx6-ddr.h>
-#include <spl.h>
-#include <libfdt.h>
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	gpio_direction_input(KEY_VOL_UP);
-
-	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
-	return gpio_get_value(KEY_VOL_UP);
-}
-#endif
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC03, &ccm->CCGR1);
-	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	if (is_mx6dqp()) {
-		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-		writel(0x007F007F, &iomux->gpr[6]);
-		writel(0x007F007F, &iomux->gpr[7]);
-	} else {
-		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-		writel(0x007F007F, &iomux->gpr[6]);
-		writel(0x007F007F, &iomux->gpr[7]);
-	}
-}
-
-static int mx6q_dcd_table[] = {
-	0x020e0798, 0x000C0000,
-	0x020e0758, 0x00000000,
-	0x020e0588, 0x00000030,
-	0x020e0594, 0x00000030,
-	0x020e056c, 0x00000030,
-	0x020e0578, 0x00000030,
-	0x020e074c, 0x00000030,
-	0x020e057c, 0x00000030,
-	0x020e058c, 0x00000000,
-	0x020e059c, 0x00000030,
-	0x020e05a0, 0x00000030,
-	0x020e078c, 0x00000030,
-	0x020e0750, 0x00020000,
-	0x020e05a8, 0x00000030,
-	0x020e05b0, 0x00000030,
-	0x020e0524, 0x00000030,
-	0x020e051c, 0x00000030,
-	0x020e0518, 0x00000030,
-	0x020e050c, 0x00000030,
-	0x020e05b8, 0x00000030,
-	0x020e05c0, 0x00000030,
-	0x020e0774, 0x00020000,
-	0x020e0784, 0x00000030,
-	0x020e0788, 0x00000030,
-	0x020e0794, 0x00000030,
-	0x020e079c, 0x00000030,
-	0x020e07a0, 0x00000030,
-	0x020e07a4, 0x00000030,
-	0x020e07a8, 0x00000030,
-	0x020e0748, 0x00000030,
-	0x020e05ac, 0x00000030,
-	0x020e05b4, 0x00000030,
-	0x020e0528, 0x00000030,
-	0x020e0520, 0x00000030,
-	0x020e0514, 0x00000030,
-	0x020e0510, 0x00000030,
-	0x020e05bc, 0x00000030,
-	0x020e05c4, 0x00000030,
-	0x021b0800, 0xa1390003,
-	0x021b080c, 0x001F001F,
-	0x021b0810, 0x001F001F,
-	0x021b480c, 0x001F001F,
-	0x021b4810, 0x001F001F,
-	0x021b083c, 0x43270338,
-	0x021b0840, 0x03200314,
-	0x021b483c, 0x431A032F,
-	0x021b4840, 0x03200263,
-	0x021b0848, 0x4B434748,
-	0x021b4848, 0x4445404C,
-	0x021b0850, 0x38444542,
-	0x021b4850, 0x4935493A,
-	0x021b081c, 0x33333333,
-	0x021b0820, 0x33333333,
-	0x021b0824, 0x33333333,
-	0x021b0828, 0x33333333,
-	0x021b481c, 0x33333333,
-	0x021b4820, 0x33333333,
-	0x021b4824, 0x33333333,
-	0x021b4828, 0x33333333,
-	0x021b08b8, 0x00000800,
-	0x021b48b8, 0x00000800,
-	0x021b0004, 0x00020036,
-	0x021b0008, 0x09444040,
-	0x021b000c, 0x555A7975,
-	0x021b0010, 0xFF538F64,
-	0x021b0014, 0x01FF00DB,
-	0x021b0018, 0x00001740,
-	0x021b001c, 0x00008000,
-	0x021b002c, 0x000026d2,
-	0x021b0030, 0x005A1023,
-	0x021b0040, 0x00000027,
-	0x021b0000, 0x831A0000,
-	0x021b001c, 0x04088032,
-	0x021b001c, 0x00008033,
-	0x021b001c, 0x00048031,
-	0x021b001c, 0x09408030,
-	0x021b001c, 0x04008040,
-	0x021b0020, 0x00005800,
-	0x021b0818, 0x00011117,
-	0x021b4818, 0x00011117,
-	0x021b0004, 0x00025576,
-	0x021b0404, 0x00011006,
-	0x021b001c, 0x00000000,
-};
-
-static int mx6qp_dcd_table[] = {
-	0x020e0798, 0x000c0000,
-	0x020e0758, 0x00000000,
-	0x020e0588, 0x00000030,
-	0x020e0594, 0x00000030,
-	0x020e056c, 0x00000030,
-	0x020e0578, 0x00000030,
-	0x020e074c, 0x00000030,
-	0x020e057c, 0x00000030,
-	0x020e058c, 0x00000000,
-	0x020e059c, 0x00000030,
-	0x020e05a0, 0x00000030,
-	0x020e078c, 0x00000030,
-	0x020e0750, 0x00020000,
-	0x020e05a8, 0x00000030,
-	0x020e05b0, 0x00000030,
-	0x020e0524, 0x00000030,
-	0x020e051c, 0x00000030,
-	0x020e0518, 0x00000030,
-	0x020e050c, 0x00000030,
-	0x020e05b8, 0x00000030,
-	0x020e05c0, 0x00000030,
-	0x020e0774, 0x00020000,
-	0x020e0784, 0x00000030,
-	0x020e0788, 0x00000030,
-	0x020e0794, 0x00000030,
-	0x020e079c, 0x00000030,
-	0x020e07a0, 0x00000030,
-	0x020e07a4, 0x00000030,
-	0x020e07a8, 0x00000030,
-	0x020e0748, 0x00000030,
-	0x020e05ac, 0x00000030,
-	0x020e05b4, 0x00000030,
-	0x020e0528, 0x00000030,
-	0x020e0520, 0x00000030,
-	0x020e0514, 0x00000030,
-	0x020e0510, 0x00000030,
-	0x020e05bc, 0x00000030,
-	0x020e05c4, 0x00000030,
-	0x021b0800, 0xa1390003,
-	0x021b080c, 0x001b001e,
-	0x021b0810, 0x002e0029,
-	0x021b480c, 0x001b002a,
-	0x021b4810, 0x0019002c,
-	0x021b083c, 0x43240334,
-	0x021b0840, 0x0324031a,
-	0x021b483c, 0x43340344,
-	0x021b4840, 0x03280276,
-	0x021b0848, 0x44383A3E,
-	0x021b4848, 0x3C3C3846,
-	0x021b0850, 0x2e303230,
-	0x021b4850, 0x38283E34,
-	0x021b081c, 0x33333333,
-	0x021b0820, 0x33333333,
-	0x021b0824, 0x33333333,
-	0x021b0828, 0x33333333,
-	0x021b481c, 0x33333333,
-	0x021b4820, 0x33333333,
-	0x021b4824, 0x33333333,
-	0x021b4828, 0x33333333,
-	0x021b08c0, 0x24912249,
-	0x021b48c0, 0x24914289,
-	0x021b08b8, 0x00000800,
-	0x021b48b8, 0x00000800,
-	0x021b0004, 0x00020036,
-	0x021b0008, 0x24444040,
-	0x021b000c, 0x555A7955,
-	0x021b0010, 0xFF320F64,
-	0x021b0014, 0x01ff00db,
-	0x021b0018, 0x00001740,
-	0x021b001c, 0x00008000,
-	0x021b002c, 0x000026d2,
-	0x021b0030, 0x005A1023,
-	0x021b0040, 0x00000027,
-	0x021b0400, 0x14420000,
-	0x021b0000, 0x831A0000,
-	0x021b0890, 0x00400C58,
-	0x00bb0008, 0x00000000,
-	0x00bb000c, 0x2891E41A,
-	0x00bb0038, 0x00000564,
-	0x00bb0014, 0x00000040,
-	0x00bb0028, 0x00000020,
-	0x00bb002c, 0x00000020,
-	0x021b001c, 0x04088032,
-	0x021b001c, 0x00008033,
-	0x021b001c, 0x00048031,
-	0x021b001c, 0x09408030,
-	0x021b001c, 0x04008040,
-	0x021b0020, 0x00005800,
-	0x021b0818, 0x00011117,
-	0x021b4818, 0x00011117,
-	0x021b0004, 0x00025576,
-	0x021b0404, 0x00011006,
-	0x021b001c, 0x00000000,
-};
-
-static int mx6dl_dcd_table[] = {
-	0x020e0774, 0x000C0000,
-	0x020e0754, 0x00000000,
-	0x020e04ac, 0x00000030,
-	0x020e04b0, 0x00000030,
-	0x020e0464, 0x00000030,
-	0x020e0490, 0x00000030,
-	0x020e074c, 0x00000030,
-	0x020e0494, 0x00000030,
-	0x020e04a0, 0x00000000,
-	0x020e04b4, 0x00000030,
-	0x020e04b8, 0x00000030,
-	0x020e076c, 0x00000030,
-	0x020e0750, 0x00020000,
-	0x020e04bc, 0x00000030,
-	0x020e04c0, 0x00000030,
-	0x020e04c4, 0x00000030,
-	0x020e04c8, 0x00000030,
-	0x020e04cc, 0x00000030,
-	0x020e04d0, 0x00000030,
-	0x020e04d4, 0x00000030,
-	0x020e04d8, 0x00000030,
-	0x020e0760, 0x00020000,
-	0x020e0764, 0x00000030,
-	0x020e0770, 0x00000030,
-	0x020e0778, 0x00000030,
-	0x020e077c, 0x00000030,
-	0x020e0780, 0x00000030,
-	0x020e0784, 0x00000030,
-	0x020e078c, 0x00000030,
-	0x020e0748, 0x00000030,
-	0x020e0470, 0x00000030,
-	0x020e0474, 0x00000030,
-	0x020e0478, 0x00000030,
-	0x020e047c, 0x00000030,
-	0x020e0480, 0x00000030,
-	0x020e0484, 0x00000030,
-	0x020e0488, 0x00000030,
-	0x020e048c, 0x00000030,
-	0x021b0800, 0xa1390003,
-	0x021b080c, 0x001F001F,
-	0x021b0810, 0x001F001F,
-	0x021b480c, 0x001F001F,
-	0x021b4810, 0x001F001F,
-	0x021b083c, 0x4220021F,
-	0x021b0840, 0x0207017E,
-	0x021b483c, 0x4201020C,
-	0x021b4840, 0x01660172,
-	0x021b0848, 0x4A4D4E4D,
-	0x021b4848, 0x4A4F5049,
-	0x021b0850, 0x3F3C3D31,
-	0x021b4850, 0x3238372B,
-	0x021b081c, 0x33333333,
-	0x021b0820, 0x33333333,
-	0x021b0824, 0x33333333,
-	0x021b0828, 0x33333333,
-	0x021b481c, 0x33333333,
-	0x021b4820, 0x33333333,
-	0x021b4824, 0x33333333,
-	0x021b4828, 0x33333333,
-	0x021b08b8, 0x00000800,
-	0x021b48b8, 0x00000800,
-	0x021b0004, 0x0002002D,
-	0x021b0008, 0x00333030,
-	0x021b000c, 0x3F435313,
-	0x021b0010, 0xB66E8B63,
-	0x021b0014, 0x01FF00DB,
-	0x021b0018, 0x00001740,
-	0x021b001c, 0x00008000,
-	0x021b002c, 0x000026d2,
-	0x021b0030, 0x00431023,
-	0x021b0040, 0x00000027,
-	0x021b0000, 0x831A0000,
-	0x021b001c, 0x04008032,
-	0x021b001c, 0x00008033,
-	0x021b001c, 0x00048031,
-	0x021b001c, 0x05208030,
-	0x021b001c, 0x04008040,
-	0x021b0020, 0x00005800,
-	0x021b0818, 0x00011117,
-	0x021b4818, 0x00011117,
-	0x021b0004, 0x0002556D,
-	0x021b0404, 0x00011006,
-	0x021b001c, 0x00000000,
-};
-
-static void ddr_init(int *table, int size)
-{
-	int i;
-
-	for (i = 0; i < size / 2 ; i++)
-		writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
-	if (is_mx6dq())
-		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
-	else if (is_mx6dqp())
-		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
-	else if (is_mx6sdl())
-		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
-}
-
-void board_init_f(ulong dummy)
-{
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-	gpr_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}
-#endif
diff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c
new file mode 100644
index 0000000..01d45ce
--- /dev/null
+++ b/board/freescale/mx6sabresd/spl.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spl.h>
+
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL		(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+				PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST  | \
+				PAD_CTL_HYS)
+#define KEY_VOL_UP		IMX_GPIO_NR(1, 4)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /* eMMC/uSDHC4 is always present */
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x1:
+		SETUP_IOMUX_PADS(usdhc2_pads);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x3:
+		SETUP_IOMUX_PADS(usdhc4_pads);
+		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	gpio_direction_input(KEY_VOL_UP);
+
+	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
+	return gpio_get_value(KEY_VOL_UP);
+}
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	if (is_mx6dqp()) {
+		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	} else {
+		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	}
+}
+
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43270338,
+	0x021b0840, 0x03200314,
+	0x021b483c, 0x431A032F,
+	0x021b4840, 0x03200263,
+	0x021b0848, 0x4B434748,
+	0x021b4848, 0x4445404C,
+	0x021b0850, 0x38444542,
+	0x021b4850, 0x4935493A,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x555A7975,
+	0x021b0010, 0xFF538F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000c0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912249,
+	0x021b48c0, 0x24914289,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x24444040,
+	0x021b000c, 0x555A7955,
+	0x021b0010, 0xFF320F64,
+	0x021b0014, 0x01ff00db,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x831A0000,
+	0x021b0890, 0x00400C58,
+	0x00bb0008, 0x00000000,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6dl_dcd_table[] = {
+	0x020e0774, 0x000C0000,
+	0x020e0754, 0x00000000,
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e076c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e04bc, 0x00000030,
+	0x020e04c0, 0x00000030,
+	0x020e04c4, 0x00000030,
+	0x020e04c8, 0x00000030,
+	0x020e04cc, 0x00000030,
+	0x020e04d0, 0x00000030,
+	0x020e04d4, 0x00000030,
+	0x020e04d8, 0x00000030,
+	0x020e0760, 0x00020000,
+	0x020e0764, 0x00000030,
+	0x020e0770, 0x00000030,
+	0x020e0778, 0x00000030,
+	0x020e077c, 0x00000030,
+	0x020e0780, 0x00000030,
+	0x020e0784, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e0470, 0x00000030,
+	0x020e0474, 0x00000030,
+	0x020e0478, 0x00000030,
+	0x020e047c, 0x00000030,
+	0x020e0480, 0x00000030,
+	0x020e0484, 0x00000030,
+	0x020e0488, 0x00000030,
+	0x020e048c, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x4220021F,
+	0x021b0840, 0x0207017E,
+	0x021b483c, 0x4201020C,
+	0x021b4840, 0x01660172,
+	0x021b0848, 0x4A4D4E4D,
+	0x021b4848, 0x4A4F5049,
+	0x021b0850, 0x3F3C3D31,
+	0x021b4850, 0x3238372B,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x0002002D,
+	0x021b0008, 0x00333030,
+	0x021b000c, 0x3F435313,
+	0x021b0010, 0xB66E8B63,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x00431023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04008032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x05208030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x0002556D,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+	else if (is_mx6sdl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 2bfacb9..33e84f0 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -48,3 +49,5 @@ CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index a8c0e03..43a4aac 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -11,6 +11,10 @@
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+#  undef CONFIG_DM_GPIO
+#  undef CONFIG_DM_MMC
+# endif
 #endif
 
 #define CONFIG_MACH_TYPE	3980
@@ -34,7 +38,6 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
 
-#define CONFIG_SYS_FSL_USDHC_NUM	3
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC3 */
 #endif
-- 
1.9.1

[U-Boot] [PATCH v7 08/17] sabresd: i.MX6QP: Add initial dts support

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Add initial devicetree support for i.MX6 Quad Plus Sabresd board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig   |  3 +++
 board/freescale/mx6sabresd/spl.c | 12 ++++++++++++
 configs/mx6sabresd_spl_defconfig |  1 +
 3 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 0497fe0..42ac9b9 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -220,6 +220,9 @@ config TARGET_MX6SABRESD
 	select PINCTRL
 	select PINCTRL_IMX6
 	select SUPPORT_SPL
+	select FIT
+	select SPL_LOAD_FIT
+	select SPL_OF_LIBFDT
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
diff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c
index 01d45ce..63847b3 100644
--- a/board/freescale/mx6sabresd/spl.c
+++ b/board/freescale/mx6sabresd/spl.c
@@ -147,6 +147,18 @@ int board_mmc_init(bd_t *bis)
 }
 #endif /* CONFIG_FSL_ESDHC */
 
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dqp() && !strcmp(name, "imx6qp-sabresd"))
+		return 0;
+	else if (is_mx6dq() && !strcmp(name, "imx6q-sabresd"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 33e84f0..ef02df1 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_LIST="imx6qp-sabresd imx6q-sabresd"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
-- 
1.9.1

[U-Boot] [PATCH v7 09/17] SabreSD: i.MX6DL: Add initial dts support

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Add initial devicetree support for i.MX6 DualLite Sabresd board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 board/freescale/mx6sabresd/spl.c | 2 ++
 configs/mx6sabresd_spl_defconfig | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c
index 63847b3..2488cb5 100644
--- a/board/freescale/mx6sabresd/spl.c
+++ b/board/freescale/mx6sabresd/spl.c
@@ -154,6 +154,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (is_mx6dq() && !strcmp(name, "imx6q-sabresd"))
 		return 0;
+	else if (is_mx6sdl() && !strcmp(name, "imx6dl-sabresd"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index ef02df1..5512d51 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -10,7 +10,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_VIDEO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
-CONFIG_OF_LIST="imx6qp-sabresd imx6q-sabresd"
+CONFIG_OF_LIST="imx6qp-sabresd imx6q-sabresd imx6dl-sabresd"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
-- 
1.9.1

[U-Boot] [PATCH v7 10/17] SabreSD: Move CONFIG_SYS_I2C_MXC to defconfigs

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Moved CONFIG_SYS_I2C_MXC from include/configs/mxsabresd.h
to imx6 sabresd defconfigs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 configs/mx6sabresd_spl_defconfig | 1 +
 include/configs/mx6sabresd.h     | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 5512d51..58d0b4b 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -52,3 +52,4 @@ CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
+CONFIG_SYS_I2C_MXC=y
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 43a4aac..b90afe0 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -51,12 +51,13 @@
 #endif
 
 /* I2C Configs */
+#ifdef CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		  100000
+#endif
 
 /* PMIC */
 #define CONFIG_POWER
-- 
1.9.1

[U-Boot] [PATCH v7 11/17] SabreSD: Enable CONFIG_DM_REGULATOR

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

Enable CONFIG_DM_REGULATOR for i.MX6 SabreSD boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 42ac9b9..f203cf6 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -216,6 +216,7 @@ config TARGET_MX6SABRESD
 	select DM
 	select DM_GPIO
 	select DM_MMC
+	select DM_REGULATOR
 	select DM_THERMAL
 	select PINCTRL
 	select PINCTRL_IMX6
-- 
1.9.1

[U-Boot] [PATCH v7 12/17] SabreSD: Enable DM_USB

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

Enable DM_USB and removed non-DM_USB related config options.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig          |  1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 65 ---------------------------------
 include/configs/mx6sabresd.h            | 11 ++----
 3 files changed, 5 insertions(+), 72 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index f203cf6..d1ba801 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -218,6 +218,7 @@ config TARGET_MX6SABRESD
 	select DM_MMC
 	select DM_REGULATOR
 	select DM_THERMAL
+	select DM_USB
 	select PINCTRL
 	select PINCTRL_IMX6
 	select SUPPORT_SPL
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 7af263d..688b326 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -26,7 +26,6 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
-#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -392,67 +391,6 @@ int board_eth_init(bd_t *bis)
 	return cpu_eth_init(bis);
 }
 
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET	0x800
-#define UCTRL_PWR_POL		(1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usb_hc1_pads[] = {
-	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_usb(void)
-{
-	SETUP_IOMUX_PADS(usb_otg_pads);
-
-	/*
-	 * set daisy chain for otg_pin_id on 6q.
-	 * for 6dl, this bit is reserved
-	 */
-	imx_iomux_set_gpr_register(1, 13, 1, 0);
-
-	SETUP_IOMUX_PADS(usb_hc1_pads);
-}
-
-int board_ehci_hcd_init(int port)
-{
-	u32 *usbnc_usb_ctrl;
-
-	if (port > 1)
-		return -EINVAL;
-
-	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
-				 port * 4);
-
-	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
-	return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		break;
-	case 1:
-		if (on)
-			gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
-		else
-			gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
-		break;
-	default:
-		printf("MXC USB port %d not yet supported\n", port);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-#endif
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -475,9 +413,6 @@ int board_init(void)
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
-#endif
 
 	return 0;
 }
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index b90afe0..44c7cf6 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -66,13 +66,10 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS		0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
+#ifdef CONFIG_USB_EHCI_MX6
+# define CONFIG_USB_HOST_ETHER
+# define CONFIG_USB_ETHER_ASIX
+# define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 
 #endif                         /* __MX6QSABRESD_CONFIG_H */
-- 
1.9.1

[U-Boot] [PATCH v7 13/17] i.MX6: Sabre: Move CONFIG_FEC_MXC to defconfigs

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Moved CONFIG_FEC_MXC from include/configs/mxsabresd.h
to imx6 sabresd and sabreauto defconfigs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 configs/mx6dlsabreauto_defconfig  | 2 ++
 configs/mx6qpsabreauto_defconfig  | 2 ++
 configs/mx6qsabreauto_defconfig   | 2 ++
 configs/mx6sabresd_spl_defconfig  | 1 +
 include/configs/mx6sabre_common.h | 3 ++-
 5 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index ba5ab8a..dae89fe 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -42,3 +42,5 @@ CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 96a248e..2f95ab0 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -41,3 +41,5 @@ CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 015207d..20b39dc 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -42,3 +42,5 @@ CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 58d0b4b..4dff0c3 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -53,3 +53,4 @@ CONFIG_OF_LIBFDT=y
 # CONFIG_BLK is not set
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_SYS_I2C_MXC=y
+CONFIG_FEC_MXC=y
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 9b0fe5a..fbddb86 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -21,7 +21,7 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
-#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RGMII
@@ -30,6 +30,7 @@
 
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
+#endif
 
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
-- 
1.9.1

[U-Boot] [PATCH v7 14/17] net: fec_mxc: Add 'phy-reset-gpios' support

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

phy-reset-gpios property needed for adding mii_dev
reset bus operation, so the board code not take care
of phy_reset anymore if it use DM_ETH

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
---
 drivers/net/fec_mxc.c | 64 +++++++++++++++++++++++++++++++++++++++++++++------
 drivers/net/fec_mxc.h |  8 +++++++
 include/netdev.h      |  5 ++++
 3 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 08bea8b..5e16f02 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -180,13 +180,27 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
 			int regaddr)
 {
-	return fec_mdio_read(bus->priv, phyaddr, regaddr);
+#ifdef CONFIG_DM_ETH
+	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct ethernet_regs *eth = priv->eth;
+#else
+	struct ethernet_regs *eth = bus->priv;
+#endif
+
+	return fec_mdio_read(eth, phyaddr, regaddr);
 }
 
 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
 			 int regaddr, u16 data)
 {
-	return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
+#ifdef CONFIG_DM_ETH
+	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct ethernet_regs *eth = priv->eth;
+#else
+	struct ethernet_regs *eth = bus->priv;
+#endif
+
+	return fec_mdio_write(eth, phyaddr, regaddr, data);
 }
 
 #ifndef CONFIG_PHYLIB
@@ -985,9 +999,36 @@ static void fec_free_descs(struct fec_priv *fec)
 	free(fec->tbd_base);
 }
 
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
+static int fec_phy_reset(struct mii_dev *bus)
+{
+	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio))
+		return 0;
+
+	/* phy reset */
+	dm_gpio_set_value(&priv->reset_gpio, 0);
+	udelay(100);
+	dm_gpio_set_value(&priv->reset_gpio, 1);
+	udelay(100);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DM_ETH
+struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id)
+#else
 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
+#endif
 {
+#ifdef CONFIG_DM_ETH
+	struct fec_priv *priv = dev_get_priv(dev);
+	struct ethernet_regs *eth = priv->eth;
+#else
 	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
+#endif
 	struct mii_dev *bus;
 	int ret;
 
@@ -998,7 +1039,14 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
 	}
 	bus->read = fec_phy_read;
 	bus->write = fec_phy_write;
+#ifdef CONFIG_DM_ETH
+	bus->priv = dev;
+# ifdef CONFIG_DM_GPIO
+	bus->reset = fec_phy_reset;
+# endif
+#else
 	bus->priv = eth;
+#endif
 	fec_set_dev_name(bus->name, dev_id);
 
 	ret = mdio_register(bus);
@@ -1223,7 +1271,7 @@ static int fecmxc_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
+	bus = fec_get_miibus(dev, dev_id);
 	if (!bus)
 		goto err_mii;
 
@@ -1292,10 +1340,12 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	/* TODO
-	 * Need to get the reset-gpio and related properties from DT
-	 * and implemet the enet reset code on .probe call
-	 */
+#ifdef CONFIG_DM_GPIO
+	/* phy reset gpio */
+	gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
+				   "phy-reset-gpios", 0,
+				   &priv->reset_gpio, GPIOD_IS_OUT);
+#endif
 
 	return 0;
 }
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 43a7d7b..74ede4a 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -17,6 +17,10 @@
 #ifndef __FEC_MXC_H
 #define __FEC_MXC_H
 
+#ifdef CONFIG_DM_GPIO
+# include <asm-generic/gpio.h>
+#endif
+
 /* Layout description of the FEC */
 struct ethernet_regs {
 	/* [10:2]addr = 00 */
@@ -254,6 +258,10 @@ struct fec_priv {
 
 #ifdef CONFIG_DM_ETH
 	u32 interface;
+
+# ifdef CONFIG_DM_GPIO
+	struct gpio_desc reset_gpio;
+# endif
 #endif
 };
 
diff --git a/include/netdev.h b/include/netdev.h
index 8eb8b46..e5668f4 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -133,7 +133,12 @@ static inline int pci_eth_init(bd_t *bis)
 	return num;
 }
 
+#ifdef CONFIG_DM_ETH
+struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id);
+#else
 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
+#endif
+
 #ifdef CONFIG_PHYLIB
 struct phy_device;
 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
-- 
1.9.1

[U-Boot] [PATCH v7 15/17] i.MX6: SabreSD: Enable DM_ETH

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

(1) Enable DM_ETH
(2) Droped board_eth_init

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig          |  1 +
 board/freescale/mx6sabresd/mx6sabresd.c | 45 ++-------------------------------
 2 files changed, 3 insertions(+), 43 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index d1ba801..f4c8c39 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -214,6 +214,7 @@ config TARGET_MX6SABRESD
 	select BOARD_LATE_INIT
 	select OF_CONTROL
 	select DM
+	select DM_ETH
 	select DM_GPIO
 	select DM_MMC
 	select DM_REGULATOR
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 688b326..7eab021 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -17,7 +17,6 @@
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/video.h>
 #include <miiphy.h>
-#include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
@@ -33,9 +32,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
@@ -60,37 +56,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const enet_pads[] = {
-	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* AR8031 PHY Reset */
-	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_enet(void)
-{
-	SETUP_IOMUX_PADS(enet_pads);
-
-	/* Reset AR8031 PHY */
-	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-	udelay(100);
-}
-
 static iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -383,14 +348,6 @@ int overwrite_console(void)
 	return 1;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	setup_iomux_enet();
-	setup_pcie();
-
-	return cpu_eth_init(bis);
-}
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -414,6 +371,8 @@ int board_init(void)
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 
+	setup_pcie();
+
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH v7 16/17] i.MX6: sabresd: Drop checkboard

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Since SabreSD is supporting fdt, there is no use
of printing the board name explicitly using checkboard
because dtb supported u-boot will print model like this

Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 7eab021..7179883 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -442,9 +442,3 @@ int board_late_init(void)
 
 	return 0;
 }
-
-int checkboard(void)
-{
-	puts("Board: MX6-SabreSD\n");
-	return 0;
-}
-- 
1.9.1

[U-Boot] [PATCH v7 17/17] i.MX6: SabreSD: Cleanup board code

[Jagan Teki]

From: Jagan Teki <jagan@openedev.com>

- Give proper tab alignment for display_info_t structure
- Add tab spaces UART_PAD_CTRL and SPI_PAD_CTRL
- Give proper alignment of reg init values on setup_display
- Add space and newline on board_init_f
- Add static qualifier for file scope structures

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 195 ++++++++++++++++----------------
 board/freescale/mx6sabresd/spl.c        |  30 ++---
 include/configs/mx6sabresd.h            |   2 +-
 3 files changed, 114 insertions(+), 113 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 7179883..609cf30 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -28,21 +28,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+			PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define I2C_PAD		MUX_PAD_CTRL(I2C_PAD_CTRL)
 #define I2C_PMIC	1
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
 #define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
 
 int dram_init(void)
@@ -147,7 +141,7 @@ static void setup_spi(void)
 	SETUP_IOMUX_PADS(ecspi1_pads);
 }
 
-iomux_v3_cfg_t const pcie_pads[] = {
+static iomux_v3_cfg_t const pcie_pads[] = {
 	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* POWER */
 	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* RESET */
 };
@@ -157,7 +151,7 @@ static void setup_pcie(void)
 	SETUP_IOMUX_PADS(pcie_pads);
 }
 
-iomux_v3_cfg_t const di0_pads[] = {
+static iomux_v3_cfg_t const di0_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),	/* DISP0_CLK */
 	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),		/* DISP0_HSYNC */
 	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),		/* DISP0_VSYNC */
@@ -220,67 +214,72 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-struct display_info_t const displays[] = {{
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB666,
-	.detect	= NULL,
-	.enable	= enable_lvds,
-	.mode	= {
-		.name           = "Hannstar-XGA",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15384,
-		.left_margin    = 160,
-		.right_margin   = 24,
-		.upper_margin   = 29,
-		.lower_margin   = 3,
-		.hsync_len      = 136,
-		.vsync_len      = 6,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
-	.enable	= do_enable_hdmi,
-	.mode	= {
-		.name           = "HDMI",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15384,
-		.left_margin    = 160,
-		.right_margin   = 24,
-		.upper_margin   = 29,
-		.lower_margin   = 3,
-		.hsync_len      = 136,
-		.vsync_len      = 6,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= 0,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= NULL,
-	.enable	= enable_rgb,
-	.mode	= {
-		.name           = "SEIKO-WVGA",
-		.refresh        = 60,
-		.xres           = 800,
-		.yres           = 480,
-		.pixclock       = 29850,
-		.left_margin    = 89,
-		.right_margin   = 164,
-		.upper_margin   = 23,
-		.lower_margin   = 10,
-		.hsync_len      = 10,
-		.vsync_len      = 10,
-		.sync           = 0,
-		.vmode          = FB_VMODE_NONINTERLACED
-} } };
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB666,
+		.detect	= NULL,
+		.enable	= enable_lvds,
+		.mode	= {
+			.name           = "Hannstar-XGA",
+			.refresh        = 60,
+			.xres           = 1024,
+			.yres           = 768,
+			.pixclock       = 15384,
+			.left_margin    = 160,
+			.right_margin   = 24,
+			.upper_margin   = 29,
+			.lower_margin   = 3,
+			.hsync_len      = 136,
+			.vsync_len      = 6,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}, {
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= do_enable_hdmi,
+		.mode	= {
+			.name           = "HDMI",
+			.refresh        = 60,
+			.xres           = 1024,
+			.yres           = 768,
+			.pixclock       = 15384,
+			.left_margin    = 160,
+			.right_margin   = 24,
+			.upper_margin   = 29,
+			.lower_margin   = 3,
+			.hsync_len      = 136,
+			.vsync_len      = 6,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}, {
+		.bus	= 0,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= NULL,
+		.enable	= enable_rgb,
+		.mode	= {
+			.name           = "SEIKO-WVGA",
+			.refresh        = 60,
+			.xres           = 800,
+			.yres           = 480,
+			.pixclock       = 29850,
+			.left_margin    = 89,
+			.right_margin   = 164,
+			.upper_margin   = 23,
+			.lower_margin   = 10,
+			.hsync_len      = 10,
+			.vsync_len      = 10,
+			.sync           = 0,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	}
+};
 size_t display_count = ARRAY_SIZE(displays);
 
 static void setup_display(void)
@@ -302,10 +301,10 @@ static void setup_display(void)
 
 	/* set LDB0, LDB1 clk select to 011/011 */
 	reg = readl(&mxc_ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-	      | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->cs2cdr);
 
 	reg = readl(&mxc_ccm->cscmr2);
@@ -313,28 +312,28 @@ static void setup_display(void)
 	writel(reg, &mxc_ccm->cscmr2);
 
 	reg = readl(&mxc_ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
-	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-	     | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
-	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	     | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
-	     | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
-	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+		IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+		IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+		IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+		IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+		IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
+		IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 	writel(reg, &iomux->gpr[2]);
 
 	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
-			| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
+		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 	writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
diff --git a/board/freescale/mx6sabresd/spl.c b/board/freescale/mx6sabresd/spl.c
index 2488cb5..77b650f 100644
--- a/board/freescale/mx6sabresd/spl.c
+++ b/board/freescale/mx6sabresd/spl.c
@@ -37,20 +37,20 @@ DECLARE_GLOBAL_DATA_PTR;
 static iomux_v3_cfg_t const usdhc2_pads[] = {
 	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -59,12 +59,12 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc4_pads[] = {
-	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -113,6 +113,7 @@ int board_mmc_init(bd_t *bis)
 {
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
+
 	/*
 	 * Upon reading BOOT_CFG register the following map is done:
 	 * Bit 11 and 12 of BOOT_CFG register can determine the current
@@ -496,6 +497,7 @@ void board_init_f(ulong dummy)
 	arch_cpu_init();
 
 	ccgr_init();
+
 	gpr_init();
 
 	/* iomux and setup of i2c */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 44c7cf6..4b48347 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -20,7 +20,7 @@
 #define CONFIG_MACH_TYPE	3980
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONSOLE_DEV		"ttymxc0"
-#define CONFIG_MMCROOT			"/dev/mmcblk1p2"
+#define CONFIG_MMCROOT		"/dev/mmcblk1p2"
 
 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 
-- 
1.9.1

[U-Boot] [PATCH v7 14/17] net: fec_mxc: Add 'phy-reset-gpios' support

[Fabio Estevam]

Hi Jagan,

On Tue, May 23, 2017 at 4:58 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
> +static int fec_phy_reset(struct mii_dev *bus)
> +{
> +       struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
> +
> +       if (!dm_gpio_is_valid(&priv->reset_gpio))
> +               return 0;
> +
> +       /* phy reset */
> +       dm_gpio_set_value(&priv->reset_gpio, 0);
> +       udelay(100);
> +       dm_gpio_set_value(&priv->reset_gpio, 1);
> +       udelay(100);

Please don't add a fixed delay here. It would be better to do like in
the kernel where we also have the 'phy-reset-duration' property that
specifies the reset duration.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

Hi Stefano/Fabio,

On Tue, May 23, 2017 at 1:28 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@openedev.com>
>
> Fabio, please add your changes on-top-of this series.
>
> Compared to previous series, this series
> - Removed 'Fabio' patch changes.
> - Droped DM_I2C and DM_PMIC, since power driver need to chage dm
> - Added phy-reset-gpio support for fec_mxc driver
> - Added Linux merge tag details on dts patches
>
> Changes for v6:
> - rebase on u-boot-imx/master
> - Droped DM_I2C and DM_PMIC changes
> - Added phy-reset-gpio support for fec_mxc driver
> - Added Linux merge tag details on dts patches
> - Removed 'Fabio' patch changes.
>
> Changes for v6:
> - rebase on u-boot-imx/master
> - Fixed comments from 'Fabio' in v5
> - Droped file/directory rename changes patches
> - Droped dm_gpio changes on board
>
> Changes for v5:
> - rebase on master
> - removed SPL support for i.MX6DL SabreSD
> - Add board_fit_config_name_match for SPL to fetch board dts
> - Add imx6qdl_sabresd_spl_defconfig for common SPL support
>
> Changes for v4:
> - rebase on master
> - Rename imx6[dl|q]_sabresd_spl_defconfig to imx6[dl|q]_sabresd_spl_defconfig
> - Update README
> - Move CONFIG_FEC_MXC to configs/mx6[dl|q|qp]sabreauto_defconfigs
> - Add dts support for non-spl based defconfigs
>
> Changes for v3:
> - rebase on master
> - Added patch 'ARM: i.MX6: sabresd: Cleanup board code'
> - Added patch 'ARM: i.MX6DL: sabresd: Move DCD reginit on SPL'
>
> Changes for v2:
> - rebase on master
> - Added new-patches.
>
> Jagan Teki (17):
>   ARM: i.MX6: sabresd: Remove SPL_I2C_SUPPORT
>   ARM: dts: i.MX6: Add imx6qdl-sabresd.dtsi
>   ARM: dts: i.MX6: Add imx6q-sabresd.dts
>   ARM: dts: i.MX6: Add imx6dl-sabresd.dts
>   ARM: dts: i.MX6: Add imx6qp.dtsi
>   ARM: dts: i.MX6: Add imx6qp-sabresd.dts
>   sabresd: i.MX6Q: Add initial dts support
>   sabresd: i.MX6QP: Add initial dts support
>   SabreSD: i.MX6DL: Add initial dts support
>   SabreSD: Move CONFIG_SYS_I2C_MXC to defconfigs
>   SabreSD: Enable CONFIG_DM_REGULATOR
>   SabreSD: Enable DM_USB
>   i.MX6: Sabre: Move CONFIG_FEC_MXC to defconfigs
>   net: fec_mxc: Add 'phy-reset-gpios' support
>   i.MX6: SabreSD: Enable DM_ETH
>   i.MX6: sabresd: Drop checkboard
>   i.MX6: SabreSD: Cleanup board code

Can you finalize this series, early to have better test.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

Hi Jagan,

On Fri, May 26, 2017 at 1:41 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> Can you finalize this series, early to have better test.

The issue I see with this series is that the 'pmic' commands are gone.

Do you plan to fix it?

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Fri, May 26, 2017 at 10:17 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Jagan,
>
> On Fri, May 26, 2017 at 1:41 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>> Can you finalize this series, early to have better test.
>
> The issue I see with this series is that the 'pmic' commands are gone.
>
> Do you plan to fix it?

Yes, Pointed the same on cover-letter, I2C and PMIC combo not using
dts as of now since pmic area require driver-model conversion so these
are as-it-is.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

Hi Jagan,

On Fri, May 26, 2017 at 1:49 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> Yes, Pointed the same on cover-letter, I2C and PMIC combo not using
> dts as of now since pmic area require driver-model conversion so these
> are as-it-is.

Ok, but we should not lose the PMIC functionality.

It is fine if PMIC code stays in the board C file for now, but what I
don't want is to have PMIC unsupported after your series gets applied.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Fri, May 26, 2017 at 10:22 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Jagan,
>
> On Fri, May 26, 2017 at 1:49 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>> Yes, Pointed the same on cover-letter, I2C and PMIC combo not using
>> dts as of now since pmic area require driver-model conversion so these
>> are as-it-is.
>
> Ok, but we should not lose the PMIC functionality.
>
> It is fine if PMIC code stays in the board C file for now, but what I
> don't want is to have PMIC unsupported after your series gets applied.

No, PMIC and I2C are as it is like old code, I never did any
modification to use it for dts since driver require dm.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

On Fri, May 26, 2017 at 1:55 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> No, PMIC and I2C are as it is like old code, I never did any
> modification to use it for dts since driver require dm.

Let me try to clarify the problem.

If I use the latest u-boot-imx:

U-Boot SPL 2017.05-35079-g4c78028 (May 26 2017 - 13:58:48)
Trying to boot from MMC1


U-Boot 2017.05-35079-g4c78028 (May 26 2017 - 13:58:48 -0300)

CPU:   Freescale i.MX6Q rev1.1 at 792MHz
CPU:   Commercial temperature grade (0C to 95C) at 31C
Reset cause: POR
Board: MX6-SabreSD
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
PCI:   pcie phy link never came up
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
=> pmic
pmic - PMIC

Usage:
pmic list - list available PMICs
pmic name dump - dump named PMIC registers
pmic name read <reg> - read register
pmic name write <reg> <value> - write register
pmic name bat state - write register
pmic name bat charge - write register

If I use your series:

U-Boot SPL 2017.05-rc3-00037-g60e903a (May 26 2017 - 14:02:35)
Trying to boot from MMC1


U-Boot 2017.05-rc3-00037-g60e903a (May 26 2017 - 14:02:35 -0300)

CPU:   Freescale i.MX6Q rev1.1 at 792MHz
CPU:   Commercial temperature grade (0C to 95C) at 38C
Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
PCI:   pcie phy link never came up
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   eth0: ethernet at 02188000
Hit any key to stop autoboot:  0
=> pmic
Unknown command 'pmic' - try 'help'
=>

As you can see the 'pmic' command is no longer present with your series.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Fri, May 26, 2017 at 10:34 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Fri, May 26, 2017 at 1:55 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>> No, PMIC and I2C are as it is like old code, I never did any
>> modification to use it for dts since driver require dm.
>
> Let me try to clarify the problem.
>
> If I use the latest u-boot-imx:
>
> U-Boot SPL 2017.05-35079-g4c78028 (May 26 2017 - 13:58:48)
> Trying to boot from MMC1
>
>
> U-Boot 2017.05-35079-g4c78028 (May 26 2017 - 13:58:48 -0300)
>
> CPU:   Freescale i.MX6Q rev1.1 at 792MHz
> CPU:   Commercial temperature grade (0C to 95C) at 31C
> Reset cause: POR
> Board: MX6-SabreSD
> I2C:   ready
> DRAM:  1 GiB
> PMIC:  PFUZE100 ID=0x10
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> PCI:   pcie phy link never came up
> No panel detected: default to Hannstar-XGA
> Display: Hannstar-XGA (1024x768)
> In:    serial
> Out:   serial
> Err:   serial
> Net:   FEC [PRIME]
> Hit any key to stop autoboot:  0
> => pmic
> pmic - PMIC
>
> Usage:
> pmic list - list available PMICs
> pmic name dump - dump named PMIC registers
> pmic name read <reg> - read register
> pmic name write <reg> <value> - write register
> pmic name bat state - write register
> pmic name bat charge - write register
>
> If I use your series:
>
> U-Boot SPL 2017.05-rc3-00037-g60e903a (May 26 2017 - 14:02:35)
> Trying to boot from MMC1
>
>
> U-Boot 2017.05-rc3-00037-g60e903a (May 26 2017 - 14:02:35 -0300)
>
> CPU:   Freescale i.MX6Q rev1.1 at 792MHz
> CPU:   Commercial temperature grade (0C to 95C) at 38C
> Reset cause: POR
> Model: Freescale i.MX6 Quad SABRE Smart Device Board
> DRAM:  1 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> PCI:   pcie phy link never came up
> No panel detected: default to Hannstar-XGA
> Display: Hannstar-XGA (1024x768)
> In:    serial
> Out:   serial
> Err:   serial
> Net:   eth0: ethernet at 02188000
> Hit any key to stop autoboot:  0
> => pmic
> Unknown command 'pmic' - try 'help'

Can you please confirm, are you using v7 series? in this I kept the
PMIC as it is.

/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR  0x08

thanks!



-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

On Fri, May 26, 2017 at 2:14 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> Can you please confirm, are you using v7 series? in this I kept the
> PMIC as it is.
>
> /* PMIC */
> #define CONFIG_POWER
> #define CONFIG_POWER_I2C
> #define CONFIG_POWER_PFUZE100
> #define CONFIG_POWER_PFUZE100_I2C_ADDR  0x08

I used the latest version from your git tree and these options seem to
be missing there.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Fri, May 26, 2017 at 10:47 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Fri, May 26, 2017 at 2:14 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>> Can you please confirm, are you using v7 series? in this I kept the
>> PMIC as it is.
>>
>> /* PMIC */
>> #define CONFIG_POWER
>> #define CONFIG_POWER_I2C
>> #define CONFIG_POWER_PFUZE100
>> #define CONFIG_POWER_PFUZE100_I2C_ADDR  0x08
>
> I used the latest version from your git tree and these options seem to
> be missing there.

OK, please rebase now, forgot to update this series changes.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Fabio Estevam]

Hi Jagan,

On Fri, May 26, 2017 at 2:28 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:

> OK, please rebase now, forgot to update this series changes.

The pmic command appears in this version, but I see other issues now:

U-Boot SPL 2017.05-00704-g16fa9ec (May 26 2017 - 14:30:16)
Trying to boot from MMC1


U-Boot 2017.05-00704-g16fa9ec (May 26 2017 - 14:30:16 -0300)

CPU:   Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 38C
Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
gpio at 020a4000: dir_output: error: gpio GPIO3_19 not reserved
gpio at 020a4000: set_value: error: gpio GPIO3_19 not reserved
gpio at 020b4000: dir_output: error: gpio GPIO7_12 not reserved
gpio at 020b4000: set_value: error: gpio GPIO7_12 not reserved

(These errors are new)

PCI:   pcie phy link never came up
No panel detected: default to Hannstar-XGA
gpio at 0209c000: dir_output: error: gpio GPIO1_21 not reserved
Display: Hannstar-XGA (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet at 02188000 MAC addresses don't match:
Address in ROM is          00:04:9f:02:70:67
Address in environment is  00:04:9f:02:19:a0
eth0: ethernet at 02188000
Hit any key to stop autoboot:  0
=> dhcp zImage
Read MDIO failed...
Read MDIO failed...
Read MDIO failed...
Read MDIO failed...
Read MDIO failed...
Read MDIO failed...
Read MDIO failed...

(Ethernet does not work anymore).

[U-Boot] [PATCH v7 00/17] ARM: i.MX6: SabreSD: Add dts support

[Jagan Teki]

On Fri, May 26, 2017 at 11:04 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Jagan,
>
> On Fri, May 26, 2017 at 2:28 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>
>> OK, please rebase now, forgot to update this series changes.
>
> The pmic command appears in this version, but I see other issues now:
>
> U-Boot SPL 2017.05-00704-g16fa9ec (May 26 2017 - 14:30:16)
> Trying to boot from MMC1
>
>
> U-Boot 2017.05-00704-g16fa9ec (May 26 2017 - 14:30:16 -0300)
>
> CPU:   Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
> CPU:   Automotive temperature grade (-40C to 125C) at 38C
> Reset cause: POR
> Model: Freescale i.MX6 Quad SABRE Smart Device Board
> I2C:   ready
> DRAM:  1 GiB
> PMIC:  PFUZE100 ID=0x10
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> gpio at 020a4000: dir_output: error: gpio GPIO3_19 not reserved
> gpio at 020a4000: set_value: error: gpio GPIO3_19 not reserved
> gpio at 020b4000: dir_output: error: gpio GPIO7_12 not reserved
> gpio at 020b4000: set_value: error: gpio GPIO7_12 not reserved
>
> (These errors are new)

Yes, because of non-dm-gpio calls.

>
> PCI:   pcie phy link never came up
> No panel detected: default to Hannstar-XGA
> gpio at 0209c000: dir_output: error: gpio GPIO1_21 not reserved
> Display: Hannstar-XGA (1024x768)
> In:    serial
> Out:   serial
> Err:   serial
> Net:
> Warning: ethernet at 02188000 MAC addresses don't match:
> Address in ROM is          00:04:9f:02:70:67
> Address in environment is  00:04:9f:02:19:a0
> eth0: ethernet at 02188000
> Hit any key to stop autoboot:  0
> => dhcp zImage
> Read MDIO failed...
> Read MDIO failed...
> Read MDIO failed...
> Read MDIO failed...
> Read MDIO failed...
> Read MDIO failed...
> Read MDIO failed...
>
> (Ethernet does not work anymore).

Will fix, and get back.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v7 14/17] net: fec_mxc: Add 'phy-reset-gpios' support

[Lothar Waßmann]

Hi,

On Tue, 23 May 2017 13:28:27 +0530 Jagan Teki wrote:
> From: Jagan Teki <jagan@openedev.com>
> 
> phy-reset-gpios property needed for adding mii_dev
> reset bus operation, so the board code not take care
> of phy_reset anymore if it use DM_ETH
> 
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Jagan Teki <jagan@openedev.com>
> ---
>  drivers/net/fec_mxc.c | 64 +++++++++++++++++++++++++++++++++++++++++++++------
>  drivers/net/fec_mxc.h |  8 +++++++
>  include/netdev.h      |  5 ++++
>  3 files changed, 70 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 08bea8b..5e16f02 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -180,13 +180,27 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
>  static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
>  			int regaddr)
>  {
> -	return fec_mdio_read(bus->priv, phyaddr, regaddr);
> +#ifdef CONFIG_DM_ETH
> +	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
> +	struct ethernet_regs *eth = priv->eth;
> +#else
> +	struct ethernet_regs *eth = bus->priv;
> +#endif
> +
> +	return fec_mdio_read(eth, phyaddr, regaddr);
>  }
>  
>  static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
>  			 int regaddr, u16 data)
>  {
> -	return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
> +#ifdef CONFIG_DM_ETH
> +	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
> +	struct ethernet_regs *eth = priv->eth;
> +#else
> +	struct ethernet_regs *eth = bus->priv;
> +#endif
> +
> +	return fec_mdio_write(eth, phyaddr, regaddr, data);
>  }
>  
>  #ifndef CONFIG_PHYLIB
> @@ -985,9 +999,36 @@ static void fec_free_descs(struct fec_priv *fec)
>  	free(fec->tbd_base);
>  }
>  
> +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
> +static int fec_phy_reset(struct mii_dev *bus)
> +{
> +	struct fec_priv *priv = dev_get_priv((struct udevice *)bus->priv);
> +
> +	if (!dm_gpio_is_valid(&priv->reset_gpio))
> +		return 0;
> +
> +	/* phy reset */
> +	dm_gpio_set_value(&priv->reset_gpio, 0);
> +	udelay(100);
> +	dm_gpio_set_value(&priv->reset_gpio, 1);
> +	udelay(100);
> +
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_DM_ETH
> +struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id)
> +#else
>  struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
> +#endif
>  {
> +#ifdef CONFIG_DM_ETH
> +	struct fec_priv *priv = dev_get_priv(dev);
> +	struct ethernet_regs *eth = priv->eth;
> +#else
>  	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
> +#endif
>  	struct mii_dev *bus;
>  	int ret;
>  
> @@ -998,7 +1039,14 @@ struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
>  	}
>  	bus->read = fec_phy_read;
>  	bus->write = fec_phy_write;
> +#ifdef CONFIG_DM_ETH
> +	bus->priv = dev;
> +# ifdef CONFIG_DM_GPIO
> +	bus->reset = fec_phy_reset;
> +# endif
> +#else
>  	bus->priv = eth;
> +#endif
>  	fec_set_dev_name(bus->name, dev_id);
>  
>  	ret = mdio_register(bus);
> @@ -1223,7 +1271,7 @@ static int fecmxc_probe(struct udevice *dev)
>  	if (ret)
>  		return ret;
>  
> -	bus = fec_get_miibus((uint32_t)priv->eth, dev_id);
> +	bus = fec_get_miibus(dev, dev_id);
>
This should be conditional on CONFIG_DM_ETH like the definition of
fec_get_miibus().

>  	if (!bus)
>  		goto err_mii;
>  
> @@ -1292,10 +1340,12 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
>  		return -EINVAL;
>  	}
>  
> -	/* TODO
> -	 * Need to get the reset-gpio and related properties from DT
> -	 * and implemet the enet reset code on .probe call
> -	 */
> +#ifdef CONFIG_DM_GPIO
> +	/* phy reset gpio */
> +	gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
> +				   "phy-reset-gpios", 0,
> +				   &priv->reset_gpio, GPIOD_IS_OUT);
> +#endif
>  
>  	return 0;
>  }
> diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
> index 43a7d7b..74ede4a 100644
> --- a/drivers/net/fec_mxc.h
> +++ b/drivers/net/fec_mxc.h
> @@ -17,6 +17,10 @@
>  #ifndef __FEC_MXC_H
>  #define __FEC_MXC_H
>  
> +#ifdef CONFIG_DM_GPIO
> +# include <asm-generic/gpio.h>
> +#endif
> +
>  /* Layout description of the FEC */
>  struct ethernet_regs {
>  	/* [10:2]addr = 00 */
> @@ -254,6 +258,10 @@ struct fec_priv {
>  
>  #ifdef CONFIG_DM_ETH
>  	u32 interface;
> +
> +# ifdef CONFIG_DM_GPIO
> +	struct gpio_desc reset_gpio;
> +# endif
>  #endif
>  };
>  
> diff --git a/include/netdev.h b/include/netdev.h
> index 8eb8b46..e5668f4 100644
> --- a/include/netdev.h
> +++ b/include/netdev.h
> @@ -133,7 +133,12 @@ static inline int pci_eth_init(bd_t *bis)
>  	return num;
>  }
>  
> +#ifdef CONFIG_DM_ETH
> +struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id);
> +#else
>  struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
> +#endif
> +
>  #ifdef CONFIG_PHYLIB
>  struct phy_device;
>  int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,


Lothar Waßmann