[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Geert Uytterhoeven]

        Hi all,

This patch series enables SMP on R-Car E2 (r8a7794).
The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
arch_timer CNTVOFF register, which thus needs workarounds on Linux.

  - The first patch adds a definition for MON_MODE, as suggested by Marc
    Zyngier,
  - The second patch makes sure CNTVOFF is initialized for boot and
    secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
    for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
    does not work on secondary CPU cores.
    This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
    arch timer frequency on RZ/G1E".
  - The third patch adds the required infrastructure (APMU device node
    and corresponding enable-method) to DT.
    Obviously this must not be applied on a branch that does not contain
    the first two patches!

Due to dependencies, I think it is easiest if the ARM maintainers provide
their Acked-by for patch 1, so the whole series can go in through Simon's
Renesas tree.

Changes compared to v2:
  - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
    allmodconfig),

Changes compared to v1:
  - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
  - Initialize CNTVOFF on Cortex-A15, too,
  - Use *_MODE definitions instead of hardcoded values,
  - Reduce duplication by calling the asm version from C,
  - Always build headsmp-apmu.o on R-Car Gen2.

This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested
on r8a7790/lager (quad Cortex-A15), and r8a7791/koelsch, r8a7791/porter,
r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).

Thanks!

Geert Uytterhoeven (2):
  ARM: Add definition for monitor mode
  ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

Sergei Shtylyov (1):
  ARM: dts: r8a7794: Add SMP support

 arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
 arch/arm/include/uapi/asm/ptrace.h       |  1 +
 arch/arm/mach-shmobile/Makefile          |  1 +
 arch/arm/mach-shmobile/common.h          |  2 ++
 arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
 7 files changed, 51 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S

-- 
2.7.4

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Geert Uytterhoeven]

        Hi all,

This patch series enables SMP on R-Car E2 (r8a7794).
The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
arch_timer CNTVOFF register, which thus needs workarounds on Linux.

  - The first patch adds a definition for MON_MODE, as suggested by Marc
    Zyngier,
  - The second patch makes sure CNTVOFF is initialized for boot and
    secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
    for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
    does not work on secondary CPU cores.
    This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
    arch timer frequency on RZ/G1E".
  - The third patch adds the required infrastructure (APMU device node
    and corresponding enable-method) to DT.
    Obviously this must not be applied on a branch that does not contain
    the first two patches!

Due to dependencies, I think it is easiest if the ARM maintainers provide
their Acked-by for patch 1, so the whole series can go in through Simon's
Renesas tree.

Changes compared to v2:
  - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
    allmodconfig),

Changes compared to v1:
  - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
  - Initialize CNTVOFF on Cortex-A15, too,
  - Use *_MODE definitions instead of hardcoded values,
  - Reduce duplication by calling the asm version from C,
  - Always build headsmp-apmu.o on R-Car Gen2.

This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested
on r8a7790/lager (quad Cortex-A15), and r8a7791/koelsch, r8a7791/porter,
r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).

Thanks!

Geert Uytterhoeven (2):
  ARM: Add definition for monitor mode
  ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

Sergei Shtylyov (1):
  ARM: dts: r8a7794: Add SMP support

 arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
 arch/arm/include/uapi/asm/ptrace.h       |  1 +
 arch/arm/mach-shmobile/Makefile          |  1 +
 arch/arm/mach-shmobile/common.h          |  2 ++
 arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
 7 files changed, 51 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S

-- 
2.7.4

[PATCH v3 1/3] ARM: Add definition for monitor mode

[Geert Uytterhoeven]

<asm/ptrace.h> provides *_MODE definitions for the various processor
modes, but monitor mode was missing.

Add MON_MODE to avoid code using the hardcoded value.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
ARM maintainers: Please provide your ack, as this is a dependency for a
mach-shmobile patch.

v3:
  - No changes,

v2:
  - New.
---
 arch/arm/include/uapi/asm/ptrace.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 5af0ed1b825a2aa9..70ff6bf489f31193 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -53,6 +53,7 @@
 #endif
 #define FIQ_MODE	0x00000011
 #define IRQ_MODE	0x00000012
+#define MON_MODE	0x00000016
 #define ABT_MODE	0x00000017
 #define HYP_MODE	0x0000001a
 #define UND_MODE	0x0000001b
-- 
2.7.4

[PATCH v3 2/3] ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

[Geert Uytterhoeven]

On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
Ideally it should be initialized by the boot loader, but it isn't.

For the boot CPU, CNTVOFF is initialized by Linux since commit
9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
initialization for r8a7794").
For secondary CPU cores, no such initialization is done.

Hence when enabling SMP on r8a7794, the kernel log is spammed with:

    WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
	     Please report this, consider using a different clocksource, if possible.
	     Your kernel is probably still fine.

As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
respect to CNTVOFF, we have been very lucky this just worked on R-Car
Gen2 SoCs with Cortex-A15 cores.

To fix this:
  - Move the existing inline asm code to initialize CNTVOFF to an
    assembler source file (adding comments and replacing hardcoded
    constants by definitions in the process), so it can be reused,
  - Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
    Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
  - Wrap the standard secondary_startup() routine inside a routine which
    initializes CNTVOFF.

Based on patches by Hisashi Nakamura in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
    allmodconfig),

v2:
  - Initialize CNTVOFF on Cortex-A15, too,
  - Use *_MODE definitions instead of hardcoded values,
  - Reduce duplication by calling the asm version from C,
  - Always build headsmp-apmu.o on R-Car Gen2.
---
 arch/arm/mach-shmobile/Makefile          |  1 +
 arch/arm/mach-shmobile/common.h          |  2 ++
 arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
 arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
 5 files changed, 43 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 64611a1b4276517b..32176a00c664ba16 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -22,6 +22,7 @@ cpu-y				:= platsmp.o headsmp.o
 # Shared SoC family objects
 obj-$(CONFIG_ARCH_RCAR_GEN2)	+= setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
 CFLAGS_setup-rcar-gen2.o	+= -march=armv7-a
+obj-$(CONFIG_ARCH_RCAR_GEN2)	+= headsmp-apmu.o
 obj-$(CONFIG_ARCH_R8A7790)	+= regulator-quirk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)	+= regulator-quirk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7793)	+= regulator-quirk-rcar-gen2.o
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 1a8f7b3ab449db56..ea6e9e2be3f7f4da 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -1,6 +1,7 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
+extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
@@ -11,6 +12,7 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
 			      unsigned long arg);
 extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
 extern bool shmobile_smp_init_fallback_ops(void);
+extern void shmobile_boot_apmu(void);
 extern void shmobile_boot_scu(void);
 extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
 					  unsigned int max_cpus);
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S
new file mode 100644
index 0000000000000000..db4743d2bf91cdf6
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -0,0 +1,37 @@
+/*
+ * SMP support for APMU based systems with Cortex A7/A15
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(shmobile_init_cntvoff)
+	/*
+	 * CNTVOFF has to be initialized either from non-secure Hypervisor
+	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+	 * then it should be handled by the secure code
+	 */
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */
+	instr_sync
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */
+	instr_sync
+	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */
+	instr_sync
+	cps	#SVC_MODE
+	ret	lr
+ENDPROC(shmobile_init_cntvoff)
+
+ENTRY(shmobile_boot_apmu)
+	bl	shmobile_init_cntvoff
+	b	secondary_startup
+ENDPROC(shmobile_boot_apmu)
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 3ca2c13346f0cbc3..4422b615a6ee6045 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	/* For this particular CPU register boot vector */
-	shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0);
+	shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
 
 	return apmu_wrap(cpu, apmu_power_on);
 }
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 7ab1690fab8299eb..5561dbed7a332a58 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -70,28 +70,12 @@ void __init rcar_gen2_timer_init(void)
 	void __iomem *base;
 	u32 freq;
 
+	shmobile_init_cntvoff();
+
 	if (of_machine_is_compatible("renesas,r8a7745") ||
 	    of_machine_is_compatible("renesas,r8a7792") ||
 	    of_machine_is_compatible("renesas,r8a7794")) {
 		freq = 260000000 / 8;	/* ZS / 8 */
-		/* CNTVOFF has to be initialized either from non-secure
-		 * Hypervisor mode or secure Monitor mode with SCR.NS==1.
-		 * If TrustZone is enabled then it should be handled by the
-		 * secure code.
-		 */
-		asm volatile(
-		"	cps	0x16\n"
-		"	mrc	p15, 0, r1, c1, c1, 0\n"
-		"	orr	r0, r1, #1\n"
-		"	mcr	p15, 0, r0, c1, c1, 0\n"
-		"	isb\n"
-		"	mov	r0, #0\n"
-		"	mcrr	p15, 4, r0, r0, c14\n"
-		"	isb\n"
-		"	mcr	p15, 0, r1, c1, c1, 0\n"
-		"	isb\n"
-		"	cps	0x13\n"
-			: : : "r0", "r1");
 	} else {
 		/* At Linux boot time the r8a7790 arch timer comes up
 		 * with the counter disabled. Moreover, it may also report
-- 
2.7.4

[PATCH v3 3/3] ARM: dts: r8a7794: Add SMP support

[Geert Uytterhoeven]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Add the device tree node for the Advanced Power Management Unit (APMU).
Use the "enable-method" prop to  point out that the APMU should be used
for the SMP support.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index a4c35d29f77c16dc..8d70e860468c5603 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -37,6 +37,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "renesas,apmu";
 
 		cpu0: cpu@0 {
 			device_type = "cpu";
@@ -65,6 +66,12 @@
 		};
 	};
 
+	apmu@e6151000 {
+		compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+		reg = <0 0xe6151000 0 0x188>;
+		cpus = <&cpu0 &cpu1>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
2.7.4

[PATCH v3 3/3] ARM: dts: r8a7794: Add SMP support

[Geert Uytterhoeven]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Add the device tree node for the Advanced Power Management Unit (APMU).
Use the "enable-method" prop to  point out that the APMU should be used
for the SMP support.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/boot/dts/r8a7794.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index a4c35d29f77c16dc..8d70e860468c5603 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -37,6 +37,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "renesas,apmu";
 
 		cpu0: cpu at 0 {
 			device_type = "cpu";
@@ -65,6 +66,12 @@
 		};
 	};
 
+	apmu at e6151000 {
+		compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+		reg = <0 0xe6151000 0 0x188>;
+		cpus = <&cpu0 &cpu1>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
2.7.4

Re: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Simon Horman]

On Fri, Sep 01, 2017 at 10:37:43AM +0200, Geert Uytterhoeven wrote:
>         Hi all,
> 
> This patch series enables SMP on R-Car E2 (r8a7794).
> The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
> arch_timer CNTVOFF register, which thus needs workarounds on Linux.
> 
>   - The first patch adds a definition for MON_MODE, as suggested by Marc
>     Zyngier,
>   - The second patch makes sure CNTVOFF is initialized for boot and
>     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
>     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
>     does not work on secondary CPU cores.
>     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
>     arch timer frequency on RZ/G1E".
>   - The third patch adds the required infrastructure (APMU device node
>     and corresponding enable-method) to DT.
>     Obviously this must not be applied on a branch that does not contain
>     the first two patches!
> 
> Due to dependencies, I think it is easiest if the ARM maintainers provide
> their Acked-by for patch 1, so the whole series can go in through Simon's
> Renesas tree.

Thanks Geert, this merge strategy is fine by me.

> 
> Changes compared to v2:
>   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
>     allmodconfig),
> 
> Changes compared to v1:
>   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
>   - Initialize CNTVOFF on Cortex-A15, too,
>   - Use *_MODE definitions instead of hardcoded values,
>   - Reduce duplication by calling the asm version from C,
>   - Always build headsmp-apmu.o on R-Car Gen2.
> 
> This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested
> on r8a7790/lager (quad Cortex-A15), and r8a7791/koelsch, r8a7791/porter,
> r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).
> 
> Thanks!
> 
> Geert Uytterhoeven (2):
>   ARM: Add definition for monitor mode
>   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
> 
> Sergei Shtylyov (1):
>   ARM: dts: r8a7794: Add SMP support
> 
>  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
>  arch/arm/include/uapi/asm/ptrace.h       |  1 +
>  arch/arm/mach-shmobile/Makefile          |  1 +
>  arch/arm/mach-shmobile/common.h          |  2 ++
>  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
>  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
>  7 files changed, 51 insertions(+), 19 deletions(-)
>  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
> 
> -- 
> 2.7.4
> 

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Simon Horman]

On Fri, Sep 01, 2017 at 10:37:43AM +0200, Geert Uytterhoeven wrote:
>         Hi all,
> 
> This patch series enables SMP on R-Car E2 (r8a7794).
> The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
> arch_timer CNTVOFF register, which thus needs workarounds on Linux.
> 
>   - The first patch adds a definition for MON_MODE, as suggested by Marc
>     Zyngier,
>   - The second patch makes sure CNTVOFF is initialized for boot and
>     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
>     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
>     does not work on secondary CPU cores.
>     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
>     arch timer frequency on RZ/G1E".
>   - The third patch adds the required infrastructure (APMU device node
>     and corresponding enable-method) to DT.
>     Obviously this must not be applied on a branch that does not contain
>     the first two patches!
> 
> Due to dependencies, I think it is easiest if the ARM maintainers provide
> their Acked-by for patch 1, so the whole series can go in through Simon's
> Renesas tree.

Thanks Geert, this merge strategy is fine by me.

> 
> Changes compared to v2:
>   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
>     allmodconfig),
> 
> Changes compared to v1:
>   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
>   - Initialize CNTVOFF on Cortex-A15, too,
>   - Use *_MODE definitions instead of hardcoded values,
>   - Reduce duplication by calling the asm version from C,
>   - Always build headsmp-apmu.o on R-Car Gen2.
> 
> This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested
> on r8a7790/lager (quad Cortex-A15), and r8a7791/koelsch, r8a7791/porter,
> r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).
> 
> Thanks!
> 
> Geert Uytterhoeven (2):
>   ARM: Add definition for monitor mode
>   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
> 
> Sergei Shtylyov (1):
>   ARM: dts: r8a7794: Add SMP support
> 
>  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
>  arch/arm/include/uapi/asm/ptrace.h       |  1 +
>  arch/arm/mach-shmobile/Makefile          |  1 +
>  arch/arm/mach-shmobile/common.h          |  2 ++
>  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
>  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
>  7 files changed, 51 insertions(+), 19 deletions(-)
>  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
> 
> -- 
> 2.7.4
> 

RE: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Fabrizio Castro]

> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org [mailto:linux-renesas-soc-owner@vger.kernel.org] On Behalf Of Geert
> Uytterhoeven
> Sent: 01 September 2017 09:38
> To: Simon Horman <horms@verge.net.au>; Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>;
> Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> Cc: linux-renesas-soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> Subject: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
>
>         Hi all,
>
> This patch series enables SMP on R-Car E2 (r8a7794).
> The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs
> workarounds on Linux.
>
>   - The first patch adds a definition for MON_MODE, as suggested by Marc
>     Zyngier,
>   - The second patch makes sure CNTVOFF is initialized for boot and
>     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
>     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
>     does not work on secondary CPU cores.
>     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
>     arch timer frequency on RZ/G1E".
>   - The third patch adds the required infrastructure (APMU device node
>     and corresponding enable-method) to DT.
>     Obviously this must not be applied on a branch that does not contain
>     the first two patches!
>
> Due to dependencies, I think it is easiest if the ARM maintainers provide their Acked-by for patch 1, so the whole series can go in
> through Simon's Renesas tree.
>
> Changes compared to v2:
>   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
>     allmodconfig),
>
> Changes compared to v1:
>   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
>   - Initialize CNTVOFF on Cortex-A15, too,
>   - Use *_MODE definitions instead of hardcoded values,
>   - Reduce duplication by calling the asm version from C,
>   - Always build headsmp-apmu.o on R-Car Gen2.
>
> This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested on r8a7790/lager (quad Cortex-A15), and
> r8a7791/koelsch, r8a7791/porter, r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).

Hello Geert,

last week we tried to enable APMU/SMP on the iWave RZG1E (r8a7745, dual Cortex-A7) G22D-SODIMM board unsuccessfully, this patch series fixes the problems we have been experiencing.

Thanks,
Fabrizio

Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>
> Thanks!
>
> Geert Uytterhoeven (2):
>   ARM: Add definition for monitor mode
>   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
>
> Sergei Shtylyov (1):
>   ARM: dts: r8a7794: Add SMP support
>
>  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
>  arch/arm/include/uapi/asm/ptrace.h       |  1 +
>  arch/arm/mach-shmobile/Makefile          |  1 +
>  arch/arm/mach-shmobile/common.h          |  2 ++
>  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
>  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
>  7 files changed, 51 insertions(+), 19 deletions(-)  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
>
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Fabrizio Castro]

> -----Original Message-----
> From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
> Uytterhoeven
> Sent: 01 September 2017 09:38
> To: Simon Horman <horms@verge.net.au>; Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>;
> Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> Cc: linux-renesas-soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> Subject: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
>
>         Hi all,
>
> This patch series enables SMP on R-Car E2 (r8a7794).
> The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs
> workarounds on Linux.
>
>   - The first patch adds a definition for MON_MODE, as suggested by Marc
>     Zyngier,
>   - The second patch makes sure CNTVOFF is initialized for boot and
>     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
>     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
>     does not work on secondary CPU cores.
>     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
>     arch timer frequency on RZ/G1E".
>   - The third patch adds the required infrastructure (APMU device node
>     and corresponding enable-method) to DT.
>     Obviously this must not be applied on a branch that does not contain
>     the first two patches!
>
> Due to dependencies, I think it is easiest if the ARM maintainers provide their Acked-by for patch 1, so the whole series can go in
> through Simon's Renesas tree.
>
> Changes compared to v2:
>   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
>     allmodconfig),
>
> Changes compared to v1:
>   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
>   - Initialize CNTVOFF on Cortex-A15, too,
>   - Use *_MODE definitions instead of hardcoded values,
>   - Reduce duplication by calling the asm version from C,
>   - Always build headsmp-apmu.o on R-Car Gen2.
>
> This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested on r8a7790/lager (quad Cortex-A15), and
> r8a7791/koelsch, r8a7791/porter, r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).

Hello Geert,

last week we tried to enable APMU/SMP on the iWave RZG1E (r8a7745, dual Cortex-A7) G22D-SODIMM board unsuccessfully, this patch series fixes the problems we have been experiencing.

Thanks,
Fabrizio

Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

>
> Thanks!
>
> Geert Uytterhoeven (2):
>   ARM: Add definition for monitor mode
>   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
>
> Sergei Shtylyov (1):
>   ARM: dts: r8a7794: Add SMP support
>
>  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
>  arch/arm/include/uapi/asm/ptrace.h       |  1 +
>  arch/arm/mach-shmobile/Makefile          |  1 +
>  arch/arm/mach-shmobile/common.h          |  2 ++
>  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
>  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
>  7 files changed, 51 insertions(+), 19 deletions(-)  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
>
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

RE: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Fabrizio Castro]

> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org [mailto:linux-renesas-soc-owner@vger.kernel.org] On Behalf Of Fabrizio Castro
> Sent: 01 September 2017 18:04
> To: Geert Uytterhoeven <geert+renesas@glider.be>; Simon Horman <horms@verge.net.au>; Magnus Damm
> <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier
> <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> Cc: linux-renesas-soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: RE: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
>
> > -----Original Message-----
> > From: linux-renesas-soc-owner@vger.kernel.org [mailto:linux-renesas-soc-owner@vger.kernel.org] On Behalf Of Geert
> > Uytterhoeven
> > Sent: 01 September 2017 09:38
> > To: Simon Horman <horms@verge.net.au>; Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>;
> > Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> > Cc: linux-renesas-soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> > Subject: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
> >
> >         Hi all,
> >
> > This patch series enables SMP on R-Car E2 (r8a7794).
> > The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs
> > workarounds on Linux.
> >
> >   - The first patch adds a definition for MON_MODE, as suggested by Marc
> >     Zyngier,
> >   - The second patch makes sure CNTVOFF is initialized for boot and
> >     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
> >     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
> >     does not work on secondary CPU cores.
> >     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
> >     arch timer frequency on RZ/G1E".
> >   - The third patch adds the required infrastructure (APMU device node
> >     and corresponding enable-method) to DT.
> >     Obviously this must not be applied on a branch that does not contain
> >     the first two patches!
> >
> > Due to dependencies, I think it is easiest if the ARM maintainers provide their Acked-by for patch 1, so the whole series can go in
> > through Simon's Renesas tree.
> >
> > Changes compared to v2:
> >   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
> >     allmodconfig),
> >
> > Changes compared to v1:
> >   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
> >   - Initialize CNTVOFF on Cortex-A15, too,
> >   - Use *_MODE definitions instead of hardcoded values,
> >   - Reduce duplication by calling the asm version from C,
> >   - Always build headsmp-apmu.o on R-Car Gen2.
> >
> > This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested on r8a7790/lager (quad Cortex-A15), and
> > r8a7791/koelsch, r8a7791/porter, r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).
>
> Hello Geert,
>
> last week we tried to enable APMU/SMP on the iWave RZG1E (r8a7745, dual Cortex-A7) G22D-SODIMM board unsuccessfully, this
> patch series fixes the problems we have been experiencing.

Hello Geert,

we tested your patch series on the RZG1M (r8a7743, dual Cortex-A15) too which was working well already, and it looks like the system keeps behaving properly.

Thanks,
Fabrizio

>
> Thanks,
> Fabrizio
>
> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> >
> > Thanks!
> >
> > Geert Uytterhoeven (2):
> >   ARM: Add definition for monitor mode
> >   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
> >
> > Sergei Shtylyov (1):
> >   ARM: dts: r8a7794: Add SMP support
> >
> >  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
> >  arch/arm/include/uapi/asm/ptrace.h       |  1 +
> >  arch/arm/mach-shmobile/Makefile          |  1 +
> >  arch/arm/mach-shmobile/common.h          |  2 ++
> >  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
> >  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
> >  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
> >  7 files changed, 51 insertions(+), 19 deletions(-)  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
> >
> > --
> > 2.7.4
>
>
>
>
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England &
> Wales under Registered No. 04586709.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Fabrizio Castro]

> -----Original Message-----
> From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Fabrizio Castro
> Sent: 01 September 2017 18:04
> To: Geert Uytterhoeven <geert+renesas@glider.be>; Simon Horman <horms@verge.net.au>; Magnus Damm
> <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier
> <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> Cc: linux-renesas-soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: RE: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
>
> > -----Original Message-----
> > From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
> > Uytterhoeven
> > Sent: 01 September 2017 09:38
> > To: Simon Horman <horms@verge.net.au>; Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>;
> > Catalin Marinas <catalin.marinas@arm.com>; Marc Zyngier <marc.zyngier@arm.com>; Mark Rutland <mark.rutland@arm.com>
> > Cc: linux-renesas-soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> > Subject: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2
> >
> >         Hi all,
> >
> > This patch series enables SMP on R-Car E2 (r8a7794).
> > The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs
> > workarounds on Linux.
> >
> >   - The first patch adds a definition for MON_MODE, as suggested by Marc
> >     Zyngier,
> >   - The second patch makes sure CNTVOFF is initialized for boot and
> >     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
> >     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
> >     does not work on secondary CPU cores.
> >     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
> >     arch timer frequency on RZ/G1E".
> >   - The third patch adds the required infrastructure (APMU device node
> >     and corresponding enable-method) to DT.
> >     Obviously this must not be applied on a branch that does not contain
> >     the first two patches!
> >
> > Due to dependencies, I think it is easiest if the ARM maintainers provide their Acked-by for patch 1, so the whole series can go in
> > through Simon's Renesas tree.
> >
> > Changes compared to v2:
> >   - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
> >     allmodconfig),
> >
> > Changes compared to v1:
> >   - New patch "[PATCH v2 1/3] ARM: Add definition for monitor mode",
> >   - Initialize CNTVOFF on Cortex-A15, too,
> >   - Use *_MODE definitions instead of hardcoded values,
> >   - Reduce duplication by calling the asm version from C,
> >   - Always build headsmp-apmu.o on R-Car Gen2.
> >
> > This has been tested on r8a7794/alt (dual Cortex-A7), and regression-tested on r8a7790/lager (quad Cortex-A15), and
> > r8a7791/koelsch, r8a7791/porter, r8a7792/blanche, and r8a7793/gose (dual Cortex-A15).
>
> Hello Geert,
>
> last week we tried to enable APMU/SMP on the iWave RZG1E (r8a7745, dual Cortex-A7) G22D-SODIMM board unsuccessfully, this
> patch series fixes the problems we have been experiencing.

Hello Geert,

we tested your patch series on the RZG1M (r8a7743, dual Cortex-A15) too which was working well already, and it looks like the system keeps behaving properly.

Thanks,
Fabrizio

>
> Thanks,
> Fabrizio
>
> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> >
> > Thanks!
> >
> > Geert Uytterhoeven (2):
> >   ARM: Add definition for monitor mode
> >   ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
> >
> > Sergei Shtylyov (1):
> >   ARM: dts: r8a7794: Add SMP support
> >
> >  arch/arm/boot/dts/r8a7794.dtsi           |  7 ++++++
> >  arch/arm/include/uapi/asm/ptrace.h       |  1 +
> >  arch/arm/mach-shmobile/Makefile          |  1 +
> >  arch/arm/mach-shmobile/common.h          |  2 ++
> >  arch/arm/mach-shmobile/headsmp-apmu.S    | 37 ++++++++++++++++++++++++++++++++
> >  arch/arm/mach-shmobile/platsmp-apmu.c    |  2 +-
> >  arch/arm/mach-shmobile/setup-rcar-gen2.c | 20 ++---------------
> >  7 files changed, 51 insertions(+), 19 deletions(-)  create mode 100644 arch/arm/mach-shmobile/headsmp-apmu.S
> >
> > --
> > 2.7.4
>
>
>
>
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England &
> Wales under Registered No. 04586709.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Simon Horman]

On Fri, Sep 01, 2017 at 10:42:44AM +0200, Simon Horman wrote:
> On Fri, Sep 01, 2017 at 10:37:43AM +0200, Geert Uytterhoeven wrote:
> >         Hi all,
> > 
> > This patch series enables SMP on R-Car E2 (r8a7794).
> > The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
> > arch_timer CNTVOFF register, which thus needs workarounds on Linux.
> > 
> >   - The first patch adds a definition for MON_MODE, as suggested by Marc
> >     Zyngier,
> >   - The second patch makes sure CNTVOFF is initialized for boot and
> >     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
> >     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
> >     does not work on secondary CPU cores.
> >     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
> >     arch timer frequency on RZ/G1E".
> >   - The third patch adds the required infrastructure (APMU device node
> >     and corresponding enable-method) to DT.
> >     Obviously this must not be applied on a branch that does not contain
> >     the first two patches!
> > 
> > Due to dependencies, I think it is easiest if the ARM maintainers provide
> > their Acked-by for patch 1, so the whole series can go in through Simon's
> > Renesas tree.
> 
> Thanks Geert, this merge strategy is fine by me.

This patch-set has been floating around one form or another for quite
some time now and this version is now well over a week old.

I've gone ahead and applied the first two patches for v4.15:
* ARM: Add definition for monitor mode
* ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

I will push those to the devel branch of the renesas tree later today.

I would like to deffer the third and last patch until v4.16 to avoid
an awkward branch dependency on the above - the branches are different
even though the tree is the same. Please resubmit this patch once the
above dependencies are present in an rc release, which at this stage
I expect to be v4.15-rc1.

* ARM: dts: r8a7794: Add SMP support

[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2

[Simon Horman]

On Fri, Sep 01, 2017 at 10:42:44AM +0200, Simon Horman wrote:
> On Fri, Sep 01, 2017 at 10:37:43AM +0200, Geert Uytterhoeven wrote:
> >         Hi all,
> > 
> > This patch series enables SMP on R-Car E2 (r8a7794).
> > The main hurdle here is that R-Car Gen2 boot loaders do not initialize the
> > arch_timer CNTVOFF register, which thus needs workarounds on Linux.
> > 
> >   - The first patch adds a definition for MON_MODE, as suggested by Marc
> >     Zyngier,
> >   - The second patch makes sure CNTVOFF is initialized for boot and
> >     secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done
> >     for the boot Cortex-A7 CPU core.  Without this, the ARM arch timer
> >     does not work on secondary CPU cores.
> >     This patch depends on "[PATCH v2] ARM: shmobile: rcar-gen2: Correct
> >     arch timer frequency on RZ/G1E".
> >   - The third patch adds the required infrastructure (APMU device node
> >     and corresponding enable-method) to DT.
> >     Obviously this must not be applied on a branch that does not contain
> >     the first two patches!
> > 
> > Due to dependencies, I think it is easiest if the ARM maintainers provide
> > their Acked-by for patch 1, so the whole series can go in through Simon's
> > Renesas tree.
> 
> Thanks Geert, this merge strategy is fine by me.

This patch-set has been floating around one form or another for quite
some time now and this version is now well over a week old.

I've gone ahead and applied the first two patches for v4.15:
* ARM: Add definition for monitor mode
* ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

I will push those to the devel branch of the renesas tree later today.

I would like to deffer the third and last patch until v4.16 to avoid
an awkward branch dependency on the above - the branches are different
even though the tree is the same. Please resubmit this patch once the
above dependencies are present in an rc release, which at this stage
I expect to be v4.15-rc1.

* ARM: dts: r8a7794: Add SMP support