* [PATCH 00/14] Add MMCI support for STM32F SoCs family
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard-qxv4g6HH51o @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Patrice Chotard
From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
This series reworks patches submitted one year ago by Andrea Merello [1]
but without succeed to merged it.
STM32F4 and STM32F7 SoCs families embeds a variant of the ARM PrimeCell
PL18x SD host controller, for which the mmci driver exists.
This series adds support for these SoCs to the mmci driver.
As other variants, this one need some specific quirks, that this
series address.
This series has been tested on following boards :
_ stm32f429-eval
_ stm32f469-disco
_ stm32f746-eval
_ stm32f769-disco
DT update for stm32f7 pinctrl, stm32f746-eval and stm32f769-disco boards
will be sent later to avoid conflict with pending stm32f7 series [1] which
is not yet merged on kernel mainline.
[1] https://www.spinics.net/lists/linux-mmc/msg41616.html
[2] https://patchwork.kernel.org/patch/10104447/
Andrea Merello (2):
ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
Patrice Chotard (12):
mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
mmc: mmci: Add support for setting pad type via pinctrl
mmc: mmci: Add STM32 variant
ARM: dts: stm32: Add SDIO controller for stm32f746
ARM: dts: stm32: Add SDIO controller for stm32f429
ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
ARM: configs: stm32: Enable MMC_ARMMMCI support
ARM: configs: stm32: Enable EXT3_FS support
clk: stm32: Add clk entry for SDMMC2 on stm32F769
gpio: stmpe: i2c transfer are forbiden in atomic context
arch/arm/boot/dts/stm32429i-eval.dts | 19 ++++++
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++
arch/arm/boot/dts/stm32f429.dtsi | 11 +++
arch/arm/boot/dts/stm32f469-disco.dts | 19 ++++++
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++
arch/arm/configs/stm32_defconfig | 3 +
arch/arm/mach-stm32/Kconfig | 3 +
drivers/clk/clk-stm32f4.c | 3 +-
drivers/gpio/gpio-stmpe.c | 20 +++---
drivers/mmc/host/mmci.c | 120 ++++++++++++++++++++++++++++-----
drivers/mmc/host/mmci.h | 6 ++
11 files changed, 231 insertions(+), 26 deletions(-)
--
1.9.1
--
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^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 00/14] Add MMCI support for STM32F SoCs family
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
This series reworks patches submitted one year ago by Andrea Merello [1]
but without succeed to merged it.
STM32F4 and STM32F7 SoCs families embeds a variant of the ARM PrimeCell
PL18x SD host controller, for which the mmci driver exists.
This series adds support for these SoCs to the mmci driver.
As other variants, this one need some specific quirks, that this
series address.
This series has been tested on following boards :
_ stm32f429-eval
_ stm32f469-disco
_ stm32f746-eval
_ stm32f769-disco
DT update for stm32f7 pinctrl, stm32f746-eval and stm32f769-disco boards
will be sent later to avoid conflict with pending stm32f7 series [1] which
is not yet merged on kernel mainline.
[1] https://www.spinics.net/lists/linux-mmc/msg41616.html
[2] https://patchwork.kernel.org/patch/10104447/
Andrea Merello (2):
ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
Patrice Chotard (12):
mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
mmc: mmci: Add support for setting pad type via pinctrl
mmc: mmci: Add STM32 variant
ARM: dts: stm32: Add SDIO controller for stm32f746
ARM: dts: stm32: Add SDIO controller for stm32f429
ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
ARM: configs: stm32: Enable MMC_ARMMMCI support
ARM: configs: stm32: Enable EXT3_FS support
clk: stm32: Add clk entry for SDMMC2 on stm32F769
gpio: stmpe: i2c transfer are forbiden in atomic context
arch/arm/boot/dts/stm32429i-eval.dts | 19 ++++++
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++
arch/arm/boot/dts/stm32f429.dtsi | 11 +++
arch/arm/boot/dts/stm32f469-disco.dts | 19 ++++++
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++
arch/arm/configs/stm32_defconfig | 3 +
arch/arm/mach-stm32/Kconfig | 3 +
drivers/clk/clk-stm32f4.c | 3 +-
drivers/gpio/gpio-stmpe.c | 20 +++---
drivers/mmc/host/mmci.c | 120 ++++++++++++++++++++++++++++-----
drivers/mmc/host/mmci.h | 6 ++
11 files changed, 231 insertions(+), 26 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 00/14] Add MMCI support for STM32F SoCs family
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
This series reworks patches submitted one year ago by Andrea Merello [1]
but without succeed to merged it.
STM32F4 and STM32F7 SoCs families embeds a variant of the ARM PrimeCell
PL18x SD host controller, for which the mmci driver exists.
This series adds support for these SoCs to the mmci driver.
As other variants, this one need some specific quirks, that this
series address.
This series has been tested on following boards :
_ stm32f429-eval
_ stm32f469-disco
_ stm32f746-eval
_ stm32f769-disco
DT update for stm32f7 pinctrl, stm32f746-eval and stm32f769-disco boards
will be sent later to avoid conflict with pending stm32f7 series [1] which
is not yet merged on kernel mainline.
[1] https://www.spinics.net/lists/linux-mmc/msg41616.html
[2] https://patchwork.kernel.org/patch/10104447/
Andrea Merello (2):
ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
Patrice Chotard (12):
mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
mmc: mmci: Add support for setting pad type via pinctrl
mmc: mmci: Add STM32 variant
ARM: dts: stm32: Add SDIO controller for stm32f746
ARM: dts: stm32: Add SDIO controller for stm32f429
ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
ARM: configs: stm32: Enable MMC_ARMMMCI support
ARM: configs: stm32: Enable EXT3_FS support
clk: stm32: Add clk entry for SDMMC2 on stm32F769
gpio: stmpe: i2c transfer are forbiden in atomic context
arch/arm/boot/dts/stm32429i-eval.dts | 19 ++++++
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++
arch/arm/boot/dts/stm32f429.dtsi | 11 +++
arch/arm/boot/dts/stm32f469-disco.dts | 19 ++++++
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++
arch/arm/configs/stm32_defconfig | 3 +
arch/arm/mach-stm32/Kconfig | 3 +
drivers/clk/clk-stm32f4.c | 3 +-
drivers/gpio/gpio-stmpe.c | 20 +++---
drivers/mmc/host/mmci.c | 120 ++++++++++++++++++++++++++++-----
drivers/mmc/host/mmci.h | 6 ++
11 files changed, 231 insertions(+), 26 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:15 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
Two mask registers are used in order to select which events have to
actually generate an interrupt on each IRQ line.
It seems that in the single-IRQ case it's assumed that the IRQs lines
are simply OR-ed, while the two mask registers are still present. The
driver still programs the two mask registers separately.
However the STM32 variant has only one IRQ, and also has only one mask
register.
This patch prepares for STM32 variant support by making the driver using
only one mask register.
This patch also optimize the MMCIMASK1 mask usage by caching it into
host->mask1_reg which avoid to read it into mmci_irq().
Tested only on STM32 variant. RFT for variants other than STM32
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 28 ++++++++++++++++++++++++----
drivers/mmc/host/mmci.h | 1 +
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 97da0fc..3125dc0 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -82,6 +82,7 @@
* @qcom_fifo: enables qcom specific fifo pio read logic.
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
+ * @mmcimask1: true if variant have a MMCIMASK1 register.
*/
struct variant_data {
unsigned int clkreg;
@@ -111,6 +112,7 @@ struct variant_data {
bool qcom_fifo;
bool qcom_dml;
bool reversed_irq_handling;
+ bool mmcimask1;
};
static struct variant_data variant_arm = {
@@ -120,6 +122,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.reversed_irq_handling = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -128,6 +131,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -137,6 +141,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_u300 = {
@@ -152,6 +157,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_nomadik = {
@@ -168,6 +174,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500 = {
@@ -190,6 +197,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500v2 = {
@@ -214,6 +222,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_qcom = {
@@ -232,6 +241,7 @@ struct variant_data {
.explicit_mclk_control = true,
.qcom_fifo = true,
.qcom_dml = true,
+ .mmcimask1 = true,
};
/* Busy detection for the ST Micro variant */
@@ -396,6 +406,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
void __iomem *base = host->base;
+ struct variant_data *variant = host->variant;
if (host->singleirq) {
unsigned int mask0 = readl(base + MMCIMASK0);
@@ -406,7 +417,10 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
writel(mask0, base + MMCIMASK0);
}
- writel(mask, base + MMCIMASK1);
+ if (variant->mmcimask1)
+ writel(mask, base + MMCIMASK1);
+
+ host->mask1_reg = mask;
}
static void mmci_stop_data(struct mmci_host *host)
@@ -1286,7 +1300,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
status = readl(host->base + MMCISTATUS);
if (host->singleirq) {
- if (status & readl(host->base + MMCIMASK1))
+ if (status & host->mask1_reg)
mmci_pio_irq(irq, dev_id);
status &= ~MCI_IRQ1MASK;
@@ -1729,7 +1743,10 @@ static int mmci_probe(struct amba_device *dev,
spin_lock_init(&host->lock);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
+
writel(0xfff, host->base + MMCICLEAR);
/*
@@ -1809,6 +1826,7 @@ static int mmci_remove(struct amba_device *dev)
if (mmc) {
struct mmci_host *host = mmc_priv(mmc);
+ struct variant_data *variant = host->variant;
/*
* Undo pm_runtime_put() in probe. We use the _sync
@@ -1819,7 +1837,9 @@ static int mmci_remove(struct amba_device *dev)
mmc_remove_host(mmc);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
writel(0, host->base + MMCICOMMAND);
writel(0, host->base + MMCIDATACTRL);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 4a8bef1..83160a9 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -223,6 +223,7 @@ struct mmci_host {
u32 clk_reg;
u32 datactrl_reg;
u32 busy_status;
+ u32 mask1_reg;
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
Two mask registers are used in order to select which events have to
actually generate an interrupt on each IRQ line.
It seems that in the single-IRQ case it's assumed that the IRQs lines
are simply OR-ed, while the two mask registers are still present. The
driver still programs the two mask registers separately.
However the STM32 variant has only one IRQ, and also has only one mask
register.
This patch prepares for STM32 variant support by making the driver using
only one mask register.
This patch also optimize the MMCIMASK1 mask usage by caching it into
host->mask1_reg which avoid to read it into mmci_irq().
Tested only on STM32 variant. RFT for variants other than STM32
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 28 ++++++++++++++++++++++++----
drivers/mmc/host/mmci.h | 1 +
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 97da0fc..3125dc0 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -82,6 +82,7 @@
* @qcom_fifo: enables qcom specific fifo pio read logic.
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
+ * @mmcimask1: true if variant have a MMCIMASK1 register.
*/
struct variant_data {
unsigned int clkreg;
@@ -111,6 +112,7 @@ struct variant_data {
bool qcom_fifo;
bool qcom_dml;
bool reversed_irq_handling;
+ bool mmcimask1;
};
static struct variant_data variant_arm = {
@@ -120,6 +122,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.reversed_irq_handling = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -128,6 +131,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -137,6 +141,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_u300 = {
@@ -152,6 +157,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_nomadik = {
@@ -168,6 +174,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500 = {
@@ -190,6 +197,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500v2 = {
@@ -214,6 +222,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_qcom = {
@@ -232,6 +241,7 @@ struct variant_data {
.explicit_mclk_control = true,
.qcom_fifo = true,
.qcom_dml = true,
+ .mmcimask1 = true,
};
/* Busy detection for the ST Micro variant */
@@ -396,6 +406,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
void __iomem *base = host->base;
+ struct variant_data *variant = host->variant;
if (host->singleirq) {
unsigned int mask0 = readl(base + MMCIMASK0);
@@ -406,7 +417,10 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
writel(mask0, base + MMCIMASK0);
}
- writel(mask, base + MMCIMASK1);
+ if (variant->mmcimask1)
+ writel(mask, base + MMCIMASK1);
+
+ host->mask1_reg = mask;
}
static void mmci_stop_data(struct mmci_host *host)
@@ -1286,7 +1300,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
status = readl(host->base + MMCISTATUS);
if (host->singleirq) {
- if (status & readl(host->base + MMCIMASK1))
+ if (status & host->mask1_reg)
mmci_pio_irq(irq, dev_id);
status &= ~MCI_IRQ1MASK;
@@ -1729,7 +1743,10 @@ static int mmci_probe(struct amba_device *dev,
spin_lock_init(&host->lock);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
+
writel(0xfff, host->base + MMCICLEAR);
/*
@@ -1809,6 +1826,7 @@ static int mmci_remove(struct amba_device *dev)
if (mmc) {
struct mmci_host *host = mmc_priv(mmc);
+ struct variant_data *variant = host->variant;
/*
* Undo pm_runtime_put() in probe. We use the _sync
@@ -1819,7 +1837,9 @@ static int mmci_remove(struct amba_device *dev)
mmc_remove_host(mmc);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
writel(0, host->base + MMCICOMMAND);
writel(0, host->base + MMCIDATACTRL);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 4a8bef1..83160a9 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -223,6 +223,7 @@ struct mmci_host {
u32 clk_reg;
u32 datactrl_reg;
u32 busy_status;
+ u32 mask1_reg;
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
Two mask registers are used in order to select which events have to
actually generate an interrupt on each IRQ line.
It seems that in the single-IRQ case it's assumed that the IRQs lines
are simply OR-ed, while the two mask registers are still present. The
driver still programs the two mask registers separately.
However the STM32 variant has only one IRQ, and also has only one mask
register.
This patch prepares for STM32 variant support by making the driver using
only one mask register.
This patch also optimize the MMCIMASK1 mask usage by caching it into
host->mask1_reg which avoid to read it into mmci_irq().
Tested only on STM32 variant. RFT for variants other than STM32
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 28 ++++++++++++++++++++++++----
drivers/mmc/host/mmci.h | 1 +
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 97da0fc..3125dc0 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -82,6 +82,7 @@
* @qcom_fifo: enables qcom specific fifo pio read logic.
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
+ * @mmcimask1: true if variant have a MMCIMASK1 register.
*/
struct variant_data {
unsigned int clkreg;
@@ -111,6 +112,7 @@ struct variant_data {
bool qcom_fifo;
bool qcom_dml;
bool reversed_irq_handling;
+ bool mmcimask1;
};
static struct variant_data variant_arm = {
@@ -120,6 +122,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.reversed_irq_handling = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -128,6 +131,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -137,6 +141,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_u300 = {
@@ -152,6 +157,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_nomadik = {
@@ -168,6 +174,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500 = {
@@ -190,6 +197,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500v2 = {
@@ -214,6 +222,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_qcom = {
@@ -232,6 +241,7 @@ struct variant_data {
.explicit_mclk_control = true,
.qcom_fifo = true,
.qcom_dml = true,
+ .mmcimask1 = true,
};
/* Busy detection for the ST Micro variant */
@@ -396,6 +406,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
void __iomem *base = host->base;
+ struct variant_data *variant = host->variant;
if (host->singleirq) {
unsigned int mask0 = readl(base + MMCIMASK0);
@@ -406,7 +417,10 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
writel(mask0, base + MMCIMASK0);
}
- writel(mask, base + MMCIMASK1);
+ if (variant->mmcimask1)
+ writel(mask, base + MMCIMASK1);
+
+ host->mask1_reg = mask;
}
static void mmci_stop_data(struct mmci_host *host)
@@ -1286,7 +1300,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
status = readl(host->base + MMCISTATUS);
if (host->singleirq) {
- if (status & readl(host->base + MMCIMASK1))
+ if (status & host->mask1_reg)
mmci_pio_irq(irq, dev_id);
status &= ~MCI_IRQ1MASK;
@@ -1729,7 +1743,10 @@ static int mmci_probe(struct amba_device *dev,
spin_lock_init(&host->lock);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
+
writel(0xfff, host->base + MMCICLEAR);
/*
@@ -1809,6 +1826,7 @@ static int mmci_remove(struct amba_device *dev)
if (mmc) {
struct mmci_host *host = mmc_priv(mmc);
+ struct variant_data *variant = host->variant;
/*
* Undo pm_runtime_put() in probe. We use the _sync
@@ -1819,7 +1837,9 @@ static int mmci_remove(struct amba_device *dev)
mmc_remove_host(mmc);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
writel(0, host->base + MMCICOMMAND);
writel(0, host->base + MMCIDATACTRL);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 4a8bef1..83160a9 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -223,6 +223,7 @@ struct mmci_host {
u32 clk_reg;
u32 datactrl_reg;
u32 busy_status;
+ u32 mask1_reg;
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:15 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
This patch prepares for supporting the STM32 variant that
has no such bit in the status register.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3125dc0..7e56f85 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -83,6 +83,8 @@
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
* @mmcimask1: true if variant have a MMCIMASK1 register.
+ * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
+ * register.
*/
struct variant_data {
unsigned int clkreg;
@@ -113,6 +115,7 @@ struct variant_data {
bool qcom_dml;
bool reversed_irq_handling;
bool mmcimask1;
+ bool start_err;
};
static struct variant_data variant_arm = {
@@ -123,6 +126,7 @@ struct variant_data {
.f_max = 100000000,
.reversed_irq_handling = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -132,6 +136,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -142,6 +147,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_u300 = {
@@ -158,6 +164,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_nomadik = {
@@ -175,6 +182,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500 = {
@@ -198,6 +206,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500v2 = {
@@ -223,6 +232,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_qcom = {
@@ -242,6 +252,7 @@ struct variant_data {
.qcom_fifo = true,
.qcom_dml = true,
.mmcimask1 = true,
+ .start_err = true,
};
/* Busy detection for the ST Micro variant */
@@ -935,8 +946,9 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
return;
/* First check for errors */
- if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
- MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+ if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
+ (host->variant->start_err ? MCI_STARTBITERR : 0) |
+ MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
u32 remain, success;
/* Terminate the DMA transfer */
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
This patch prepares for supporting the STM32 variant that
has no such bit in the status register.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3125dc0..7e56f85 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -83,6 +83,8 @@
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
* @mmcimask1: true if variant have a MMCIMASK1 register.
+ * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
+ * register.
*/
struct variant_data {
unsigned int clkreg;
@@ -113,6 +115,7 @@ struct variant_data {
bool qcom_dml;
bool reversed_irq_handling;
bool mmcimask1;
+ bool start_err;
};
static struct variant_data variant_arm = {
@@ -123,6 +126,7 @@ struct variant_data {
.f_max = 100000000,
.reversed_irq_handling = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -132,6 +136,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -142,6 +147,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_u300 = {
@@ -158,6 +164,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_nomadik = {
@@ -175,6 +182,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500 = {
@@ -198,6 +206,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500v2 = {
@@ -223,6 +232,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_qcom = {
@@ -242,6 +252,7 @@ struct variant_data {
.qcom_fifo = true,
.qcom_dml = true,
.mmcimask1 = true,
+ .start_err = true,
};
/* Busy detection for the ST Micro variant */
@@ -935,8 +946,9 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
return;
/* First check for errors */
- if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
- MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+ if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
+ (host->variant->start_err ? MCI_STARTBITERR : 0) |
+ MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
u32 remain, success;
/* Terminate the DMA transfer */
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
This patch prepares for supporting the STM32 variant that
has no such bit in the status register.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3125dc0..7e56f85 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -83,6 +83,8 @@
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
* @mmcimask1: true if variant have a MMCIMASK1 register.
+ * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
+ * register.
*/
struct variant_data {
unsigned int clkreg;
@@ -113,6 +115,7 @@ struct variant_data {
bool qcom_dml;
bool reversed_irq_handling;
bool mmcimask1;
+ bool start_err;
};
static struct variant_data variant_arm = {
@@ -123,6 +126,7 @@ struct variant_data {
.f_max = 100000000,
.reversed_irq_handling = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -132,6 +136,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -142,6 +147,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_u300 = {
@@ -158,6 +164,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_nomadik = {
@@ -175,6 +182,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500 = {
@@ -198,6 +206,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500v2 = {
@@ -223,6 +232,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_qcom = {
@@ -242,6 +252,7 @@ struct variant_data {
.qcom_fifo = true,
.qcom_dml = true,
.mmcimask1 = true,
+ .start_err = true,
};
/* Busy detection for the ST Micro variant */
@@ -935,8 +946,9 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
return;
/* First check for errors */
- if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
- MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+ if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
+ (host->variant->start_err ? MCI_STARTBITERR : 0) |
+ MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
u32 remain, success;
/* Terminate the DMA transfer */
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:15 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
The STM32 variant hasn't the control bit to switch pads in opendrain mode.
In this case we can achieve the same result by asking to the pinmux driver
to configure pins for us.
This patch make the mmci driver able to do this whenever needed.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
drivers/mmc/host/mmci.h | 5 +++++
2 files changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7e56f85..38e8c20 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -85,6 +85,8 @@
* @mmcimask1: true if variant have a MMCIMASK1 register.
* @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
* register.
+ * @opendrain: true if variant have dedicated bit for opendrain pins
+ * configuration.
*/
struct variant_data {
unsigned int clkreg;
@@ -116,6 +118,7 @@ struct variant_data {
bool reversed_irq_handling;
bool mmcimask1;
bool start_err;
+ bool opendrain;
};
static struct variant_data variant_arm = {
@@ -127,6 +130,7 @@ struct variant_data {
.reversed_irq_handling = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -137,6 +141,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -148,6 +153,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_u300 = {
@@ -165,6 +171,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_nomadik = {
@@ -183,6 +190,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500 = {
@@ -207,6 +215,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500v2 = {
@@ -233,6 +242,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_qcom = {
@@ -253,6 +263,7 @@ struct variant_data {
.qcom_dml = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
/* Busy detection for the ST Micro variant */
@@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct mmci_host *host = mmc_priv(mmc);
struct variant_data *variant = host->variant;
+ struct pinctrl_state *pins;
u32 pwr = 0;
unsigned long flags;
int ret;
+ bool is_opendrain;
if (host->plat->ios_handler &&
host->plat->ios_handler(mmc_dev(mmc), ios))
@@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
~MCI_ST_DATA2DIREN);
}
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
- if (host->hw_designer != AMBA_VENDOR_ST)
- pwr |= MCI_ROD;
- else {
- /*
- * The ST Micro variant use the ROD bit for something
- * else and only has OD (Open Drain).
- */
- pwr |= MCI_OD;
+ if (host->variant->opendrain) {
+ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
+ if (host->hw_designer != AMBA_VENDOR_ST) {
+ pwr |= MCI_ROD;
+ } else {
+ /*
+ * The ST Micro variant use the ROD bit for
+ * something else and only has OD (Open Drain).
+ */
+ pwr |= MCI_OD;
+ }
}
+ } else {
+ /*
+ * If the variant cannot configure the pads by its own, then we
+ * expect the pinctrl to be able to do that for us
+ */
+ is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
+ pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
+ MMCI_PINCTRL_STATE_OPENDRAIN :
+ MMCI_PINCTRL_STATE_PUSHPULL);
+ if (IS_ERR(pins))
+ dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
+ else
+ pinctrl_select_state(host->pinctrl, pins);
}
/*
@@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
host = mmc_priv(mmc);
host->mmc = mmc;
+ if (!variant->opendrain) {
+ host->pinctrl = devm_pinctrl_get(&dev->dev);
+ if (IS_ERR(host->pinctrl)) {
+ dev_err(&dev->dev, "failed to get pinctrl");
+ goto host_free;
+ }
+ }
+
host->hw_designer = amba_manf(dev);
host->hw_revision = amba_rev(dev);
dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 83160a9..de3d0b3 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -192,6 +192,10 @@
#define NR_SG 128
+/* pinctrl configs */
+#define MMCI_PINCTRL_STATE_PUSHPULL "default"
+#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
+
struct clk;
struct variant_data;
struct dma_chan;
@@ -227,6 +231,7 @@ struct mmci_host {
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
+ struct pinctrl *pinctrl;
u8 hw_designer;
u8 hw_revision:4;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
The STM32 variant hasn't the control bit to switch pads in opendrain mode.
In this case we can achieve the same result by asking to the pinmux driver
to configure pins for us.
This patch make the mmci driver able to do this whenever needed.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
drivers/mmc/host/mmci.h | 5 +++++
2 files changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7e56f85..38e8c20 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -85,6 +85,8 @@
* @mmcimask1: true if variant have a MMCIMASK1 register.
* @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
* register.
+ * @opendrain: true if variant have dedicated bit for opendrain pins
+ * configuration.
*/
struct variant_data {
unsigned int clkreg;
@@ -116,6 +118,7 @@ struct variant_data {
bool reversed_irq_handling;
bool mmcimask1;
bool start_err;
+ bool opendrain;
};
static struct variant_data variant_arm = {
@@ -127,6 +130,7 @@ struct variant_data {
.reversed_irq_handling = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -137,6 +141,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -148,6 +153,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_u300 = {
@@ -165,6 +171,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_nomadik = {
@@ -183,6 +190,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500 = {
@@ -207,6 +215,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500v2 = {
@@ -233,6 +242,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_qcom = {
@@ -253,6 +263,7 @@ struct variant_data {
.qcom_dml = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
/* Busy detection for the ST Micro variant */
@@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct mmci_host *host = mmc_priv(mmc);
struct variant_data *variant = host->variant;
+ struct pinctrl_state *pins;
u32 pwr = 0;
unsigned long flags;
int ret;
+ bool is_opendrain;
if (host->plat->ios_handler &&
host->plat->ios_handler(mmc_dev(mmc), ios))
@@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
~MCI_ST_DATA2DIREN);
}
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
- if (host->hw_designer != AMBA_VENDOR_ST)
- pwr |= MCI_ROD;
- else {
- /*
- * The ST Micro variant use the ROD bit for something
- * else and only has OD (Open Drain).
- */
- pwr |= MCI_OD;
+ if (host->variant->opendrain) {
+ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
+ if (host->hw_designer != AMBA_VENDOR_ST) {
+ pwr |= MCI_ROD;
+ } else {
+ /*
+ * The ST Micro variant use the ROD bit for
+ * something else and only has OD (Open Drain).
+ */
+ pwr |= MCI_OD;
+ }
}
+ } else {
+ /*
+ * If the variant cannot configure the pads by its own, then we
+ * expect the pinctrl to be able to do that for us
+ */
+ is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
+ pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
+ MMCI_PINCTRL_STATE_OPENDRAIN :
+ MMCI_PINCTRL_STATE_PUSHPULL);
+ if (IS_ERR(pins))
+ dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
+ else
+ pinctrl_select_state(host->pinctrl, pins);
}
/*
@@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
host = mmc_priv(mmc);
host->mmc = mmc;
+ if (!variant->opendrain) {
+ host->pinctrl = devm_pinctrl_get(&dev->dev);
+ if (IS_ERR(host->pinctrl)) {
+ dev_err(&dev->dev, "failed to get pinctrl");
+ goto host_free;
+ }
+ }
+
host->hw_designer = amba_manf(dev);
host->hw_revision = amba_rev(dev);
dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 83160a9..de3d0b3 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -192,6 +192,10 @@
#define NR_SG 128
+/* pinctrl configs */
+#define MMCI_PINCTRL_STATE_PUSHPULL "default"
+#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
+
struct clk;
struct variant_data;
struct dma_chan;
@@ -227,6 +231,7 @@ struct mmci_host {
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
+ struct pinctrl *pinctrl;
u8 hw_designer;
u8 hw_revision:4;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
The STM32 variant hasn't the control bit to switch pads in opendrain mode.
In this case we can achieve the same result by asking to the pinmux driver
to configure pins for us.
This patch make the mmci driver able to do this whenever needed.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
drivers/mmc/host/mmci.h | 5 +++++
2 files changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7e56f85..38e8c20 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -85,6 +85,8 @@
* @mmcimask1: true if variant have a MMCIMASK1 register.
* @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
* register.
+ * @opendrain: true if variant have dedicated bit for opendrain pins
+ * configuration.
*/
struct variant_data {
unsigned int clkreg;
@@ -116,6 +118,7 @@ struct variant_data {
bool reversed_irq_handling;
bool mmcimask1;
bool start_err;
+ bool opendrain;
};
static struct variant_data variant_arm = {
@@ -127,6 +130,7 @@ struct variant_data {
.reversed_irq_handling = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -137,6 +141,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -148,6 +153,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_u300 = {
@@ -165,6 +171,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_nomadik = {
@@ -183,6 +190,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500 = {
@@ -207,6 +215,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500v2 = {
@@ -233,6 +242,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_qcom = {
@@ -253,6 +263,7 @@ struct variant_data {
.qcom_dml = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
/* Busy detection for the ST Micro variant */
@@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct mmci_host *host = mmc_priv(mmc);
struct variant_data *variant = host->variant;
+ struct pinctrl_state *pins;
u32 pwr = 0;
unsigned long flags;
int ret;
+ bool is_opendrain;
if (host->plat->ios_handler &&
host->plat->ios_handler(mmc_dev(mmc), ios))
@@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
~MCI_ST_DATA2DIREN);
}
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
- if (host->hw_designer != AMBA_VENDOR_ST)
- pwr |= MCI_ROD;
- else {
- /*
- * The ST Micro variant use the ROD bit for something
- * else and only has OD (Open Drain).
- */
- pwr |= MCI_OD;
+ if (host->variant->opendrain) {
+ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
+ if (host->hw_designer != AMBA_VENDOR_ST) {
+ pwr |= MCI_ROD;
+ } else {
+ /*
+ * The ST Micro variant use the ROD bit for
+ * something else and only has OD (Open Drain).
+ */
+ pwr |= MCI_OD;
+ }
}
+ } else {
+ /*
+ * If the variant cannot configure the pads by its own, then we
+ * expect the pinctrl to be able to do that for us
+ */
+ is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
+ pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
+ MMCI_PINCTRL_STATE_OPENDRAIN :
+ MMCI_PINCTRL_STATE_PUSHPULL);
+ if (IS_ERR(pins))
+ dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
+ else
+ pinctrl_select_state(host->pinctrl, pins);
}
/*
@@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
host = mmc_priv(mmc);
host->mmc = mmc;
+ if (!variant->opendrain) {
+ host->pinctrl = devm_pinctrl_get(&dev->dev);
+ if (IS_ERR(host->pinctrl)) {
+ dev_err(&dev->dev, "failed to get pinctrl");
+ goto host_free;
+ }
+ }
+
host->hw_designer = amba_manf(dev);
host->hw_revision = amba_rev(dev);
dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 83160a9..de3d0b3 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -192,6 +192,10 @@
#define NR_SG 128
+/* pinctrl configs */
+#define MMCI_PINCTRL_STATE_PUSHPULL "default"
+#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
+
struct clk;
struct variant_data;
struct dma_chan;
@@ -227,6 +231,7 @@ struct mmci_host {
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
+ struct pinctrl *pinctrl;
u8 hw_designer;
u8 hw_revision:4;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:15 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
an ARM pl810.
This patch adds the STM32 variant so that mmci driver supports it.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 38e8c20..9fb5035 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -245,6 +245,23 @@ struct variant_data {
.opendrain = true,
};
+static struct variant_data variant_stm32 = {
+ .fifosize = 32 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+ .datalength_bits = 24,
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .st_sdio = true,
+ .st_clkdiv = true,
+ .pwrreg_powerup = MCI_PWR_ON,
+ .f_max = 48000000,
+ .pwrreg_clkgate = true,
+ .pwrreg_nopower = true,
+};
+
static struct variant_data variant_qcom = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
@@ -2019,6 +2036,11 @@ static int mmci_runtime_resume(struct device *dev)
.mask = 0xf0ffffff,
.data = &variant_ux500v2,
},
+ {
+ .id = 0x00880180,
+ .mask = 0x00ffffff,
+ .data = &variant_stm32,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
an ARM pl810.
This patch adds the STM32 variant so that mmci driver supports it.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 38e8c20..9fb5035 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -245,6 +245,23 @@ struct variant_data {
.opendrain = true,
};
+static struct variant_data variant_stm32 = {
+ .fifosize = 32 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+ .datalength_bits = 24,
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .st_sdio = true,
+ .st_clkdiv = true,
+ .pwrreg_powerup = MCI_PWR_ON,
+ .f_max = 48000000,
+ .pwrreg_clkgate = true,
+ .pwrreg_nopower = true,
+};
+
static struct variant_data variant_qcom = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
@@ -2019,6 +2036,11 @@ static int mmci_runtime_resume(struct device *dev)
.mask = 0xf0ffffff,
.data = &variant_ux500v2,
},
+ {
+ .id = 0x00880180,
+ .mask = 0x00ffffff,
+ .data = &variant_stm32,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
an ARM pl810.
This patch adds the STM32 variant so that mmci driver supports it.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 38e8c20..9fb5035 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -245,6 +245,23 @@ struct variant_data {
.opendrain = true,
};
+static struct variant_data variant_stm32 = {
+ .fifosize = 32 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+ .datalength_bits = 24,
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .st_sdio = true,
+ .st_clkdiv = true,
+ .pwrreg_powerup = MCI_PWR_ON,
+ .f_max = 48000000,
+ .pwrreg_clkgate = true,
+ .pwrreg_nopower = true,
+};
+
static struct variant_data variant_qcom = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
@@ -2019,6 +2036,11 @@ static int mmci_runtime_resume(struct device *dev)
.mask = 0xf0ffffff,
.data = &variant_ux500v2,
},
+ {
+ .id = 0x00880180,
+ .mask = 0x00ffffff,
+ .data = &variant_stm32,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 05/14] ARM: dts: stm32: Add SDIO controller for stm32f746
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:15 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
stm32f746 embeds ARM_PL180 sdio IP, adds SDIO controller
nodes to allow MMC support.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d15..cffe1b1 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -429,6 +429,28 @@
status = "disabled";
};
+ sdio2: sdio2@40011c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ clock-names = "apb_pclk";
+ interrupts = <103>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ sdio: sdio@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 05/14] ARM: dts: stm32: Add SDIO controller for stm32f746
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:15 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
stm32f746 embeds ARM_PL180 sdio IP, adds SDIO controller
nodes to allow MMC support.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d15..cffe1b1 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -429,6 +429,28 @@
status = "disabled";
};
+ sdio2: sdio2@40011c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ clock-names = "apb_pclk";
+ interrupts = <103>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ sdio: sdio@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 05/14] ARM: dts: stm32: Add SDIO controller for stm32f746
@ 2018-01-12 12:15 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
stm32f746 embeds ARM_PL180 sdio IP, adds SDIO controller
nodes to allow MMC support.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d15..cffe1b1 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -429,6 +429,28 @@
status = "disabled";
};
+ sdio2: sdio2 at 40011c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ clock-names = "apb_pclk";
+ interrupts = <103>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ sdio: sdio at 40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config at 40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 06/14] ARM: dts: stm32: Add SDIO controller for stm32f429
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
stm32f429 embeds ARM_PL180 sdi IP, adds SDIO controller
node to allow MMC support.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df..ede77e0 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
};
};
+ sdio: sdio@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 06/14] ARM: dts: stm32: Add SDIO controller for stm32f429
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard, Andrea Merello
From: Patrice Chotard <patrice.chotard@st.com>
stm32f429 embeds ARM_PL180 sdi IP, adds SDIO controller
node to allow MMC support.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df..ede77e0 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
};
};
+ sdio: sdio@40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 06/14] ARM: dts: stm32: Add SDIO controller for stm32f429
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
stm32f429 embeds ARM_PL180 sdi IP, adds SDIO controller
node to allow MMC support.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df..ede77e0 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
};
};
+ sdio: sdio at 40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config at 40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 07/14] ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Andrea Merello, Patrice Chotard
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds the pin configuration for SDIO controller on
stm32f4.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86..3520289 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
slew-rate = <3>;
};
};
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 07/14] ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Andrea Merello, Patrice Chotard
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds the pin configuration for SDIO controller on
stm32f4.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86..3520289 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
slew-rate = <3>;
};
};
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 07/14] ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds the pin configuration for SDIO controller on
stm32f4.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86..3520289 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
slew-rate = <3>;
};
};
+
+ sdio_pins: sdio_pins at 0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od at 0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 08/14] ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Andrea Merello, Patrice Chotard
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds SDIO-related DT nodes required by stm32f469 board
There is a hardware issue on these boards, it misses a pullup on
the GPIO line used as card detect to allow correct SD card
detection. To allow correct card detection "broken-cd" property
is used.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 318fb12..ebb97c3 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,13 @@
serial0 = &usart3;
};
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -120,6 +127,18 @@
};
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpiog 2 0>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 08/14] ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Andrea Merello, Patrice Chotard
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds SDIO-related DT nodes required by stm32f469 board
There is a hardware issue on these boards, it misses a pullup on
the GPIO line used as card detect to allow correct SD card
detection. To allow correct card detection "broken-cd" property
is used.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 318fb12..ebb97c3 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,13 @@
serial0 = &usart3;
};
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -120,6 +127,18 @@
};
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpiog 2 0>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 08/14] ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds SDIO-related DT nodes required by stm32f469 board
There is a hardware issue on these boards, it misses a pullup on
the GPIO line used as card detect to allow correct SD card
detection. To allow correct card detection "broken-cd" property
is used.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 318fb12..ebb97c3 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,13 @@
serial0 = &usart3;
};
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -120,6 +127,18 @@
};
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpiog 2 0>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 09/14] ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
This patch adds SDIO related DT nodes for stm32429i-eval board.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 1e3d4c6..6a5c701 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
};
};
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&adc {
@@ -254,6 +261,18 @@
status = "okay";
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <12500000>;
+};
+
&timers1 {
status = "okay";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 09/14] ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
This patch adds SDIO related DT nodes for stm32429i-eval board.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 1e3d4c6..6a5c701 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
};
};
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&adc {
@@ -254,6 +261,18 @@
status = "okay";
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <12500000>;
+};
+
&timers1 {
status = "okay";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 09/14] ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
This patch adds SDIO related DT nodes for stm32429i-eval board.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 1e3d4c6..6a5c701 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
};
};
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&adc {
@@ -254,6 +261,18 @@
status = "okay";
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <12500000>;
+};
+
&timers1 {
status = "okay";
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 10/14] ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
As both STM32F4 and STM32F7 SoCs embeds an AMBA PL180 mmci IP,
we need to enable AMBA support in mach-stm32.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/mach-stm32/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889b..f53a8db 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -13,16 +13,19 @@ config ARCH_STM32
config MACH_STM32F429
bool "STMicrolectronics STM32F429"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F469
bool "STMicrolectronics STM32F469"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F746
bool "STMicrolectronics STM32F746"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32H743
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 10/14] ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
As both STM32F4 and STM32F7 SoCs embeds an AMBA PL180 mmci IP,
we need to enable AMBA support in mach-stm32.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/mach-stm32/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889b..f53a8db 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -13,16 +13,19 @@ config ARCH_STM32
config MACH_STM32F429
bool "STMicrolectronics STM32F429"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F469
bool "STMicrolectronics STM32F469"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F746
bool "STMicrolectronics STM32F746"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32H743
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 10/14] ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
As both STM32F4 and STM32F7 SoCs embeds an AMBA PL180 mmci IP,
we need to enable AMBA support in mach-stm32.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/mach-stm32/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889b..f53a8db 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -13,16 +13,19 @@ config ARCH_STM32
config MACH_STM32F429
bool "STMicrolectronics STM32F429"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F469
bool "STMicrolectronics STM32F469"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F746
bool "STMicrolectronics STM32F746"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32H743
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 11/14] ARM: configs: stm32: Enable MMC_ARMMMCI support
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Enable MMC_ARMMCI support to add SDIO support for
STM32F4 and STM32F7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 21b2bf7..8b64a9e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -56,6 +56,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 11/14] ARM: configs: stm32: Enable MMC_ARMMMCI support
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Enable MMC_ARMMCI support to add SDIO support for
STM32F4 and STM32F7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 21b2bf7..8b64a9e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -56,6 +56,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 11/14] ARM: configs: stm32: Enable MMC_ARMMMCI support
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
Enable MMC_ARMMCI support to add SDIO support for
STM32F4 and STM32F7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 21b2bf7..8b64a9e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -56,6 +56,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 12/14] ARM: configs: stm32: Enable EXT3_FS support
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Enable EXT3_FS support to be able to read rootfs from MMC partition
formatted in EXT2/3/4 .
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 8b64a9e..b736823 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -72,6 +72,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
+CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 12/14] ARM: configs: stm32: Enable EXT3_FS support
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Enable EXT3_FS support to be able to read rootfs from MMC partition
formatted in EXT2/3/4 .
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 8b64a9e..b736823 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -72,6 +72,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
+CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 12/14] ARM: configs: stm32: Enable EXT3_FS support
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
Enable EXT3_FS support to be able to read rootfs from MMC partition
formatted in EXT2/3/4 .
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 8b64a9e..b736823 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -72,6 +72,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
+CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
STM32F769 has 2 SDMMC port, add clock entry for the second one.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/clk/clk-stm32f4.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..8f8a178 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
@@ -315,7 +316,7 @@ struct stm32f4_gate_data {
static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0x0000000000000003ull,
- 0x04f77f033e01c9ffull };
+ 0x04f77f833e01c9ffull };
static const u64 *stm32f4_gate_map;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
STM32F769 has 2 SDMMC port, add clock entry for the second one.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/clk/clk-stm32f4.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..8f8a178 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
@@ -315,7 +316,7 @@ struct stm32f4_gate_data {
static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0x0000000000000003ull,
- 0x04f77f033e01c9ffull };
+ 0x04f77f833e01c9ffull };
static const u64 *stm32f4_gate_map;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
STM32F769 has 2 SDMMC port, add clock entry for the second one.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/clk/clk-stm32f4.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..8f8a178 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
@@ -315,7 +316,7 @@ struct stm32f4_gate_data {
static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0x0000000000000003ull,
- 0x04f77f033e01c9ffull };
+ 0x04f77f833e01c9ffull };
static const u64 *stm32f4_gate_map;
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-12 12:16 ` patrice.chotard
-1 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Move the workaround from stmpe_gpio_irq_unmask() which is executed
in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
It fixes the following issue:
[ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
[ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
[ 1.520000] Hardware name: STM32 (Device Tree Support)
[ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
[ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
[ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
[ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
[ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
[ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
[ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
[ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
[ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
[ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
[ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
[ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
[ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
[ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
[ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
[ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
[ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
[ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
[ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
[ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
[ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
[ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
[ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
[ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
[ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
[ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
[ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
[ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
[ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
[ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
[ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
[ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/gpio/gpio-stmpe.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index e6e5cca..91c8ae2 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
};
int i, j;
+ /*
+ * STMPE1600: to be able to get IRQ from pins,
+ * a read must be done on GPMR register, or a write in
+ * GPSR or GPCR registers
+ */
+ if (stmpe->partnum == STMPE1600) {
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
+ };
+
for (i = 0; i < CACHE_NR_REGS; i++) {
/* STMPE801 and STMPE1600 don't have RE and FE registers */
if ((stmpe->partnum == STMPE801 ||
@@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
- struct stmpe *stmpe = stmpe_gpio->stmpe;
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
-
- /*
- * STMPE1600 workaround: to be able to get IRQ from pins,
- * a read must be done on GPMR register, or a write in
- * GPSR or GPCR registers
- */
- if (stmpe->partnum == STMPE1600)
- stmpe_reg_read(stmpe,
- stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
}
static void stmpe_dbg_show_one(struct seq_file *s,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard @ 2018-01-12 12:16 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Linus Walleij, Rob Herring, Mark Rutland, Alexandre Torgue
Cc: linux-mmc, linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree, Patrice Chotard
From: Patrice Chotard <patrice.chotard@st.com>
Move the workaround from stmpe_gpio_irq_unmask() which is executed
in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
It fixes the following issue:
[ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
[ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
[ 1.520000] Hardware name: STM32 (Device Tree Support)
[ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
[ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
[ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
[ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
[ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
[ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
[ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
[ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
[ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
[ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
[ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
[ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
[ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
[ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
[ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
[ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
[ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
[ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
[ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
[ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
[ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
[ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
[ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
[ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
[ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
[ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
[ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
[ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
[ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
[ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
[ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
[ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/gpio/gpio-stmpe.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index e6e5cca..91c8ae2 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
};
int i, j;
+ /*
+ * STMPE1600: to be able to get IRQ from pins,
+ * a read must be done on GPMR register, or a write in
+ * GPSR or GPCR registers
+ */
+ if (stmpe->partnum == STMPE1600) {
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
+ };
+
for (i = 0; i < CACHE_NR_REGS; i++) {
/* STMPE801 and STMPE1600 don't have RE and FE registers */
if ((stmpe->partnum == STMPE801 ||
@@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
- struct stmpe *stmpe = stmpe_gpio->stmpe;
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
-
- /*
- * STMPE1600 workaround: to be able to get IRQ from pins,
- * a read must be done on GPMR register, or a write in
- * GPSR or GPCR registers
- */
- if (stmpe->partnum == STMPE1600)
- stmpe_reg_read(stmpe,
- stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
}
static void stmpe_dbg_show_one(struct seq_file *s,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
@ 2018-01-12 12:16 ` patrice.chotard
0 siblings, 0 replies; 87+ messages in thread
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
Move the workaround from stmpe_gpio_irq_unmask() which is executed
in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
It fixes the following issue:
[ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
[ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
[ 1.520000] Hardware name: STM32 (Device Tree Support)
[ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
[ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
[ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
[ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
[ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
[ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
[ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
[ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
[ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
[ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
[ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
[ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
[ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
[ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
[ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
[ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
[ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
[ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
[ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
[ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
[ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
[ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
[ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
[ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
[ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
[ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
[ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
[ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
[ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
[ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
[ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
[ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/gpio/gpio-stmpe.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index e6e5cca..91c8ae2 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
};
int i, j;
+ /*
+ * STMPE1600: to be able to get IRQ from pins,
+ * a read must be done on GPMR register, or a write in
+ * GPSR or GPCR registers
+ */
+ if (stmpe->partnum == STMPE1600) {
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
+ };
+
for (i = 0; i < CACHE_NR_REGS; i++) {
/* STMPE801 and STMPE1600 don't have RE and FE registers */
if ((stmpe->partnum == STMPE801 ||
@@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
- struct stmpe *stmpe = stmpe_gpio->stmpe;
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
-
- /*
- * STMPE1600 workaround: to be able to get IRQ from pins,
- * a read must be done on GPMR register, or a write in
- * GPSR or GPCR registers
- */
- if (stmpe->partnum == STMPE1600)
- stmpe_reg_read(stmpe,
- stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
}
static void stmpe_dbg_show_one(struct seq_file *s,
--
1.9.1
^ permalink raw reply related [flat|nested] 87+ messages in thread
* Re: [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
2018-01-12 12:16 ` patrice.chotard
@ 2018-01-12 18:52 ` Stephen Boyd
-1 siblings, 0 replies; 87+ messages in thread
From: Stephen Boyd @ 2018-01-12 18:52 UTC (permalink / raw)
To: patrice.chotard
Cc: Russell King, Ulf Hansson, Michael Turquette, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, linux-arm-kernel, linux-gpio,
devicetree
On 01/12, patrice.chotard@st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> STM32F769 has 2 SDMMC port, add clock entry for the second one.
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
@ 2018-01-12 18:52 ` Stephen Boyd
0 siblings, 0 replies; 87+ messages in thread
From: Stephen Boyd @ 2018-01-12 18:52 UTC (permalink / raw)
To: linux-arm-kernel
On 01/12, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> STM32F769 has 2 SDMMC port, add clock entry for the second one.
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
2018-01-12 12:15 ` patrice.chotard
(?)
(?)
@ 2018-01-15 1:01 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:01 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-clk, Linux ARM,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard-qxv4g6HH51o@public.gmane.org> wrote:
> From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
>
> Two mask registers are used in order to select which events have to
> actually generate an interrupt on each IRQ line.
>
> It seems that in the single-IRQ case it's assumed that the IRQs lines
> are simply OR-ed, while the two mask registers are still present. The
> driver still programs the two mask registers separately.
>
> However the STM32 variant has only one IRQ, and also has only one mask
> register.
>
> This patch prepares for STM32 variant support by making the driver using
> only one mask register.
>
> This patch also optimize the MMCIMASK1 mask usage by caching it into
> host->mask1_reg which avoid to read it into mmci_irq().
>
> Tested only on STM32 variant. RFT for variants other than STM32
>
> Signed-off-by: Andrea Merello <andrea.merello-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
@ 2018-01-15 1:01 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:01 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Two mask registers are used in order to select which events have to
> actually generate an interrupt on each IRQ line.
>
> It seems that in the single-IRQ case it's assumed that the IRQs lines
> are simply OR-ed, while the two mask registers are still present. The
> driver still programs the two mask registers separately.
>
> However the STM32 variant has only one IRQ, and also has only one mask
> register.
>
> This patch prepares for STM32 variant support by making the driver using
> only one mask register.
>
> This patch also optimize the MMCIMASK1 mask usage by caching it into
> host->mask1_reg which avoid to read it into mmci_irq().
>
> Tested only on STM32 variant. RFT for variants other than STM32
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
@ 2018-01-15 1:01 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:01 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Two mask registers are used in order to select which events have to
> actually generate an interrupt on each IRQ line.
>
> It seems that in the single-IRQ case it's assumed that the IRQs lines
> are simply OR-ed, while the two mask registers are still present. The
> driver still programs the two mask registers separately.
>
> However the STM32 variant has only one IRQ, and also has only one mask
> register.
>
> This patch prepares for STM32 variant support by making the driver using
> only one mask register.
>
> This patch also optimize the MMCIMASK1 mask usage by caching it into
> host->mask1_reg which avoid to read it into mmci_irq().
>
> Tested only on STM32 variant. RFT for variants other than STM32
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
@ 2018-01-15 1:01 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:01 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Two mask registers are used in order to select which events have to
> actually generate an interrupt on each IRQ line.
>
> It seems that in the single-IRQ case it's assumed that the IRQs lines
> are simply OR-ed, while the two mask registers are still present. The
> driver still programs the two mask registers separately.
>
> However the STM32 variant has only one IRQ, and also has only one mask
> register.
>
> This patch prepares for STM32 variant support by making the driver using
> only one mask register.
>
> This patch also optimize the MMCIMASK1 mask usage by caching it into
> host->mask1_reg which avoid to read it into mmci_irq().
>
> Tested only on STM32 variant. RFT for variants other than STM32
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
2018-01-12 12:15 ` patrice.chotard
(?)
(?)
@ 2018-01-15 1:03 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:03 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-clk, Linux ARM,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard-qxv4g6HH51o@public.gmane.org> wrote:
> From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Reviewed-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 1:03 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:03 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 1:03 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:03 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 1:03 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:03 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
2018-01-12 12:15 ` patrice.chotard
(?)
(?)
@ 2018-01-15 1:07 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:07 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-clk, Linux ARM,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard-qxv4g6HH51o@public.gmane.org> wrote:
> From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Nice and clean way to use pin control for this.
Hats off!
Reviewed-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 1:07 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:07 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Nice and clean way to use pin control for this.
Hats off!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 1:07 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:07 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Nice and clean way to use pin control for this.
Hats off!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 1:07 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:07 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Nice and clean way to use pin control for this.
Hats off!
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
2018-01-12 12:15 ` patrice.chotard
(?)
@ 2018-01-15 1:13 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:13 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
> an ARM pl810.
PL180 you mean. Ulf can fix while applying.
> This patch adds the STM32 variant so that mmci driver supports it.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
(...)
> +static struct variant_data variant_stm32 = {
> + .fifosize = 32 * 4,
> + .fifohalfsize = 8 * 4,
> + .clkreg = MCI_CLK_ENABLE,
> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
If the asic designed derived this from ux500 I guess it is proper.
> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
> + .datalength_bits = 24,
> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
> + .st_sdio = true,
Did you test SDIO? I think we lack features for that.
> + {
> + .id = 0x00880180,
> + .mask = 0x00ffffff,
> + .data = &variant_stm32,
> + },
Since ux500 was 480180 I wonder what variants 5,6,7 are...
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-15 1:13 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:13 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
> an ARM pl810.
PL180 you mean. Ulf can fix while applying.
> This patch adds the STM32 variant so that mmci driver supports it.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
(...)
> +static struct variant_data variant_stm32 = {
> + .fifosize = 32 * 4,
> + .fifohalfsize = 8 * 4,
> + .clkreg = MCI_CLK_ENABLE,
> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
If the asic designed derived this from ux500 I guess it is proper.
> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
> + .datalength_bits = 24,
> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
> + .st_sdio = true,
Did you test SDIO? I think we lack features for that.
> + {
> + .id = 0x00880180,
> + .mask = 0x00ffffff,
> + .data = &variant_stm32,
> + },
Since ux500 was 480180 I wonder what variants 5,6,7 are...
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-15 1:13 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 1:13 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
> an ARM pl810.
PL180 you mean. Ulf can fix while applying.
> This patch adds the STM32 variant so that mmci driver supports it.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
(...)
> +static struct variant_data variant_stm32 = {
> + .fifosize = 32 * 4,
> + .fifohalfsize = 8 * 4,
> + .clkreg = MCI_CLK_ENABLE,
> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
If the asic designed derived this from ux500 I guess it is proper.
> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
> + .datalength_bits = 24,
> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
> + .st_sdio = true,
Did you test SDIO? I think we lack features for that.
> + {
> + .id = 0x00880180,
> + .mask = 0x00ffffff,
> + .data = &variant_stm32,
> + },
Since ux500 was 480180 I wonder what variants 5,6,7 are...
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
2018-01-12 12:16 ` patrice.chotard
(?)
(?)
@ 2018-01-15 9:57 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 9:57 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-clk, Linux ARM,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Fri, Jan 12, 2018 at 1:16 PM, <patrice.chotard-qxv4g6HH51o@public.gmane.org> wrote:
> From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
>
> Move the workaround from stmpe_gpio_irq_unmask() which is executed
> in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
>
> It fixes the following issue:
>
> [ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
> [ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
> [ 1.520000] Hardware name: STM32 (Device Tree Support)
> [ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
> [ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
> [ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
> [ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
> [ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
> [ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
> [ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
> [ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
> [ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
> [ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
> [ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
> [ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
> [ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
> [ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
> [ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
> [ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
> [ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
> [ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
> [ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
> [ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
> [ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
> [ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
> [ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
> [ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
> [ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
> [ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
> [ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
> [ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
> [ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
> [ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
> [ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
> [ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
> Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Patch applied.
Yours,
Linus Walleij
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
@ 2018-01-15 9:57 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 9:57 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Fri, Jan 12, 2018 at 1:16 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Move the workaround from stmpe_gpio_irq_unmask() which is executed
> in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
>
> It fixes the following issue:
>
> [ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
> [ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
> [ 1.520000] Hardware name: STM32 (Device Tree Support)
> [ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
> [ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
> [ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
> [ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
> [ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
> [ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
> [ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
> [ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
> [ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
> [ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
> [ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
> [ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
> [ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
> [ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
> [ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
> [ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
> [ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
> [ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
> [ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
> [ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
> [ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
> [ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
> [ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
> [ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
> [ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
> [ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
> [ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
> [ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
> [ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
> [ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
> [ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
> [ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
@ 2018-01-15 9:57 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 9:57 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Fri, Jan 12, 2018 at 1:16 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Move the workaround from stmpe_gpio_irq_unmask() which is executed
> in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
>
> It fixes the following issue:
>
> [ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
> [ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
> [ 1.520000] Hardware name: STM32 (Device Tree Support)
> [ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
> [ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
> [ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
> [ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
> [ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
> [ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
> [ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
> [ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
> [ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
> [ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
> [ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
> [ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
> [ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
> [ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
> [ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
> [ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
> [ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
> [ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
> [ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
> [ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
> [ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
> [ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
> [ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
> [ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
> [ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
> [ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
> [ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
> [ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
> [ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
> [ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
> [ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
> [ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
@ 2018-01-15 9:57 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-15 9:57 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 12, 2018 at 1:16 PM, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> Move the workaround from stmpe_gpio_irq_unmask() which is executed
> in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
>
> It fixes the following issue:
>
> [ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
> [ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
> [ 1.520000] Hardware name: STM32 (Device Tree Support)
> [ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
> [ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
> [ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
> [ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
> [ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
> [ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
> [ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
> [ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
> [ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
> [ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
> [ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
> [ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
> [ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
> [ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
> [ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
> [ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
> [ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
> [ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
> [ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
> [ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
> [ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
> [ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
> [ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
> [ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
> [ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
> [ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
> [ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
> [ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
> [ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
> [ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
> [ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
> [ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
>
> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
2018-01-12 12:15 ` patrice.chotard
@ 2018-01-15 12:32 ` Ulf Hansson
-1 siblings, 0 replies; 87+ messages in thread
From: Ulf Hansson @ 2018-01-15 12:32 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> drivers/mmc/host/mmci.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 3125dc0..7e56f85 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -83,6 +83,8 @@
> * @qcom_dml: enables qcom specific dma glue for dma transfers.
> * @reversed_irq_handling: handle data irq before cmd irq.
> * @mmcimask1: true if variant have a MMCIMASK1 register.
> + * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
> + * register.
> */
> struct variant_data {
> unsigned int clkreg;
> @@ -113,6 +115,7 @@ struct variant_data {
> bool qcom_dml;
> bool reversed_irq_handling;
> bool mmcimask1;
> + bool start_err;
To be consistent with how we implement support for similar variant
variations, I would prefer to have this being a u32. Something along
the lines of how the "busy_detect_flag" is being used.
Otherwise this looks good to me.
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 12:32 ` Ulf Hansson
0 siblings, 0 replies; 87+ messages in thread
From: Ulf Hansson @ 2018-01-15 12:32 UTC (permalink / raw)
To: linux-arm-kernel
On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch prepares for supporting the STM32 variant that
> has no such bit in the status register.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> drivers/mmc/host/mmci.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 3125dc0..7e56f85 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -83,6 +83,8 @@
> * @qcom_dml: enables qcom specific dma glue for dma transfers.
> * @reversed_irq_handling: handle data irq before cmd irq.
> * @mmcimask1: true if variant have a MMCIMASK1 register.
> + * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
> + * register.
> */
> struct variant_data {
> unsigned int clkreg;
> @@ -113,6 +115,7 @@ struct variant_data {
> bool qcom_dml;
> bool reversed_irq_handling;
> bool mmcimask1;
> + bool start_err;
To be consistent with how we implement support for similar variant
variations, I would prefer to have this being a u32. Something along
the lines of how the "busy_detect_flag" is being used.
Otherwise this looks good to me.
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
2018-01-12 12:15 ` patrice.chotard
@ 2018-01-15 12:43 ` Ulf Hansson
-1 siblings, 0 replies; 87+ messages in thread
From: Ulf Hansson @ 2018-01-15 12:43 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre Torgue, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
> drivers/mmc/host/mmci.h | 5 +++++
> 2 files changed, 50 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 7e56f85..38e8c20 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -85,6 +85,8 @@
> * @mmcimask1: true if variant have a MMCIMASK1 register.
> * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
> * register.
> + * @opendrain: true if variant have dedicated bit for opendrain pins
> + * configuration.
> */
> struct variant_data {
> unsigned int clkreg;
> @@ -116,6 +118,7 @@ struct variant_data {
> bool reversed_irq_handling;
> bool mmcimask1;
> bool start_err;
> + bool opendrain;
Similar comment as for patch2.
To be consistent with how we implement support for similar variant
variations, I would prefer to have this being a u32. Something along
the lines of how the "busy_detect_flag" is being used.
[...]
> @@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> {
> struct mmci_host *host = mmc_priv(mmc);
> struct variant_data *variant = host->variant;
> + struct pinctrl_state *pins;
> u32 pwr = 0;
> unsigned long flags;
> int ret;
> + bool is_opendrain;
>
> if (host->plat->ios_handler &&
> host->plat->ios_handler(mmc_dev(mmc), ios))
> @@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> ~MCI_ST_DATA2DIREN);
> }
>
> - if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
> - if (host->hw_designer != AMBA_VENDOR_ST)
> - pwr |= MCI_ROD;
> - else {
> - /*
> - * The ST Micro variant use the ROD bit for something
> - * else and only has OD (Open Drain).
> - */
> - pwr |= MCI_OD;
Seems like you should actually split this change into two parts.
One that adds the variant flag for the open drain bit, when then can
clean up this code. Then a patch on top that starts using pinctrl in
case there is no open drain bit set.
Does that sounds reasonable?
> + if (host->variant->opendrain) {
> + if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
> + if (host->hw_designer != AMBA_VENDOR_ST) {
> + pwr |= MCI_ROD;
> + } else {
> + /*
> + * The ST Micro variant use the ROD bit for
> + * something else and only has OD (Open Drain).
> + */
> + pwr |= MCI_OD;
> + }
> }
> + } else {
> + /*
> + * If the variant cannot configure the pads by its own, then we
> + * expect the pinctrl to be able to do that for us
> + */
> + is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
> + pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
How about doing the lookup in ->probe() instead? Then just select the
state here, if supported?
> + MMCI_PINCTRL_STATE_OPENDRAIN :
> + MMCI_PINCTRL_STATE_PUSHPULL);
> + if (IS_ERR(pins))
> + dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
> + else
> + pinctrl_select_state(host->pinctrl, pins);
> }
>
> /*
> @@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
> host = mmc_priv(mmc);
> host->mmc = mmc;
>
> + if (!variant->opendrain) {
> + host->pinctrl = devm_pinctrl_get(&dev->dev);
> + if (IS_ERR(host->pinctrl)) {
> + dev_err(&dev->dev, "failed to get pinctrl");
> + goto host_free;
> + }
> + }
> +
> host->hw_designer = amba_manf(dev);
> host->hw_revision = amba_rev(dev);
> dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
> index 83160a9..de3d0b3 100644
> --- a/drivers/mmc/host/mmci.h
> +++ b/drivers/mmc/host/mmci.h
> @@ -192,6 +192,10 @@
>
> #define NR_SG 128
>
> +/* pinctrl configs */
> +#define MMCI_PINCTRL_STATE_PUSHPULL "default"
Seems like we should be able to cope fine without having to add a
separate define for the PUSHPULL, but rather just select the default
state instead.
> +#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
> +
> struct clk;
> struct variant_data;
> struct dma_chan;
> @@ -227,6 +231,7 @@ struct mmci_host {
> bool vqmmc_enabled;
> struct mmci_platform_data *plat;
> struct variant_data *variant;
> + struct pinctrl *pinctrl;
>
> u8 hw_designer;
> u8 hw_revision:4;
> --
> 1.9.1
>
Kind regards
Uffe
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 12:43 ` Ulf Hansson
0 siblings, 0 replies; 87+ messages in thread
From: Ulf Hansson @ 2018-01-15 12:43 UTC (permalink / raw)
To: linux-arm-kernel
On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
> In this case we can achieve the same result by asking to the pinmux driver
> to configure pins for us.
>
> This patch make the mmci driver able to do this whenever needed.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
> drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
> drivers/mmc/host/mmci.h | 5 +++++
> 2 files changed, 50 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 7e56f85..38e8c20 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -85,6 +85,8 @@
> * @mmcimask1: true if variant have a MMCIMASK1 register.
> * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
> * register.
> + * @opendrain: true if variant have dedicated bit for opendrain pins
> + * configuration.
> */
> struct variant_data {
> unsigned int clkreg;
> @@ -116,6 +118,7 @@ struct variant_data {
> bool reversed_irq_handling;
> bool mmcimask1;
> bool start_err;
> + bool opendrain;
Similar comment as for patch2.
To be consistent with how we implement support for similar variant
variations, I would prefer to have this being a u32. Something along
the lines of how the "busy_detect_flag" is being used.
[...]
> @@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> {
> struct mmci_host *host = mmc_priv(mmc);
> struct variant_data *variant = host->variant;
> + struct pinctrl_state *pins;
> u32 pwr = 0;
> unsigned long flags;
> int ret;
> + bool is_opendrain;
>
> if (host->plat->ios_handler &&
> host->plat->ios_handler(mmc_dev(mmc), ios))
> @@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> ~MCI_ST_DATA2DIREN);
> }
>
> - if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
> - if (host->hw_designer != AMBA_VENDOR_ST)
> - pwr |= MCI_ROD;
> - else {
> - /*
> - * The ST Micro variant use the ROD bit for something
> - * else and only has OD (Open Drain).
> - */
> - pwr |= MCI_OD;
Seems like you should actually split this change into two parts.
One that adds the variant flag for the open drain bit, when then can
clean up this code. Then a patch on top that starts using pinctrl in
case there is no open drain bit set.
Does that sounds reasonable?
> + if (host->variant->opendrain) {
> + if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
> + if (host->hw_designer != AMBA_VENDOR_ST) {
> + pwr |= MCI_ROD;
> + } else {
> + /*
> + * The ST Micro variant use the ROD bit for
> + * something else and only has OD (Open Drain).
> + */
> + pwr |= MCI_OD;
> + }
> }
> + } else {
> + /*
> + * If the variant cannot configure the pads by its own, then we
> + * expect the pinctrl to be able to do that for us
> + */
> + is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
> + pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
How about doing the lookup in ->probe() instead? Then just select the
state here, if supported?
> + MMCI_PINCTRL_STATE_OPENDRAIN :
> + MMCI_PINCTRL_STATE_PUSHPULL);
> + if (IS_ERR(pins))
> + dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
> + else
> + pinctrl_select_state(host->pinctrl, pins);
> }
>
> /*
> @@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
> host = mmc_priv(mmc);
> host->mmc = mmc;
>
> + if (!variant->opendrain) {
> + host->pinctrl = devm_pinctrl_get(&dev->dev);
> + if (IS_ERR(host->pinctrl)) {
> + dev_err(&dev->dev, "failed to get pinctrl");
> + goto host_free;
> + }
> + }
> +
> host->hw_designer = amba_manf(dev);
> host->hw_revision = amba_rev(dev);
> dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
> index 83160a9..de3d0b3 100644
> --- a/drivers/mmc/host/mmci.h
> +++ b/drivers/mmc/host/mmci.h
> @@ -192,6 +192,10 @@
>
> #define NR_SG 128
>
> +/* pinctrl configs */
> +#define MMCI_PINCTRL_STATE_PUSHPULL "default"
Seems like we should be able to cope fine without having to add a
separate define for the PUSHPULL, but rather just select the default
state instead.
> +#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
> +
> struct clk;
> struct variant_data;
> struct dma_chan;
> @@ -227,6 +231,7 @@ struct mmci_host {
> bool vqmmc_enabled;
> struct mmci_platform_data *plat;
> struct variant_data *variant;
> + struct pinctrl *pinctrl;
>
> u8 hw_designer;
> u8 hw_revision:4;
> --
> 1.9.1
>
Kind regards
Uffe
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
2018-01-15 1:13 ` Linus Walleij
(?)
(?)
@ 2018-01-15 17:17 ` Patrice CHOTARD
-1 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:17 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
Hi Linus
On 01/15/2018 02:13 AM, Linus Walleij wrote:
> On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
>
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
>> an ARM pl810.
>
> PL180 you mean. Ulf can fix while applying.
I need to send a v2, i will fix it.
>
>> This patch adds the STM32 variant so that mmci driver supports it.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>
> (...)
>> +static struct variant_data variant_stm32 = {
>> + .fifosize = 32 * 4,
>> + .fifohalfsize = 8 * 4,
>> + .clkreg = MCI_CLK_ENABLE,
>> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
>
> If the asic designed derived this from ux500 I guess it is proper.
>
>> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
>> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
>> + .datalength_bits = 24,
>> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
>> + .st_sdio = true,
>
> Did you test SDIO? I think we lack features for that.
no, the board accept only micro SD card, so only MMC mode can be tested.
>
>> + {
>> + .id = 0x00880180,
>> + .mask = 0x00ffffff,
>> + .data = &variant_stm32,
>> + },
>
> Since ux500 was 480180 I wonder what variants 5,6,7 are...
What is the rule to define the id ? for ST Micro variants we got the
list below :
.id = 0x00180180, u300
.id = 0x10180180, nomadik
.id = 0x00280180, nomadik
.id = 0x00480180, ux500
.id = 0x10480180, ux500v2
.id = 0x00880180, variant_stm32
I simply update the sixth digit for stm32 variant.
Patrice
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-15 17:17 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:17 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
Hi Linus
On 01/15/2018 02:13 AM, Linus Walleij wrote:
> On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
>
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
>> an ARM pl810.
>
> PL180 you mean. Ulf can fix while applying.
I need to send a v2, i will fix it.
>
>> This patch adds the STM32 variant so that mmci driver supports it.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>
> (...)
>> +static struct variant_data variant_stm32 = {
>> + .fifosize = 32 * 4,
>> + .fifohalfsize = 8 * 4,
>> + .clkreg = MCI_CLK_ENABLE,
>> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
>
> If the asic designed derived this from ux500 I guess it is proper.
>
>> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
>> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
>> + .datalength_bits = 24,
>> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
>> + .st_sdio = true,
>
> Did you test SDIO? I think we lack features for that.
no, the board accept only micro SD card, so only MMC mode can be tested.
>
>> + {
>> + .id = 0x00880180,
>> + .mask = 0x00ffffff,
>> + .data = &variant_stm32,
>> + },
>
> Since ux500 was 480180 I wonder what variants 5,6,7 are...
What is the rule to define the id ? for ST Micro variants we got the
list below :
.id = 0x00180180, u300
.id = 0x10180180, nomadik
.id = 0x00280180, nomadik
.id = 0x00480180, ux500
.id = 0x10480180, ux500v2
.id = 0x00880180, variant_stm32
I simply update the sixth digit for stm32 variant.
Patrice
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-15 17:17 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:17 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
SGkgTGludXMNCg0KT24gMDEvMTUvMjAxOCAwMjoxMyBBTSwgTGludXMgV2FsbGVpaiB3cm90ZToN
Cj4gT24gRnJpLCBKYW4gMTIsIDIwMTggYXQgMToxNSBQTSwgIDxwYXRyaWNlLmNob3RhcmRAc3Qu
Y29tPiB3cm90ZToNCj4gDQo+PiBGcm9tOiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFy
ZEBzdC5jb20+DQo+Pg0KPj4gU1RNMzJGNCBhbmQgU1RNMzJGNyBNQ1VzIGhhcyBhIFNESU8gY29u
dHJvbGxlciB0aGF0IGxvb2tzIGxpa2UNCj4+IGFuIEFSTSBwbDgxMC4NCj4gDQo+IFBMMTgwIHlv
dSBtZWFuLiBVbGYgY2FuIGZpeCB3aGlsZSBhcHBseWluZy4NCg0KSSBuZWVkIHRvIHNlbmQgYSB2
MiwgaSB3aWxsIGZpeCBpdC4NCg0KPiANCj4+IFRoaXMgcGF0Y2ggYWRkcyB0aGUgU1RNMzIgdmFy
aWFudCBzbyB0aGF0IG1tY2kgZHJpdmVyIHN1cHBvcnRzIGl0Lg0KPj4NCj4+IFNpZ25lZC1vZmYt
Ynk6IEFuZHJlYSBNZXJlbGxvIDxhbmRyZWEubWVyZWxsb0BnbWFpbC5jb20+DQo+PiBTaWduZWQt
b2ZmLWJ5OiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFyZEBzdC5jb20+DQo+IA0KPiAo
Li4uKQ0KPj4gK3N0YXRpYyBzdHJ1Y3QgdmFyaWFudF9kYXRhIHZhcmlhbnRfc3RtMzIgPSB7DQo+
PiArICAgICAgIC5maWZvc2l6ZSAgICAgICAgICAgICAgID0gMzIgKiA0LA0KPj4gKyAgICAgICAu
Zmlmb2hhbGZzaXplICAgICAgICAgICA9IDggKiA0LA0KPj4gKyAgICAgICAuY2xrcmVnICAgICAg
ICAgICAgICAgICA9IE1DSV9DTEtfRU5BQkxFLA0KPj4gKyAgICAgICAuY2xrcmVnX2VuYWJsZSAg
ICAgICAgICA9IE1DSV9TVF9VWDUwMF9IV0ZDRU4sDQo+IA0KPiBJZiB0aGUgYXNpYyBkZXNpZ25l
ZCBkZXJpdmVkIHRoaXMgZnJvbSB1eDUwMCBJIGd1ZXNzIGl0IGlzIHByb3Blci4NCj4gDQo+PiAr
ICAgICAgIC5jbGtyZWdfOGJpdF9idXNfZW5hYmxlID0gTUNJX1NUXzhCSVRfQlVTLA0KPj4gKyAg
ICAgICAuY2xrcmVnX25lZ19lZGdlX2VuYWJsZSA9IE1DSV9TVF9VWDUwMF9ORUdfRURHRSwNCj4+
ICsgICAgICAgLmRhdGFsZW5ndGhfYml0cyAgICAgICAgPSAyNCwNCj4+ICsgICAgICAgLmRhdGFj
dHJsX21hc2tfc2RpbyAgICAgPSBNQ0lfRFBTTV9TVF9TRElPRU4sDQo+PiArICAgICAgIC5zdF9z
ZGlvICAgICAgICAgICAgICAgID0gdHJ1ZSwNCj4gDQo+IERpZCB5b3UgdGVzdCBTRElPPyBJIHRo
aW5rIHdlIGxhY2sgZmVhdHVyZXMgZm9yIHRoYXQuDQoNCm5vLCB0aGUgYm9hcmQgYWNjZXB0IG9u
bHkgbWljcm8gU0QgY2FyZCwgc28gb25seSBNTUMgbW9kZSBjYW4gYmUgdGVzdGVkLg0KDQo+IA0K
Pj4gKyAgICAgICB7DQo+PiArICAgICAgICAgICAgICAgLmlkICAgICA9IDB4MDA4ODAxODAsDQo+
PiArICAgICAgICAgICAgICAgLm1hc2sgICA9IDB4MDBmZmZmZmYsDQo+PiArICAgICAgICAgICAg
ICAgLmRhdGEgICA9ICZ2YXJpYW50X3N0bTMyLA0KPj4gKyAgICAgICB9LA0KPiANCj4gU2luY2Ug
dXg1MDAgd2FzIDQ4MDE4MCBJIHdvbmRlciB3aGF0IHZhcmlhbnRzIDUsNiw3IGFyZS4uLg0KDQpX
aGF0IGlzIHRoZSBydWxlIHRvIGRlZmluZSB0aGUgaWQgPyBmb3IgU1QgTWljcm8gdmFyaWFudHMg
d2UgZ290IHRoZSANCmxpc3QgYmVsb3cgOg0KCS5pZCAgICAgPSAweDAwMTgwMTgwLCAgdTMwMA0K
CS5pZCAgICAgPSAweDEwMTgwMTgwLCAgbm9tYWRpaw0KCS5pZCAgICAgPSAweDAwMjgwMTgwLCAg
bm9tYWRpaw0KCS5pZCAgICAgPSAweDAwNDgwMTgwLCAgdXg1MDANCgkuaWQgICAgID0gMHgxMDQ4
MDE4MCwgIHV4NTAwdjINCgkuaWQgICAgID0gMHgwMDg4MDE4MCwgIHZhcmlhbnRfc3RtMzINCg0K
SSBzaW1wbHkgdXBkYXRlIHRoZSBzaXh0aCBkaWdpdCBmb3Igc3RtMzIgdmFyaWFudC4NCg0KDQpQ
YXRyaWNlDQoNCj4gDQo+IFJldmlld2VkLWJ5OiBMaW51cyBXYWxsZWlqIDxsaW51cy53YWxsZWlq
QGxpbmFyby5vcmc+DQo+IA0KPiBZb3VycywNCj4gTGludXMgV2FsbGVpag0KPiA=
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-15 17:17 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus
On 01/15/2018 02:13 AM, Linus Walleij wrote:
> On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@st.com> wrote:
>
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
>> an ARM pl810.
>
> PL180 you mean. Ulf can fix while applying.
I need to send a v2, i will fix it.
>
>> This patch adds the STM32 variant so that mmci driver supports it.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>
> (...)
>> +static struct variant_data variant_stm32 = {
>> + .fifosize = 32 * 4,
>> + .fifohalfsize = 8 * 4,
>> + .clkreg = MCI_CLK_ENABLE,
>> + .clkreg_enable = MCI_ST_UX500_HWFCEN,
>
> If the asic designed derived this from ux500 I guess it is proper.
>
>> + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
>> + .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
>> + .datalength_bits = 24,
>> + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
>> + .st_sdio = true,
>
> Did you test SDIO? I think we lack features for that.
no, the board accept only micro SD card, so only MMC mode can be tested.
>
>> + {
>> + .id = 0x00880180,
>> + .mask = 0x00ffffff,
>> + .data = &variant_stm32,
>> + },
>
> Since ux500 was 480180 I wonder what variants 5,6,7 are...
What is the rule to define the id ? for ST Micro variants we got the
list below :
.id = 0x00180180, u300
.id = 0x10180180, nomadik
.id = 0x00280180, nomadik
.id = 0x00480180, ux500
.id = 0x10480180, ux500v2
.id = 0x00880180, variant_stm32
I simply update the sixth digit for stm32 variant.
Patrice
>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
2018-01-15 12:32 ` Ulf Hansson
(?)
(?)
@ 2018-01-15 17:27 ` Patrice CHOTARD
-1 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:27 UTC (permalink / raw)
To: Ulf Hansson
Cc: Mark Rutland, devicetree, linux-clk, Alexandre TORGUE,
Andrea Merello, linux-mmc, Michael Turquette, Stephen Boyd,
Russell King, Linux Kernel Mailing List, linux-gpio, Rob Herring,
Linus Walleij, linux-arm-kernel
Hi Ulf
On 01/15/2018 01:32 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch prepares for supporting the STM32 variant that
>> has no such bit in the status register.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 3125dc0..7e56f85 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -83,6 +83,8 @@
>> * @qcom_dml: enables qcom specific dma glue for dma transfers.
>> * @reversed_irq_handling: handle data irq before cmd irq.
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> + * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> + * register.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -113,6 +115,7 @@ struct variant_data {
>> bool qcom_dml;
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> + bool start_err;
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
OK i will update this in v2
Thanks
Patrice
>
> Otherwise this looks good to me.
>
> [...]
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 17:27 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:27 UTC (permalink / raw)
To: Ulf Hansson
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
Hi Ulf
On 01/15/2018 01:32 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch prepares for supporting the STM32 variant that
>> has no such bit in the status register.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 3125dc0..7e56f85 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -83,6 +83,8 @@
>> * @qcom_dml: enables qcom specific dma glue for dma transfers.
>> * @reversed_irq_handling: handle data irq before cmd irq.
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> + * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> + * register.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -113,6 +115,7 @@ struct variant_data {
>> bool qcom_dml;
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> + bool start_err;
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
OK i will update this in v2
Thanks
Patrice
>
> Otherwise this looks good to me.
>
> [...]
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 17:27 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:27 UTC (permalink / raw)
To: Ulf Hansson
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
SGkgVWxmDQoNCk9uIDAxLzE1LzIwMTggMDE6MzIgUE0sIFVsZiBIYW5zc29uIHdyb3RlOg0KPiBP
biAxMiBKYW51YXJ5IDIwMTggYXQgMTM6MTUsICA8cGF0cmljZS5jaG90YXJkQHN0LmNvbT4gd3Jv
dGU6DQo+PiBGcm9tOiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFyZEBzdC5jb20+DQo+
Pg0KPj4gVGhpcyBwYXRjaCBwcmVwYXJlcyBmb3Igc3VwcG9ydGluZyB0aGUgU1RNMzIgdmFyaWFu
dCB0aGF0DQo+PiBoYXMgbm8gc3VjaCBiaXQgaW4gdGhlIHN0YXR1cyByZWdpc3Rlci4NCj4+DQo+
PiBTaWduZWQtb2ZmLWJ5OiBBbmRyZWEgTWVyZWxsbyA8YW5kcmVhLm1lcmVsbG9AZ21haWwuY29t
Pg0KPj4gU2lnbmVkLW9mZi1ieTogUGF0cmljZSBDaG90YXJkIDxwYXRyaWNlLmNob3RhcmRAc3Qu
Y29tPg0KPj4gLS0tDQo+PiAgIGRyaXZlcnMvbW1jL2hvc3QvbW1jaS5jIHwgMTYgKysrKysrKysr
KysrKystLQ0KPj4gICAxIGZpbGUgY2hhbmdlZCwgMTQgaW5zZXJ0aW9ucygrKSwgMiBkZWxldGlv
bnMoLSkNCj4+DQo+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tbWMvaG9zdC9tbWNpLmMgYi9kcml2
ZXJzL21tYy9ob3N0L21tY2kuYw0KPj4gaW5kZXggMzEyNWRjMC4uN2U1NmY4NSAxMDA2NDQNCj4+
IC0tLSBhL2RyaXZlcnMvbW1jL2hvc3QvbW1jaS5jDQo+PiArKysgYi9kcml2ZXJzL21tYy9ob3N0
L21tY2kuYw0KPj4gQEAgLTgzLDYgKzgzLDggQEANCj4+ICAgICogQHFjb21fZG1sOiBlbmFibGVz
IHFjb20gc3BlY2lmaWMgZG1hIGdsdWUgZm9yIGRtYSB0cmFuc2ZlcnMuDQo+PiAgICAqIEByZXZl
cnNlZF9pcnFfaGFuZGxpbmc6IGhhbmRsZSBkYXRhIGlycSBiZWZvcmUgY21kIGlycS4NCj4+ICAg
ICogQG1tY2ltYXNrMTogdHJ1ZSBpZiB2YXJpYW50IGhhdmUgYSBNTUNJTUFTSzEgcmVnaXN0ZXIu
DQo+PiArICogQHN0YXJ0X2VycjogdHJ1ZSBpcyB0aGUgdmFyaWFudCBoYXMgU1RBUlRCSVRFUlIg
Yml0IGluc2lkZSBNTUNJU1RBVFVTDQo+PiArICogICAgICAgICAgICByZWdpc3Rlci4NCj4+ICAg
ICovDQo+PiAgIHN0cnVjdCB2YXJpYW50X2RhdGEgew0KPj4gICAgICAgICAgdW5zaWduZWQgaW50
ICAgICAgICAgICAgY2xrcmVnOw0KPj4gQEAgLTExMyw2ICsxMTUsNyBAQCBzdHJ1Y3QgdmFyaWFu
dF9kYXRhIHsNCj4+ICAgICAgICAgIGJvb2wgICAgICAgICAgICAgICAgICAgIHFjb21fZG1sOw0K
Pj4gICAgICAgICAgYm9vbCAgICAgICAgICAgICAgICAgICAgcmV2ZXJzZWRfaXJxX2hhbmRsaW5n
Ow0KPj4gICAgICAgICAgYm9vbCAgICAgICAgICAgICAgICAgICAgbW1jaW1hc2sxOw0KPj4gKyAg
ICAgICBib29sICAgICAgICAgICAgICAgICAgICBzdGFydF9lcnI7DQo+IA0KPiBUbyBiZSBjb25z
aXN0ZW50IHdpdGggaG93IHdlIGltcGxlbWVudCBzdXBwb3J0IGZvciBzaW1pbGFyIHZhcmlhbnQN
Cj4gdmFyaWF0aW9ucywgSSB3b3VsZCBwcmVmZXIgdG8gaGF2ZSB0aGlzIGJlaW5nIGEgdTMyLiBT
b21ldGhpbmcgYWxvbmcNCj4gdGhlIGxpbmVzIG9mIGhvdyB0aGUgImJ1c3lfZGV0ZWN0X2ZsYWci
IGlzIGJlaW5nIHVzZWQuDQoNCk9LIGkgd2lsbCB1cGRhdGUgdGhpcyBpbiB2Mg0KDQpUaGFua3MN
Cg0KUGF0cmljZQ0KDQo+IA0KPiBPdGhlcndpc2UgdGhpcyBsb29rcyBnb29kIHRvIG1lLg0KPiAN
Cj4gWy4uLl0NCj4gDQo+IEtpbmQgcmVnYXJkcw0KPiBVZmZlDQo+IA==
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
@ 2018-01-15 17:27 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Ulf
On 01/15/2018 01:32 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch prepares for supporting the STM32 variant that
>> has no such bit in the status register.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 16 ++++++++++++++--
>> 1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 3125dc0..7e56f85 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -83,6 +83,8 @@
>> * @qcom_dml: enables qcom specific dma glue for dma transfers.
>> * @reversed_irq_handling: handle data irq before cmd irq.
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> + * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> + * register.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -113,6 +115,7 @@ struct variant_data {
>> bool qcom_dml;
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> + bool start_err;
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
OK i will update this in v2
Thanks
Patrice
>
> Otherwise this looks good to me.
>
> [...]
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
2018-01-15 12:43 ` Ulf Hansson
(?)
(?)
@ 2018-01-15 17:42 ` Patrice CHOTARD
-1 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:42 UTC (permalink / raw)
To: Ulf Hansson
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
Hi Ulf
On 01/15/2018 01:43 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
>> In this case we can achieve the same result by asking to the pinmux driver
>> to configure pins for us.
>>
>> This patch make the mmci driver able to do this whenever needed.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
>> drivers/mmc/host/mmci.h | 5 +++++
>> 2 files changed, 50 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 7e56f85..38e8c20 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -85,6 +85,8 @@
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> * register.
>> + * @opendrain: true if variant have dedicated bit for opendrain pins
>> + * configuration.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -116,6 +118,7 @@ struct variant_data {
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> bool start_err;
>> + bool opendrain;
>
> Similar comment as for patch2.
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
ok
>
> [...]
>
>> @@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> {
>> struct mmci_host *host = mmc_priv(mmc);
>> struct variant_data *variant = host->variant;
>> + struct pinctrl_state *pins;
>> u32 pwr = 0;
>> unsigned long flags;
>> int ret;
>> + bool is_opendrain;
>>
>> if (host->plat->ios_handler &&
>> host->plat->ios_handler(mmc_dev(mmc), ios))
>> @@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> ~MCI_ST_DATA2DIREN);
>> }
>>
>> - if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> - if (host->hw_designer != AMBA_VENDOR_ST)
>> - pwr |= MCI_ROD;
>> - else {
>> - /*
>> - * The ST Micro variant use the ROD bit for something
>> - * else and only has OD (Open Drain).
>> - */
>> - pwr |= MCI_OD;
>
> Seems like you should actually split this change into two parts.
>
> One that adds the variant flag for the open drain bit, when then can
> clean up this code. Then a patch on top that starts using pinctrl in
> case there is no open drain bit set.
>
> Does that sounds reasonable?
Of course
>
>> + if (host->variant->opendrain) {
>> + if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> + if (host->hw_designer != AMBA_VENDOR_ST) {
>> + pwr |= MCI_ROD;
>> + } else {
>> + /*
>> + * The ST Micro variant use the ROD bit for
>> + * something else and only has OD (Open Drain).
>> + */
>> + pwr |= MCI_OD;
>> + }
>> }
>> + } else {
>> + /*
>> + * If the variant cannot configure the pads by its own, then we
>> + * expect the pinctrl to be able to do that for us
>> + */
>> + is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
>> + pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
>
> How about doing the lookup in ->probe() instead? Then just select the
> state here, if supported?
ok
>
>> + MMCI_PINCTRL_STATE_OPENDRAIN :
>> + MMCI_PINCTRL_STATE_PUSHPULL);
>> + if (IS_ERR(pins))
>> + dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
>> + else
>> + pinctrl_select_state(host->pinctrl, pins);
>> }
>>
>> /*
>> @@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
>> host = mmc_priv(mmc);
>> host->mmc = mmc;
>>
>> + if (!variant->opendrain) {
>> + host->pinctrl = devm_pinctrl_get(&dev->dev);
>> + if (IS_ERR(host->pinctrl)) {
>> + dev_err(&dev->dev, "failed to get pinctrl");
>> + goto host_free;
>> + }
>> + }
>> +
>> host->hw_designer = amba_manf(dev);
>> host->hw_revision = amba_rev(dev);
>> dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
>> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
>> index 83160a9..de3d0b3 100644
>> --- a/drivers/mmc/host/mmci.h
>> +++ b/drivers/mmc/host/mmci.h
>> @@ -192,6 +192,10 @@
>>
>> #define NR_SG 128
>>
>> +/* pinctrl configs */
>> +#define MMCI_PINCTRL_STATE_PUSHPULL "default"
>
> Seems like we should be able to cope fine without having to add a
> separate define for the PUSHPULL, but rather just select the default
> state instead.
yes agree
Thanks
Patrice
>
>> +#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
>> +
>> struct clk;
>> struct variant_data;
>> struct dma_chan;
>> @@ -227,6 +231,7 @@ struct mmci_host {
>> bool vqmmc_enabled;
>> struct mmci_platform_data *plat;
>> struct variant_data *variant;
>> + struct pinctrl *pinctrl;
>>
>> u8 hw_designer;
>> u8 hw_revision:4;
>> --
>> 1.9.1
>>
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 17:42 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:42 UTC (permalink / raw)
To: Ulf Hansson
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
Hi Ulf
On 01/15/2018 01:43 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
>> In this case we can achieve the same result by asking to the pinmux driver
>> to configure pins for us.
>>
>> This patch make the mmci driver able to do this whenever needed.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
>> drivers/mmc/host/mmci.h | 5 +++++
>> 2 files changed, 50 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 7e56f85..38e8c20 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -85,6 +85,8 @@
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> * register.
>> + * @opendrain: true if variant have dedicated bit for opendrain pins
>> + * configuration.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -116,6 +118,7 @@ struct variant_data {
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> bool start_err;
>> + bool opendrain;
>
> Similar comment as for patch2.
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
ok
>
> [...]
>
>> @@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> {
>> struct mmci_host *host = mmc_priv(mmc);
>> struct variant_data *variant = host->variant;
>> + struct pinctrl_state *pins;
>> u32 pwr = 0;
>> unsigned long flags;
>> int ret;
>> + bool is_opendrain;
>>
>> if (host->plat->ios_handler &&
>> host->plat->ios_handler(mmc_dev(mmc), ios))
>> @@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> ~MCI_ST_DATA2DIREN);
>> }
>>
>> - if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> - if (host->hw_designer != AMBA_VENDOR_ST)
>> - pwr |= MCI_ROD;
>> - else {
>> - /*
>> - * The ST Micro variant use the ROD bit for something
>> - * else and only has OD (Open Drain).
>> - */
>> - pwr |= MCI_OD;
>
> Seems like you should actually split this change into two parts.
>
> One that adds the variant flag for the open drain bit, when then can
> clean up this code. Then a patch on top that starts using pinctrl in
> case there is no open drain bit set.
>
> Does that sounds reasonable?
Of course
>
>> + if (host->variant->opendrain) {
>> + if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> + if (host->hw_designer != AMBA_VENDOR_ST) {
>> + pwr |= MCI_ROD;
>> + } else {
>> + /*
>> + * The ST Micro variant use the ROD bit for
>> + * something else and only has OD (Open Drain).
>> + */
>> + pwr |= MCI_OD;
>> + }
>> }
>> + } else {
>> + /*
>> + * If the variant cannot configure the pads by its own, then we
>> + * expect the pinctrl to be able to do that for us
>> + */
>> + is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
>> + pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
>
> How about doing the lookup in ->probe() instead? Then just select the
> state here, if supported?
ok
>
>> + MMCI_PINCTRL_STATE_OPENDRAIN :
>> + MMCI_PINCTRL_STATE_PUSHPULL);
>> + if (IS_ERR(pins))
>> + dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
>> + else
>> + pinctrl_select_state(host->pinctrl, pins);
>> }
>>
>> /*
>> @@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
>> host = mmc_priv(mmc);
>> host->mmc = mmc;
>>
>> + if (!variant->opendrain) {
>> + host->pinctrl = devm_pinctrl_get(&dev->dev);
>> + if (IS_ERR(host->pinctrl)) {
>> + dev_err(&dev->dev, "failed to get pinctrl");
>> + goto host_free;
>> + }
>> + }
>> +
>> host->hw_designer = amba_manf(dev);
>> host->hw_revision = amba_rev(dev);
>> dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
>> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
>> index 83160a9..de3d0b3 100644
>> --- a/drivers/mmc/host/mmci.h
>> +++ b/drivers/mmc/host/mmci.h
>> @@ -192,6 +192,10 @@
>>
>> #define NR_SG 128
>>
>> +/* pinctrl configs */
>> +#define MMCI_PINCTRL_STATE_PUSHPULL "default"
>
> Seems like we should be able to cope fine without having to add a
> separate define for the PUSHPULL, but rather just select the default
> state instead.
yes agree
Thanks
Patrice
>
>> +#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
>> +
>> struct clk;
>> struct variant_data;
>> struct dma_chan;
>> @@ -227,6 +231,7 @@ struct mmci_host {
>> bool vqmmc_enabled;
>> struct mmci_platform_data *plat;
>> struct variant_data *variant;
>> + struct pinctrl *pinctrl;
>>
>> u8 hw_designer;
>> u8 hw_revision:4;
>> --
>> 1.9.1
>>
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 17:42 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:42 UTC (permalink / raw)
To: Ulf Hansson
Cc: Russell King, Michael Turquette, Stephen Boyd, Linus Walleij,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
Linux Kernel Mailing List, linux-clk, linux-arm-kernel,
linux-gpio, devicetree, Andrea Merello
SGkgVWxmDQoNCk9uIDAxLzE1LzIwMTggMDE6NDMgUE0sIFVsZiBIYW5zc29uIHdyb3RlOg0KPiBP
biAxMiBKYW51YXJ5IDIwMTggYXQgMTM6MTUsICA8cGF0cmljZS5jaG90YXJkQHN0LmNvbT4gd3Jv
dGU6DQo+PiBGcm9tOiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFyZEBzdC5jb20+DQo+
Pg0KPj4gVGhlIFNUTTMyIHZhcmlhbnQgaGFzbid0IHRoZSBjb250cm9sIGJpdCB0byBzd2l0Y2gg
cGFkcyBpbiBvcGVuZHJhaW4gbW9kZS4NCj4+IEluIHRoaXMgY2FzZSB3ZSBjYW4gYWNoaWV2ZSB0
aGUgc2FtZSByZXN1bHQgYnkgYXNraW5nIHRvIHRoZSBwaW5tdXggZHJpdmVyDQo+PiB0byBjb25m
aWd1cmUgcGlucyBmb3IgdXMuDQo+Pg0KPj4gVGhpcyBwYXRjaCBtYWtlIHRoZSBtbWNpIGRyaXZl
ciBhYmxlIHRvIGRvIHRoaXMgd2hlbmV2ZXIgbmVlZGVkLg0KPj4NCj4+IFNpZ25lZC1vZmYtYnk6
IEFuZHJlYSBNZXJlbGxvIDxhbmRyZWEubWVyZWxsb0BnbWFpbC5jb20+DQo+PiBTaWduZWQtb2Zm
LWJ5OiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFyZEBzdC5jb20+DQo+PiAtLS0NCj4+
ICAgZHJpdmVycy9tbWMvaG9zdC9tbWNpLmMgfCA1NCArKysrKysrKysrKysrKysrKysrKysrKysr
KysrKysrKysrKysrKysrLS0tLS0tLS0tDQo+PiAgIGRyaXZlcnMvbW1jL2hvc3QvbW1jaS5oIHwg
IDUgKysrKysNCj4+ICAgMiBmaWxlcyBjaGFuZ2VkLCA1MCBpbnNlcnRpb25zKCspLCA5IGRlbGV0
aW9ucygtKQ0KPj4NCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL21tYy9ob3N0L21tY2kuYyBiL2Ry
aXZlcnMvbW1jL2hvc3QvbW1jaS5jDQo+PiBpbmRleCA3ZTU2Zjg1Li4zOGU4YzIwIDEwMDY0NA0K
Pj4gLS0tIGEvZHJpdmVycy9tbWMvaG9zdC9tbWNpLmMNCj4+ICsrKyBiL2RyaXZlcnMvbW1jL2hv
c3QvbW1jaS5jDQo+PiBAQCAtODUsNiArODUsOCBAQA0KPj4gICAgKiBAbW1jaW1hc2sxOiB0cnVl
IGlmIHZhcmlhbnQgaGF2ZSBhIE1NQ0lNQVNLMSByZWdpc3Rlci4NCj4+ICAgICogQHN0YXJ0X2Vy
cjogdHJ1ZSBpcyB0aGUgdmFyaWFudCBoYXMgU1RBUlRCSVRFUlIgYml0IGluc2lkZSBNTUNJU1RB
VFVTDQo+PiAgICAqICAgICAgICAgICAgcmVnaXN0ZXIuDQo+PiArICogQG9wZW5kcmFpbjogdHJ1
ZSBpZiB2YXJpYW50IGhhdmUgZGVkaWNhdGVkIGJpdCBmb3Igb3BlbmRyYWluIHBpbnMNCj4+ICsg
KiAgICAgICAgICAgIGNvbmZpZ3VyYXRpb24uDQo+PiAgICAqLw0KPj4gICBzdHJ1Y3QgdmFyaWFu
dF9kYXRhIHsNCj4+ICAgICAgICAgIHVuc2lnbmVkIGludCAgICAgICAgICAgIGNsa3JlZzsNCj4+
IEBAIC0xMTYsNiArMTE4LDcgQEAgc3RydWN0IHZhcmlhbnRfZGF0YSB7DQo+PiAgICAgICAgICBi
b29sICAgICAgICAgICAgICAgICAgICByZXZlcnNlZF9pcnFfaGFuZGxpbmc7DQo+PiAgICAgICAg
ICBib29sICAgICAgICAgICAgICAgICAgICBtbWNpbWFzazE7DQo+PiAgICAgICAgICBib29sICAg
ICAgICAgICAgICAgICAgICBzdGFydF9lcnI7DQo+PiArICAgICAgIGJvb2wgICAgICAgICAgICAg
ICAgICAgIG9wZW5kcmFpbjsNCj4gDQo+IFNpbWlsYXIgY29tbWVudCBhcyBmb3IgcGF0Y2gyLg0K
PiANCj4gVG8gYmUgY29uc2lzdGVudCB3aXRoIGhvdyB3ZSBpbXBsZW1lbnQgc3VwcG9ydCBmb3Ig
c2ltaWxhciB2YXJpYW50DQo+IHZhcmlhdGlvbnMsIEkgd291bGQgcHJlZmVyIHRvIGhhdmUgdGhp
cyBiZWluZyBhIHUzMi4gU29tZXRoaW5nIGFsb25nDQo+IHRoZSBsaW5lcyBvZiBob3cgdGhlICJi
dXN5X2RldGVjdF9mbGFnIiBpcyBiZWluZyB1c2VkLg0KDQpvaw0KDQo+IA0KPiBbLi4uXQ0KPiAN
Cj4+IEBAIC0xMzk0LDkgKzE0MDUsMTEgQEAgc3RhdGljIHZvaWQgbW1jaV9zZXRfaW9zKHN0cnVj
dCBtbWNfaG9zdCAqbW1jLCBzdHJ1Y3QgbW1jX2lvcyAqaW9zKQ0KPj4gICB7DQo+PiAgICAgICAg
ICBzdHJ1Y3QgbW1jaV9ob3N0ICpob3N0ID0gbW1jX3ByaXYobW1jKTsNCj4+ICAgICAgICAgIHN0
cnVjdCB2YXJpYW50X2RhdGEgKnZhcmlhbnQgPSBob3N0LT52YXJpYW50Ow0KPj4gKyAgICAgICBz
dHJ1Y3QgcGluY3RybF9zdGF0ZSAqcGluczsNCj4+ICAgICAgICAgIHUzMiBwd3IgPSAwOw0KPj4g
ICAgICAgICAgdW5zaWduZWQgbG9uZyBmbGFnczsNCj4+ICAgICAgICAgIGludCByZXQ7DQo+PiAr
ICAgICAgIGJvb2wgaXNfb3BlbmRyYWluOw0KPj4NCj4+ICAgICAgICAgIGlmIChob3N0LT5wbGF0
LT5pb3NfaGFuZGxlciAmJg0KPj4gICAgICAgICAgICAgICAgICBob3N0LT5wbGF0LT5pb3NfaGFu
ZGxlcihtbWNfZGV2KG1tYyksIGlvcykpDQo+PiBAQCAtMTQ1NSwxNiArMTQ2OCwzMSBAQCBzdGF0
aWMgdm9pZCBtbWNpX3NldF9pb3Moc3RydWN0IG1tY19ob3N0ICptbWMsIHN0cnVjdCBtbWNfaW9z
ICppb3MpDQo+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB+TUNJX1NUX0RBVEEy
RElSRU4pOw0KPj4gICAgICAgICAgfQ0KPj4NCj4+IC0gICAgICAgaWYgKGlvcy0+YnVzX21vZGUg
PT0gTU1DX0JVU01PREVfT1BFTkRSQUlOKSB7DQo+PiAtICAgICAgICAgICAgICAgaWYgKGhvc3Qt
Pmh3X2Rlc2lnbmVyICE9IEFNQkFfVkVORE9SX1NUKQ0KPj4gLSAgICAgICAgICAgICAgICAgICAg
ICAgcHdyIHw9IE1DSV9ST0Q7DQo+PiAtICAgICAgICAgICAgICAgZWxzZSB7DQo+PiAtICAgICAg
ICAgICAgICAgICAgICAgICAvKg0KPj4gLSAgICAgICAgICAgICAgICAgICAgICAgICogVGhlIFNU
IE1pY3JvIHZhcmlhbnQgdXNlIHRoZSBST0QgYml0IGZvciBzb21ldGhpbmcNCj4+IC0gICAgICAg
ICAgICAgICAgICAgICAgICAqIGVsc2UgYW5kIG9ubHkgaGFzIE9EIChPcGVuIERyYWluKS4NCj4+
IC0gICAgICAgICAgICAgICAgICAgICAgICAqLw0KPj4gLSAgICAgICAgICAgICAgICAgICAgICAg
cHdyIHw9IE1DSV9PRDsNCj4gDQo+IFNlZW1zIGxpa2UgeW91IHNob3VsZCBhY3R1YWxseSBzcGxp
dCB0aGlzIGNoYW5nZSBpbnRvIHR3byBwYXJ0cy4NCj4gDQo+IE9uZSB0aGF0IGFkZHMgdGhlIHZh
cmlhbnQgZmxhZyBmb3IgdGhlIG9wZW4gZHJhaW4gYml0LCB3aGVuIHRoZW4gY2FuDQo+IGNsZWFu
IHVwIHRoaXMgY29kZS4gVGhlbiBhIHBhdGNoIG9uIHRvcCB0aGF0IHN0YXJ0cyB1c2luZyBwaW5j
dHJsIGluDQo+IGNhc2UgdGhlcmUgaXMgbm8gb3BlbiBkcmFpbiBiaXQgc2V0Lg0KPiANCj4gRG9l
cyB0aGF0IHNvdW5kcyByZWFzb25hYmxlPw0KDQpPZiBjb3Vyc2UNCg0KPiANCj4+ICsgICAgICAg
aWYgKGhvc3QtPnZhcmlhbnQtPm9wZW5kcmFpbikgew0KPj4gKyAgICAgICAgICAgICAgIGlmIChp
b3MtPmJ1c19tb2RlID09IE1NQ19CVVNNT0RFX09QRU5EUkFJTikgew0KPj4gKyAgICAgICAgICAg
ICAgICAgICAgICAgaWYgKGhvc3QtPmh3X2Rlc2lnbmVyICE9IEFNQkFfVkVORE9SX1NUKSB7DQo+
PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHB3ciB8PSBNQ0lfUk9EOw0KPj4gKyAg
ICAgICAgICAgICAgICAgICAgICAgfSBlbHNlIHsNCj4+ICsgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgLyoNCj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICogVGhlIFNU
IE1pY3JvIHZhcmlhbnQgdXNlIHRoZSBST0QgYml0IGZvcg0KPj4gKyAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgKiBzb21ldGhpbmcgZWxzZSBhbmQgb25seSBoYXMgT0QgKE9wZW4gRHJh
aW4pLg0KPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgKi8NCj4+ICsgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgcHdyIHw9IE1DSV9PRDsNCj4+ICsgICAgICAgICAgICAg
ICAgICAgICAgIH0NCj4+ICAgICAgICAgICAgICAgICAgfQ0KPj4gKyAgICAgICB9IGVsc2Ugew0K
Pj4gKyAgICAgICAgICAgICAgIC8qDQo+PiArICAgICAgICAgICAgICAgICogSWYgdGhlIHZhcmlh
bnQgY2Fubm90IGNvbmZpZ3VyZSB0aGUgcGFkcyBieSBpdHMgb3duLCB0aGVuIHdlDQo+PiArICAg
ICAgICAgICAgICAgICogZXhwZWN0IHRoZSBwaW5jdHJsIHRvIGJlIGFibGUgdG8gZG8gdGhhdCBm
b3IgdXMNCj4+ICsgICAgICAgICAgICAgICAgKi8NCj4+ICsgICAgICAgICAgICAgICBpc19vcGVu
ZHJhaW4gPSAoaW9zLT5idXNfbW9kZSA9PSBNTUNfQlVTTU9ERV9PUEVORFJBSU4pOw0KPj4gKyAg
ICAgICAgICAgICAgIHBpbnMgPSBwaW5jdHJsX2xvb2t1cF9zdGF0ZShob3N0LT5waW5jdHJsLCBp
c19vcGVuZHJhaW4gPw0KPiANCj4gSG93IGFib3V0IGRvaW5nIHRoZSBsb29rdXAgaW4gLT5wcm9i
ZSgpIGluc3RlYWQ/IFRoZW4ganVzdCBzZWxlY3QgdGhlDQo+IHN0YXRlIGhlcmUsIGlmIHN1cHBv
cnRlZD8NCg0Kb2sNCg0KPiANCj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICBNTUNJX1BJTkNUUkxfU1RBVEVfT1BFTkRSQUlOIDoNCj4+ICsgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICBNTUNJX1BJTkNUUkxfU1RBVEVfUFVTSFBVTEwpOw0KPj4g
KyAgICAgICAgICAgICAgIGlmIChJU19FUlIocGlucykpDQo+PiArICAgICAgICAgICAgICAgICAg
ICAgICBkZXZfd2FybihtbWNfZGV2KG1tYyksICJDYW5ub3Qgc2VsZWN0IHBpbiBkcml2ZSB0eXBl
IHZpYSBwaW5jdHJsXG4iKTsNCj4+ICsgICAgICAgICAgICAgICBlbHNlDQo+PiArICAgICAgICAg
ICAgICAgICAgICAgICBwaW5jdHJsX3NlbGVjdF9zdGF0ZShob3N0LT5waW5jdHJsLCBwaW5zKTsN
Cj4+ICAgICAgICAgIH0NCj4+DQo+PiAgICAgICAgICAvKg0KPj4gQEAgLTE2MDksNiArMTYzNywx
NCBAQCBzdGF0aWMgaW50IG1tY2lfcHJvYmUoc3RydWN0IGFtYmFfZGV2aWNlICpkZXYsDQo+PiAg
ICAgICAgICBob3N0ID0gbW1jX3ByaXYobW1jKTsNCj4+ICAgICAgICAgIGhvc3QtPm1tYyA9IG1t
YzsNCj4+DQo+PiArICAgICAgIGlmICghdmFyaWFudC0+b3BlbmRyYWluKSB7DQo+PiArICAgICAg
ICAgICAgICAgaG9zdC0+cGluY3RybCA9IGRldm1fcGluY3RybF9nZXQoJmRldi0+ZGV2KTsNCj4+
ICsgICAgICAgICAgICAgICBpZiAoSVNfRVJSKGhvc3QtPnBpbmN0cmwpKSB7DQo+PiArICAgICAg
ICAgICAgICAgICAgICAgICBkZXZfZXJyKCZkZXYtPmRldiwgImZhaWxlZCB0byBnZXQgcGluY3Ry
bCIpOw0KPj4gKyAgICAgICAgICAgICAgICAgICAgICAgZ290byBob3N0X2ZyZWU7DQo+PiArICAg
ICAgICAgICAgICAgfQ0KPj4gKyAgICAgICB9DQo+PiArDQo+PiAgICAgICAgICBob3N0LT5od19k
ZXNpZ25lciA9IGFtYmFfbWFuZihkZXYpOw0KPj4gICAgICAgICAgaG9zdC0+aHdfcmV2aXNpb24g
PSBhbWJhX3JldihkZXYpOw0KPj4gICAgICAgICAgZGV2X2RiZyhtbWNfZGV2KG1tYyksICJkZXNp
Z25lciBJRCA9IDB4JTAyeFxuIiwgaG9zdC0+aHdfZGVzaWduZXIpOw0KPj4gZGlmZiAtLWdpdCBh
L2RyaXZlcnMvbW1jL2hvc3QvbW1jaS5oIGIvZHJpdmVycy9tbWMvaG9zdC9tbWNpLmgNCj4+IGlu
ZGV4IDgzMTYwYTkuLmRlM2QwYjMgMTAwNjQ0DQo+PiAtLS0gYS9kcml2ZXJzL21tYy9ob3N0L21t
Y2kuaA0KPj4gKysrIGIvZHJpdmVycy9tbWMvaG9zdC9tbWNpLmgNCj4+IEBAIC0xOTIsNiArMTky
LDEwIEBADQo+Pg0KPj4gICAjZGVmaW5lIE5SX1NHICAgICAgICAgIDEyOA0KPj4NCj4+ICsvKiBw
aW5jdHJsIGNvbmZpZ3MgKi8NCj4+ICsjZGVmaW5lIE1NQ0lfUElOQ1RSTF9TVEFURV9QVVNIUFVM
TCAiZGVmYXVsdCINCj4gDQo+IFNlZW1zIGxpa2Ugd2Ugc2hvdWxkIGJlIGFibGUgdG8gY29wZSBm
aW5lIHdpdGhvdXQgaGF2aW5nIHRvIGFkZCBhDQo+IHNlcGFyYXRlIGRlZmluZSBmb3IgdGhlIFBV
U0hQVUxMLCBidXQgcmF0aGVyIGp1c3Qgc2VsZWN0IHRoZSBkZWZhdWx0DQo+IHN0YXRlIGluc3Rl
YWQuDQoNCnllcyBhZ3JlZQ0KDQpUaGFua3MNCg0KUGF0cmljZQ0KDQo+IA0KPj4gKyNkZWZpbmUg
TU1DSV9QSU5DVFJMX1NUQVRFX09QRU5EUkFJTiAib3BlbmRyYWluIg0KPj4gKw0KPj4gICBzdHJ1
Y3QgY2xrOw0KPj4gICBzdHJ1Y3QgdmFyaWFudF9kYXRhOw0KPj4gICBzdHJ1Y3QgZG1hX2NoYW47
DQo+PiBAQCAtMjI3LDYgKzIzMSw3IEBAIHN0cnVjdCBtbWNpX2hvc3Qgew0KPj4gICAgICAgICAg
Ym9vbCAgICAgICAgICAgICAgICAgICAgdnFtbWNfZW5hYmxlZDsNCj4+ICAgICAgICAgIHN0cnVj
dCBtbWNpX3BsYXRmb3JtX2RhdGEgKnBsYXQ7DQo+PiAgICAgICAgICBzdHJ1Y3QgdmFyaWFudF9k
YXRhICAgICAqdmFyaWFudDsNCj4+ICsgICAgICAgc3RydWN0IHBpbmN0cmwgICAgICAgICAgKnBp
bmN0cmw7DQo+Pg0KPj4gICAgICAgICAgdTggICAgICAgICAgICAgICAgICAgICAgaHdfZGVzaWdu
ZXI7DQo+PiAgICAgICAgICB1OCAgICAgICAgICAgICAgICAgICAgICBod19yZXZpc2lvbjo0Ow0K
Pj4gLS0NCj4+IDEuOS4xDQo+Pg0KPiANCj4gS2luZCByZWdhcmRzDQo+IFVmZmUNCj4g
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
@ 2018-01-15 17:42 ` Patrice CHOTARD
0 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-01-15 17:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Ulf
On 01/15/2018 01:43 PM, Ulf Hansson wrote:
> On 12 January 2018 at 13:15, <patrice.chotard@st.com> wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> The STM32 variant hasn't the control bit to switch pads in opendrain mode.
>> In this case we can achieve the same result by asking to the pinmux driver
>> to configure pins for us.
>>
>> This patch make the mmci driver able to do this whenever needed.
>>
>> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>> ---
>> drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
>> drivers/mmc/host/mmci.h | 5 +++++
>> 2 files changed, 50 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 7e56f85..38e8c20 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -85,6 +85,8 @@
>> * @mmcimask1: true if variant have a MMCIMASK1 register.
>> * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
>> * register.
>> + * @opendrain: true if variant have dedicated bit for opendrain pins
>> + * configuration.
>> */
>> struct variant_data {
>> unsigned int clkreg;
>> @@ -116,6 +118,7 @@ struct variant_data {
>> bool reversed_irq_handling;
>> bool mmcimask1;
>> bool start_err;
>> + bool opendrain;
>
> Similar comment as for patch2.
>
> To be consistent with how we implement support for similar variant
> variations, I would prefer to have this being a u32. Something along
> the lines of how the "busy_detect_flag" is being used.
ok
>
> [...]
>
>> @@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> {
>> struct mmci_host *host = mmc_priv(mmc);
>> struct variant_data *variant = host->variant;
>> + struct pinctrl_state *pins;
>> u32 pwr = 0;
>> unsigned long flags;
>> int ret;
>> + bool is_opendrain;
>>
>> if (host->plat->ios_handler &&
>> host->plat->ios_handler(mmc_dev(mmc), ios))
>> @@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>> ~MCI_ST_DATA2DIREN);
>> }
>>
>> - if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> - if (host->hw_designer != AMBA_VENDOR_ST)
>> - pwr |= MCI_ROD;
>> - else {
>> - /*
>> - * The ST Micro variant use the ROD bit for something
>> - * else and only has OD (Open Drain).
>> - */
>> - pwr |= MCI_OD;
>
> Seems like you should actually split this change into two parts.
>
> One that adds the variant flag for the open drain bit, when then can
> clean up this code. Then a patch on top that starts using pinctrl in
> case there is no open drain bit set.
>
> Does that sounds reasonable?
Of course
>
>> + if (host->variant->opendrain) {
>> + if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
>> + if (host->hw_designer != AMBA_VENDOR_ST) {
>> + pwr |= MCI_ROD;
>> + } else {
>> + /*
>> + * The ST Micro variant use the ROD bit for
>> + * something else and only has OD (Open Drain).
>> + */
>> + pwr |= MCI_OD;
>> + }
>> }
>> + } else {
>> + /*
>> + * If the variant cannot configure the pads by its own, then we
>> + * expect the pinctrl to be able to do that for us
>> + */
>> + is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
>> + pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
>
> How about doing the lookup in ->probe() instead? Then just select the
> state here, if supported?
ok
>
>> + MMCI_PINCTRL_STATE_OPENDRAIN :
>> + MMCI_PINCTRL_STATE_PUSHPULL);
>> + if (IS_ERR(pins))
>> + dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
>> + else
>> + pinctrl_select_state(host->pinctrl, pins);
>> }
>>
>> /*
>> @@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
>> host = mmc_priv(mmc);
>> host->mmc = mmc;
>>
>> + if (!variant->opendrain) {
>> + host->pinctrl = devm_pinctrl_get(&dev->dev);
>> + if (IS_ERR(host->pinctrl)) {
>> + dev_err(&dev->dev, "failed to get pinctrl");
>> + goto host_free;
>> + }
>> + }
>> +
>> host->hw_designer = amba_manf(dev);
>> host->hw_revision = amba_rev(dev);
>> dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
>> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
>> index 83160a9..de3d0b3 100644
>> --- a/drivers/mmc/host/mmci.h
>> +++ b/drivers/mmc/host/mmci.h
>> @@ -192,6 +192,10 @@
>>
>> #define NR_SG 128
>>
>> +/* pinctrl configs */
>> +#define MMCI_PINCTRL_STATE_PUSHPULL "default"
>
> Seems like we should be able to cope fine without having to add a
> separate define for the PUSHPULL, but rather just select the default
> state instead.
yes agree
Thanks
Patrice
>
>> +#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
>> +
>> struct clk;
>> struct variant_data;
>> struct dma_chan;
>> @@ -227,6 +231,7 @@ struct mmci_host {
>> bool vqmmc_enabled;
>> struct mmci_platform_data *plat;
>> struct variant_data *variant;
>> + struct pinctrl *pinctrl;
>>
>> u8 hw_designer;
>> u8 hw_revision:4;
>> --
>> 1.9.1
>>
>
> Kind regards
> Uffe
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
2018-01-15 17:17 ` Patrice CHOTARD
(?)
(?)
@ 2018-01-16 7:38 ` Linus Walleij
-1 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-16 7:38 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-clk, Linux ARM,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Mon, Jan 15, 2018 at 6:17 PM, Patrice CHOTARD <patrice.chotard-qxv4g6HH51o@public.gmane.org> wrote:
>>> + {
>>> + .id = 0x00880180,
>>> + .mask = 0x00ffffff,
>>> + .data = &variant_stm32,
>>> + },
>>
>> Since ux500 was 480180 I wonder what variants 5,6,7 are...
>
> What is the rule to define the id ?
These four bits mean "revision".
The number comes from hardware, so the ST ASIC department
has some person who is responsible for revising the VHDL or
Verilog code that this hardware is compiled from, and that person
is bumping the version.
Theoretically it is a "company function" or something bureaucratic
like that updating the hardware so I guess it could be several
people following procedure who have updated this number in the
hardware over the years.
But I bet it is a single person in Grenoble who has been doing
the MMC/SD block since it appeared.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-16 7:38 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-16 7:38 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Mon, Jan 15, 2018 at 6:17 PM, Patrice CHOTARD <patrice.chotard@st.com> wrote:
>>> + {
>>> + .id = 0x00880180,
>>> + .mask = 0x00ffffff,
>>> + .data = &variant_stm32,
>>> + },
>>
>> Since ux500 was 480180 I wonder what variants 5,6,7 are...
>
> What is the rule to define the id ?
These four bits mean "revision".
The number comes from hardware, so the ST ASIC department
has some person who is responsible for revising the VHDL or
Verilog code that this hardware is compiled from, and that person
is bumping the version.
Theoretically it is a "company function" or something bureaucratic
like that updating the hardware so I guess it could be several
people following procedure who have updated this number in the
hardware over the years.
But I bet it is a single person in Grenoble who has been doing
the MMC/SD block since it appeared.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-16 7:38 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-16 7:38 UTC (permalink / raw)
To: Patrice CHOTARD
Cc: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Alexandre TORGUE, linux-mmc,
linux-kernel, linux-clk, Linux ARM, linux-gpio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andrea Merello
On Mon, Jan 15, 2018 at 6:17 PM, Patrice CHOTARD <patrice.chotard@st.com> wrote:
>>> + {
>>> + .id = 0x00880180,
>>> + .mask = 0x00ffffff,
>>> + .data = &variant_stm32,
>>> + },
>>
>> Since ux500 was 480180 I wonder what variants 5,6,7 are...
>
> What is the rule to define the id ?
These four bits mean "revision".
The number comes from hardware, so the ST ASIC department
has some person who is responsible for revising the VHDL or
Verilog code that this hardware is compiled from, and that person
is bumping the version.
Theoretically it is a "company function" or something bureaucratic
like that updating the hardware so I guess it could be several
people following procedure who have updated this number in the
hardware over the years.
But I bet it is a single person in Grenoble who has been doing
the MMC/SD block since it appeared.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH 04/14] mmc: mmci: Add STM32 variant
@ 2018-01-16 7:38 ` Linus Walleij
0 siblings, 0 replies; 87+ messages in thread
From: Linus Walleij @ 2018-01-16 7:38 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 15, 2018 at 6:17 PM, Patrice CHOTARD <patrice.chotard@st.com> wrote:
>>> + {
>>> + .id = 0x00880180,
>>> + .mask = 0x00ffffff,
>>> + .data = &variant_stm32,
>>> + },
>>
>> Since ux500 was 480180 I wonder what variants 5,6,7 are...
>
> What is the rule to define the id ?
These four bits mean "revision".
The number comes from hardware, so the ST ASIC department
has some person who is responsible for revising the VHDL or
Verilog code that this hardware is compiled from, and that person
is bumping the version.
Theoretically it is a "company function" or something bureaucratic
like that updating the hardware so I guess it could be several
people following procedure who have updated this number in the
hardware over the years.
But I bet it is a single person in Grenoble who has been doing
the MMC/SD block since it appeared.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
2018-01-12 18:52 ` Stephen Boyd
(?)
@ 2018-02-05 8:11 ` Patrice CHOTARD
-1 siblings, 0 replies; 87+ messages in thread
From: Patrice CHOTARD @ 2018-02-05 8:11 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Michael Turquette, linux-clk
SGkgU3RlcGhlbiwgTWljaGFlbA0KDQpJdCdzIGEgZ2VudGxlIHJlbWluZGVyIGFzIHRoaXMgcGF0
Y2ggZG9lc24ndCBhcHBlYXIgdG8gYmUgbWVyZ2VkIGluIGFueSANCmNsay0qIGJyYW5jaCBmb3Ig
bmV4dCBrZXJuZWwuDQoNClRoYW5rcw0KDQpQYXRyaWNlDQoNCg0KT24gMDEvMTIvMjAxOCAwNzo1
MiBQTSwgU3RlcGhlbiBCb3lkIHdyb3RlOg0KPiBPbiAwMS8xMiwgcGF0cmljZS5jaG90YXJkQHN0
LmNvbSB3cm90ZToNCj4+IEZyb206IFBhdHJpY2UgQ2hvdGFyZCA8cGF0cmljZS5jaG90YXJkQHN0
LmNvbT4NCj4+DQo+PiBTVE0zMkY3NjkgaGFzIDIgU0RNTUMgcG9ydCwgYWRkIGNsb2NrIGVudHJ5
IGZvciB0aGUgc2Vjb25kIG9uZS4NCj4+DQo+PiBTaWduZWQtb2ZmLWJ5OiBBbGV4YW5kcmUgVE9S
R1VFIDxhbGV4YW5kcmUudG9yZ3VlQHN0LmNvbT4NCj4+IFNpZ25lZC1vZmYtYnk6IFBhdHJpY2Ug
Q2hvdGFyZCA8cGF0cmljZS5jaG90YXJkQHN0LmNvbT4NCj4+IC0tLQ0KPiANCj4gQWNrZWQtYnk6
IFN0ZXBoZW4gQm95ZCA8c2JveWRAY29kZWF1cm9yYS5vcmc+DQo+IA==
^ permalink raw reply [flat|nested] 87+ messages in thread
end of thread, other threads:[~2018-02-05 8:11 UTC | newest]
Thread overview: 87+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-12 12:15 [PATCH 00/14] Add MMCI support for STM32F SoCs family patrice.chotard-qxv4g6HH51o
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
2018-01-12 12:15 ` [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register patrice.chotard
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
[not found] ` <1515759368-16946-2-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
2018-01-15 1:01 ` Linus Walleij
2018-01-15 1:01 ` Linus Walleij
2018-01-15 1:01 ` Linus Walleij
2018-01-15 1:01 ` Linus Walleij
2018-01-12 12:15 ` [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag patrice.chotard
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
[not found] ` <1515759368-16946-3-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
2018-01-15 1:03 ` Linus Walleij
2018-01-15 1:03 ` Linus Walleij
2018-01-15 1:03 ` Linus Walleij
2018-01-15 1:03 ` Linus Walleij
2018-01-15 12:32 ` Ulf Hansson
2018-01-15 12:32 ` Ulf Hansson
2018-01-15 17:27 ` Patrice CHOTARD
2018-01-15 17:27 ` Patrice CHOTARD
2018-01-15 17:27 ` Patrice CHOTARD
2018-01-15 17:27 ` Patrice CHOTARD
2018-01-12 12:15 ` [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl patrice.chotard
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
[not found] ` <1515759368-16946-4-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
2018-01-15 1:07 ` Linus Walleij
2018-01-15 1:07 ` Linus Walleij
2018-01-15 1:07 ` Linus Walleij
2018-01-15 1:07 ` Linus Walleij
2018-01-15 12:43 ` Ulf Hansson
2018-01-15 12:43 ` Ulf Hansson
2018-01-15 17:42 ` Patrice CHOTARD
2018-01-15 17:42 ` Patrice CHOTARD
2018-01-15 17:42 ` Patrice CHOTARD
2018-01-15 17:42 ` Patrice CHOTARD
2018-01-12 12:15 ` [PATCH 04/14] mmc: mmci: Add STM32 variant patrice.chotard
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
2018-01-15 1:13 ` Linus Walleij
2018-01-15 1:13 ` Linus Walleij
2018-01-15 1:13 ` Linus Walleij
2018-01-15 17:17 ` Patrice CHOTARD
2018-01-15 17:17 ` Patrice CHOTARD
2018-01-15 17:17 ` Patrice CHOTARD
2018-01-15 17:17 ` Patrice CHOTARD
[not found] ` <ce14077b-2b8b-f8a7-2107-78b1d9dcab27-qxv4g6HH51o@public.gmane.org>
2018-01-16 7:38 ` Linus Walleij
2018-01-16 7:38 ` Linus Walleij
2018-01-16 7:38 ` Linus Walleij
2018-01-16 7:38 ` Linus Walleij
2018-01-12 12:15 ` [PATCH 05/14] ARM: dts: stm32: Add SDIO controller for stm32f746 patrice.chotard
2018-01-12 12:15 ` patrice.chotard at st.com
2018-01-12 12:15 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 06/14] ARM: dts: stm32: Add SDIO controller for stm32f429 patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 07/14] ARM: dts: stm32: Add pin map for SDIO controller on stm32f4 patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 08/14] ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 09/14] ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 10/14] ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 11/14] ARM: configs: stm32: Enable MMC_ARMMMCI support patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 12/14] ARM: configs: stm32: Enable EXT3_FS support patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 12:16 ` [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769 patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
2018-01-12 18:52 ` Stephen Boyd
2018-01-12 18:52 ` Stephen Boyd
2018-02-05 8:11 ` Patrice CHOTARD
2018-01-12 12:16 ` [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context patrice.chotard
2018-01-12 12:16 ` patrice.chotard at st.com
2018-01-12 12:16 ` patrice.chotard
[not found] ` <1515759368-16946-15-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
2018-01-15 9:57 ` Linus Walleij
2018-01-15 9:57 ` Linus Walleij
2018-01-15 9:57 ` Linus Walleij
2018-01-15 9:57 ` Linus Walleij
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