* [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h
@ 2018-03-22 11:40 Rex Zhu
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I087bcdc56977a8434706362f4e05593c5e7c2522
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 3 +++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 15 ++++++---------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
index 6429dc2..d37d16e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -27,6 +27,9 @@
struct pp_hwmgr;
struct phm_ppt_v1_voltage_lookup_table;
+uint8_t convert_to_vid(uint16_t vddc);
+uint16_t convert_to_vddc(uint8_t vid);
+
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index,
uint32_t value, uint32_t mask);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d742d9d..17f811d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -39,9 +39,6 @@
#define VOLTAGE_SCALE 4
-uint8_t convert_to_vid(uint16_t vddc);
-uint16_t convert_to_vddc(uint8_t vid);
-
enum DISPLAY_GAP {
DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
@@ -784,12 +781,12 @@ struct pp_hwmgr {
uint32_t workload_setting[Workload_Policy_Max];
};
-extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
-extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
-extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
-extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
-extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
-extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
+int hwmgr_early_init(struct pp_hwmgr *hwmgr);
+int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
+int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
+int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
+int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
+int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 11:40 ` Rex Zhu
[not found] ` <1521718818-22687-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table Rex Zhu
` (4 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Clean up pp ip functions
Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
3 files changed, 145 insertions(+), 304 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7e8ad30..5d7d9ec 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -31,24 +31,11 @@
#include "amdgpu.h"
#include "hwmgr.h"
-#define PP_DPM_DISABLED 0xCCCC
-
static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
static const struct amd_pm_funcs pp_dpm_funcs;
-static inline int pp_check(struct pp_hwmgr *hwmgr)
-{
- if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
- return -EINVAL;
-
- if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
- return PP_DPM_DISABLED;
-
- return 0;
-}
-
static int amd_powerplay_create(struct amdgpu_device *adev)
{
struct pp_hwmgr *hwmgr;
@@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
}
-static int amd_powerplay_destroy(struct amdgpu_device *adev)
+static void amd_powerplay_destroy(struct amdgpu_device *adev)
{
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
@@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
kfree(hwmgr);
hwmgr = NULL;
-
- return 0;
}
static int pp_early_init(void *handle)
@@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret >= 0) {
- if (hwmgr->smumgr_funcs->smu_init == NULL)
- return -EINVAL;
+ ret = hwmgr_sw_init(hwmgr);
- ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
-
- phm_register_irq_handlers(hwmgr);
-
- pr_debug("amdgpu: powerplay sw initialized\n");
- }
+ pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
return ret;
}
@@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret = 0;
- ret = pp_check(hwmgr);
- if (ret >= 0) {
- if (hwmgr->smumgr_funcs->smu_fini != NULL)
- hwmgr->smumgr_funcs->smu_fini(hwmgr);
- }
+ hwmgr_sw_fini(hwmgr);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_fini_bo(adev);
@@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_init_bo(adev);
- ret = pp_check(hwmgr);
+ ret = hwmgr_hw_init(hwmgr);
- if (ret >= 0) {
- if (hwmgr->smumgr_funcs->start_smu == NULL)
- return -EINVAL;
+ if (ret)
+ pr_err("amdgpu: powerplay hw init failed\n");
- if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
- pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(hwmgr);
- return -EINVAL;
- }
- if (ret == PP_DPM_DISABLED)
- goto exit;
- ret = hwmgr_hw_init(hwmgr);
- if (ret)
- goto exit;
- }
return ret;
-exit:
- hwmgr->pm_en = 0;
- cgs_notify_dpm_enabled(hwmgr->device, false);
- return 0;
-
}
static int pp_hw_fini(void *handle)
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret = 0;
- ret = pp_check(hwmgr);
- if (ret == 0)
- hwmgr_hw_fini(hwmgr);
+ hwmgr_hw_fini(hwmgr);
return 0;
}
@@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret == 0)
+ if (hwmgr && hwmgr->pm_en)
pp_dpm_dispatch_tasks(hwmgr,
AMD_PP_TASK_COMPLETE_INIT, NULL);
@@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret = 0;
- ret = pp_check(hwmgr);
- if (ret == 0)
- hwmgr_hw_suspend(hwmgr);
- return 0;
+ return hwmgr_suspend(hwmgr);
}
static int pp_resume(void *handle)
{
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- int ret;
-
- ret = pp_check(hwmgr);
-
- if (ret < 0)
- return ret;
-
- if (hwmgr->smumgr_funcs->start_smu == NULL)
- return -EINVAL;
-
- if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
- pr_err("smc start failed\n");
- hwmgr->smumgr_funcs->smu_fini(hwmgr);
- return -EINVAL;
- }
-
- if (ret == PP_DPM_DISABLED)
- return 0;
- return hwmgr_hw_resume(hwmgr);
+ return hwmgr_resume(hwmgr);
}
static int pp_set_clockgating_state(void *handle,
@@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (level == hwmgr->dpm_level)
return 0;
@@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
void *handle)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
enum amd_dpm_forced_level level;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
level = hwmgr->dpm_level;
@@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
uint32_t clk = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
if (hwmgr->hwmgr_func->get_sclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
uint32_t clk = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
if (hwmgr->hwmgr_func->get_mclk == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
static void pp_dpm_powergate_vce(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
+ if (!hwmgr || !hwmgr->pm_en)
return;
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
@@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
+ if (!hwmgr || !hwmgr->pm_en)
return;
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
@@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
int ret = 0;
struct pp_hwmgr *hwmgr = handle;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
ret = hwmgr_handle_task(hwmgr, task_id, user_state);
@@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
{
struct pp_hwmgr *hwmgr = handle;
struct pp_power_state *state;
- int ret = 0;
enum amd_pm_state_type pm_type;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
-
- if (hwmgr->current_ps == NULL)
+ if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
+ if (!hwmgr || !hwmgr->pm_en)
return;
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
@@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
static uint32_t pp_dpm_get_fan_control_mode(void *handle)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
uint32_t mode = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
return -EINVAL;
@@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
{
struct pp_hwmgr *hwmgr = handle;
int i;
- int ret = 0;
memset(data, 0, sizeof(*data));
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
-
- if (hwmgr->ps == NULL)
+ if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
static int pp_dpm_get_pp_table(void *handle, char **table)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
int size = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
-
- if (!hwmgr->soft_pp_table)
+ if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
struct pp_hwmgr *hwmgr = handle;
int ret;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
ret = hwmgr_hw_fini(hwmgr);
if (ret)
return ret;
@@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
if (!hwmgr->hardcode_pp_table) {
@@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->force_clock_level == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (value == NULL)
+ if (!hwmgr || !hwmgr->pm_en || !value)
return -EINVAL;
switch (idx) {
@@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
+ if (!hwmgr || !hwmgr->pm_en)
return NULL;
- if (hwmgr && idx < hwmgr->num_vce_state_tables)
+ if (idx < hwmgr->num_vce_state_tables)
return &hwmgr->vce_states[idx];
return NULL;
}
@@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
{
struct pp_hwmgr *hwmgr = handle;
- if (!buf || pp_check(hwmgr))
+ if (!hwmgr || !hwmgr->pm_en || !buf)
return -EINVAL;
if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
@@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
struct pp_hwmgr *hwmgr = handle;
int ret = -EINVAL;
- if (pp_check(hwmgr))
- return -EINVAL;
+ if (!hwmgr || !hwmgr->pm_en)
+ return ret;
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
pr_info("%s was not implemented.\n", __func__);
- return -EINVAL;
+ return ret;
}
mutex_lock(&hwmgr->smu_lock);
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
@@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
{
struct pp_hwmgr *hwmgr = handle;
- if (pp_check(hwmgr))
+ if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
@@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
long workload;
uint32_t index;
- if (pp_check(hwmgr))
+ if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
@@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
static int pp_set_power_limit(void *handle, uint32_t limit)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->set_power_limit == NULL) {
pr_info("%s was not implemented.\n", __func__);
@@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
hwmgr->power_limit = limit;
mutex_unlock(&hwmgr->smu_lock);
- return ret;
+ return 0;
}
static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (limit == NULL)
+ if (!hwmgr || !hwmgr->pm_en ||!limit)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
mutex_unlock(&hwmgr->smu_lock);
- return ret;
+ return 0;
}
static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
phm_store_dal_configuration_data(hwmgr, display_config);
@@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
-
- if (output == NULL)
+ if (!hwmgr || !hwmgr->pm_en ||!output)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (clocks == NULL)
return -EINVAL;
@@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (!clocks)
+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (!clocks)
+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (!wm_with_clock_ranges)
+ if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
-
- if (!clock)
+ if (!hwmgr || !hwmgr->pm_en ||!clock)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
struct pp_hwmgr *hwmgr = handle;
int ret = 0;
- ret = pp_check(hwmgr);
-
- if (ret)
- return ret;
-
- if (clocks == NULL)
+ if (!hwmgr || !hwmgr->pm_en ||!clocks)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
@@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
static int pp_set_mmhub_powergating_by_smu(void *handle)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
-
- ret = pp_check(hwmgr);
- if (ret)
- return ret;
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
pr_info("%s was not implemented.\n", __func__);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 4298205..96a2d01 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
int hwmgr_early_init(struct pp_hwmgr *hwmgr)
{
- if (hwmgr == NULL)
+ if (!hwmgr)
return -EINVAL;
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
@@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
return 0;
}
+int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
+{
+ if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
+ return -EINVAL;
+
+ phm_register_irq_handlers(hwmgr);
+
+ return hwmgr->smumgr_funcs->smu_init(hwmgr);
+}
+
+
+int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
+ hwmgr->smumgr_funcs->smu_fini(hwmgr);
+
+ return 0;
+}
+
int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- if (hwmgr == NULL)
+ if (!hwmgr || !hwmgr->smumgr_funcs)
return -EINVAL;
- if (hwmgr->pptable_func == NULL ||
- hwmgr->pptable_func->pptable_init == NULL ||
- hwmgr->hwmgr_func->backend_init == NULL)
- return -EINVAL;
+ if (hwmgr->smumgr_funcs->start_smu) {
+ ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
+ if (ret) {
+ pr_err("smc start failed\n");
+ return -EINVAL;
+ }
+ }
+
+ if (!hwmgr->pm_en)
+ return 0;
+
+ if (!hwmgr->pptable_func ||
+ !hwmgr->pptable_func->pptable_init ||
+ !hwmgr->hwmgr_func->backend_init) {
+ hwmgr->pm_en = false;
+ cgs_notify_dpm_enabled(hwmgr->device, false);
+ pr_info("dpm not supported \n");
+ return 0;
+ }
ret = hwmgr->pptable_func->pptable_init(hwmgr);
if (ret)
@@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
if (hwmgr->pptable_func->pptable_fini)
hwmgr->pptable_func->pptable_fini(hwmgr);
err:
- pr_err("amdgpu: powerplay initialization failed\n");
return ret;
}
int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
{
- if (hwmgr == NULL)
- return -EINVAL;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
phm_stop_thermal_controller(hwmgr);
psm_set_boot_states(hwmgr);
@@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
return psm_fini_power_state_table(hwmgr);
}
-int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
+int hwmgr_suspend(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- if (hwmgr == NULL)
- return -EINVAL;
+ if (!hwmgr || !hwmgr->pm_en)
+ return 0;
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
@@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
return ret;
}
-int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
+int hwmgr_resume(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- if (hwmgr == NULL)
+ if (!hwmgr)
return -EINVAL;
+ if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
+ if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
+ pr_err("smc start failed\n");
+ return -EINVAL;
+ }
+ }
+
+ if (!hwmgr->pm_en)
+ return 0;
+
ret = phm_setup_asic(hwmgr);
if (ret)
return ret;
@@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
if (ret)
return ret;
ret = phm_start_thermal_controller(hwmgr);
- if (ret)
- return ret;
-
ret |= psm_set_performance_states(hwmgr);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 17f811d..d6c9a3b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -782,10 +782,13 @@ struct pp_hwmgr {
};
int hwmgr_early_init(struct pp_hwmgr *hwmgr);
+int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
+int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
-int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
-int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
+int hwmgr_suspend(struct pp_hwmgr *hwmgr);
+int hwmgr_resume(struct pp_hwmgr *hwmgr);
+
int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
enum amd_pp_task task_id,
enum amd_pm_state_type *user_state);
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins Rex Zhu
@ 2018-03-22 11:40 ` Rex Zhu
[not found] ` <1521718818-22687-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 4/6] drm/amd/pp: Save vf state in pp context Rex Zhu
` (3 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ib02cd71593bee9606822a466a56f2d01ac2e04cc
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 28 +++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5d7d9ec..1ae4905 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -31,8 +31,6 @@
#include "amdgpu.h"
#include "hwmgr.h"
-static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
- enum amd_pm_state_type *user_state);
static const struct amd_pm_funcs pp_dpm_funcs;
@@ -146,10 +144,12 @@ static int pp_late_init(void *handle)
struct amdgpu_device *adev = handle;
struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
- if (hwmgr && hwmgr->pm_en)
- pp_dpm_dispatch_tasks(hwmgr,
+ if (hwmgr && hwmgr->pm_en) {
+ mutex_lock(&hwmgr->smu_lock);
+ hwmgr_handle_task(hwmgr,
AMD_PP_TASK_COMPLETE_INIT, NULL);
-
+ mutex_unlock(&hwmgr->smu_lock);
+ }
return 0;
}
@@ -620,7 +620,7 @@ static int amd_powerplay_reset(void *handle)
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
struct pp_hwmgr *hwmgr = handle;
- int ret = 0;
+ int ret = -ENOMEM;
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
@@ -630,28 +630,28 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
hwmgr->soft_pp_table_size,
GFP_KERNEL);
- if (!hwmgr->hardcode_pp_table) {
- mutex_unlock(&hwmgr->smu_lock);
- return -ENOMEM;
- }
+ if (!hwmgr->hardcode_pp_table)
+ goto err;
}
memcpy(hwmgr->hardcode_pp_table, buf, size);
hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
- mutex_unlock(&hwmgr->smu_lock);
ret = amd_powerplay_reset(handle);
if (ret)
- return ret;
+ goto err;
if (hwmgr->hwmgr_func->avfs_control) {
ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
if (ret)
- return ret;
+ goto err;
}
-
+ mutex_unlock(&hwmgr->smu_lock);
return 0;
+err:
+ mutex_unlock(&hwmgr->smu_lock);
+ return ret;
}
static int pp_dpm_force_clock_level(void *handle,
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 4/6] drm/amd/pp: Save vf state in pp context
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins Rex Zhu
2018-03-22 11:40 ` [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table Rex Zhu
@ 2018-03-22 11:40 ` Rex Zhu
[not found] ` <1521718818-22687-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 5/6] drm/amd/pp: Use release_firmware function directly in powerplay Rex Zhu
` (2 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ic77e961317113942023b25523df6a4399535fb06
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ++-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 7 +++----
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 3 +--
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 10 +++++-----
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 3 +--
6 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 1ae4905..5717859 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -46,7 +46,8 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
return -ENOMEM;
hwmgr->adev = adev;
- hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
+ hwmgr->not_vf = !amdgpu_sriov_vf(adev);
+ hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
hwmgr->device = amdgpu_cgs_create_device(adev);
mutex_init(&hwmgr->smu_lock);
hwmgr->chip_family = adev->family;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d6c9a3b..d5cadc6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -718,6 +718,7 @@ struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
uint32_t smu_version;
+ bool not_vf;
bool pm_en;
struct mutex smu_lock;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index faef783..35b947e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -288,8 +288,7 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
/* Only start SMC if SMC RAM is not running */
- if (!(smu7_is_smc_ram_running(hwmgr)
- || cgs_is_virtualization_enabled(hwmgr->device))) {
+ if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
/* Check if SMU is running in protected mode */
if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC,
@@ -335,8 +334,8 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
uint32_t efuse = 0;
uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
- if (cgs_is_virtualization_enabled(hwmgr->device))
- return 0;
+ if (!hwmgr->not_vf)
+ return false;
if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
mask, &efuse)) {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 997a777..b861c26 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -295,8 +295,7 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
/* Only start SMC if SMC RAM is not running */
- if (!(smu7_is_smc_ram_running(hwmgr)
- || cgs_is_virtualization_enabled(hwmgr->device))) {
+ if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 0399c10..3684822 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -375,7 +375,7 @@ static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
entry->meta_data_addr_low = 0;
/* digest need be excluded out */
- if (cgs_is_virtualization_enabled(hwmgr->device))
+ if (!hwmgr->not_vf)
info.image_size -= 20;
entry->data_size_byte = info.image_size;
entry->num_register_entries = 0;
@@ -409,7 +409,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
0x0);
if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
- if (!cgs_is_virtualization_enabled(hwmgr->device)) {
+ if (hwmgr->not_vf) {
smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SMU_DRAM_ADDR_HI,
upper_32_bits(smu_data->smu_buffer.mc_addr));
@@ -467,7 +467,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
- if (cgs_is_virtualization_enabled(hwmgr->device))
+ if (!hwmgr->not_vf)
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
"Failed to Get Firmware Entry.", return -EINVAL);
@@ -608,7 +608,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
smu_data->header = smu_data->header_buffer.kaddr;
smu_data->header_buffer.mc_addr = mc_addr;
- if (cgs_is_virtualization_enabled(hwmgr->device))
+ if (!hwmgr->not_vf)
return 0;
smu_data->smu_buffer.data_size = 200*4096;
@@ -643,7 +643,7 @@ int smu7_smu_fini(struct pp_hwmgr *hwmgr)
&smu_data->header_buffer.mc_addr,
&smu_data->header_buffer.kaddr);
- if (!cgs_is_virtualization_enabled(hwmgr->device))
+ if (hwmgr->not_vf)
amdgpu_bo_free_kernel(&smu_data->smu_buffer.handle,
&smu_data->smu_buffer.mc_addr,
&smu_data->smu_buffer.kaddr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index b51d746..2ba05d2 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -199,8 +199,7 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
int result;
/* Only start SMC if SMC RAM is not running */
- if (!(smu7_is_smc_ram_running(hwmgr) ||
- cgs_is_virtualization_enabled(hwmgr->device))) {
+ if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
/*Check if SMU is running in protected mode*/
if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 5/6] drm/amd/pp: Use release_firmware function directly in powerplay
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-03-22 11:40 ` [PATCH 4/6] drm/amd/pp: Save vf state in pp context Rex Zhu
@ 2018-03-22 11:40 ` Rex Zhu
[not found] ` <1521718818-22687-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 6/6] drm/amd/pp: Delete some cgs functions Rex Zhu
2018-03-22 13:10 ` [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h Alex Deucher
5 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I7e3c01d0d413bbada67c044b88f2e5f0a53f0b38
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 ++++-
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 3 ++-
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 1 -
5 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5717859..315e25c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -107,8 +107,11 @@ static int pp_sw_fini(void *handle)
hwmgr_sw_fini(hwmgr);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
+ release_firmware(adev->pm.fw);
+ adev->pm.fw = NULL;
amdgpu_ucode_fini_bo(adev);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index fe36659..c7d6533 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -31,5 +31,6 @@
#include "dm_pp_interface.h"
#include "kgd_pp_interface.h"
#include "amdgpu.h"
+#include <linux/firmware.h>
#endif /* _AMD_POWERPLAY_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 08d0001..e30a2ee 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -2784,7 +2784,6 @@ static int ci_smu_fini(struct pp_hwmgr *hwmgr)
{
kfree(hwmgr->smu_backend);
hwmgr->smu_backend = NULL;
- cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index b861c26..3e80d61 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -308,7 +308,8 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
/* If failed, try with different security Key. */
if (result != 0) {
smu_data->smu7_data.security_hard_key ^= 1;
- cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
+ release_firmware(((struct amdgpu_device *)hwmgr->adev)->pm.fw);
+ ((struct amdgpu_device *)hwmgr->adev)->pm.fw = NULL;
result = polaris10_start_smu_in_protection_mode(hwmgr);
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 3684822..41fab2d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -650,6 +650,5 @@ int smu7_smu_fini(struct pp_hwmgr *hwmgr)
kfree(hwmgr->smu_backend);
hwmgr->smu_backend = NULL;
- cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0;
}
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 6/6] drm/amd/pp: Delete some cgs functions
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-03-22 11:40 ` [PATCH 5/6] drm/amd/pp: Use release_firmware function directly in powerplay Rex Zhu
@ 2018-03-22 11:40 ` Rex Zhu
[not found] ` <1521718818-22687-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:10 ` [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h Alex Deucher
5 siblings, 1 reply; 19+ messages in thread
From: Rex Zhu @ 2018-03-22 11:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: If90e946b915a30e14123f9892f12ddcf6c653095
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 30 ----------------------
drivers/gpu/drm/amd/include/cgs_common.h | 19 +-------------
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 14 ++--------
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
4 files changed, 4 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 71a57b2..1da6c17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -271,18 +271,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
return result;
}
-static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
-{
- CGS_FUNC_ADEV;
- if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
- release_firmware(adev->pm.fw);
- adev->pm.fw = NULL;
- return 0;
- }
- /* cannot release other firmware because they are not created by cgs */
- return -EINVAL;
-}
-
static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
enum cgs_ucode_id type)
{
@@ -598,11 +586,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
return 0;
}
-static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
-{
- CGS_FUNC_ADEV;
- return amdgpu_sriov_vf(adev);
-}
static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
struct cgs_display_info *info)
@@ -661,16 +644,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
return 0;
}
-
-static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
-{
- CGS_FUNC_ADEV;
-
- adev->pm.dpm_enabled = enabled;
-
- return 0;
-}
-
static const struct cgs_ops amdgpu_cgs_ops = {
.read_register = amdgpu_cgs_read_register,
.write_register = amdgpu_cgs_write_register,
@@ -681,12 +654,9 @@ static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool ena
.atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
.atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
.get_firmware_info = amdgpu_cgs_get_firmware_info,
- .rel_firmware = amdgpu_cgs_rel_firmware,
.set_powergating_state = amdgpu_cgs_set_powergating_state,
.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
- .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
- .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
};
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index f2814ae..69109a0e 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -235,9 +235,6 @@ typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
enum cgs_ucode_id type,
struct cgs_firmware_info *info);
-typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
- enum cgs_ucode_id type);
-
typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
enum amd_ip_block_type block_type,
enum amd_powergating_state state);
@@ -250,10 +247,6 @@ typedef int(*cgs_get_active_displays_info)(
struct cgs_device *cgs_device,
struct cgs_display_info *info);
-typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
-
-typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
-
typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
@@ -272,15 +265,11 @@ struct cgs_ops {
cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
/* Firmware Info */
cgs_get_firmware_info get_firmware_info;
- cgs_rel_firmware rel_firmware;
/* cg pg interface*/
cgs_set_powergating_state set_powergating_state;
cgs_set_clockgating_state set_clockgating_state;
/* display manager */
cgs_get_active_displays_info get_active_displays_info;
- /* notify dpm enabled */
- cgs_notify_dpm_enabled notify_dpm_enabled;
- cgs_is_virtualization_enabled_t is_virtualization_enabled;
cgs_enter_safe_mode enter_safe_mode;
cgs_lock_grbm_idx lock_grbm_idx;
};
@@ -318,14 +307,11 @@ struct cgs_device
#define cgs_get_firmware_info(dev, type, info) \
CGS_CALL(get_firmware_info, dev, type, info)
-#define cgs_rel_firmware(dev, type) \
- CGS_CALL(rel_firmware, dev, type)
#define cgs_set_powergating_state(dev, block_type, state) \
CGS_CALL(set_powergating_state, dev, block_type, state)
#define cgs_set_clockgating_state(dev, block_type, state) \
CGS_CALL(set_clockgating_state, dev, block_type, state)
-#define cgs_notify_dpm_enabled(dev, enabled) \
- CGS_CALL(notify_dpm_enabled, dev, enabled)
+
#define cgs_get_active_displays_info(dev, info) \
CGS_CALL(get_active_displays_info, dev, info)
@@ -335,9 +321,6 @@ struct cgs_device
CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
resource_base)
-#define cgs_is_virtualization_enabled(cgs_device) \
- CGS_CALL(is_virtualization_enabled, cgs_device)
-
#define cgs_enter_safe_mode(cgs_device, en) \
CGS_CALL(enter_safe_mode, cgs_device, en)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index ae2e933..dcceadb 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -75,8 +75,7 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
- int ret = 1;
- bool enabled;
+ int ret = -EINVAL;;
PHM_FUNC_CHECK(hwmgr);
if (smum_is_dpm_running(hwmgr)) {
@@ -87,17 +86,12 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
- enabled = ret == 0;
-
- cgs_notify_dpm_enabled(hwmgr->device, enabled);
-
return ret;
}
int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
- int ret = -1;
- bool enabled;
+ int ret = -EINVAL;
PHM_FUNC_CHECK(hwmgr);
@@ -109,10 +103,6 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
if (hwmgr->hwmgr_func->dynamic_state_management_disable)
ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
- enabled = ret == 0 ? false : true;
-
- cgs_notify_dpm_enabled(hwmgr->device, enabled);
-
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 96a2d01..30ff8a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -211,7 +211,7 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
!hwmgr->pptable_func->pptable_init ||
!hwmgr->hwmgr_func->backend_init) {
hwmgr->pm_en = false;
- cgs_notify_dpm_enabled(hwmgr->device, false);
+ ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = false;
pr_info("dpm not supported \n");
return 0;
}
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-03-22 11:40 ` [PATCH 6/6] drm/amd/pp: Delete some cgs functions Rex Zhu
@ 2018-03-22 13:10 ` Alex Deucher
5 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:10 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I087bcdc56977a8434706362f4e05593c5e7c2522
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 3 +++
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 15 ++++++---------
> 2 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> index 6429dc2..d37d16e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> @@ -27,6 +27,9 @@
> struct pp_hwmgr;
> struct phm_ppt_v1_voltage_lookup_table;
>
> +uint8_t convert_to_vid(uint16_t vddc);
> +uint16_t convert_to_vddc(uint8_t vid);
> +
> extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
> uint32_t index,
> uint32_t value, uint32_t mask);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index d742d9d..17f811d 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -39,9 +39,6 @@
>
> #define VOLTAGE_SCALE 4
>
> -uint8_t convert_to_vid(uint16_t vddc);
> -uint16_t convert_to_vddc(uint8_t vid);
> -
> enum DISPLAY_GAP {
> DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
> DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
> @@ -784,12 +781,12 @@ struct pp_hwmgr {
> uint32_t workload_setting[Workload_Policy_Max];
> };
>
> -extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> -extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
> -extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
> -extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
> -extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> -extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> +int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
> +int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
> +int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> +int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <1521718818-22687-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 13:10 ` Alex Deucher
[not found] ` <CADnq5_PsnzfqnsHXsjBY36TaT85d6hVOWpgL-04coK8gcvOyGA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-03-23 1:49 ` Huang Rui
1 sibling, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:10 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Clean up pp ip functions
>
> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
> 3 files changed, 145 insertions(+), 304 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7e8ad30..5d7d9ec 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -31,24 +31,11 @@
> #include "amdgpu.h"
> #include "hwmgr.h"
>
> -#define PP_DPM_DISABLED 0xCCCC
> -
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> static const struct amd_pm_funcs pp_dpm_funcs;
>
> -static inline int pp_check(struct pp_hwmgr *hwmgr)
> -{
> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
> - return PP_DPM_DISABLED;
> -
> - return 0;
> -}
> -
> static int amd_powerplay_create(struct amdgpu_device *adev)
> {
> struct pp_hwmgr *hwmgr;
> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
> }
>
>
> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
> {
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
>
> kfree(hwmgr);
> hwmgr = NULL;
> -
> - return 0;
> }
>
> static int pp_early_init(void *handle)
> @@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_init == NULL)
> - return -EINVAL;
> + ret = hwmgr_sw_init(hwmgr);
>
> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
> -
> - phm_register_irq_handlers(hwmgr);
> -
> - pr_debug("amdgpu: powerplay sw initialized\n");
> - }
> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
>
> return ret;
> }
> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - }
> + hwmgr_sw_fini(hwmgr);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_fini_bo(adev);
> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_init_bo(adev);
>
> - ret = pp_check(hwmgr);
> + ret = hwmgr_hw_init(hwmgr);
>
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> + if (ret)
> + pr_err("amdgpu: powerplay hw init failed\n");
>
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> - if (ret == PP_DPM_DISABLED)
> - goto exit;
> - ret = hwmgr_hw_init(hwmgr);
> - if (ret)
> - goto exit;
> - }
> return ret;
> -exit:
> - hwmgr->pm_en = 0;
> - cgs_notify_dpm_enabled(hwmgr->device, false);
> - return 0;
> -
> }
>
> static int pp_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_fini(hwmgr);
> + hwmgr_hw_fini(hwmgr);
>
> return 0;
> }
> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret == 0)
> + if (hwmgr && hwmgr->pm_en)
> pp_dpm_dispatch_tasks(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
>
> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_suspend(hwmgr);
> - return 0;
> + return hwmgr_suspend(hwmgr);
> }
>
> static int pp_resume(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret;
> -
> - ret = pp_check(hwmgr);
> -
> - if (ret < 0)
> - return ret;
> -
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> -
> - if (ret == PP_DPM_DISABLED)
> - return 0;
>
> - return hwmgr_hw_resume(hwmgr);
> + return hwmgr_resume(hwmgr);
> }
>
> static int pp_set_clockgating_state(void *handle,
> @@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
> enum amd_dpm_forced_level level)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (level == hwmgr->dpm_level)
> return 0;
> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> enum amd_dpm_forced_level level;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> level = hwmgr->dpm_level;
> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_sclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_mclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> static void pp_dpm_powergate_vce(void *handle, bool gate)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
> @@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
> static void pp_dpm_powergate_uvd(void *handle, bool gate)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
> @@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> int ret = 0;
> struct pp_hwmgr *hwmgr = handle;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr_handle_task(hwmgr, task_id, user_state);
> @@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> struct pp_power_state *state;
> - int ret = 0;
> enum amd_pm_state_type pm_type;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->current_ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
> @@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t mode = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
> return -EINVAL;
> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
> {
> struct pp_hwmgr *hwmgr = handle;
> int i;
> - int ret = 0;
>
> memset(data, 0, sizeof(*data));
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
> static int pp_dpm_get_pp_table(void *handle, char **table)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> int size = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (!hwmgr->soft_pp_table)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> ret = hwmgr_hw_fini(hwmgr);
> if (ret)
> return ret;
> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> if (!hwmgr->hardcode_pp_table) {
> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (value == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !value)
> return -EINVAL;
>
> switch (idx) {
> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return NULL;
>
> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
> + if (idx < hwmgr->num_vce_state_tables)
> return &hwmgr->vce_states[idx];
> return NULL;
> }
> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
> {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (!buf || pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en || !buf)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
> @@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = -EINVAL;
>
> - if (pp_check(hwmgr))
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return ret;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> - return -EINVAL;
> + return ret;
> }
> mutex_lock(&hwmgr->smu_lock);
> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
> @@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
> {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
> @@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
> long workload;
> uint32_t index;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> @@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> static int pp_set_power_limit(void *handle, uint32_t limit)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
> hwmgr->power_limit = limit;
> mutex_unlock(&hwmgr->smu_lock);
> - return ret;
> + return 0;
> }
>
> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> -
> - if (limit == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!limit)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>
> mutex_unlock(&hwmgr->smu_lock);
>
> - return ret;
> + return 0;
> }
>
> static int pp_display_configuration_change(void *handle,
> const struct amd_pp_display_configuration *display_config)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> phm_store_dal_configuration_data(hwmgr, display_config);
> @@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (output == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!output)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
>
> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (clocks == NULL)
> return -EINVAL;
> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!wm_with_clock_ranges)
> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clock)
> + if (!hwmgr || !hwmgr->pm_en ||!clock)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (clocks == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> static int pp_set_mmhub_powergating_by_smu(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 4298205..96a2d01 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> {
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
> @@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
> +{
> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
> + return -EINVAL;
> +
> + phm_register_irq_handlers(hwmgr);
> +
> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
> +}
> +
> +
> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
> +{
> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> +
> + return 0;
> +}
> +
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr || !hwmgr->smumgr_funcs)
> return -EINVAL;
>
> - if (hwmgr->pptable_func == NULL ||
> - hwmgr->pptable_func->pptable_init == NULL ||
> - hwmgr->hwmgr_func->backend_init == NULL)
> - return -EINVAL;
> + if (hwmgr->smumgr_funcs->start_smu) {
> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
> + if (ret) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> + if (!hwmgr->pptable_func ||
> + !hwmgr->pptable_func->pptable_init ||
> + !hwmgr->hwmgr_func->backend_init) {
> + hwmgr->pm_en = false;
> + cgs_notify_dpm_enabled(hwmgr->device, false);
> + pr_info("dpm not supported \n");
> + return 0;
> + }
>
> ret = hwmgr->pptable_func->pptable_init(hwmgr);
> if (ret)
> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> if (hwmgr->pptable_func->pptable_fini)
> hwmgr->pptable_func->pptable_fini(hwmgr);
> err:
> - pr_err("amdgpu: powerplay initialization failed\n");
> return ret;
> }
>
> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> {
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_stop_thermal_controller(hwmgr);
> psm_set_boot_states(hwmgr);
> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> return psm_fini_power_state_table(hwmgr);
> }
>
> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_disable_smc_firmware_ctf(hwmgr);
> ret = psm_set_boot_states(hwmgr);
> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> return ret;
> }
>
> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> ret = phm_setup_asic(hwmgr);
> if (ret)
> return ret;
> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> if (ret)
> return ret;
> ret = phm_start_thermal_controller(hwmgr);
> - if (ret)
> - return ret;
> -
> ret |= psm_set_performance_states(hwmgr);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 17f811d..d6c9a3b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -782,10 +782,13 @@ struct pp_hwmgr {
> };
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr);
> +int hwmgr_resume(struct pp_hwmgr *hwmgr);
> +
> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <CADnq5_PsnzfqnsHXsjBY36TaT85d6hVOWpgL-04coK8gcvOyGA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-03-22 13:13 ` Alex Deucher
[not found] ` <CADnq5_N9uegS=tM+=OEeL+kYy2xhYpBLisjfawQgwqFuLTpwkA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:13 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 9:10 AM, Alex Deucher <alexdeucher@gmail.com> wrote:
> On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
>> Clean up pp ip functions
>>
>> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Actually, doesn't this patch have a dependency on patch 3? I think
this part of patch 3:
+ hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
should be in this patch rather than the other patch. With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
>> 3 files changed, 145 insertions(+), 304 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> index 7e8ad30..5d7d9ec 100644
>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> @@ -31,24 +31,11 @@
>> #include "amdgpu.h"
>> #include "hwmgr.h"
>>
>> -#define PP_DPM_DISABLED 0xCCCC
>> -
>> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>> enum amd_pm_state_type *user_state);
>>
>> static const struct amd_pm_funcs pp_dpm_funcs;
>>
>> -static inline int pp_check(struct pp_hwmgr *hwmgr)
>> -{
>> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
>> - return -EINVAL;
>> -
>> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
>> - return PP_DPM_DISABLED;
>> -
>> - return 0;
>> -}
>> -
>> static int amd_powerplay_create(struct amdgpu_device *adev)
>> {
>> struct pp_hwmgr *hwmgr;
>> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
>> }
>>
>>
>> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
>> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
>> {
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>
>> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
>>
>> kfree(hwmgr);
>> hwmgr = NULL;
>> -
>> - return 0;
>> }
>>
>> static int pp_early_init(void *handle)
>> @@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret >= 0) {
>> - if (hwmgr->smumgr_funcs->smu_init == NULL)
>> - return -EINVAL;
>> + ret = hwmgr_sw_init(hwmgr);
>>
>> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
>> -
>> - phm_register_irq_handlers(hwmgr);
>> -
>> - pr_debug("amdgpu: powerplay sw initialized\n");
>> - }
>> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
>>
>> return ret;
>> }
>> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret >= 0) {
>> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>> - }
>> + hwmgr_sw_fini(hwmgr);
>>
>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>> amdgpu_ucode_fini_bo(adev);
>> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>> amdgpu_ucode_init_bo(adev);
>>
>> - ret = pp_check(hwmgr);
>> + ret = hwmgr_hw_init(hwmgr);
>>
>> - if (ret >= 0) {
>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>> - return -EINVAL;
>> + if (ret)
>> + pr_err("amdgpu: powerplay hw init failed\n");
>>
>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>> - pr_err("smc start failed\n");
>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>> - return -EINVAL;
>> - }
>> - if (ret == PP_DPM_DISABLED)
>> - goto exit;
>> - ret = hwmgr_hw_init(hwmgr);
>> - if (ret)
>> - goto exit;
>> - }
>> return ret;
>> -exit:
>> - hwmgr->pm_en = 0;
>> - cgs_notify_dpm_enabled(hwmgr->device, false);
>> - return 0;
>> -
>> }
>>
>> static int pp_hw_fini(void *handle)
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret == 0)
>> - hwmgr_hw_fini(hwmgr);
>> + hwmgr_hw_fini(hwmgr);
>>
>> return 0;
>> }
>> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret == 0)
>> + if (hwmgr && hwmgr->pm_en)
>> pp_dpm_dispatch_tasks(hwmgr,
>> AMD_PP_TASK_COMPLETE_INIT, NULL);
>>
>> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret == 0)
>> - hwmgr_hw_suspend(hwmgr);
>> - return 0;
>> + return hwmgr_suspend(hwmgr);
>> }
>>
>> static int pp_resume(void *handle)
>> {
>> struct amdgpu_device *adev = handle;
>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>> - int ret;
>> -
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret < 0)
>> - return ret;
>> -
>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>> - return -EINVAL;
>> -
>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>> - pr_err("smc start failed\n");
>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>> - return -EINVAL;
>> - }
>> -
>> - if (ret == PP_DPM_DISABLED)
>> - return 0;
>>
>> - return hwmgr_hw_resume(hwmgr);
>> + return hwmgr_resume(hwmgr);
>> }
>>
>> static int pp_set_clockgating_state(void *handle,
>> @@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
>> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
>> enum amd_dpm_forced_level level)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (level == hwmgr->dpm_level)
>> return 0;
>> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>> void *handle)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> enum amd_dpm_forced_level level;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> level = hwmgr->dpm_level;
>> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> uint32_t clk = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> if (hwmgr->hwmgr_func->get_sclk == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> uint32_t clk = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> if (hwmgr->hwmgr_func->get_mclk == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>> static void pp_dpm_powergate_vce(void *handle, bool gate)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> + if (!hwmgr || !hwmgr->pm_en)
>> return;
>>
>> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
>> @@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
>> static void pp_dpm_powergate_uvd(void *handle, bool gate)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> + if (!hwmgr || !hwmgr->pm_en)
>> return;
>>
>> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
>> @@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>> int ret = 0;
>> struct pp_hwmgr *hwmgr = handle;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> ret = hwmgr_handle_task(hwmgr, task_id, user_state);
>> @@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> struct pp_power_state *state;
>> - int ret = 0;
>> enum amd_pm_state_type pm_type;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> -
>> - if (hwmgr->current_ps == NULL)
>> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> + if (!hwmgr || !hwmgr->pm_en)
>> return;
>>
>> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
>> @@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> uint32_t mode = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
>> return -EINVAL;
>> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> int i;
>> - int ret = 0;
>>
>> memset(data, 0, sizeof(*data));
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> -
>> - if (hwmgr->ps == NULL)
>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
>> static int pp_dpm_get_pp_table(void *handle, char **table)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> int size = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> -
>> - if (!hwmgr->soft_pp_table)
>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> ret = hwmgr_hw_fini(hwmgr);
>> if (ret)
>> return ret;
>> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> if (!hwmgr->hardcode_pp_table) {
>> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> - if (value == NULL)
>> + if (!hwmgr || !hwmgr->pm_en || !value)
>> return -EINVAL;
>>
>> switch (idx) {
>> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> + if (!hwmgr || !hwmgr->pm_en)
>> return NULL;
>>
>> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
>> + if (idx < hwmgr->num_vce_state_tables)
>> return &hwmgr->vce_states[idx];
>> return NULL;
>> }
>> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>>
>> - if (!buf || pp_check(hwmgr))
>> + if (!hwmgr || !hwmgr->pm_en || !buf)
>> return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
>> @@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = -EINVAL;
>>
>> - if (pp_check(hwmgr))
>> - return -EINVAL;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return ret;
>>
>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> - return -EINVAL;
>> + return ret;
>> }
>> mutex_lock(&hwmgr->smu_lock);
>> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
>> @@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
>> {
>> struct pp_hwmgr *hwmgr = handle;
>>
>> - if (pp_check(hwmgr))
>> + if (!hwmgr || !hwmgr->pm_en)
>> return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
>> @@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
>> long workload;
>> uint32_t index;
>>
>> - if (pp_check(hwmgr))
>> + if (!hwmgr || !hwmgr->pm_en)
>> return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>> @@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>> static int pp_set_power_limit(void *handle, uint32_t limit)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> @@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
>> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
>> hwmgr->power_limit = limit;
>> mutex_unlock(&hwmgr->smu_lock);
>> - return ret;
>> + return 0;
>> }
>>
>> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> - return ret;
>> -
>> - if (limit == NULL)
>> + if (!hwmgr || !hwmgr->pm_en ||!limit)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>>
>> mutex_unlock(&hwmgr->smu_lock);
>>
>> - return ret;
>> + return 0;
>> }
>>
>> static int pp_display_configuration_change(void *handle,
>> const struct amd_pp_display_configuration *display_config)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> phm_store_dal_configuration_data(hwmgr, display_config);
>> @@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> -
>> - if (output == NULL)
>> + if (!hwmgr || !hwmgr->pm_en ||!output)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>>
>> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (clocks == NULL)
>> return -EINVAL;
>> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> - if (!clocks)
>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> - if (!clocks)
>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> - if (!wm_with_clock_ranges)
>> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> - if (!clock)
>> + if (!hwmgr || !hwmgr->pm_en ||!clock)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>> struct pp_hwmgr *hwmgr = handle;
>> int ret = 0;
>>
>> - ret = pp_check(hwmgr);
>> -
>> - if (ret)
>> - return ret;
>> -
>> - if (clocks == NULL)
>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>> return -EINVAL;
>>
>> mutex_lock(&hwmgr->smu_lock);
>> @@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>> static int pp_set_mmhub_powergating_by_smu(void *handle)
>> {
>> struct pp_hwmgr *hwmgr = handle;
>> - int ret = 0;
>> -
>> - ret = pp_check(hwmgr);
>>
>> - if (ret)
>> - return ret;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return -EINVAL;
>>
>> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
>> pr_info("%s was not implemented.\n", __func__);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index 4298205..96a2d01 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
>>
>> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>> {
>> - if (hwmgr == NULL)
>> + if (!hwmgr)
>> return -EINVAL;
>>
>> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
>> @@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>> return 0;
>> }
>>
>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
>> +{
>> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
>> + return -EINVAL;
>> +
>> + phm_register_irq_handlers(hwmgr);
>> +
>> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
>> +}
>> +
>> +
>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
>> +{
>> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
>> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
>> +
>> + return 0;
>> +}
>> +
>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>> {
>> int ret = 0;
>>
>> - if (hwmgr == NULL)
>> + if (!hwmgr || !hwmgr->smumgr_funcs)
>> return -EINVAL;
>>
>> - if (hwmgr->pptable_func == NULL ||
>> - hwmgr->pptable_func->pptable_init == NULL ||
>> - hwmgr->hwmgr_func->backend_init == NULL)
>> - return -EINVAL;
>> + if (hwmgr->smumgr_funcs->start_smu) {
>> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
>> + if (ret) {
>> + pr_err("smc start failed\n");
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + if (!hwmgr->pm_en)
>> + return 0;
>> +
>> + if (!hwmgr->pptable_func ||
>> + !hwmgr->pptable_func->pptable_init ||
>> + !hwmgr->hwmgr_func->backend_init) {
>> + hwmgr->pm_en = false;
>> + cgs_notify_dpm_enabled(hwmgr->device, false);
>> + pr_info("dpm not supported \n");
>> + return 0;
>> + }
>>
>> ret = hwmgr->pptable_func->pptable_init(hwmgr);
>> if (ret)
>> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>> if (hwmgr->pptable_func->pptable_fini)
>> hwmgr->pptable_func->pptable_fini(hwmgr);
>> err:
>> - pr_err("amdgpu: powerplay initialization failed\n");
>> return ret;
>> }
>>
>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>> {
>> - if (hwmgr == NULL)
>> - return -EINVAL;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> phm_stop_thermal_controller(hwmgr);
>> psm_set_boot_states(hwmgr);
>> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>> return psm_fini_power_state_table(hwmgr);
>> }
>>
>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
>> {
>> int ret = 0;
>>
>> - if (hwmgr == NULL)
>> - return -EINVAL;
>> + if (!hwmgr || !hwmgr->pm_en)
>> + return 0;
>>
>> phm_disable_smc_firmware_ctf(hwmgr);
>> ret = psm_set_boot_states(hwmgr);
>> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>> return ret;
>> }
>>
>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
>> {
>> int ret = 0;
>>
>> - if (hwmgr == NULL)
>> + if (!hwmgr)
>> return -EINVAL;
>>
>> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
>> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>> + pr_err("smc start failed\n");
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + if (!hwmgr->pm_en)
>> + return 0;
>> +
>> ret = phm_setup_asic(hwmgr);
>> if (ret)
>> return ret;
>> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>> if (ret)
>> return ret;
>> ret = phm_start_thermal_controller(hwmgr);
>> - if (ret)
>> - return ret;
>> -
>> ret |= psm_set_performance_states(hwmgr);
>> if (ret)
>> return ret;
>> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>> index 17f811d..d6c9a3b 100644
>> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>> @@ -782,10 +782,13 @@ struct pp_hwmgr {
>> };
>>
>> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr);
>> +int hwmgr_resume(struct pp_hwmgr *hwmgr);
>> +
>> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
>> enum amd_pp_task task_id,
>> enum amd_pm_state_type *user_state);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <CADnq5_N9uegS=tM+=OEeL+kYy2xhYpBLisjfawQgwqFuLTpwkA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-03-22 13:13 ` Alex Deucher
[not found] ` <CADnq5_NbKvyAEqkpGsNGUFBQkVrELctS2_rkRR+YHJMDfSajEg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:13 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 9:13 AM, Alex Deucher <alexdeucher@gmail.com> wrote:
> On Thu, Mar 22, 2018 at 9:10 AM, Alex Deucher <alexdeucher@gmail.com> wrote:
>> On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
>>> Clean up pp ip functions
>>>
>>> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
>>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Actually, doesn't this patch have a dependency on patch 3? I think
> this part of patch 3:
Sorry, patch 4.
> + hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
> should be in this patch rather than the other patch. With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>>
>>> ---
>>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
>>> 3 files changed, 145 insertions(+), 304 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> index 7e8ad30..5d7d9ec 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> @@ -31,24 +31,11 @@
>>> #include "amdgpu.h"
>>> #include "hwmgr.h"
>>>
>>> -#define PP_DPM_DISABLED 0xCCCC
>>> -
>>> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>>> enum amd_pm_state_type *user_state);
>>>
>>> static const struct amd_pm_funcs pp_dpm_funcs;
>>>
>>> -static inline int pp_check(struct pp_hwmgr *hwmgr)
>>> -{
>>> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
>>> - return -EINVAL;
>>> -
>>> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
>>> - return PP_DPM_DISABLED;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> static int amd_powerplay_create(struct amdgpu_device *adev)
>>> {
>>> struct pp_hwmgr *hwmgr;
>>> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
>>> }
>>>
>>>
>>> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
>>> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
>>> {
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>>
>>> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
>>>
>>> kfree(hwmgr);
>>> hwmgr = NULL;
>>> -
>>> - return 0;
>>> }
>>>
>>> static int pp_early_init(void *handle)
>>> @@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->smu_init == NULL)
>>> - return -EINVAL;
>>> + ret = hwmgr_sw_init(hwmgr);
>>>
>>> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
>>> -
>>> - phm_register_irq_handlers(hwmgr);
>>> -
>>> - pr_debug("amdgpu: powerplay sw initialized\n");
>>> - }
>>> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
>>>
>>> return ret;
>>> }
>>> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - }
>>> + hwmgr_sw_fini(hwmgr);
>>>
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>>> amdgpu_ucode_fini_bo(adev);
>>> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>>> amdgpu_ucode_init_bo(adev);
>>>
>>> - ret = pp_check(hwmgr);
>>> + ret = hwmgr_hw_init(hwmgr);
>>>
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>>> - return -EINVAL;
>>> + if (ret)
>>> + pr_err("amdgpu: powerplay hw init failed\n");
>>>
>>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> - pr_err("smc start failed\n");
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - return -EINVAL;
>>> - }
>>> - if (ret == PP_DPM_DISABLED)
>>> - goto exit;
>>> - ret = hwmgr_hw_init(hwmgr);
>>> - if (ret)
>>> - goto exit;
>>> - }
>>> return ret;
>>> -exit:
>>> - hwmgr->pm_en = 0;
>>> - cgs_notify_dpm_enabled(hwmgr->device, false);
>>> - return 0;
>>> -
>>> }
>>>
>>> static int pp_hw_fini(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret == 0)
>>> - hwmgr_hw_fini(hwmgr);
>>> + hwmgr_hw_fini(hwmgr);
>>>
>>> return 0;
>>> }
>>> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret == 0)
>>> + if (hwmgr && hwmgr->pm_en)
>>> pp_dpm_dispatch_tasks(hwmgr,
>>> AMD_PP_TASK_COMPLETE_INIT, NULL);
>>>
>>> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret == 0)
>>> - hwmgr_hw_suspend(hwmgr);
>>> - return 0;
>>> + return hwmgr_suspend(hwmgr);
>>> }
>>>
>>> static int pp_resume(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret;
>>> -
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret < 0)
>>> - return ret;
>>> -
>>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>>> - return -EINVAL;
>>> -
>>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> - pr_err("smc start failed\n");
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - if (ret == PP_DPM_DISABLED)
>>> - return 0;
>>>
>>> - return hwmgr_hw_resume(hwmgr);
>>> + return hwmgr_resume(hwmgr);
>>> }
>>>
>>> static int pp_set_clockgating_state(void *handle,
>>> @@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
>>> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
>>> enum amd_dpm_forced_level level)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (level == hwmgr->dpm_level)
>>> return 0;
>>> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>>> void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> enum amd_dpm_forced_level level;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> level = hwmgr->dpm_level;
>>> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>>> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t clk = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_sclk == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>>> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t clk = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_mclk == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>>> static void pp_dpm_powergate_vce(void *handle, bool gate)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
>>> @@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
>>> static void pp_dpm_powergate_uvd(void *handle, bool gate)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
>>> @@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>>> int ret = 0;
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> ret = hwmgr_handle_task(hwmgr, task_id, user_state);
>>> @@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> struct pp_power_state *state;
>>> - int ret = 0;
>>> enum amd_pm_state_type pm_type;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (hwmgr->current_ps == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>>> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
>>> @@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>>> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t mode = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
>>> return -EINVAL;
>>> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> int i;
>>> - int ret = 0;
>>>
>>> memset(data, 0, sizeof(*data));
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (hwmgr->ps == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
>>> static int pp_dpm_get_pp_table(void *handle, char **table)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> int size = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!hwmgr->soft_pp_table)
>>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> ret = hwmgr_hw_fini(hwmgr);
>>> if (ret)
>>> return ret;
>>> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> if (!hwmgr->hardcode_pp_table) {
>>> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (value == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en || !value)
>>> return -EINVAL;
>>>
>>> switch (idx) {
>>> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>>> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return NULL;
>>>
>>> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
>>> + if (idx < hwmgr->num_vce_state_tables)
>>> return &hwmgr->vce_states[idx];
>>> return NULL;
>>> }
>>> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - if (!buf || pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en || !buf)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
>>> @@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = -EINVAL;
>>>
>>> - if (pp_check(hwmgr))
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return ret;
>>>
>>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> - return -EINVAL;
>>> + return ret;
>>> }
>>> mutex_lock(&hwmgr->smu_lock);
>>> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
>>> @@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - if (pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
>>> @@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
>>> long workload;
>>> uint32_t index;
>>>
>>> - if (pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>>> @@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>>> static int pp_set_power_limit(void *handle, uint32_t limit)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
>>> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
>>> hwmgr->power_limit = limit;
>>> mutex_unlock(&hwmgr->smu_lock);
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (limit == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!limit)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>>>
>>> mutex_unlock(&hwmgr->smu_lock);
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> static int pp_display_configuration_change(void *handle,
>>> const struct amd_pp_display_configuration *display_config)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> phm_store_dal_configuration_data(hwmgr, display_config);
>>> @@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (output == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!output)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>>
>>> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (clocks == NULL)
>>> return -EINVAL;
>>> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clocks)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clocks)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!wm_with_clock_ranges)
>>> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clock)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clock)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (clocks == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>>> static int pp_set_mmhub_powergating_by_smu(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> index 4298205..96a2d01 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
>>>
>>> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>>> {
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr)
>>> return -EINVAL;
>>>
>>> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
>>> @@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>>> return 0;
>>> }
>>>
>>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
>>> +{
>>> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
>>> + return -EINVAL;
>>> +
>>> + phm_register_irq_handlers(hwmgr);
>>> +
>>> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
>>> +}
>>> +
>>> +
>>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
>>> +{
>>> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
>>> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr || !hwmgr->smumgr_funcs)
>>> return -EINVAL;
>>>
>>> - if (hwmgr->pptable_func == NULL ||
>>> - hwmgr->pptable_func->pptable_init == NULL ||
>>> - hwmgr->hwmgr_func->backend_init == NULL)
>>> - return -EINVAL;
>>> + if (hwmgr->smumgr_funcs->start_smu) {
>>> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
>>> + if (ret) {
>>> + pr_err("smc start failed\n");
>>> + return -EINVAL;
>>> + }
>>> + }
>>> +
>>> + if (!hwmgr->pm_en)
>>> + return 0;
>>> +
>>> + if (!hwmgr->pptable_func ||
>>> + !hwmgr->pptable_func->pptable_init ||
>>> + !hwmgr->hwmgr_func->backend_init) {
>>> + hwmgr->pm_en = false;
>>> + cgs_notify_dpm_enabled(hwmgr->device, false);
>>> + pr_info("dpm not supported \n");
>>> + return 0;
>>> + }
>>>
>>> ret = hwmgr->pptable_func->pptable_init(hwmgr);
>>> if (ret)
>>> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>>> if (hwmgr->pptable_func->pptable_fini)
>>> hwmgr->pptable_func->pptable_fini(hwmgr);
>>> err:
>>> - pr_err("amdgpu: powerplay initialization failed\n");
>>> return ret;
>>> }
>>>
>>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>>> {
>>> - if (hwmgr == NULL)
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> phm_stop_thermal_controller(hwmgr);
>>> psm_set_boot_states(hwmgr);
>>> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>>> return psm_fini_power_state_table(hwmgr);
>>> }
>>>
>>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> phm_disable_smc_firmware_ctf(hwmgr);
>>> ret = psm_set_boot_states(hwmgr);
>>> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>>> return ret;
>>> }
>>>
>>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>>> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr)
>>> return -EINVAL;
>>>
>>> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
>>> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> + pr_err("smc start failed\n");
>>> + return -EINVAL;
>>> + }
>>> + }
>>> +
>>> + if (!hwmgr->pm_en)
>>> + return 0;
>>> +
>>> ret = phm_setup_asic(hwmgr);
>>> if (ret)
>>> return ret;
>>> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>>> if (ret)
>>> return ret;
>>> ret = phm_start_thermal_controller(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> ret |= psm_set_performance_states(hwmgr);
>>> if (ret)
>>> return ret;
>>> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> index 17f811d..d6c9a3b 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> @@ -782,10 +782,13 @@ struct pp_hwmgr {
>>> };
>>>
>>> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
>>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
>>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
>>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
>>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_resume(struct pp_hwmgr *hwmgr);
>>> +
>>> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
>>> enum amd_pp_task task_id,
>>> enum amd_pm_state_type *user_state);
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
[not found] ` <1521718818-22687-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 13:17 ` Alex Deucher
[not found] ` <CADnq5_PoA0JtqbsepaX0D0RMxTwDi89Uw9DHmvL7tzXduk_EaA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:17 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ib02cd71593bee9606822a466a56f2d01ac2e04cc
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Please include a commit description. It's not clear to me what's
happening here.
Alex
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 28 +++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 5d7d9ec..1ae4905 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -31,8 +31,6 @@
> #include "amdgpu.h"
> #include "hwmgr.h"
>
> -static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> - enum amd_pm_state_type *user_state);
>
> static const struct amd_pm_funcs pp_dpm_funcs;
>
> @@ -146,10 +144,12 @@ static int pp_late_init(void *handle)
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> - if (hwmgr && hwmgr->pm_en)
> - pp_dpm_dispatch_tasks(hwmgr,
> + if (hwmgr && hwmgr->pm_en) {
> + mutex_lock(&hwmgr->smu_lock);
> + hwmgr_handle_task(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
> -
> + mutex_unlock(&hwmgr->smu_lock);
> + }
> return 0;
> }
>
> @@ -620,7 +620,7 @@ static int amd_powerplay_reset(void *handle)
> static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> + int ret = -ENOMEM;
>
> if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
> @@ -630,28 +630,28 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
> hwmgr->soft_pp_table_size,
> GFP_KERNEL);
> - if (!hwmgr->hardcode_pp_table) {
> - mutex_unlock(&hwmgr->smu_lock);
> - return -ENOMEM;
> - }
> + if (!hwmgr->hardcode_pp_table)
> + goto err;
> }
>
> memcpy(hwmgr->hardcode_pp_table, buf, size);
>
> hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
> - mutex_unlock(&hwmgr->smu_lock);
>
> ret = amd_powerplay_reset(handle);
> if (ret)
> - return ret;
> + goto err;
>
> if (hwmgr->hwmgr_func->avfs_control) {
> ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
> if (ret)
> - return ret;
> + goto err;
> }
> -
> + mutex_unlock(&hwmgr->smu_lock);
> return 0;
> +err:
> + mutex_unlock(&hwmgr->smu_lock);
> + return ret;
> }
>
> static int pp_dpm_force_clock_level(void *handle,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/6] drm/amd/pp: Save vf state in pp context
[not found] ` <1521718818-22687-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 13:21 ` Alex Deucher
0 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:21 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ic77e961317113942023b25523df6a4399535fb06
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Please include a patch description. E.g.,
Store vf state in pp_context so we can deprecate the cgs interface.
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ++-
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 7 +++----
> drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 3 +--
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 10 +++++-----
> drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 3 +--
> 6 files changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 1ae4905..5717859 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -46,7 +46,8 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
> return -ENOMEM;
>
> hwmgr->adev = adev;
> - hwmgr->pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
> + hwmgr->not_vf = !amdgpu_sriov_vf(adev);
> + hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
This should be part of patch 2. With these comments addressed the patch is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> hwmgr->device = amdgpu_cgs_create_device(adev);
> mutex_init(&hwmgr->smu_lock);
> hwmgr->chip_family = adev->family;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index d6c9a3b..d5cadc6 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -718,6 +718,7 @@ struct pp_hwmgr {
> uint32_t chip_family;
> uint32_t chip_id;
> uint32_t smu_version;
> + bool not_vf;
> bool pm_en;
> struct mutex smu_lock;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index faef783..35b947e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -288,8 +288,7 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
> struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
>
> /* Only start SMC if SMC RAM is not running */
> - if (!(smu7_is_smc_ram_running(hwmgr)
> - || cgs_is_virtualization_enabled(hwmgr->device))) {
> + if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
> /* Check if SMU is running in protected mode */
> if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> CGS_IND_REG__SMC,
> @@ -335,8 +334,8 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
> uint32_t efuse = 0;
> uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
>
> - if (cgs_is_virtualization_enabled(hwmgr->device))
> - return 0;
> + if (!hwmgr->not_vf)
> + return false;
>
> if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
> mask, &efuse)) {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index 997a777..b861c26 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -295,8 +295,7 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
> struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
>
> /* Only start SMC if SMC RAM is not running */
> - if (!(smu7_is_smc_ram_running(hwmgr)
> - || cgs_is_virtualization_enabled(hwmgr->device))) {
> + if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
> smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
> smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 0399c10..3684822 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -375,7 +375,7 @@ static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
> entry->meta_data_addr_low = 0;
>
> /* digest need be excluded out */
> - if (cgs_is_virtualization_enabled(hwmgr->device))
> + if (!hwmgr->not_vf)
> info.image_size -= 20;
> entry->data_size_byte = info.image_size;
> entry->num_register_entries = 0;
> @@ -409,7 +409,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> 0x0);
>
> if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
> - if (!cgs_is_virtualization_enabled(hwmgr->device)) {
> + if (hwmgr->not_vf) {
> smu7_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SMU_DRAM_ADDR_HI,
> upper_32_bits(smu_data->smu_buffer.mc_addr));
> @@ -467,7 +467,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
> PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
> UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
> "Failed to Get Firmware Entry.", return -EINVAL);
> - if (cgs_is_virtualization_enabled(hwmgr->device))
> + if (!hwmgr->not_vf)
> PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
> UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
> "Failed to Get Firmware Entry.", return -EINVAL);
> @@ -608,7 +608,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
> smu_data->header = smu_data->header_buffer.kaddr;
> smu_data->header_buffer.mc_addr = mc_addr;
>
> - if (cgs_is_virtualization_enabled(hwmgr->device))
> + if (!hwmgr->not_vf)
> return 0;
>
> smu_data->smu_buffer.data_size = 200*4096;
> @@ -643,7 +643,7 @@ int smu7_smu_fini(struct pp_hwmgr *hwmgr)
> &smu_data->header_buffer.mc_addr,
> &smu_data->header_buffer.kaddr);
>
> - if (!cgs_is_virtualization_enabled(hwmgr->device))
> + if (hwmgr->not_vf)
> amdgpu_bo_free_kernel(&smu_data->smu_buffer.handle,
> &smu_data->smu_buffer.mc_addr,
> &smu_data->smu_buffer.kaddr);
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index b51d746..2ba05d2 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -199,8 +199,7 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
> int result;
>
> /* Only start SMC if SMC RAM is not running */
> - if (!(smu7_is_smc_ram_running(hwmgr) ||
> - cgs_is_virtualization_enabled(hwmgr->device))) {
> + if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
> /*Check if SMU is running in protected mode*/
> if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
> SMU_FIRMWARE, SMU_MODE)) {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/6] drm/amd/pp: Use release_firmware function directly in powerplay
[not found] ` <1521718818-22687-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 13:23 ` Alex Deucher
0 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:23 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I7e3c01d0d413bbada67c044b88f2e5f0a53f0b38
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Please include a patch description. E.g.,
Use release_firmware directly so we can remove the cgs firmware wrapper.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 ++++-
> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 1 -
> drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 3 ++-
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 1 -
> 5 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 5717859..315e25c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -107,8 +107,11 @@ static int pp_sw_fini(void *handle)
>
> hwmgr_sw_fini(hwmgr);
>
> - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
> + release_firmware(adev->pm.fw);
> + adev->pm.fw = NULL;
> amdgpu_ucode_fini_bo(adev);
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> index fe36659..c7d6533 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> @@ -31,5 +31,6 @@
> #include "dm_pp_interface.h"
> #include "kgd_pp_interface.h"
> #include "amdgpu.h"
> +#include <linux/firmware.h>
>
> #endif /* _AMD_POWERPLAY_H_ */
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index 08d0001..e30a2ee 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -2784,7 +2784,6 @@ static int ci_smu_fini(struct pp_hwmgr *hwmgr)
> {
> kfree(hwmgr->smu_backend);
> hwmgr->smu_backend = NULL;
> - cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index b861c26..3e80d61 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -308,7 +308,8 @@ static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
> /* If failed, try with different security Key. */
> if (result != 0) {
> smu_data->smu7_data.security_hard_key ^= 1;
> - cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
> + release_firmware(((struct amdgpu_device *)hwmgr->adev)->pm.fw);
> + ((struct amdgpu_device *)hwmgr->adev)->pm.fw = NULL;
> result = polaris10_start_smu_in_protection_mode(hwmgr);
> }
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 3684822..41fab2d 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -650,6 +650,5 @@ int smu7_smu_fini(struct pp_hwmgr *hwmgr)
>
> kfree(hwmgr->smu_backend);
> hwmgr->smu_backend = NULL;
> - cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 6/6] drm/amd/pp: Delete some cgs functions
[not found] ` <1521718818-22687-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-22 13:24 ` Alex Deucher
0 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:24 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: If90e946b915a30e14123f9892f12ddcf6c653095
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Please include a patch description. E.g.,
Drop cgs wrappers that are no longer uses.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 30 ----------------------
> drivers/gpu/drm/amd/include/cgs_common.h | 19 +-------------
> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 14 ++--------
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
> 4 files changed, 4 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 71a57b2..1da6c17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -271,18 +271,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
> return result;
> }
>
> -static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
> -{
> - CGS_FUNC_ADEV;
> - if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
> - release_firmware(adev->pm.fw);
> - adev->pm.fw = NULL;
> - return 0;
> - }
> - /* cannot release other firmware because they are not created by cgs */
> - return -EINVAL;
> -}
> -
> static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
> enum cgs_ucode_id type)
> {
> @@ -598,11 +586,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
> return 0;
> }
>
> -static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
> -{
> - CGS_FUNC_ADEV;
> - return amdgpu_sriov_vf(adev);
> -}
>
> static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
> struct cgs_display_info *info)
> @@ -661,16 +644,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
> return 0;
> }
>
> -
> -static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
> -{
> - CGS_FUNC_ADEV;
> -
> - adev->pm.dpm_enabled = enabled;
> -
> - return 0;
> -}
> -
> static const struct cgs_ops amdgpu_cgs_ops = {
> .read_register = amdgpu_cgs_read_register,
> .write_register = amdgpu_cgs_write_register,
> @@ -681,12 +654,9 @@ static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool ena
> .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
> .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
> .get_firmware_info = amdgpu_cgs_get_firmware_info,
> - .rel_firmware = amdgpu_cgs_rel_firmware,
> .set_powergating_state = amdgpu_cgs_set_powergating_state,
> .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
> .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
> - .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
> - .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
> .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
> .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
> };
> diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
> index f2814ae..69109a0e 100644
> --- a/drivers/gpu/drm/amd/include/cgs_common.h
> +++ b/drivers/gpu/drm/amd/include/cgs_common.h
> @@ -235,9 +235,6 @@ typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
> enum cgs_ucode_id type,
> struct cgs_firmware_info *info);
>
> -typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
> - enum cgs_ucode_id type);
> -
> typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
> enum amd_ip_block_type block_type,
> enum amd_powergating_state state);
> @@ -250,10 +247,6 @@ typedef int(*cgs_get_active_displays_info)(
> struct cgs_device *cgs_device,
> struct cgs_display_info *info);
>
> -typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
> -
> -typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
> -
> typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
>
> typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
> @@ -272,15 +265,11 @@ struct cgs_ops {
> cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
> /* Firmware Info */
> cgs_get_firmware_info get_firmware_info;
> - cgs_rel_firmware rel_firmware;
> /* cg pg interface*/
> cgs_set_powergating_state set_powergating_state;
> cgs_set_clockgating_state set_clockgating_state;
> /* display manager */
> cgs_get_active_displays_info get_active_displays_info;
> - /* notify dpm enabled */
> - cgs_notify_dpm_enabled notify_dpm_enabled;
> - cgs_is_virtualization_enabled_t is_virtualization_enabled;
> cgs_enter_safe_mode enter_safe_mode;
> cgs_lock_grbm_idx lock_grbm_idx;
> };
> @@ -318,14 +307,11 @@ struct cgs_device
>
> #define cgs_get_firmware_info(dev, type, info) \
> CGS_CALL(get_firmware_info, dev, type, info)
> -#define cgs_rel_firmware(dev, type) \
> - CGS_CALL(rel_firmware, dev, type)
> #define cgs_set_powergating_state(dev, block_type, state) \
> CGS_CALL(set_powergating_state, dev, block_type, state)
> #define cgs_set_clockgating_state(dev, block_type, state) \
> CGS_CALL(set_clockgating_state, dev, block_type, state)
> -#define cgs_notify_dpm_enabled(dev, enabled) \
> - CGS_CALL(notify_dpm_enabled, dev, enabled)
> +
>
> #define cgs_get_active_displays_info(dev, info) \
> CGS_CALL(get_active_displays_info, dev, info)
> @@ -335,9 +321,6 @@ struct cgs_device
> CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
> resource_base)
>
> -#define cgs_is_virtualization_enabled(cgs_device) \
> - CGS_CALL(is_virtualization_enabled, cgs_device)
> -
> #define cgs_enter_safe_mode(cgs_device, en) \
> CGS_CALL(enter_safe_mode, cgs_device, en)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index ae2e933..dcceadb 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -75,8 +75,7 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
>
> int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
> {
> - int ret = 1;
> - bool enabled;
> + int ret = -EINVAL;;
> PHM_FUNC_CHECK(hwmgr);
>
> if (smum_is_dpm_running(hwmgr)) {
> @@ -87,17 +86,12 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
> if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
> ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
>
> - enabled = ret == 0;
> -
> - cgs_notify_dpm_enabled(hwmgr->device, enabled);
> -
> return ret;
> }
>
> int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
> {
> - int ret = -1;
> - bool enabled;
> + int ret = -EINVAL;
>
> PHM_FUNC_CHECK(hwmgr);
>
> @@ -109,10 +103,6 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
> if (hwmgr->hwmgr_func->dynamic_state_management_disable)
> ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
>
> - enabled = ret == 0 ? false : true;
> -
> - cgs_notify_dpm_enabled(hwmgr->device, enabled);
> -
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 96a2d01..30ff8a9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -211,7 +211,7 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> !hwmgr->pptable_func->pptable_init ||
> !hwmgr->hwmgr_func->backend_init) {
> hwmgr->pm_en = false;
> - cgs_notify_dpm_enabled(hwmgr->device, false);
> + ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = false;
> pr_info("dpm not supported \n");
> return 0;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
[not found] ` <CADnq5_PoA0JtqbsepaX0D0RMxTwDi89Uw9DHmvL7tzXduk_EaA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-03-22 13:44 ` Zhu, Rex
[not found] ` <CY4PR12MB16878FF235D78E9C0A3A722BFBA90-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 19+ messages in thread
From: Zhu, Rex @ 2018-03-22 13:44 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 4393 bytes --]
Please see inline.
Best Regards
Rex
________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, March 22, 2018 9:17 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> Change-Id: Ib02cd71593bee9606822a466a56f2d01ac2e04cc
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Please include a commit description. It's not clear to me what's
happening here.
Alex
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 28 +++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 5d7d9ec..1ae4905 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -31,8 +31,6 @@
> #include "amdgpu.h"
> #include "hwmgr.h"
>
> -static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> - enum amd_pm_state_type *user_state);
>
> static const struct amd_pm_funcs pp_dpm_funcs;
>
> @@ -146,10 +144,12 @@ static int pp_late_init(void *handle)
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> - if (hwmgr && hwmgr->pm_en)
> - pp_dpm_dispatch_tasks(hwmgr,
> + if (hwmgr && hwmgr->pm_en) {
> + mutex_lock(&hwmgr->smu_lock);
> + hwmgr_handle_task(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
> -
> + mutex_unlock(&hwmgr->smu_lock);
> + }
> return 0;
> }
Rex : use hwmgr_handle_task instand of pp_dpm_dispatch_tasks. because i think it is not make sense that call
pp_function in ip_function.
> @@ -620,7 +620,7 @@ static int amd_powerplay_reset(void *handle)
> static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> + int ret = -ENOMEM;
>
> if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
> @@ -630,28 +630,28 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
> hwmgr->soft_pp_table_size,
> GFP_KERNEL);
> - if (!hwmgr->hardcode_pp_table) {
> - mutex_unlock(&hwmgr->smu_lock);
> - return -ENOMEM;
> - }
> + if (!hwmgr->hardcode_pp_table)
> + goto err;
> }
>
> memcpy(hwmgr->hardcode_pp_table, buf, size);
>
> hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
> - mutex_unlock(&hwmgr->smu_lock);
>
> ret = amd_powerplay_reset(handle);
> if (ret)
> - return ret;
> + goto err;
>
> if (hwmgr->hwmgr_func->avfs_control) {
> ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
> if (ret)
> - return ret;
> + goto err;
> }
> -
> + mutex_unlock(&hwmgr->smu_lock);
> return 0;
> +err:
> + mutex_unlock(&hwmgr->smu_lock);
> + return ret;
> }
Rex: unlock mutex until set pp table complete to avoid other pp functions were called simultaneously<http://www.baidu.com/link?url=8RpXVOm53HQyZI9h-ZIs8Ipio9NEDj98vxJiiM0Wx4hbUUpanLuj7jZHEnm0Javd7_rpySIGVAwaxX_ICV-y2nDz_TZqF8mzUGZT8RPrw2WCcNsGFsoAh9nirArCSm9s>.
> static int pp_dpm_force_clock_level(void *handle,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9xlNPtJONSTn@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
amd-gfx Info Page - freedesktop.org<https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
lists.freedesktop.org
Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the following form. Use of all freedesktop.org lists is subject to our Code of ...
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
[not found] ` <CY4PR12MB16878FF235D78E9C0A3A722BFBA90-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-03-22 13:47 ` Alex Deucher
0 siblings, 0 replies; 19+ messages in thread
From: Alex Deucher @ 2018-03-22 13:47 UTC (permalink / raw)
To: Zhu, Rex; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 4734 bytes --]
On Thu, Mar 22, 2018 at 9:44 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> Please see inline.
>
> Best Regards
> Rex
> ------------------------------
> *From:* Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Thursday, March 22, 2018 9:17 PM
> *To:* Zhu, Rex
> *Cc:* amd-gfx list
> *Subject:* Re: [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table
>
> On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> > Change-Id: Ib02cd71593bee9606822a466a56f2d01ac2e04cc
> > Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>
> Please include a commit description. It's not clear to me what's
> happening here.
>
> Alex
>
> > ---
> > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 28
> +++++++++++++--------------
> > 1 file changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index 5d7d9ec..1ae4905 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -31,8 +31,6 @@
> > #include "amdgpu.h"
> > #include "hwmgr.h"
> >
> > -static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> > - enum amd_pm_state_type *user_state);
> >
> > static const struct amd_pm_funcs pp_dpm_funcs;
> >
> > @@ -146,10 +144,12 @@ static int pp_late_init(void *handle)
> > struct amdgpu_device *adev = handle;
> > struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> >
> > - if (hwmgr && hwmgr->pm_en)
> > - pp_dpm_dispatch_tasks(hwmgr,
> > + if (hwmgr && hwmgr->pm_en) {
> > + mutex_lock(&hwmgr->smu_lock);
> > + hwmgr_handle_task(hwmgr,
> > AMD_PP_TASK_COMPLETE_INIT,
> NULL);
> > -
> > + mutex_unlock(&hwmgr->smu_lock);
> > + }
> > return 0;
> > }
>
> Rex : use hwmgr_handle_task instand of pp_dpm_dispatch_tasks. because i
> think it is not make sense that call
> pp_function in ip_function.
>
> > @@ -620,7 +620,7 @@ static int amd_powerplay_reset(void *handle)
> > static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t
> size)
> > {
> > struct pp_hwmgr *hwmgr = handle;
> > - int ret = 0;
> > + int ret = -ENOMEM;
> >
> > if (!hwmgr || !hwmgr->pm_en)
> > return -EINVAL;
> > @@ -630,28 +630,28 @@ static int pp_dpm_set_pp_table(void *handle, const
> char *buf, size_t size)
> > hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
> >
> hwmgr->soft_pp_table_size,
> > GFP_KERNEL);
> > - if (!hwmgr->hardcode_pp_table) {
> > - mutex_unlock(&hwmgr->smu_lock);
> > - return -ENOMEM;
> > - }
> > + if (!hwmgr->hardcode_pp_table)
> > + goto err;
> > }
> >
> > memcpy(hwmgr->hardcode_pp_table, buf, size);
> >
> > hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
> > - mutex_unlock(&hwmgr->smu_lock);
> >
> > ret = amd_powerplay_reset(handle);
> > if (ret)
> > - return ret;
> > + goto err;
> >
> > if (hwmgr->hwmgr_func->avfs_control) {
> > ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
> > if (ret)
> > - return ret;
> > + goto err;
> > }
> > -
> > + mutex_unlock(&hwmgr->smu_lock);
> > return 0;
> > +err:
> > + mutex_unlock(&hwmgr->smu_lock);
> > + return ret;
> > }
>
>
> Rex: unlock mutex until set pp table complete to avoid other pp functions
> were called simultaneously
> <http://www.baidu.com/link?url=8RpXVOm53HQyZI9h-ZIs8Ipio9NEDj98vxJiiM0Wx4hbUUpanLuj7jZHEnm0Javd7_rpySIGVAwaxX_ICV-y2nDz_TZqF8mzUGZT8RPrw2WCcNsGFsoAh9nirArCSm9s>
> .
>
Thanks. Please include these comments in the patch description. With that
fixed:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
>
>
> > static int pp_dpm_force_clock_level(void *handle,
> > --
> > 1.9.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx-PD4FTy7X32lNgt0PjOBp9xlNPtJONSTn@public.gmane.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> amd-gfx Info Page - freedesktop.org
> <https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
> lists.freedesktop.org
> Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the following
> form. Use of all freedesktop.org lists is subject to our Code of ...
>
>
>
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_______________________________________________
amd-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <CADnq5_NbKvyAEqkpGsNGUFBQkVrELctS2_rkRR+YHJMDfSajEg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-03-22 14:49 ` Zhu, Rex
0 siblings, 0 replies; 19+ messages in thread
From: Zhu, Rex @ 2018-03-22 14:49 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 35366 bytes --]
Thanks Alex.
I should be more careful when reorder patches .
Best Regards
Rex
________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, March 22, 2018 9:13 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
On Thu, Mar 22, 2018 at 9:13 AM, Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Mar 22, 2018 at 9:10 AM, Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> On Thu, Mar 22, 2018 at 7:40 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
>>> Clean up pp ip functions
>>>
>>> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
>>> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>>
>> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
>
> Actually, doesn't this patch have a dependency on patch 3? I think
> this part of patch 3:
Sorry, patch 4.
> + hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
> should be in this patch rather than the other patch. With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
>
>>
>>> ---
>>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
>>> 3 files changed, 145 insertions(+), 304 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> index 7e8ad30..5d7d9ec 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> @@ -31,24 +31,11 @@
>>> #include "amdgpu.h"
>>> #include "hwmgr.h"
>>>
>>> -#define PP_DPM_DISABLED 0xCCCC
>>> -
>>> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>>> enum amd_pm_state_type *user_state);
>>>
>>> static const struct amd_pm_funcs pp_dpm_funcs;
>>>
>>> -static inline int pp_check(struct pp_hwmgr *hwmgr)
>>> -{
>>> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
>>> - return -EINVAL;
>>> -
>>> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
>>> - return PP_DPM_DISABLED;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> static int amd_powerplay_create(struct amdgpu_device *adev)
>>> {
>>> struct pp_hwmgr *hwmgr;
>>> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
>>> }
>>>
>>>
>>> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
>>> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
>>> {
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>>
>>> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
>>>
>>> kfree(hwmgr);
>>> hwmgr = NULL;
>>> -
>>> - return 0;
>>> }
>>>
>>> static int pp_early_init(void *handle)
>>> @@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->smu_init == NULL)
>>> - return -EINVAL;
>>> + ret = hwmgr_sw_init(hwmgr);
>>>
>>> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
>>> -
>>> - phm_register_irq_handlers(hwmgr);
>>> -
>>> - pr_debug("amdgpu: powerplay sw initialized\n");
>>> - }
>>> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
>>>
>>> return ret;
>>> }
>>> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - }
>>> + hwmgr_sw_fini(hwmgr);
>>>
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>>> amdgpu_ucode_fini_bo(adev);
>>> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
>>> amdgpu_ucode_init_bo(adev);
>>>
>>> - ret = pp_check(hwmgr);
>>> + ret = hwmgr_hw_init(hwmgr);
>>>
>>> - if (ret >= 0) {
>>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>>> - return -EINVAL;
>>> + if (ret)
>>> + pr_err("amdgpu: powerplay hw init failed\n");
>>>
>>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> - pr_err("smc start failed\n");
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - return -EINVAL;
>>> - }
>>> - if (ret == PP_DPM_DISABLED)
>>> - goto exit;
>>> - ret = hwmgr_hw_init(hwmgr);
>>> - if (ret)
>>> - goto exit;
>>> - }
>>> return ret;
>>> -exit:
>>> - hwmgr->pm_en = 0;
>>> - cgs_notify_dpm_enabled(hwmgr->device, false);
>>> - return 0;
>>> -
>>> }
>>>
>>> static int pp_hw_fini(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret == 0)
>>> - hwmgr_hw_fini(hwmgr);
>>> + hwmgr_hw_fini(hwmgr);
>>>
>>> return 0;
>>> }
>>> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret == 0)
>>> + if (hwmgr && hwmgr->pm_en)
>>> pp_dpm_dispatch_tasks(hwmgr,
>>> AMD_PP_TASK_COMPLETE_INIT, NULL);
>>>
>>> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret == 0)
>>> - hwmgr_hw_suspend(hwmgr);
>>> - return 0;
>>> + return hwmgr_suspend(hwmgr);
>>> }
>>>
>>> static int pp_resume(void *handle)
>>> {
>>> struct amdgpu_device *adev = handle;
>>> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>>> - int ret;
>>> -
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret < 0)
>>> - return ret;
>>> -
>>> - if (hwmgr->smumgr_funcs->start_smu == NULL)
>>> - return -EINVAL;
>>> -
>>> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> - pr_err("smc start failed\n");
>>> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - if (ret == PP_DPM_DISABLED)
>>> - return 0;
>>>
>>> - return hwmgr_hw_resume(hwmgr);
>>> + return hwmgr_resume(hwmgr);
>>> }
>>>
>>> static int pp_set_clockgating_state(void *handle,
>>> @@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
>>> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
>>> enum amd_dpm_forced_level level)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (level == hwmgr->dpm_level)
>>> return 0;
>>> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>>> void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> enum amd_dpm_forced_level level;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> level = hwmgr->dpm_level;
>>> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
>>> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t clk = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_sclk == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
>>> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t clk = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_mclk == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
>>> static void pp_dpm_powergate_vce(void *handle, bool gate)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
>>> @@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
>>> static void pp_dpm_powergate_uvd(void *handle, bool gate)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
>>> @@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
>>> int ret = 0;
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> ret = hwmgr_handle_task(hwmgr, task_id, user_state);
>>> @@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> struct pp_power_state *state;
>>> - int ret = 0;
>>> enum amd_pm_state_type pm_type;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (hwmgr->current_ps == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
>>> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return;
>>>
>>> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
>>> @@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
>>> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> uint32_t mode = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
>>> return -EINVAL;
>>> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> int i;
>>> - int ret = 0;
>>>
>>> memset(data, 0, sizeof(*data));
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (hwmgr->ps == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
>>> static int pp_dpm_get_pp_table(void *handle, char **table)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> int size = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!hwmgr->soft_pp_table)
>>> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> ret = hwmgr_hw_fini(hwmgr);
>>> if (ret)
>>> return ret;
>>> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> if (!hwmgr->hardcode_pp_table) {
>>> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (value == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en || !value)
>>> return -EINVAL;
>>>
>>> switch (idx) {
>>> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
>>> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return NULL;
>>>
>>> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
>>> + if (idx < hwmgr->num_vce_state_tables)
>>> return &hwmgr->vce_states[idx];
>>> return NULL;
>>> }
>>> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - if (!buf || pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en || !buf)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
>>> @@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = -EINVAL;
>>>
>>> - if (pp_check(hwmgr))
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return ret;
>>>
>>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> - return -EINVAL;
>>> + return ret;
>>> }
>>> mutex_lock(&hwmgr->smu_lock);
>>> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
>>> @@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>>
>>> - if (pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
>>> @@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
>>> long workload;
>>> uint32_t index;
>>>
>>> - if (pp_check(hwmgr))
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
>>> @@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>>> static int pp_set_power_limit(void *handle, uint32_t limit)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> @@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
>>> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
>>> hwmgr->power_limit = limit;
>>> mutex_unlock(&hwmgr->smu_lock);
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (limit == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!limit)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>>>
>>> mutex_unlock(&hwmgr->smu_lock);
>>>
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> static int pp_display_configuration_change(void *handle,
>>> const struct amd_pp_display_configuration *display_config)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> phm_store_dal_configuration_data(hwmgr, display_config);
>>> @@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (output == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!output)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>>
>>> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (clocks == NULL)
>>> return -EINVAL;
>>> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clocks)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clocks)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!wm_with_clock_ranges)
>>> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (!clock)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clock)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>>> struct pp_hwmgr *hwmgr = handle;
>>> int ret = 0;
>>>
>>> - ret = pp_check(hwmgr);
>>> -
>>> - if (ret)
>>> - return ret;
>>> -
>>> - if (clocks == NULL)
>>> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
>>> return -EINVAL;
>>>
>>> mutex_lock(&hwmgr->smu_lock);
>>> @@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
>>> static int pp_set_mmhub_powergating_by_smu(void *handle)
>>> {
>>> struct pp_hwmgr *hwmgr = handle;
>>> - int ret = 0;
>>> -
>>> - ret = pp_check(hwmgr);
>>>
>>> - if (ret)
>>> - return ret;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return -EINVAL;
>>>
>>> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
>>> pr_info("%s was not implemented.\n", __func__);
>>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> index 4298205..96a2d01 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>>> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
>>>
>>> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>>> {
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr)
>>> return -EINVAL;
>>>
>>> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
>>> @@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>>> return 0;
>>> }
>>>
>>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
>>> +{
>>> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
>>> + return -EINVAL;
>>> +
>>> + phm_register_irq_handlers(hwmgr);
>>> +
>>> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
>>> +}
>>> +
>>> +
>>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
>>> +{
>>> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
>>> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr || !hwmgr->smumgr_funcs)
>>> return -EINVAL;
>>>
>>> - if (hwmgr->pptable_func == NULL ||
>>> - hwmgr->pptable_func->pptable_init == NULL ||
>>> - hwmgr->hwmgr_func->backend_init == NULL)
>>> - return -EINVAL;
>>> + if (hwmgr->smumgr_funcs->start_smu) {
>>> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
>>> + if (ret) {
>>> + pr_err("smc start failed\n");
>>> + return -EINVAL;
>>> + }
>>> + }
>>> +
>>> + if (!hwmgr->pm_en)
>>> + return 0;
>>> +
>>> + if (!hwmgr->pptable_func ||
>>> + !hwmgr->pptable_func->pptable_init ||
>>> + !hwmgr->hwmgr_func->backend_init) {
>>> + hwmgr->pm_en = false;
>>> + cgs_notify_dpm_enabled(hwmgr->device, false);
>>> + pr_info("dpm not supported \n");
>>> + return 0;
>>> + }
>>>
>>> ret = hwmgr->pptable_func->pptable_init(hwmgr);
>>> if (ret)
>>> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
>>> if (hwmgr->pptable_func->pptable_fini)
>>> hwmgr->pptable_func->pptable_fini(hwmgr);
>>> err:
>>> - pr_err("amdgpu: powerplay initialization failed\n");
>>> return ret;
>>> }
>>>
>>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>>> {
>>> - if (hwmgr == NULL)
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> phm_stop_thermal_controller(hwmgr);
>>> psm_set_boot_states(hwmgr);
>>> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
>>> return psm_fini_power_state_table(hwmgr);
>>> }
>>>
>>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> - return -EINVAL;
>>> + if (!hwmgr || !hwmgr->pm_en)
>>> + return 0;
>>>
>>> phm_disable_smc_firmware_ctf(hwmgr);
>>> ret = psm_set_boot_states(hwmgr);
>>> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
>>> return ret;
>>> }
>>>
>>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>>> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
>>> {
>>> int ret = 0;
>>>
>>> - if (hwmgr == NULL)
>>> + if (!hwmgr)
>>> return -EINVAL;
>>>
>>> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
>>> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
>>> + pr_err("smc start failed\n");
>>> + return -EINVAL;
>>> + }
>>> + }
>>> +
>>> + if (!hwmgr->pm_en)
>>> + return 0;
>>> +
>>> ret = phm_setup_asic(hwmgr);
>>> if (ret)
>>> return ret;
>>> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
>>> if (ret)
>>> return ret;
>>> ret = phm_start_thermal_controller(hwmgr);
>>> - if (ret)
>>> - return ret;
>>> -
>>> ret |= psm_set_performance_states(hwmgr);
>>> if (ret)
>>> return ret;
>>> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> index 17f811d..d6c9a3b 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>>> @@ -782,10 +782,13 @@ struct pp_hwmgr {
>>> };
>>>
>>> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
>>> int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
>>> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
>>> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
>>> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_suspend(struct pp_hwmgr *hwmgr);
>>> +int hwmgr_resume(struct pp_hwmgr *hwmgr);
>>> +
>>> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
>>> enum amd_pp_task task_id,
>>> enum amd_pm_state_type *user_state);
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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lists.freedesktop.org
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
[not found] ` <1521718818-22687-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:10 ` Alex Deucher
@ 2018-03-23 1:49 ` Huang Rui
2018-03-23 2:13 ` Zhu, Rex
1 sibling, 1 reply; 19+ messages in thread
From: Huang Rui @ 2018-03-23 1:49 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Thu, Mar 22, 2018 at 07:40:14PM +0800, Rex Zhu wrote:
> Clean up pp ip functions
>
> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
> 3 files changed, 145 insertions(+), 304 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7e8ad30..5d7d9ec 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -31,24 +31,11 @@
> #include "amdgpu.h"
> #include "hwmgr.h"
>
> -#define PP_DPM_DISABLED 0xCCCC
> -
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> static const struct amd_pm_funcs pp_dpm_funcs;
>
> -static inline int pp_check(struct pp_hwmgr *hwmgr)
> -{
> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
> - return PP_DPM_DISABLED;
> -
> - return 0;
> -}
> -
> static int amd_powerplay_create(struct amdgpu_device *adev)
> {
> struct pp_hwmgr *hwmgr;
> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device *adev)
> }
>
>
> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
> {
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct amdgpu_device *adev)
>
> kfree(hwmgr);
> hwmgr = NULL;
> -
> - return 0;
> }
>
> static int pp_early_init(void *handle)
> @@ -109,18 +94,9 @@ static int pp_sw_init(void *handle)
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_init == NULL)
> - return -EINVAL;
> + ret = hwmgr_sw_init(hwmgr);
>
> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
> -
> - phm_register_irq_handlers(hwmgr);
> -
> - pr_debug("amdgpu: powerplay sw initialized\n");
> - }
> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" : "successfully");
Actually, we don't need to add the prefix like "amdgpu: ", because in pr_*
prints, we already added the powerplay specific prefix.
[ 105.758104] amdgpu: [powerplay] amdgpu: powerplay sw initialized
^^^^^^^
The same with comments with other part of this patch.
Thanks,
Ray
>
> return ret;
> }
> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - }
> + hwmgr_sw_fini(hwmgr);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_fini_bo(adev);
> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_init_bo(adev);
>
> - ret = pp_check(hwmgr);
> + ret = hwmgr_hw_init(hwmgr);
>
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> + if (ret)
> + pr_err("amdgpu: powerplay hw init failed\n");
>
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> - if (ret == PP_DPM_DISABLED)
> - goto exit;
> - ret = hwmgr_hw_init(hwmgr);
> - if (ret)
> - goto exit;
> - }
> return ret;
> -exit:
> - hwmgr->pm_en = 0;
> - cgs_notify_dpm_enabled(hwmgr->device, false);
> - return 0;
> -
> }
>
> static int pp_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_fini(hwmgr);
> + hwmgr_hw_fini(hwmgr);
>
> return 0;
> }
> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret == 0)
> + if (hwmgr && hwmgr->pm_en)
> pp_dpm_dispatch_tasks(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
>
> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -254,38 +199,16 @@ static int pp_suspend(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_suspend(hwmgr);
> - return 0;
> + return hwmgr_suspend(hwmgr);
> }
>
> static int pp_resume(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret;
> -
> - ret = pp_check(hwmgr);
> -
> - if (ret < 0)
> - return ret;
> -
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> -
> - if (ret == PP_DPM_DISABLED)
> - return 0;
>
> - return hwmgr_hw_resume(hwmgr);
> + return hwmgr_resume(hwmgr);
> }
>
> static int pp_set_clockgating_state(void *handle,
> @@ -334,12 +257,9 @@ static int pp_dpm_fw_loading_complete(void *handle)
> static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -389,12 +309,9 @@ static int pp_dpm_force_performance_level(void *handle,
> enum amd_dpm_forced_level level)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (level == hwmgr->dpm_level)
> return 0;
> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> enum amd_dpm_forced_level level;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> level = hwmgr->dpm_level;
> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_sclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -450,13 +361,10 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_mclk == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -471,11 +379,8 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> static void pp_dpm_powergate_vce(void *handle, bool gate)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
> @@ -490,11 +395,8 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
> static void pp_dpm_powergate_uvd(void *handle, bool gate)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
> @@ -512,10 +414,8 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> int ret = 0;
> struct pp_hwmgr *hwmgr = handle;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr_handle_task(hwmgr, task_id, user_state);
> @@ -528,15 +428,9 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> struct pp_power_state *state;
> - int ret = 0;
> enum amd_pm_state_type pm_type;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->current_ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -568,11 +462,8 @@ static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
> static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
> @@ -587,13 +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
> static uint32_t pp_dpm_get_fan_control_mode(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t mode = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -610,10 +498,8 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -630,10 +516,8 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -651,10 +535,8 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
> return -EINVAL;
> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void *handle,
> {
> struct pp_hwmgr *hwmgr = handle;
> int i;
> - int ret = 0;
>
> memset(data, 0, sizeof(*data));
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
> static int pp_dpm_get_pp_table(void *handle, char **table)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> int size = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (!hwmgr->soft_pp_table)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> ret = hwmgr_hw_fini(hwmgr);
> if (ret)
> return ret;
> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> if (!hwmgr->hardcode_pp_table) {
> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -820,10 +682,8 @@ static int pp_dpm_print_clock_levels(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -840,10 +700,8 @@ static int pp_dpm_get_sclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -860,10 +718,8 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -881,10 +737,8 @@ static int pp_dpm_get_mclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -901,10 +755,8 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -922,11 +774,7 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (value == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !value)
> return -EINVAL;
>
> switch (idx) {
> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int idx,
> pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return NULL;
>
> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
> + if (idx < hwmgr->num_vce_state_tables)
> return &hwmgr->vce_states[idx];
> return NULL;
> }
> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle, char *buf)
> {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (!buf || pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en || !buf)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
> @@ -980,12 +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = -EINVAL;
>
> - if (pp_check(hwmgr))
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return ret;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> - return -EINVAL;
> + return ret;
> }
> mutex_lock(&hwmgr->smu_lock);
> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
> @@ -998,7 +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
> {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
> @@ -1016,7 +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
> long workload;
> uint32_t index;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> @@ -1058,10 +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -1082,12 +925,9 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> static int pp_set_power_limit(void *handle, uint32_t limit)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> @@ -1104,20 +944,14 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
> hwmgr->power_limit = limit;
> mutex_unlock(&hwmgr->smu_lock);
> - return ret;
> + return 0;
> }
>
> static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> -
> - if (limit == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!limit)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
>
> mutex_unlock(&hwmgr->smu_lock);
>
> - return ret;
> + return 0;
> }
>
> static int pp_display_configuration_change(void *handle,
> const struct amd_pp_display_configuration *display_config)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> phm_store_dal_configuration_data(hwmgr, display_config);
> @@ -1155,12 +986,7 @@ static int pp_get_display_power_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (output == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!output)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
>
> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (clocks == NULL)
> return -EINVAL;
> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!wm_with_clock_ranges)
> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clock)
> + if (!hwmgr || !hwmgr->pm_en ||!clock)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (clocks == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1348,12 +1149,9 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> static int pp_set_mmhub_powergating_by_smu(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 4298205..96a2d01 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> {
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
> @@ -170,17 +170,51 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
> +{
> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
> + return -EINVAL;
> +
> + phm_register_irq_handlers(hwmgr);
> +
> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
> +}
> +
> +
> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
> +{
> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> +
> + return 0;
> +}
> +
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr || !hwmgr->smumgr_funcs)
> return -EINVAL;
>
> - if (hwmgr->pptable_func == NULL ||
> - hwmgr->pptable_func->pptable_init == NULL ||
> - hwmgr->hwmgr_func->backend_init == NULL)
> - return -EINVAL;
> + if (hwmgr->smumgr_funcs->start_smu) {
> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
> + if (ret) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> + if (!hwmgr->pptable_func ||
> + !hwmgr->pptable_func->pptable_init ||
> + !hwmgr->hwmgr_func->backend_init) {
> + hwmgr->pm_en = false;
> + cgs_notify_dpm_enabled(hwmgr->device, false);
> + pr_info("dpm not supported \n");
> + return 0;
> + }
>
> ret = hwmgr->pptable_func->pptable_init(hwmgr);
> if (ret)
> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> if (hwmgr->pptable_func->pptable_fini)
> hwmgr->pptable_func->pptable_fini(hwmgr);
> err:
> - pr_err("amdgpu: powerplay initialization failed\n");
> return ret;
> }
>
> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> {
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_stop_thermal_controller(hwmgr);
> psm_set_boot_states(hwmgr);
> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> return psm_fini_power_state_table(hwmgr);
> }
>
> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_disable_smc_firmware_ctf(hwmgr);
> ret = psm_set_boot_states(hwmgr);
> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> return ret;
> }
>
> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> ret = phm_setup_asic(hwmgr);
> if (ret)
> return ret;
> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> if (ret)
> return ret;
> ret = phm_start_thermal_controller(hwmgr);
> - if (ret)
> - return ret;
> -
> ret |= psm_set_performance_states(hwmgr);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 17f811d..d6c9a3b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -782,10 +782,13 @@ struct pp_hwmgr {
> };
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr);
> +int hwmgr_resume(struct pp_hwmgr *hwmgr);
> +
> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
2018-03-23 1:49 ` Huang Rui
@ 2018-03-23 2:13 ` Zhu, Rex
0 siblings, 0 replies; 19+ messages in thread
From: Zhu, Rex @ 2018-03-23 2:13 UTC (permalink / raw)
To: Huang, Ray; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Good.
Thanks
Best Regards
Rex
-----Original Message-----
From: Huang Rui [mailto:ray.huang@amd.com]
Sent: Friday, March 23, 2018 9:49 AM
To: Zhu, Rex
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins
On Thu, Mar 22, 2018 at 07:40:14PM +0800, Rex Zhu wrote:
> Clean up pp ip functions
>
> Change-Id: Id06159202edabdfcb19fcc20e1291ce93db56d5d
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 368 ++++++--------------------
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 74 ++++--
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
> 3 files changed, 145 insertions(+), 304 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7e8ad30..5d7d9ec 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -31,24 +31,11 @@
> #include "amdgpu.h"
> #include "hwmgr.h"
>
> -#define PP_DPM_DISABLED 0xCCCC
> -
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
>
> static const struct amd_pm_funcs pp_dpm_funcs;
>
> -static inline int pp_check(struct pp_hwmgr *hwmgr) -{
> - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL)
> - return PP_DPM_DISABLED;
> -
> - return 0;
> -}
> -
> static int amd_powerplay_create(struct amdgpu_device *adev) {
> struct pp_hwmgr *hwmgr;
> @@ -73,7 +60,7 @@ static int amd_powerplay_create(struct amdgpu_device
> *adev) }
>
>
> -static int amd_powerplay_destroy(struct amdgpu_device *adev)
> +static void amd_powerplay_destroy(struct amdgpu_device *adev)
> {
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
>
> @@ -82,8 +69,6 @@ static int amd_powerplay_destroy(struct
> amdgpu_device *adev)
>
> kfree(hwmgr);
> hwmgr = NULL;
> -
> - return 0;
> }
>
> static int pp_early_init(void *handle) @@ -109,18 +94,9 @@ static int
> pp_sw_init(void *handle)
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_init == NULL)
> - return -EINVAL;
> + ret = hwmgr_sw_init(hwmgr);
>
> - ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
> -
> - phm_register_irq_handlers(hwmgr);
> -
> - pr_debug("amdgpu: powerplay sw initialized\n");
> - }
> + pr_debug("amdgpu: powerplay sw init %s\n", ret ? "failed" :
> +"successfully");
Actually, we don't need to add the prefix like "amdgpu: ", because in pr_* prints, we already added the powerplay specific prefix.
[ 105.758104] amdgpu: [powerplay] amdgpu: powerplay sw initialized
^^^^^^^
The same with comments with other part of this patch.
Thanks,
Ray
>
> return ret;
> }
> @@ -129,13 +105,8 @@ static int pp_sw_fini(void *handle) {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->smu_fini != NULL)
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - }
> + hwmgr_sw_fini(hwmgr);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_fini_bo(adev);
> @@ -152,40 +123,20 @@ static int pp_hw_init(void *handle)
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
> amdgpu_ucode_init_bo(adev);
>
> - ret = pp_check(hwmgr);
> + ret = hwmgr_hw_init(hwmgr);
>
> - if (ret >= 0) {
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> + if (ret)
> + pr_err("amdgpu: powerplay hw init failed\n");
>
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> - if (ret == PP_DPM_DISABLED)
> - goto exit;
> - ret = hwmgr_hw_init(hwmgr);
> - if (ret)
> - goto exit;
> - }
> return ret;
> -exit:
> - hwmgr->pm_en = 0;
> - cgs_notify_dpm_enabled(hwmgr->device, false);
> - return 0;
> -
> }
>
> static int pp_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_fini(hwmgr);
> + hwmgr_hw_fini(hwmgr);
>
> return 0;
> }
> @@ -194,11 +145,8 @@ static int pp_late_init(void *handle) {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret == 0)
> + if (hwmgr && hwmgr->pm_en)
> pp_dpm_dispatch_tasks(hwmgr,
> AMD_PP_TASK_COMPLETE_INIT, NULL);
>
> @@ -233,12 +181,9 @@ static int pp_set_powergating_state(void *handle,
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -254,38 +199,16
> @@ static int pp_suspend(void *handle) {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret == 0)
> - hwmgr_hw_suspend(hwmgr);
> - return 0;
> + return hwmgr_suspend(hwmgr);
> }
>
> static int pp_resume(void *handle)
> {
> struct amdgpu_device *adev = handle;
> struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> - int ret;
> -
> - ret = pp_check(hwmgr);
> -
> - if (ret < 0)
> - return ret;
> -
> - if (hwmgr->smumgr_funcs->start_smu == NULL)
> - return -EINVAL;
> -
> - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> - pr_err("smc start failed\n");
> - hwmgr->smumgr_funcs->smu_fini(hwmgr);
> - return -EINVAL;
> - }
> -
> - if (ret == PP_DPM_DISABLED)
> - return 0;
>
> - return hwmgr_hw_resume(hwmgr);
> + return hwmgr_resume(hwmgr);
> }
>
> static int pp_set_clockgating_state(void *handle, @@ -334,12 +257,9
> @@ static int pp_dpm_fw_loading_complete(void *handle) static int
> pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -389,12 +309,9
> @@ static int pp_dpm_force_performance_level(void *handle,
> enum amd_dpm_forced_level level) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (level == hwmgr->dpm_level)
> return 0;
> @@ -412,13 +329,10 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
> void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> enum amd_dpm_forced_level level;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> level = hwmgr->dpm_level;
> @@ -429,13 +343,10 @@ static enum amd_dpm_forced_level
> pp_dpm_get_performance_level( static uint32_t pp_dpm_get_sclk(void
> *handle, bool low) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_sclk == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -450,13 +361,10
> @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low) static
> uint32_t pp_dpm_get_mclk(void *handle, bool low) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t clk = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_mclk == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -471,11 +379,8
> @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low) static
> void pp_dpm_powergate_vce(void *handle, bool gate) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_vce == NULL) { @@ -490,11 +395,8 @@
> static void pp_dpm_powergate_vce(void *handle, bool gate) static void
> pp_dpm_powergate_uvd(void *handle, bool gate) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->powergate_uvd == NULL) { @@ -512,10 +414,8 @@
> static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
> int ret = 0;
> struct pp_hwmgr *hwmgr = handle;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> ret = hwmgr_handle_task(hwmgr, task_id, user_state); @@ -528,15
> +428,9 @@ static enum amd_pm_state_type
> pp_dpm_get_current_power_state(void *handle) {
> struct pp_hwmgr *hwmgr = handle;
> struct pp_power_state *state;
> - int ret = 0;
> enum amd_pm_state_type pm_type;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->current_ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -568,11 +462,8 @@ static enum amd_pm_state_type
> pp_dpm_get_current_power_state(void *handle) static void
> pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return;
>
> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { @@ -587,13
> +478,10 @@ static void pp_dpm_set_fan_control_mode(void *handle,
> uint32_t mode) static uint32_t pp_dpm_get_fan_control_mode(void
> *handle) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> uint32_t mode = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -610,10 +498,8
> @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -630,10 +516,8
> @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -651,10 +535,8
> @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
> return -EINVAL;
> @@ -670,16 +552,10 @@ static int pp_dpm_get_pp_num_states(void
> *handle, {
> struct pp_hwmgr *hwmgr = handle;
> int i;
> - int ret = 0;
>
> memset(data, 0, sizeof(*data));
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (hwmgr->ps == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -713,15 +589,9 @@ static int pp_dpm_get_pp_num_states(void *handle,
> static int pp_dpm_get_pp_table(void *handle, char **table) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> int size = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (!hwmgr->soft_pp_table)
> + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -736,10 +606,6 @@ static int amd_powerplay_reset(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> ret = hwmgr_hw_fini(hwmgr);
> if (ret)
> return ret;
> @@ -756,10 +622,8 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> if (!hwmgr->hardcode_pp_table) {
> @@ -796,10 +660,8 @@ static int pp_dpm_force_clock_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -820,10 +682,8
> @@ static int pp_dpm_print_clock_levels(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -840,10 +700,8
> @@ static int pp_dpm_get_sclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -860,10 +718,8
> @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -881,10 +737,8
> @@ static int pp_dpm_get_mclk_od(void *handle)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -901,10 +755,8
> @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -922,11 +774,7
> @@ static int pp_dpm_read_sensor(void *handle, int idx,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (value == NULL)
> + if (!hwmgr || !hwmgr->pm_en || !value)
> return -EINVAL;
>
> switch (idx) {
> @@ -948,14 +796,11 @@ static int pp_dpm_read_sensor(void *handle, int
> idx, pp_dpm_get_vce_clock_state(void *handle, unsigned idx) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> + if (!hwmgr || !hwmgr->pm_en)
> return NULL;
>
> - if (hwmgr && idx < hwmgr->num_vce_state_tables)
> + if (idx < hwmgr->num_vce_state_tables)
> return &hwmgr->vce_states[idx];
> return NULL;
> }
> @@ -964,7 +809,7 @@ static int pp_get_power_profile_mode(void *handle,
> char *buf) {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (!buf || pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en || !buf)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) { @@ -980,12
> +825,12 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> struct pp_hwmgr *hwmgr = handle;
> int ret = -EINVAL;
>
> - if (pp_check(hwmgr))
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return ret;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
> pr_info("%s was not implemented.\n", __func__);
> - return -EINVAL;
> + return ret;
> }
> mutex_lock(&hwmgr->smu_lock);
> if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) @@ -998,7
> +843,7 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t
> type, long *input, uint3 {
> struct pp_hwmgr *hwmgr = handle;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { @@ -1016,7
> +861,7 @@ static int pp_dpm_switch_power_profile(void *handle,
> long workload;
> uint32_t index;
>
> - if (pp_check(hwmgr))
> + if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { @@ -1058,10
> +903,8 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -1082,12 +925,9
> @@ static int pp_dpm_notify_smu_memory_info(void *handle, static int
> pp_set_power_limit(void *handle, uint32_t limit) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_power_limit == NULL) {
> pr_info("%s was not implemented.\n", __func__); @@ -1104,20 +944,14
> @@ static int pp_set_power_limit(void *handle, uint32_t limit)
> hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
> hwmgr->power_limit = limit;
> mutex_unlock(&hwmgr->smu_lock);
> - return ret;
> + return 0;
> }
>
> static int pp_get_power_limit(void *handle, uint32_t *limit, bool
> default_limit) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> -
> - if (limit == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!limit)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1129,19 +963,16 @@ static int pp_get_power_limit(void *handle,
> uint32_t *limit, bool default_limit)
>
> mutex_unlock(&hwmgr->smu_lock);
>
> - return ret;
> + return 0;
> }
>
> static int pp_display_configuration_change(void *handle,
> const struct amd_pp_display_configuration *display_config) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> phm_store_dal_configuration_data(hwmgr, display_config); @@ -1155,12
> +986,7 @@ static int pp_get_display_power_level(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (output == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!output)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1177,10 +1003,8 @@ static int pp_get_current_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
>
> @@ -1225,10 +1049,8 @@ static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struc
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (clocks == NULL)
> return -EINVAL;
> @@ -1246,11 +1068,7 @@ static int pp_get_clock_by_type_with_latency(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1266,11 +1084,7 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clocks)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1287,11 +1101,7 @@ static int pp_set_watermarks_for_clocks_ranges(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!wm_with_clock_ranges)
> + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1308,11 +1118,7 @@ static int pp_display_clock_voltage_request(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> - if (ret)
> - return ret;
> -
> - if (!clock)
> + if (!hwmgr || !hwmgr->pm_en ||!clock)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1328,12 +1134,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - ret = pp_check(hwmgr);
> -
> - if (ret)
> - return ret;
> -
> - if (clocks == NULL)
> + if (!hwmgr || !hwmgr->pm_en ||!clocks)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> @@ -1348,12 +1149,9 @@ static int
> pp_get_display_mode_validation_clocks(void *handle, static int
> pp_set_mmhub_powergating_by_smu(void *handle) {
> struct pp_hwmgr *hwmgr = handle;
> - int ret = 0;
> -
> - ret = pp_check(hwmgr);
>
> - if (ret)
> - return ret;
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
> pr_info("%s was not implemented.\n", __func__); diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 4298205..96a2d01 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -76,7 +76,7 @@ static void hwmgr_init_workload_prority(struct
> pp_hwmgr *hwmgr)
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr) {
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; @@ -170,17 +170,51 @@
> int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr) {
> + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
> + return -EINVAL;
> +
> + phm_register_irq_handlers(hwmgr);
> +
> + return hwmgr->smumgr_funcs->smu_init(hwmgr);
> +}
> +
> +
> +int hwmgr_sw_fini(struct pp_hwmgr *hwmgr) {
> + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
> + hwmgr->smumgr_funcs->smu_fini(hwmgr);
> +
> + return 0;
> +}
> +
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr) {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr || !hwmgr->smumgr_funcs)
> return -EINVAL;
>
> - if (hwmgr->pptable_func == NULL ||
> - hwmgr->pptable_func->pptable_init == NULL ||
> - hwmgr->hwmgr_func->backend_init == NULL)
> - return -EINVAL;
> + if (hwmgr->smumgr_funcs->start_smu) {
> + ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
> + if (ret) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> + if (!hwmgr->pptable_func ||
> + !hwmgr->pptable_func->pptable_init ||
> + !hwmgr->hwmgr_func->backend_init) {
> + hwmgr->pm_en = false;
> + cgs_notify_dpm_enabled(hwmgr->device, false);
> + pr_info("dpm not supported \n");
> + return 0;
> + }
>
> ret = hwmgr->pptable_func->pptable_init(hwmgr);
> if (ret)
> @@ -214,14 +248,13 @@ int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
> if (hwmgr->pptable_func->pptable_fini)
> hwmgr->pptable_func->pptable_fini(hwmgr);
> err:
> - pr_err("amdgpu: powerplay initialization failed\n");
> return ret;
> }
>
> int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) {
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_stop_thermal_controller(hwmgr);
> psm_set_boot_states(hwmgr);
> @@ -236,12 +269,12 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
> return psm_fini_power_state_table(hwmgr);
> }
>
> -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> - return -EINVAL;
> + if (!hwmgr || !hwmgr->pm_en)
> + return 0;
>
> phm_disable_smc_firmware_ctf(hwmgr);
> ret = psm_set_boot_states(hwmgr);
> @@ -255,13 +288,23 @@ int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr)
> return ret;
> }
>
> -int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> +int hwmgr_resume(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - if (hwmgr == NULL)
> + if (!hwmgr)
> return -EINVAL;
>
> + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
> + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
> + pr_err("smc start failed\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!hwmgr->pm_en)
> + return 0;
> +
> ret = phm_setup_asic(hwmgr);
> if (ret)
> return ret;
> @@ -270,9 +313,6 @@ int hwmgr_hw_resume(struct pp_hwmgr *hwmgr)
> if (ret)
> return ret;
> ret = phm_start_thermal_controller(hwmgr);
> - if (ret)
> - return ret;
> -
> ret |= psm_set_performance_states(hwmgr);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 17f811d..d6c9a3b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -782,10 +782,13 @@ struct pp_hwmgr { };
>
> int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> +int hwmgr_sw_init(struct pp_hwmgr *hwmgr); int hwmgr_sw_fini(struct
> +pp_hwmgr *hwmgr);
> int hwmgr_hw_init(struct pp_hwmgr *hwmgr); int hwmgr_hw_fini(struct
> pp_hwmgr *hwmgr); -int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr); -int
> hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
> +int hwmgr_suspend(struct pp_hwmgr *hwmgr); int hwmgr_resume(struct
> +pp_hwmgr *hwmgr);
> +
> int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
> enum amd_pm_state_type *user_state);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2018-03-23 2:13 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-22 11:40 [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h Rex Zhu
[not found] ` <1521718818-22687-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 11:40 ` [PATCH 2/6] drm/amd/pp: Add hwmgr_sw_init/fini functioins Rex Zhu
[not found] ` <1521718818-22687-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:10 ` Alex Deucher
[not found] ` <CADnq5_PsnzfqnsHXsjBY36TaT85d6hVOWpgL-04coK8gcvOyGA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-03-22 13:13 ` Alex Deucher
[not found] ` <CADnq5_N9uegS=tM+=OEeL+kYy2xhYpBLisjfawQgwqFuLTpwkA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-03-22 13:13 ` Alex Deucher
[not found] ` <CADnq5_NbKvyAEqkpGsNGUFBQkVrELctS2_rkRR+YHJMDfSajEg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-03-22 14:49 ` Zhu, Rex
2018-03-23 1:49 ` Huang Rui
2018-03-23 2:13 ` Zhu, Rex
2018-03-22 11:40 ` [PATCH 3/6] drm/amd/pp: Lock powerplay when reset pp table Rex Zhu
[not found] ` <1521718818-22687-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:17 ` Alex Deucher
[not found] ` <CADnq5_PoA0JtqbsepaX0D0RMxTwDi89Uw9DHmvL7tzXduk_EaA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-03-22 13:44 ` Zhu, Rex
[not found] ` <CY4PR12MB16878FF235D78E9C0A3A722BFBA90-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-03-22 13:47 ` Alex Deucher
2018-03-22 11:40 ` [PATCH 4/6] drm/amd/pp: Save vf state in pp context Rex Zhu
[not found] ` <1521718818-22687-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:21 ` Alex Deucher
2018-03-22 11:40 ` [PATCH 5/6] drm/amd/pp: Use release_firmware function directly in powerplay Rex Zhu
[not found] ` <1521718818-22687-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:23 ` Alex Deucher
2018-03-22 11:40 ` [PATCH 6/6] drm/amd/pp: Delete some cgs functions Rex Zhu
[not found] ` <1521718818-22687-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-03-22 13:24 ` Alex Deucher
2018-03-22 13:10 ` [PATCH 1/6] drm/amd/pp: clean header file hwmgr.h Alex Deucher
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