* [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
@ 2018-04-29 20:39 Abhay Kumar
2018-04-30 10:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (14 more replies)
0 siblings, 15 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-04-29 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
drivers/gpu/drm/i915/intel_display.c | 7 +++++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
5 files changed, 63 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 193176bcddf5..34c31ef0761e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1708,6 +1708,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..f001fcf05d3a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
I915_WRITE(aud_config, tmp);
}
+
/**
* intel_audio_codec_enable - Enable the audio codec for HD audio
* @encoder: encoder on which to enable audio
@@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+ * Protects dev_priv->cdclk.force_min_cdclk
+ * Need to lock this here in case we have no active pipes
+ * and thus wouldn't lock it during the commit otherwise.
+ */
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
@@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
if (!IS_GEN9(dev_priv))
return;
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
+
i915_audio_component_get_power(kdev);
/*
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ebca83a44d9b..4086730018f9 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
}
/*
- * According to BSpec, "The CD clock frequency must be at least twice
- * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
- *
- * FIXME: Check the actual, not default, BCLK being used.
- *
- * FIXME: This does not depend on ->has_audio because the higher CDCLK
- * is required for audio probe, also when there are no audio capable
- * displays connected at probe time. This leads to unnecessarily high
- * CDCLK when audio is not required.
- *
- * FIXME: This limit is only applied when there are displays connected
- * at probe time. If we probe without displays, we'll still end up using
- * the platform minimum CDCLK, failing audio probe.
- */
- if (INTEL_GEN(dev_priv) >= 9)
- min_cdclk = max(2 * 96000, min_cdclk);
-
- /*
* On Valleyview some DSI panels lose (v|h)sync when the clock is lower
* than 320000KHz.
*/
@@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
intel_state->min_cdclk[i] = min_cdclk;
}
- min_cdclk = 0;
+ min_cdclk = intel_state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
@@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
- cdclk = vlv_calc_cdclk(dev_priv, 0);
+ cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = bdw_calc_cdclk(0);
+ cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = skl_calc_cdclk(0, vco);
+ cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
@@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
- cdclk = glk_calc_cdclk(0);
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = glk_de_pll_vco(dev_priv, cdclk);
} else {
- cdclk = bxt_calc_cdclk(0);
+ cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
@@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = cnl_calc_cdclk(0);
+ cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
@@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
if (!intel_state->active_crtcs) {
- cdclk = icl_calc_cdclk(0, ref);
+ cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84ce66be88f2..7c369e15f193 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return -EINVAL;
}
+ /* keep the current setting */
+ if (!intel_state->modeset)
+ intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
intel_state->modeset = true;
intel_state->active_crtcs = dev_priv->active_crtcs;
intel_state->cdclk.logical = dev_priv->cdclk.logical;
@@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *crtc_state;
int ret, i;
- bool any_ms = false;
+ bool any_ms = intel_state->modeset;
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
+ dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 11a1932cde6e..79928505d0d0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -461,6 +461,7 @@ struct intel_atomic_state {
* state only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
+ int force_min_cdclk;
} cdclk;
bool dpll_set, modeset;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
@ 2018-04-30 10:27 ` Patchwork
2018-04-30 10:28 ` ✗ Fi.CI.SPARSE: " Patchwork
` (13 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-04-30 10:27 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b8c009b51c95 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-:38: CHECK:LINE_SPACING: Please don't use multiple blank lines
#38: FILE: drivers/gpu/drm/i915/intel_audio.c:597:
+
-:47: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#47: FILE: drivers/gpu/drm/i915/intel_audio.c:718:
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
total: 0 errors, 0 warnings, 2 checks, 188 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-04-30 10:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-04-30 10:28 ` Patchwork
2018-04-30 10:43 ` ✓ Fi.CI.BAT: success " Patchwork
` (12 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-04-30 10:28 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-O:drivers/gpu/drm/i915/intel_cdclk.c:2159:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2200:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2200:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2182:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2182:29: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3660:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3662:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-04-30 10:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-04-30 10:28 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-04-30 10:43 ` Patchwork
2018-04-30 13:01 ` ✗ Fi.CI.IGT: failure " Patchwork
` (11 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-04-30 10:43 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4112 -> Patchwork_8838 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8838 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8838, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42459/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8838:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_8838 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-skl-6770hq: PASS -> FAIL (fdo#103481)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-ivb-3520m: PASS -> DMESG-WARN (fdo#106084) +1
==== Possible fixes ====
igt@gem_mmap_gtt@basic-small-bo-tiledx:
fi-gdg-551: FAIL (fdo#102575) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-ivb-3520m: DMESG-WARN (fdo#106084) -> PASS
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084
== Participating hosts (39 -> 36) ==
Missing (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4112 -> Patchwork_8838
CI_DRM_4112: 423a00794c9d9610a71d8a02cd3bc17c6fe5fae1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4452: 29ae12bd764e3b1876356e7628a32192b4ec9066 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8838: b8c009b51c953f557d7fab5154dbc743dcbece42 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4452: 04a2952c5b3782eb03cb136bb16d89daaf243f14 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
b8c009b51c95 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8838/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (2 preceding siblings ...)
2018-04-30 10:43 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-30 13:01 ` Patchwork
2018-04-30 18:22 ` [PATCH] " Du,Wenkai
` (10 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-04-30 13:01 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
URL : https://patchwork.freedesktop.org/series/42459/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4112_full -> Patchwork_8838_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_8838_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8838_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42459/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8838_full:
=== IGT changes ===
==== Possible regressions ====
igt@drv_module_reload@basic-reload:
shard-glk: PASS -> INCOMPLETE
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-kbl: PASS -> SKIP
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_8838_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#106087)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-kbl: PASS -> FAIL (fdo#103060)
shard-glk: PASS -> FAIL (fdo#103060)
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-glk: PASS -> FAIL (fdo#100368)
==== Possible fixes ====
igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
shard-hsw: FAIL (fdo#104873) -> PASS
igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
shard-hsw: FAIL (fdo#103928) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: FAIL (fdo#105707) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS +2
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
shard-kbl: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (9 -> 8) ==
Missing (1): shard-glkb
== Build changes ==
* Linux: CI_DRM_4112 -> Patchwork_8838
CI_DRM_4112: 423a00794c9d9610a71d8a02cd3bc17c6fe5fae1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4452: 29ae12bd764e3b1876356e7628a32192b4ec9066 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8838: b8c009b51c953f557d7fab5154dbc743dcbece42 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4452: 04a2952c5b3782eb03cb136bb16d89daaf243f14 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8838/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (3 preceding siblings ...)
2018-04-30 13:01 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-04-30 18:22 ` Du,Wenkai
2018-05-01 9:15 ` Saarinen, Jani
2018-05-02 15:12 ` Ville Syrjälä
` (9 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Du,Wenkai @ 2018-04-30 18:22 UTC (permalink / raw)
To: Abhay Kumar, intel-gfx; +Cc: Nikula, Jani
On 4/29/2018 1:39 PM, Abhay Kumar wrote:
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Tested-by: Wenkai Du <wenkai.du@intel.com>
Thanks,
Wenkai
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 63 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 193176bcddf5..34c31ef0761e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..f001fcf05d3a 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
> I915_WRITE(aud_config, tmp);
> }
>
> +
> /**
> * intel_audio_codec_enable - Enable the audio codec for HD audio
> * @encoder: encoder on which to enable audio
> @@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(&ctx, 0);
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx = &ctx;
> +
> +retry:
> + to_intel_atomic_state(state)->modeset = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> static void i915_audio_component_get_power(struct device *kdev)
> {
> intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> @@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
> if (!IS_GEN9(dev_priv))
> return;
>
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, true);
> +
> i915_audio_component_get_power(kdev);
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ebca83a44d9b..4086730018f9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> }
>
> /*
> - * According to BSpec, "The CD clock frequency must be at least twice
> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> - *
> - * FIXME: Check the actual, not default, BCLK being used.
> - *
> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> - * is required for audio probe, also when there are no audio capable
> - * displays connected at probe time. This leads to unnecessarily high
> - * CDCLK when audio is not required.
> - *
> - * FIXME: This limit is only applied when there are displays connected
> - * at probe time. If we probe without displays, we'll still end up using
> - * the platform minimum CDCLK, failing audio probe.
> - */
> - if (INTEL_GEN(dev_priv) >= 9)
> - min_cdclk = max(2 * 96000, min_cdclk);
> -
> - /*
> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> * than 320000KHz.
> */
> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> intel_state->min_cdclk[i] = min_cdclk;
> }
>
> - min_cdclk = 0;
> + min_cdclk = intel_state->cdclk.force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>
> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> bdw_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = bdw_calc_cdclk(0);
> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> skl_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = skl_calc_cdclk(0, vco);
> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> @@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(0);
> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = glk_de_pll_vco(dev_priv, cdclk);
> } else {
> - cdclk = bxt_calc_cdclk(0);
> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = bxt_de_pll_vco(dev_priv, cdclk);
> }
>
> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> - cdclk = cnl_calc_cdclk(0);
> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> @@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> intel_state->cdclk.logical.cdclk = cdclk;
>
> if (!intel_state->active_crtcs) {
> - cdclk = icl_calc_cdclk(0, ref);
> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 84ce66be88f2..7c369e15f193 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> return -EINVAL;
> }
>
> + /* keep the current setting */
> + if (!intel_state->modeset)
> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
> +
> intel_state->modeset = true;
> intel_state->active_crtcs = dev_priv->active_crtcs;
> intel_state->cdclk.logical = dev_priv->cdclk.logical;
> @@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
> struct drm_crtc *crtc;
> struct drm_crtc_state *old_crtc_state, *crtc_state;
> int ret, i;
> - bool any_ms = false;
> + bool any_ms = intel_state->modeset;
>
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> @@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> dev_priv->active_crtcs = intel_state->active_crtcs;
> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
> }
>
> drm_atomic_state_get(state);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 11a1932cde6e..79928505d0d0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -461,6 +461,7 @@ struct intel_atomic_state {
> * state only when all crtc's are DPMS off.
> */
> struct intel_cdclk_state actual;
> + int force_min_cdclk;
> } cdclk;
>
> bool dpll_set, modeset;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-30 18:22 ` [PATCH] " Du,Wenkai
@ 2018-05-01 9:15 ` Saarinen, Jani
2018-05-01 23:42 ` Kumar, Abhay
0 siblings, 1 reply; 36+ messages in thread
From: Saarinen, Jani @ 2018-05-01 9:15 UTC (permalink / raw)
To: Du, Wenkai, Kumar, Abhay, intel-gfx; +Cc: Nikula, Jani
HI,
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Du,Wenkai
> Sent: maanantai 30. huhtikuuta 2018 21.23
> To: Kumar, Abhay <abhay.kumar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when
> audio power is enabled
>
>
>
> On 4/29/2018 1:39 PM, Abhay Kumar wrote:
> > CDCLK has to be at least twice the BLCK regardless of audio. Audio
> > driver has to probe using this hook and increase the clock even in
> > absence of any display.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> Tested-by: Wenkai Du <wenkai.du@intel.com>
Please note that failed on CI/GLK: https://patchwork.freedesktop.org/series/42459/
==== Possible regressions ====
igt@drv_module_reload@basic-reload:
shard-glk: PASS -> INCOMPLETE
Br,
Jani
>
> Thanks,
> Wenkai
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_audio.c | 46
> ++++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
> > drivers/gpu/drm/i915/intel_display.c | 7 +++++-
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 5 files changed, 63 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 193176bcddf5..34c31ef0761e
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1708,6 +1708,8 @@ struct drm_i915_private {
> > struct intel_cdclk_state actual;
> > /* The current hardware cdclk state */
> > struct intel_cdclk_state hw;
> > +
> > + int force_min_cdclk;
> > } cdclk;
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 3ea566f99450..f001fcf05d3a 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct
> intel_encoder *encoder,
> > I915_WRITE(aud_config, tmp);
> > }
> >
> > +
> > /**
> > * intel_audio_codec_enable - Enable the audio codec for HD audio
> > * @encoder: encoder on which to enable audio @@ -713,6 +714,48 @@
> > void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> > + bool enable) {
> > + struct drm_modeset_acquire_ctx ctx;
> > + struct drm_atomic_state *state;
> > + int ret;
> > +
> > + drm_modeset_acquire_init(&ctx, 0);
> > + state = drm_atomic_state_alloc(&dev_priv->drm);
> > + if (WARN_ON(!state))
> > + return;
> > +
> > + state->acquire_ctx = &ctx;
> > +
> > +retry:
> > + to_intel_atomic_state(state)->modeset = true;
> > + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> > + enable ? 2 * 96000 : 0;
> > +
> > + /*
> > + * Protects dev_priv->cdclk.force_min_cdclk
> > + * Need to lock this here in case we have no active pipes
> > + * and thus wouldn't lock it during the commit otherwise.
> > + */
> > + ret = drm_modeset_lock(&dev_priv-
> >drm.mode_config.connection_mutex, &ctx);
> > + if (!ret)
> > + ret = drm_atomic_commit(state);
> > +
> > + if (ret == -EDEADLK) {
> > + drm_atomic_state_clear(state);
> > + drm_modeset_backoff(&ctx);
> > + goto retry;
> > + }
> > +
> > + WARN_ON(ret);
> > +
> > + drm_atomic_state_put(state);
> > +
> > + drm_modeset_drop_locks(&ctx);
> > + drm_modeset_acquire_fini(&ctx); }
> > +
> > static void i915_audio_component_get_power(struct device *kdev)
> > {
> > intel_display_power_get(kdev_to_i915(kdev),
> > POWER_DOMAIN_AUDIO); @@ -732,6 +775,9 @@ static void
> i915_audio_component_codec_wake_override(struct device *kdev,
> > if (!IS_GEN9(dev_priv))
> > return;
> >
> > + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> > + glk_force_audio_cdclk(dev_priv, true);
> > +
> > i915_audio_component_get_power(kdev);
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index ebca83a44d9b..4086730018f9 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> > }
> >
> > /*
> > - * According to BSpec, "The CD clock frequency must be at least twice
> > - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > - *
> > - * FIXME: Check the actual, not default, BCLK being used.
> > - *
> > - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> > - * is required for audio probe, also when there are no audio capable
> > - * displays connected at probe time. This leads to unnecessarily high
> > - * CDCLK when audio is not required.
> > - *
> > - * FIXME: This limit is only applied when there are displays connected
> > - * at probe time. If we probe without displays, we'll still end up using
> > - * the platform minimum CDCLK, failing audio probe.
> > - */
> > - if (INTEL_GEN(dev_priv) >= 9)
> > - min_cdclk = max(2 * 96000, min_cdclk);
> > -
> > - /*
> > * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> > * than 320000KHz.
> > */
> > @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct
> drm_atomic_state *state)
> > intel_state->min_cdclk[i] = min_cdclk;
> > }
> >
> > - min_cdclk = 0;
> > + min_cdclk = intel_state->cdclk.force_min_cdclk;
> > for_each_pipe(dev_priv, pipe)
> > min_cdclk = max(intel_state->min_cdclk[pipe],
> > min_cdclk);
> >
> > @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct
> drm_atomic_state *state)
> > vlv_calc_voltage_level(dev_priv, cdclk);
> >
> > if (!intel_state->active_crtcs) {
> > - cdclk = vlv_calc_cdclk(dev_priv, 0);
> > + cdclk = vlv_calc_cdclk(dev_priv,
> > + intel_state->cdclk.force_min_cdclk);
> >
> > intel_state->cdclk.actual.cdclk = cdclk;
> > intel_state->cdclk.actual.voltage_level = @@ -2289,7
> > +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state
> *state)
> > bdw_calc_voltage_level(cdclk);
> >
> > if (!intel_state->active_crtcs) {
> > - cdclk = bdw_calc_cdclk(0);
> > + cdclk =
> > + bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> >
> > intel_state->cdclk.actual.cdclk = cdclk;
> > intel_state->cdclk.actual.voltage_level = @@ -2328,7
> > +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state
> *state)
> > skl_calc_voltage_level(cdclk);
> >
> > if (!intel_state->active_crtcs) {
> > - cdclk = skl_calc_cdclk(0, vco);
> > + cdclk =
> > + skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
> >
> > intel_state->cdclk.actual.vco = vco;
> > intel_state->cdclk.actual.cdclk = cdclk; @@ -2367,10
> > +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state
> > *state)
> >
> > if (!intel_state->active_crtcs) {
> > if (IS_GEMINILAKE(dev_priv)) {
> > - cdclk = glk_calc_cdclk(0);
> > + cdclk =
> > + glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> > vco = glk_de_pll_vco(dev_priv, cdclk);
> > } else {
> > - cdclk = bxt_calc_cdclk(0);
> > + cdclk =
> > + bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> > vco = bxt_de_pll_vco(dev_priv, cdclk);
> > }
> >
> > @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct
> drm_atomic_state *state)
> > cnl_compute_min_voltage_level(intel_state));
> >
> > if (!intel_state->active_crtcs) {
> > - cdclk = cnl_calc_cdclk(0);
> > + cdclk =
> > + cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> > vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >
> > intel_state->cdclk.actual.vco = vco; @@ -2439,7
> > +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state
> *state)
> > intel_state->cdclk.logical.cdclk = cdclk;
> >
> > if (!intel_state->active_crtcs) {
> > - cdclk = icl_calc_cdclk(0, ref);
> > + cdclk =
> > + icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> > vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> >
> > intel_state->cdclk.actual.vco = vco; diff --git
> > a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 84ce66be88f2..7c369e15f193 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct
> drm_atomic_state *state)
> > return -EINVAL;
> > }
> >
> > + /* keep the current setting */
> > + if (!intel_state->modeset)
> > + intel_state->cdclk.force_min_cdclk =
> > + dev_priv->cdclk.force_min_cdclk;
> > +
> > intel_state->modeset = true;
> > intel_state->active_crtcs = dev_priv->active_crtcs;
> > intel_state->cdclk.logical = dev_priv->cdclk.logical; @@
> > -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
> > struct drm_crtc *crtc;
> > struct drm_crtc_state *old_crtc_state, *crtc_state;
> > int ret, i;
> > - bool any_ms = false;
> > + bool any_ms = intel_state->modeset;
> >
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, @@
> > -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device
> *dev,
> > dev_priv->active_crtcs = intel_state->active_crtcs;
> > dev_priv->cdclk.logical = intel_state->cdclk.logical;
> > dev_priv->cdclk.actual = intel_state->cdclk.actual;
> > + dev_priv->cdclk.force_min_cdclk =
> > + intel_state->cdclk.force_min_cdclk;
> > }
> >
> > drm_atomic_state_get(state);
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 11a1932cde6e..79928505d0d0 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -461,6 +461,7 @@ struct intel_atomic_state {
> > * state only when all crtc's are DPMS off.
> > */
> > struct intel_cdclk_state actual;
> > + int force_min_cdclk;
> > } cdclk;
> >
> > bool dpll_set, modeset;
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-01 9:15 ` Saarinen, Jani
@ 2018-05-01 23:42 ` Kumar, Abhay
2018-05-01 23:47 ` Kumar, Abhay
0 siblings, 1 reply; 36+ messages in thread
From: Kumar, Abhay @ 2018-05-01 23:42 UTC (permalink / raw)
To: Saarinen, Jani, Du, Wenkai, intel-gfx; +Cc: Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 13606 bytes --]
On 5/1/2018 2:15 AM, Saarinen, Jani wrote:
> HI,
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>> Du,Wenkai
>> Sent: maanantai 30. huhtikuuta 2018 21.23
>> To: Kumar, Abhay <abhay.kumar@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when
>> audio power is enabled
>>
>>
>>
>> On 4/29/2018 1:39 PM, Abhay Kumar wrote:
>>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>>> driver has to probe using this hook and increase the clock even in
>>> absence of any display.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>> Tested-by: Wenkai Du <wenkai.du@intel.com>
> Please note that failed on CI/GLK: https://patchwork.freedesktop.org/series/42459/
> ==== Possible regressions ====
> igt@drv_module_reload@basic-reload:
> shard-glk: PASS -> INCOMPLETE
>
> Br,
> Jani
Hi Jani,
Saw panic
@https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8838/shard-glk8/pstore11-1525091313_Panic_3.log
and was trying to reproduce this on my end with IGT but it passed for
me and never failed with DINQ, drm-tip both.
with or without external monitor connected it never fails.
ocalhost /usr/libexec/intel-gpu-tools # ./drv_module_reload
IGT-Version: 1.20-NOT-GIT (x86_64) (Linux:
4.17.0-rc3-g844dd95837ab-dirty x86_64)
Subtest basic-reload: SUCCESS (0.212s)
Reloading i915 with disable_display=1
Subtest basic-no-display: SUCCESS (0.054s)
Reloading i915 with inject_load_failure=0
Reloading i915 with inject_load_failure=1
Reloading i915 with inject_load_failure=2
Reloading i915 with inject_load_failure=3
Subtest basic-reload-inject: SUCCESS (0.329s)
localhost /usr/libexec/intel-gpu-tools # uname -r
4.17.0-rc3-g844dd95837ab-dirty
localhost /usr/libexec/intel-gpu-tools # aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: PCH [HDA Intel PCH], device 3: HDMI 0 [HDMI 0]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: PCH [HDA Intel PCH], device 7: HDMI 1 [HDMI 1]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: PCH [HDA Intel PCH], device 8: HDMI 2 [HDMI 2]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: PCH [HDA Intel PCH], device 9: HDMI 3 [HDMI 3]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: PCH [HDA Intel PCH], device 10: HDMI 4 [HDMI 4]
Subdevices: 1/1
Subdevice #0: subdevice #0
localhost /usr/libexec/intel-gpu-tools #
Regards,
Abhay
>> Thanks,
>> Wenkai
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>>> drivers/gpu/drm/i915/intel_audio.c | 46
>> ++++++++++++++++++++++++++++++++++++
>>> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
>>> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
>>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>>> 5 files changed, 63 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h index 193176bcddf5..34c31ef0761e
>>> 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
>>> struct intel_cdclk_state actual;
>>> /* The current hardware cdclk state */
>>> struct intel_cdclk_state hw;
>>> +
>>> + int force_min_cdclk;
>>> } cdclk;
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/i915/intel_audio.c
>>> b/drivers/gpu/drm/i915/intel_audio.c
>>> index 3ea566f99450..f001fcf05d3a 100644
>>> --- a/drivers/gpu/drm/i915/intel_audio.c
>>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>>> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct
>> intel_encoder *encoder,
>>> I915_WRITE(aud_config, tmp);
>>> }
>>>
>>> +
>>> /**
>>> * intel_audio_codec_enable - Enable the audio codec for HD audio
>>> * @encoder: encoder on which to enable audio @@ -713,6 +714,48 @@
>>> void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>>> }
>>> }
>>>
>>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>>> + bool enable) {
>>> + struct drm_modeset_acquire_ctx ctx;
>>> + struct drm_atomic_state *state;
>>> + int ret;
>>> +
>>> + drm_modeset_acquire_init(&ctx, 0);
>>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>>> + if (WARN_ON(!state))
>>> + return;
>>> +
>>> + state->acquire_ctx = &ctx;
>>> +
>>> +retry:
>>> + to_intel_atomic_state(state)->modeset = true;
>>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>>> + enable ? 2 * 96000 : 0;
>>> +
>>> + /*
>>> + * Protects dev_priv->cdclk.force_min_cdclk
>>> + * Need to lock this here in case we have no active pipes
>>> + * and thus wouldn't lock it during the commit otherwise.
>>> + */
>>> + ret = drm_modeset_lock(&dev_priv-
>>> drm.mode_config.connection_mutex, &ctx);
>>> + if (!ret)
>>> + ret = drm_atomic_commit(state);
>>> +
>>> + if (ret == -EDEADLK) {
>>> + drm_atomic_state_clear(state);
>>> + drm_modeset_backoff(&ctx);
>>> + goto retry;
>>> + }
>>> +
>>> + WARN_ON(ret);
>>> +
>>> + drm_atomic_state_put(state);
>>> +
>>> + drm_modeset_drop_locks(&ctx);
>>> + drm_modeset_acquire_fini(&ctx); }
>>> +
>>> static void i915_audio_component_get_power(struct device *kdev)
>>> {
>>> intel_display_power_get(kdev_to_i915(kdev),
>>> POWER_DOMAIN_AUDIO); @@ -732,6 +775,9 @@ static void
>> i915_audio_component_codec_wake_override(struct device *kdev,
>>> if (!IS_GEN9(dev_priv))
>>> return;
>>>
>>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>> + glk_force_audio_cdclk(dev_priv, true);
>>> +
>>> i915_audio_component_get_power(kdev);
>>>
>>> /*
>>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>>> b/drivers/gpu/drm/i915/intel_cdclk.c
>>> index ebca83a44d9b..4086730018f9 100644
>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct
>> intel_crtc_state *crtc_state)
>>> }
>>>
>>> /*
>>> - * According to BSpec, "The CD clock frequency must be at least twice
>>> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>>> - *
>>> - * FIXME: Check the actual, not default, BCLK being used.
>>> - *
>>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>>> - * is required for audio probe, also when there are no audio capable
>>> - * displays connected at probe time. This leads to unnecessarily high
>>> - * CDCLK when audio is not required.
>>> - *
>>> - * FIXME: This limit is only applied when there are displays connected
>>> - * at probe time. If we probe without displays, we'll still end up using
>>> - * the platform minimum CDCLK, failing audio probe.
>>> - */
>>> - if (INTEL_GEN(dev_priv) >= 9)
>>> - min_cdclk = max(2 * 96000, min_cdclk);
>>> -
>>> - /*
>>> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>>> * than 320000KHz.
>>> */
>>> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct
>> drm_atomic_state *state)
>>> intel_state->min_cdclk[i] = min_cdclk;
>>> }
>>>
>>> - min_cdclk = 0;
>>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>>> for_each_pipe(dev_priv, pipe)
>>> min_cdclk = max(intel_state->min_cdclk[pipe],
>>> min_cdclk);
>>>
>>> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct
>> drm_atomic_state *state)
>>> vlv_calc_voltage_level(dev_priv, cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>>> + cdclk = vlv_calc_cdclk(dev_priv,
>>> + intel_state->cdclk.force_min_cdclk);
>>>
>>> intel_state->cdclk.actual.cdclk = cdclk;
>>> intel_state->cdclk.actual.voltage_level = @@ -2289,7
>>> +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state
>> *state)
>>> bdw_calc_voltage_level(cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = bdw_calc_cdclk(0);
>>> + cdclk =
>>> + bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>
>>> intel_state->cdclk.actual.cdclk = cdclk;
>>> intel_state->cdclk.actual.voltage_level = @@ -2328,7
>>> +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state
>> *state)
>>> skl_calc_voltage_level(cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = skl_calc_cdclk(0, vco);
>>> + cdclk =
>>> + skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>>
>>> intel_state->cdclk.actual.vco = vco;
>>> intel_state->cdclk.actual.cdclk = cdclk; @@ -2367,10
>>> +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state
>>> *state)
>>>
>>> if (!intel_state->active_crtcs) {
>>> if (IS_GEMINILAKE(dev_priv)) {
>>> - cdclk = glk_calc_cdclk(0);
>>> + cdclk =
>>> + glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = glk_de_pll_vco(dev_priv, cdclk);
>>> } else {
>>> - cdclk = bxt_calc_cdclk(0);
>>> + cdclk =
>>> + bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>>> }
>>>
>>> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct
>> drm_atomic_state *state)
>>> cnl_compute_min_voltage_level(intel_state));
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = cnl_calc_cdclk(0);
>>> + cdclk =
>>> + cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>>
>>> intel_state->cdclk.actual.vco = vco; @@ -2439,7
>>> +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state
>> *state)
>>> intel_state->cdclk.logical.cdclk = cdclk;
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = icl_calc_cdclk(0, ref);
>>> + cdclk =
>>> + icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>>
>>> intel_state->cdclk.actual.vco = vco; diff --git
>>> a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index 84ce66be88f2..7c369e15f193 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct
>> drm_atomic_state *state)
>>> return -EINVAL;
>>> }
>>>
>>> + /* keep the current setting */
>>> + if (!intel_state->modeset)
>>> + intel_state->cdclk.force_min_cdclk =
>>> + dev_priv->cdclk.force_min_cdclk;
>>> +
>>> intel_state->modeset = true;
>>> intel_state->active_crtcs = dev_priv->active_crtcs;
>>> intel_state->cdclk.logical = dev_priv->cdclk.logical; @@
>>> -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>> struct drm_crtc *crtc;
>>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>>> int ret, i;
>>> - bool any_ms = false;
>>> + bool any_ms = intel_state->modeset;
>>>
>>> /* Catch I915_MODE_FLAG_INHERITED */
>>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, @@
>>> -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device
>> *dev,
>>> dev_priv->active_crtcs = intel_state->active_crtcs;
>>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>>> + dev_priv->cdclk.force_min_cdclk =
>>> + intel_state->cdclk.force_min_cdclk;
>>> }
>>>
>>> drm_atomic_state_get(state);
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>> b/drivers/gpu/drm/i915/intel_drv.h
>>> index 11a1932cde6e..79928505d0d0 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -461,6 +461,7 @@ struct intel_atomic_state {
>>> * state only when all crtc's are DPMS off.
>>> */
>>> struct intel_cdclk_state actual;
>>> + int force_min_cdclk;
>>> } cdclk;
>>>
>>> bool dpll_set, modeset;
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[-- Attachment #1.2: Type: text/html, Size: 53627 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-01 23:42 ` Kumar, Abhay
@ 2018-05-01 23:47 ` Kumar, Abhay
0 siblings, 0 replies; 36+ messages in thread
From: Kumar, Abhay @ 2018-05-01 23:47 UTC (permalink / raw)
To: Saarinen, Jani, intel-gfx, Ville Syrjälä; +Cc: Nikula, Jani
[-- Attachment #1.1: Type: text/plain, Size: 14037 bytes --]
+ Ville
On 5/1/2018 4:42 PM, Kumar, Abhay wrote:
>
>
>
> On 5/1/2018 2:15 AM, Saarinen, Jani wrote:
>> HI,
>>> -----Original Message-----
>>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>>> Du,Wenkai
>>> Sent: maanantai 30. huhtikuuta 2018 21.23
>>> To: Kumar, Abhay<abhay.kumar@intel.com>;intel-gfx@lists.freedesktop.org
>>> Cc: Nikula, Jani<jani.nikula@intel.com>
>>> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when
>>> audio power is enabled
>>>
>>>
>>>
>>> On 4/29/2018 1:39 PM, Abhay Kumar wrote:
>>>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>>>> driver has to probe using this hook and increase the clock even in
>>>> absence of any display.
>>>>
>>>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>> Signed-off-by: Abhay Kumar<abhay.kumar@intel.com>
>>> Tested-by: Wenkai Du<wenkai.du@intel.com>
>> Please note that failed on CI/GLK:https://patchwork.freedesktop.org/series/42459/
>> ==== Possible regressions ====
>> igt@drv_module_reload@basic-reload:
>> shard-glk: PASS -> INCOMPLETE
>>
>> Br,
>> Jani
> Hi Jani,
>
> Saw panic
> @https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8838/shard-glk8/pstore11-1525091313_Panic_3.log
> and was trying to reproduce this on my end with IGT but it passed for
> me and never failed with DINQ, drm-tip both.
>
> with or without external monitor connected it never fails.
>
> ocalhost /usr/libexec/intel-gpu-tools # ./drv_module_reload
> IGT-Version: 1.20-NOT-GIT (x86_64) (Linux:
> 4.17.0-rc3-g844dd95837ab-dirty x86_64)
> Subtest basic-reload: SUCCESS (0.212s)
> Reloading i915 with disable_display=1
>
> Subtest basic-no-display: SUCCESS (0.054s)
> Reloading i915 with inject_load_failure=0
>
> Reloading i915 with inject_load_failure=1
>
> Reloading i915 with inject_load_failure=2
>
> Reloading i915 with inject_load_failure=3
>
> Subtest basic-reload-inject: SUCCESS (0.329s)
> localhost /usr/libexec/intel-gpu-tools # uname -r
> 4.17.0-rc3-g844dd95837ab-dirty
> localhost /usr/libexec/intel-gpu-tools # aplay -l
> **** List of PLAYBACK Hardware Devices ****
> card 0: PCH [HDA Intel PCH], device 3: HDMI 0 [HDMI 0]
> Subdevices: 1/1
> Subdevice #0: subdevice #0
> card 0: PCH [HDA Intel PCH], device 7: HDMI 1 [HDMI 1]
> Subdevices: 1/1
> Subdevice #0: subdevice #0
> card 0: PCH [HDA Intel PCH], device 8: HDMI 2 [HDMI 2]
> Subdevices: 1/1
> Subdevice #0: subdevice #0
> card 0: PCH [HDA Intel PCH], device 9: HDMI 3 [HDMI 3]
> Subdevices: 1/1
> Subdevice #0: subdevice #0
> card 0: PCH [HDA Intel PCH], device 10: HDMI 4 [HDMI 4]
> Subdevices: 1/1
> Subdevice #0: subdevice #0
> localhost /usr/libexec/intel-gpu-tools #
>
> Regards,
> Abhay
>
>
>>> Thanks,
>>> Wenkai
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>>>> drivers/gpu/drm/i915/intel_audio.c | 46
>>> ++++++++++++++++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
>>>> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
>>>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>>>> 5 files changed, 63 insertions(+), 27 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>> b/drivers/gpu/drm/i915/i915_drv.h index 193176bcddf5..34c31ef0761e
>>>> 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
>>>> struct intel_cdclk_state actual;
>>>> /* The current hardware cdclk state */
>>>> struct intel_cdclk_state hw;
>>>> +
>>>> + int force_min_cdclk;
>>>> } cdclk;
>>>>
>>>> /**
>>>> diff --git a/drivers/gpu/drm/i915/intel_audio.c
>>>> b/drivers/gpu/drm/i915/intel_audio.c
>>>> index 3ea566f99450..f001fcf05d3a 100644
>>>> --- a/drivers/gpu/drm/i915/intel_audio.c
>>>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>>>> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct
>>> intel_encoder *encoder,
>>>> I915_WRITE(aud_config, tmp);
>>>> }
>>>>
>>>> +
>>>> /**
>>>> * intel_audio_codec_enable - Enable the audio codec for HD audio
>>>> * @encoder: encoder on which to enable audio @@ -713,6 +714,48 @@
>>>> void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>>>> }
>>>> }
>>>>
>>>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>>>> + bool enable) {
>>>> + struct drm_modeset_acquire_ctx ctx;
>>>> + struct drm_atomic_state *state;
>>>> + int ret;
>>>> +
>>>> + drm_modeset_acquire_init(&ctx, 0);
>>>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>>>> + if (WARN_ON(!state))
>>>> + return;
>>>> +
>>>> + state->acquire_ctx = &ctx;
>>>> +
>>>> +retry:
>>>> + to_intel_atomic_state(state)->modeset = true;
>>>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>>>> + enable ? 2 * 96000 : 0;
>>>> +
>>>> + /*
>>>> + * Protects dev_priv->cdclk.force_min_cdclk
>>>> + * Need to lock this here in case we have no active pipes
>>>> + * and thus wouldn't lock it during the commit otherwise.
>>>> + */
>>>> + ret = drm_modeset_lock(&dev_priv-
>>>> drm.mode_config.connection_mutex, &ctx);
>>>> + if (!ret)
>>>> + ret = drm_atomic_commit(state);
>>>> +
>>>> + if (ret == -EDEADLK) {
>>>> + drm_atomic_state_clear(state);
>>>> + drm_modeset_backoff(&ctx);
>>>> + goto retry;
>>>> + }
>>>> +
>>>> + WARN_ON(ret);
>>>> +
>>>> + drm_atomic_state_put(state);
>>>> +
>>>> + drm_modeset_drop_locks(&ctx);
>>>> + drm_modeset_acquire_fini(&ctx); }
>>>> +
>>>> static void i915_audio_component_get_power(struct device *kdev)
>>>> {
>>>> intel_display_power_get(kdev_to_i915(kdev),
>>>> POWER_DOMAIN_AUDIO); @@ -732,6 +775,9 @@ static void
>>> i915_audio_component_codec_wake_override(struct device *kdev,
>>>> if (!IS_GEN9(dev_priv))
>>>> return;
>>>>
>>>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>>> + glk_force_audio_cdclk(dev_priv, true);
>>>> +
>>>> i915_audio_component_get_power(kdev);
>>>>
>>>> /*
>>>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>>>> b/drivers/gpu/drm/i915/intel_cdclk.c
>>>> index ebca83a44d9b..4086730018f9 100644
>>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>>> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct
>>> intel_crtc_state *crtc_state)
>>>> }
>>>>
>>>> /*
>>>> - * According to BSpec, "The CD clock frequency must be at least twice
>>>> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>>>> - *
>>>> - * FIXME: Check the actual, not default, BCLK being used.
>>>> - *
>>>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>>>> - * is required for audio probe, also when there are no audio capable
>>>> - * displays connected at probe time. This leads to unnecessarily high
>>>> - * CDCLK when audio is not required.
>>>> - *
>>>> - * FIXME: This limit is only applied when there are displays connected
>>>> - * at probe time. If we probe without displays, we'll still end up using
>>>> - * the platform minimum CDCLK, failing audio probe.
>>>> - */
>>>> - if (INTEL_GEN(dev_priv) >= 9)
>>>> - min_cdclk = max(2 * 96000, min_cdclk);
>>>> -
>>>> - /*
>>>> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>>>> * than 320000KHz.
>>>> */
>>>> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct
>>> drm_atomic_state *state)
>>>> intel_state->min_cdclk[i] = min_cdclk;
>>>> }
>>>>
>>>> - min_cdclk = 0;
>>>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>>>> for_each_pipe(dev_priv, pipe)
>>>> min_cdclk = max(intel_state->min_cdclk[pipe],
>>>> min_cdclk);
>>>>
>>>> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct
>>> drm_atomic_state *state)
>>>> vlv_calc_voltage_level(dev_priv, cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>>>> + cdclk = vlv_calc_cdclk(dev_priv,
>>>> + intel_state->cdclk.force_min_cdclk);
>>>>
>>>> intel_state->cdclk.actual.cdclk = cdclk;
>>>> intel_state->cdclk.actual.voltage_level = @@ -2289,7
>>>> +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state
>>> *state)
>>>> bdw_calc_voltage_level(cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = bdw_calc_cdclk(0);
>>>> + cdclk =
>>>> + bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>>
>>>> intel_state->cdclk.actual.cdclk = cdclk;
>>>> intel_state->cdclk.actual.voltage_level = @@ -2328,7
>>>> +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state
>>> *state)
>>>> skl_calc_voltage_level(cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = skl_calc_cdclk(0, vco);
>>>> + cdclk =
>>>> + skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>>>
>>>> intel_state->cdclk.actual.vco = vco;
>>>> intel_state->cdclk.actual.cdclk = cdclk; @@ -2367,10
>>>> +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state
>>>> *state)
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> if (IS_GEMINILAKE(dev_priv)) {
>>>> - cdclk = glk_calc_cdclk(0);
>>>> + cdclk =
>>>> + glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = glk_de_pll_vco(dev_priv, cdclk);
>>>> } else {
>>>> - cdclk = bxt_calc_cdclk(0);
>>>> + cdclk =
>>>> + bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>>>> }
>>>>
>>>> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct
>>> drm_atomic_state *state)
>>>> cnl_compute_min_voltage_level(intel_state));
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = cnl_calc_cdclk(0);
>>>> + cdclk =
>>>> + cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>>>
>>>> intel_state->cdclk.actual.vco = vco; @@ -2439,7
>>>> +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state
>>> *state)
>>>> intel_state->cdclk.logical.cdclk = cdclk;
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = icl_calc_cdclk(0, ref);
>>>> + cdclk =
>>>> + icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>>>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>>>
>>>> intel_state->cdclk.actual.vco = vco; diff --git
>>>> a/drivers/gpu/drm/i915/intel_display.c
>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>> index 84ce66be88f2..7c369e15f193 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct
>>> drm_atomic_state *state)
>>>> return -EINVAL;
>>>> }
>>>>
>>>> + /* keep the current setting */
>>>> + if (!intel_state->modeset)
>>>> + intel_state->cdclk.force_min_cdclk =
>>>> + dev_priv->cdclk.force_min_cdclk;
>>>> +
>>>> intel_state->modeset = true;
>>>> intel_state->active_crtcs = dev_priv->active_crtcs;
>>>> intel_state->cdclk.logical = dev_priv->cdclk.logical; @@
>>>> -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>>> struct drm_crtc *crtc;
>>>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>>>> int ret, i;
>>>> - bool any_ms = false;
>>>> + bool any_ms = intel_state->modeset;
>>>>
>>>> /* Catch I915_MODE_FLAG_INHERITED */
>>>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, @@
>>>> -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device
>>> *dev,
>>>> dev_priv->active_crtcs = intel_state->active_crtcs;
>>>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>>>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>>>> + dev_priv->cdclk.force_min_cdclk =
>>>> + intel_state->cdclk.force_min_cdclk;
>>>> }
>>>>
>>>> drm_atomic_state_get(state);
>>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>>> b/drivers/gpu/drm/i915/intel_drv.h
>>>> index 11a1932cde6e..79928505d0d0 100644
>>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>>> @@ -461,6 +461,7 @@ struct intel_atomic_state {
>>>> * state only when all crtc's are DPMS off.
>>>> */
>>>> struct intel_cdclk_state actual;
>>>> + int force_min_cdclk;
>>>> } cdclk;
>>>>
>>>> bool dpll_set, modeset;
>>>> --
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
[-- Attachment #1.2: Type: text/html, Size: 54453 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (4 preceding siblings ...)
2018-04-30 18:22 ` [PATCH] " Du,Wenkai
@ 2018-05-02 15:12 ` Ville Syrjälä
2018-05-02 16:57 ` Kumar, Abhay
2018-05-10 1:25 ` [PATCH v2] " Abhay Kumar
` (8 subsequent siblings)
14 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2018-05-02 15:12 UTC (permalink / raw)
To: Abhay Kumar; +Cc: jani.nikula, intel-gfx
On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
From: me
mostly
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 5 files changed, 63 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 193176bcddf5..34c31ef0761e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..f001fcf05d3a 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
> I915_WRITE(aud_config, tmp);
> }
>
> +
> /**
> * intel_audio_codec_enable - Enable the audio codec for HD audio
> * @encoder: encoder on which to enable audio
> @@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(&ctx, 0);
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx = &ctx;
> +
> +retry:
> + to_intel_atomic_state(state)->modeset = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> static void i915_audio_component_get_power(struct device *kdev)
> {
> intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> @@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
> if (!IS_GEN9(dev_priv))
> return;
>
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, true);
> +
Where did the put_power counterpart go?
> i915_audio_component_get_power(kdev);
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ebca83a44d9b..4086730018f9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> }
>
> /*
> - * According to BSpec, "The CD clock frequency must be at least twice
> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> - *
> - * FIXME: Check the actual, not default, BCLK being used.
> - *
> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> - * is required for audio probe, also when there are no audio capable
> - * displays connected at probe time. This leads to unnecessarily high
> - * CDCLK when audio is not required.
> - *
> - * FIXME: This limit is only applied when there are displays connected
> - * at probe time. If we probe without displays, we'll still end up using
> - * the platform minimum CDCLK, failing audio probe.
> - */
> - if (INTEL_GEN(dev_priv) >= 9)
> - min_cdclk = max(2 * 96000, min_cdclk);
I suspect we just want to revert the commit that made this uncoditional.
Otherwise the user may get a display blink every time audio playback is
started/stopped.
> -
> - /*
> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> * than 320000KHz.
> */
> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> intel_state->min_cdclk[i] = min_cdclk;
> }
>
> - min_cdclk = 0;
> + min_cdclk = intel_state->cdclk.force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>
> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> bdw_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = bdw_calc_cdclk(0);
> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> skl_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = skl_calc_cdclk(0, vco);
> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> @@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(0);
> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = glk_de_pll_vco(dev_priv, cdclk);
> } else {
> - cdclk = bxt_calc_cdclk(0);
> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = bxt_de_pll_vco(dev_priv, cdclk);
> }
>
> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> - cdclk = cnl_calc_cdclk(0);
> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> @@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> intel_state->cdclk.logical.cdclk = cdclk;
>
> if (!intel_state->active_crtcs) {
> - cdclk = icl_calc_cdclk(0, ref);
> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 84ce66be88f2..7c369e15f193 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> return -EINVAL;
> }
>
> + /* keep the current setting */
> + if (!intel_state->modeset)
> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
> +
> intel_state->modeset = true;
> intel_state->active_crtcs = dev_priv->active_crtcs;
> intel_state->cdclk.logical = dev_priv->cdclk.logical;
> @@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
> struct drm_crtc *crtc;
> struct drm_crtc_state *old_crtc_state, *crtc_state;
> int ret, i;
> - bool any_ms = false;
> + bool any_ms = intel_state->modeset;
>
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> @@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> dev_priv->active_crtcs = intel_state->active_crtcs;
> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
> }
>
> drm_atomic_state_get(state);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 11a1932cde6e..79928505d0d0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -461,6 +461,7 @@ struct intel_atomic_state {
> * state only when all crtc's are DPMS off.
> */
> struct intel_cdclk_state actual;
> + int force_min_cdclk;
> } cdclk;
>
> bool dpll_set, modeset;
> --
> 2.7.4
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-02 15:12 ` Ville Syrjälä
@ 2018-05-02 16:57 ` Kumar, Abhay
2018-05-02 17:14 ` Ville Syrjälä
0 siblings, 1 reply; 36+ messages in thread
From: Kumar, Abhay @ 2018-05-02 16:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx
On 5/2/2018 8:12 AM, Ville Syrjälä wrote:
> On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
>
> From: me
>
> mostly
>
>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>> driver has to probe using this hook and increase the clock even in
>> absence of any display.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
>> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> 5 files changed, 63 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 193176bcddf5..34c31ef0761e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
>> struct intel_cdclk_state actual;
>> /* The current hardware cdclk state */
>> struct intel_cdclk_state hw;
>> +
>> + int force_min_cdclk;
>> } cdclk;
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>> index 3ea566f99450..f001fcf05d3a 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
>> I915_WRITE(aud_config, tmp);
>> }
>>
>> +
>> /**
>> * intel_audio_codec_enable - Enable the audio codec for HD audio
>> * @encoder: encoder on which to enable audio
>> @@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>> }
>> }
>>
>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>> + bool enable)
>> +{
>> + struct drm_modeset_acquire_ctx ctx;
>> + struct drm_atomic_state *state;
>> + int ret;
>> +
>> + drm_modeset_acquire_init(&ctx, 0);
>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>> + if (WARN_ON(!state))
>> + return;
>> +
>> + state->acquire_ctx = &ctx;
>> +
>> +retry:
>> + to_intel_atomic_state(state)->modeset = true;
>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>> + enable ? 2 * 96000 : 0;
>> +
>> + /*
>> + * Protects dev_priv->cdclk.force_min_cdclk
>> + * Need to lock this here in case we have no active pipes
>> + * and thus wouldn't lock it during the commit otherwise.
>> + */
>> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
>> + if (!ret)
>> + ret = drm_atomic_commit(state);
>> +
>> + if (ret == -EDEADLK) {
>> + drm_atomic_state_clear(state);
>> + drm_modeset_backoff(&ctx);
>> + goto retry;
>> + }
>> +
>> + WARN_ON(ret);
>> +
>> + drm_atomic_state_put(state);
>> +
>> + drm_modeset_drop_locks(&ctx);
>> + drm_modeset_acquire_fini(&ctx);
>> +}
>> +
>> static void i915_audio_component_get_power(struct device *kdev)
>> {
>> intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>> @@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
>> if (!IS_GEN9(dev_priv))
>> return;
>>
>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>> + glk_force_audio_cdclk(dev_priv, true);
>> +
> Where did the put_power counterpart go?
with put_power counterpart the cdclk again goes back to low and then HDA
doesn't get detected. that's why i just kept the bump up.
>
>> i915_audio_component_get_power(kdev);
>>
>> /*
>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> index ebca83a44d9b..4086730018f9 100644
>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> }
>>
>> /*
>> - * According to BSpec, "The CD clock frequency must be at least twice
>> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>> - *
>> - * FIXME: Check the actual, not default, BCLK being used.
>> - *
>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>> - * is required for audio probe, also when there are no audio capable
>> - * displays connected at probe time. This leads to unnecessarily high
>> - * CDCLK when audio is not required.
>> - *
>> - * FIXME: This limit is only applied when there are displays connected
>> - * at probe time. If we probe without displays, we'll still end up using
>> - * the platform minimum CDCLK, failing audio probe.
>> - */
>> - if (INTEL_GEN(dev_priv) >= 9)
>> - min_cdclk = max(2 * 96000, min_cdclk);
> I suspect we just want to revert the commit that made this uncoditional.
> Otherwise the user may get a display blink every time audio playback is
> started/stopped.
yeah. we should keep it. I removed this thought of redundant code. but
will keep in next patchset and just revert recent patch.
>
>> -
>> - /*
>> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>> * than 320000KHz.
>> */
>> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
>> intel_state->min_cdclk[i] = min_cdclk;
>> }
>>
>> - min_cdclk = 0;
>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>> for_each_pipe(dev_priv, pipe)
>> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>>
>> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>> vlv_calc_voltage_level(dev_priv, cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>>
>> intel_state->cdclk.actual.cdclk = cdclk;
>> intel_state->cdclk.actual.voltage_level =
>> @@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
>> bdw_calc_voltage_level(cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = bdw_calc_cdclk(0);
>> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>
>> intel_state->cdclk.actual.cdclk = cdclk;
>> intel_state->cdclk.actual.voltage_level =
>> @@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> skl_calc_voltage_level(cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = skl_calc_cdclk(0, vco);
>> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>
>> intel_state->cdclk.actual.vco = vco;
>> intel_state->cdclk.actual.cdclk = cdclk;
>> @@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>>
>> if (!intel_state->active_crtcs) {
>> if (IS_GEMINILAKE(dev_priv)) {
>> - cdclk = glk_calc_cdclk(0);
>> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = glk_de_pll_vco(dev_priv, cdclk);
>> } else {
>> - cdclk = bxt_calc_cdclk(0);
>> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>> }
>>
>> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> cnl_compute_min_voltage_level(intel_state));
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = cnl_calc_cdclk(0);
>> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>
>> intel_state->cdclk.actual.vco = vco;
>> @@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> intel_state->cdclk.logical.cdclk = cdclk;
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = icl_calc_cdclk(0, ref);
>> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>
>> intel_state->cdclk.actual.vco = vco;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 84ce66be88f2..7c369e15f193 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> return -EINVAL;
>> }
>>
>> + /* keep the current setting */
>> + if (!intel_state->modeset)
>> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
>> +
>> intel_state->modeset = true;
>> intel_state->active_crtcs = dev_priv->active_crtcs;
>> intel_state->cdclk.logical = dev_priv->cdclk.logical;
>> @@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
>> struct drm_crtc *crtc;
>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>> int ret, i;
>> - bool any_ms = false;
>> + bool any_ms = intel_state->modeset;
>>
>> /* Catch I915_MODE_FLAG_INHERITED */
>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>> @@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>> dev_priv->active_crtcs = intel_state->active_crtcs;
>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
>> }
>>
>> drm_atomic_state_get(state);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 11a1932cde6e..79928505d0d0 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -461,6 +461,7 @@ struct intel_atomic_state {
>> * state only when all crtc's are DPMS off.
>> */
>> struct intel_cdclk_state actual;
>> + int force_min_cdclk;
>> } cdclk;
>>
>> bool dpll_set, modeset;
>> --
>> 2.7.4
_______________________________________________
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-02 16:57 ` Kumar, Abhay
@ 2018-05-02 17:14 ` Ville Syrjälä
2018-05-02 18:47 ` Kumar, Abhay
0 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2018-05-02 17:14 UTC (permalink / raw)
To: Kumar, Abhay; +Cc: Nikula, Jani, intel-gfx
On Wed, May 02, 2018 at 09:57:01AM -0700, Kumar, Abhay wrote:
>
>
> On 5/2/2018 8:12 AM, Ville Syrjälä wrote:
> > On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
> >
> > From: me
> >
> > mostly
> >
> >> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> >> driver has to probe using this hook and increase the clock even in
> >> absence of any display.
> >>
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> >> drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
> >> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
> >> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
> >> drivers/gpu/drm/i915/intel_drv.h | 1 +
> >> 5 files changed, 63 insertions(+), 27 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 193176bcddf5..34c31ef0761e 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
> >> struct intel_cdclk_state actual;
> >> /* The current hardware cdclk state */
> >> struct intel_cdclk_state hw;
> >> +
> >> + int force_min_cdclk;
> >> } cdclk;
> >>
> >> /**
> >> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> >> index 3ea566f99450..f001fcf05d3a 100644
> >> --- a/drivers/gpu/drm/i915/intel_audio.c
> >> +++ b/drivers/gpu/drm/i915/intel_audio.c
> >> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
> >> I915_WRITE(aud_config, tmp);
> >> }
> >>
> >> +
> >> /**
> >> * intel_audio_codec_enable - Enable the audio codec for HD audio
> >> * @encoder: encoder on which to enable audio
> >> @@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> >> }
> >> }
> >>
> >> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> >> + bool enable)
> >> +{
> >> + struct drm_modeset_acquire_ctx ctx;
> >> + struct drm_atomic_state *state;
> >> + int ret;
> >> +
> >> + drm_modeset_acquire_init(&ctx, 0);
> >> + state = drm_atomic_state_alloc(&dev_priv->drm);
> >> + if (WARN_ON(!state))
> >> + return;
> >> +
> >> + state->acquire_ctx = &ctx;
> >> +
> >> +retry:
> >> + to_intel_atomic_state(state)->modeset = true;
> >> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> >> + enable ? 2 * 96000 : 0;
> >> +
> >> + /*
> >> + * Protects dev_priv->cdclk.force_min_cdclk
> >> + * Need to lock this here in case we have no active pipes
> >> + * and thus wouldn't lock it during the commit otherwise.
> >> + */
> >> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
> >> + if (!ret)
> >> + ret = drm_atomic_commit(state);
> >> +
> >> + if (ret == -EDEADLK) {
> >> + drm_atomic_state_clear(state);
> >> + drm_modeset_backoff(&ctx);
> >> + goto retry;
> >> + }
> >> +
> >> + WARN_ON(ret);
> >> +
> >> + drm_atomic_state_put(state);
> >> +
> >> + drm_modeset_drop_locks(&ctx);
> >> + drm_modeset_acquire_fini(&ctx);
> >> +}
> >> +
> >> static void i915_audio_component_get_power(struct device *kdev)
> >> {
> >> intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> >> @@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
> >> if (!IS_GEN9(dev_priv))
> >> return;
> >>
> >> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> >> + glk_force_audio_cdclk(dev_priv, true);
> >> +
> > Where did the put_power counterpart go?
> with put_power counterpart the cdclk again goes back to low and then HDA
> doesn't get detected. that's why i just kept the bump up.
Then fix hda to grab the power when it needs it?
Otherwise we permanently lock the cdclk to >=2*96 MHz. Ie. it would
be no different to what we have now, except a lot more complex.
>
> >
> >> i915_audio_component_get_power(kdev);
> >>
> >> /*
> >> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> >> index ebca83a44d9b..4086730018f9 100644
> >> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> >> }
> >>
> >> /*
> >> - * According to BSpec, "The CD clock frequency must be at least twice
> >> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> >> - *
> >> - * FIXME: Check the actual, not default, BCLK being used.
> >> - *
> >> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> >> - * is required for audio probe, also when there are no audio capable
> >> - * displays connected at probe time. This leads to unnecessarily high
> >> - * CDCLK when audio is not required.
> >> - *
> >> - * FIXME: This limit is only applied when there are displays connected
> >> - * at probe time. If we probe without displays, we'll still end up using
> >> - * the platform minimum CDCLK, failing audio probe.
> >> - */
> >> - if (INTEL_GEN(dev_priv) >= 9)
> >> - min_cdclk = max(2 * 96000, min_cdclk);
> > I suspect we just want to revert the commit that made this uncoditional.
> > Otherwise the user may get a display blink every time audio playback is
> > started/stopped.
> yeah. we should keep it. I removed this thought of redundant code. but
> will keep in next patchset and just revert recent patch.
> >
> >> -
> >> - /*
> >> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> >> * than 320000KHz.
> >> */
> >> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> >> intel_state->min_cdclk[i] = min_cdclk;
> >> }
> >>
> >> - min_cdclk = 0;
> >> + min_cdclk = intel_state->cdclk.force_min_cdclk;
> >> for_each_pipe(dev_priv, pipe)
> >> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
> >>
> >> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> vlv_calc_voltage_level(dev_priv, cdclk);
> >>
> >> if (!intel_state->active_crtcs) {
> >> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> >> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
> >>
> >> intel_state->cdclk.actual.cdclk = cdclk;
> >> intel_state->cdclk.actual.voltage_level =
> >> @@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> bdw_calc_voltage_level(cdclk);
> >>
> >> if (!intel_state->active_crtcs) {
> >> - cdclk = bdw_calc_cdclk(0);
> >> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> >>
> >> intel_state->cdclk.actual.cdclk = cdclk;
> >> intel_state->cdclk.actual.voltage_level =
> >> @@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> skl_calc_voltage_level(cdclk);
> >>
> >> if (!intel_state->active_crtcs) {
> >> - cdclk = skl_calc_cdclk(0, vco);
> >> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
> >>
> >> intel_state->cdclk.actual.vco = vco;
> >> intel_state->cdclk.actual.cdclk = cdclk;
> >> @@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> >>
> >> if (!intel_state->active_crtcs) {
> >> if (IS_GEMINILAKE(dev_priv)) {
> >> - cdclk = glk_calc_cdclk(0);
> >> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> >> vco = glk_de_pll_vco(dev_priv, cdclk);
> >> } else {
> >> - cdclk = bxt_calc_cdclk(0);
> >> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> >> vco = bxt_de_pll_vco(dev_priv, cdclk);
> >> }
> >>
> >> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> cnl_compute_min_voltage_level(intel_state));
> >>
> >> if (!intel_state->active_crtcs) {
> >> - cdclk = cnl_calc_cdclk(0);
> >> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> >> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >>
> >> intel_state->cdclk.actual.vco = vco;
> >> @@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> intel_state->cdclk.logical.cdclk = cdclk;
> >>
> >> if (!intel_state->active_crtcs) {
> >> - cdclk = icl_calc_cdclk(0, ref);
> >> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> >> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> >>
> >> intel_state->cdclk.actual.vco = vco;
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index 84ce66be88f2..7c369e15f193 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> >> return -EINVAL;
> >> }
> >>
> >> + /* keep the current setting */
> >> + if (!intel_state->modeset)
> >> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
> >> +
> >> intel_state->modeset = true;
> >> intel_state->active_crtcs = dev_priv->active_crtcs;
> >> intel_state->cdclk.logical = dev_priv->cdclk.logical;
> >> @@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
> >> struct drm_crtc *crtc;
> >> struct drm_crtc_state *old_crtc_state, *crtc_state;
> >> int ret, i;
> >> - bool any_ms = false;
> >> + bool any_ms = intel_state->modeset;
> >>
> >> /* Catch I915_MODE_FLAG_INHERITED */
> >> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> >> @@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> >> dev_priv->active_crtcs = intel_state->active_crtcs;
> >> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> >> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> >> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
> >> }
> >>
> >> drm_atomic_state_get(state);
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> index 11a1932cde6e..79928505d0d0 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -461,6 +461,7 @@ struct intel_atomic_state {
> >> * state only when all crtc's are DPMS off.
> >> */
> >> struct intel_cdclk_state actual;
> >> + int force_min_cdclk;
> >> } cdclk;
> >>
> >> bool dpll_set, modeset;
> >> --
> >> 2.7.4
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-02 17:14 ` Ville Syrjälä
@ 2018-05-02 18:47 ` Kumar, Abhay
0 siblings, 0 replies; 36+ messages in thread
From: Kumar, Abhay @ 2018-05-02 18:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx
On 5/2/2018 10:14 AM, Ville Syrjälä wrote:
> On Wed, May 02, 2018 at 09:57:01AM -0700, Kumar, Abhay wrote:
>>
>> On 5/2/2018 8:12 AM, Ville Syrjälä wrote:
>>> On Sun, Apr 29, 2018 at 01:39:13PM -0700, Abhay Kumar wrote:
>>>
>>> From: me
>>>
>>> mostly
>>>
>>>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>>>> driver has to probe using this hook and increase the clock even in
>>>> absence of any display.
>>>>
>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>>>> drivers/gpu/drm/i915/intel_audio.c | 46 ++++++++++++++++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/intel_cdclk.c | 34 +++++++-------------------
>>>> drivers/gpu/drm/i915/intel_display.c | 7 +++++-
>>>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>>>> 5 files changed, 63 insertions(+), 27 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index 193176bcddf5..34c31ef0761e 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -1708,6 +1708,8 @@ struct drm_i915_private {
>>>> struct intel_cdclk_state actual;
>>>> /* The current hardware cdclk state */
>>>> struct intel_cdclk_state hw;
>>>> +
>>>> + int force_min_cdclk;
>>>> } cdclk;
>>>>
>>>> /**
>>>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>>>> index 3ea566f99450..f001fcf05d3a 100644
>>>> --- a/drivers/gpu/drm/i915/intel_audio.c
>>>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>>>> @@ -594,6 +594,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
>>>> I915_WRITE(aud_config, tmp);
>>>> }
>>>>
>>>> +
>>>> /**
>>>> * intel_audio_codec_enable - Enable the audio codec for HD audio
>>>> * @encoder: encoder on which to enable audio
>>>> @@ -713,6 +714,48 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>>>> }
>>>> }
>>>>
>>>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>>>> + bool enable)
>>>> +{
>>>> + struct drm_modeset_acquire_ctx ctx;
>>>> + struct drm_atomic_state *state;
>>>> + int ret;
>>>> +
>>>> + drm_modeset_acquire_init(&ctx, 0);
>>>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>>>> + if (WARN_ON(!state))
>>>> + return;
>>>> +
>>>> + state->acquire_ctx = &ctx;
>>>> +
>>>> +retry:
>>>> + to_intel_atomic_state(state)->modeset = true;
>>>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>>>> + enable ? 2 * 96000 : 0;
>>>> +
>>>> + /*
>>>> + * Protects dev_priv->cdclk.force_min_cdclk
>>>> + * Need to lock this here in case we have no active pipes
>>>> + * and thus wouldn't lock it during the commit otherwise.
>>>> + */
>>>> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
>>>> + if (!ret)
>>>> + ret = drm_atomic_commit(state);
>>>> +
>>>> + if (ret == -EDEADLK) {
>>>> + drm_atomic_state_clear(state);
>>>> + drm_modeset_backoff(&ctx);
>>>> + goto retry;
>>>> + }
>>>> +
>>>> + WARN_ON(ret);
>>>> +
>>>> + drm_atomic_state_put(state);
>>>> +
>>>> + drm_modeset_drop_locks(&ctx);
>>>> + drm_modeset_acquire_fini(&ctx);
>>>> +}
>>>> +
>>>> static void i915_audio_component_get_power(struct device *kdev)
>>>> {
>>>> intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>>>> @@ -732,6 +775,9 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
>>>> if (!IS_GEN9(dev_priv))
>>>> return;
>>>>
>>>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>>> + glk_force_audio_cdclk(dev_priv, true);
>>>> +
>>> Where did the put_power counterpart go?
>> with put_power counterpart the cdclk again goes back to low and then HDA
>> doesn't get detected. that's why i just kept the bump up.
> Then fix hda to grab the power when it needs it?
I am afraid that this leads lot more changes as everywhere where there
is a probe we need to bump the clock.
>
> Otherwise we permanently lock the cdclk to >=2*96 MHz. Ie. it would
> be no different to what we have now, except a lot more complex.
It is different specially in resume/s0ix path. with the one we have
right now during resume time the cdclk is still 79.2 and
thus either the hda doesn't comeup or we have 4sec delay in coming up as
it loops and wait for hda verb command response.
This patch makes sure that all the time at probe we have right cdclk.
one more thing. we did probe power numbers and there was
not much significant delta.
>
>>>> i915_audio_component_get_power(kdev);
>>>>
>>>> /*
>>>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>>>> index ebca83a44d9b..4086730018f9 100644
>>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>>> @@ -2141,24 +2141,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>>>> }
>>>>
>>>> /*
>>>> - * According to BSpec, "The CD clock frequency must be at least twice
>>>> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>>>> - *
>>>> - * FIXME: Check the actual, not default, BCLK being used.
>>>> - *
>>>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>>>> - * is required for audio probe, also when there are no audio capable
>>>> - * displays connected at probe time. This leads to unnecessarily high
>>>> - * CDCLK when audio is not required.
>>>> - *
>>>> - * FIXME: This limit is only applied when there are displays connected
>>>> - * at probe time. If we probe without displays, we'll still end up using
>>>> - * the platform minimum CDCLK, failing audio probe.
>>>> - */
>>>> - if (INTEL_GEN(dev_priv) >= 9)
>>>> - min_cdclk = max(2 * 96000, min_cdclk);
>>> I suspect we just want to revert the commit that made this uncoditional.
>>> Otherwise the user may get a display blink every time audio playback is
>>> started/stopped.
>> yeah. we should keep it. I removed this thought of redundant code. but
>> will keep in next patchset and just revert recent patch.
>>>> -
>>>> - /*
>>>> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>>>> * than 320000KHz.
>>>> */
>>>> @@ -2195,7 +2177,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
>>>> intel_state->min_cdclk[i] = min_cdclk;
>>>> }
>>>>
>>>> - min_cdclk = 0;
>>>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>>>> for_each_pipe(dev_priv, pipe)
>>>> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>>>>
>>>> @@ -2256,7 +2238,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>> vlv_calc_voltage_level(dev_priv, cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>>>> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>>>>
>>>> intel_state->cdclk.actual.cdclk = cdclk;
>>>> intel_state->cdclk.actual.voltage_level =
>>>> @@ -2289,7 +2271,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>> bdw_calc_voltage_level(cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = bdw_calc_cdclk(0);
>>>> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>>
>>>> intel_state->cdclk.actual.cdclk = cdclk;
>>>> intel_state->cdclk.actual.voltage_level =
>>>> @@ -2328,7 +2310,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>> skl_calc_voltage_level(cdclk);
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = skl_calc_cdclk(0, vco);
>>>> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>>>
>>>> intel_state->cdclk.actual.vco = vco;
>>>> intel_state->cdclk.actual.cdclk = cdclk;
>>>> @@ -2367,10 +2349,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> if (IS_GEMINILAKE(dev_priv)) {
>>>> - cdclk = glk_calc_cdclk(0);
>>>> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = glk_de_pll_vco(dev_priv, cdclk);
>>>> } else {
>>>> - cdclk = bxt_calc_cdclk(0);
>>>> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>>>> }
>>>>
>>>> @@ -2406,7 +2388,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>> cnl_compute_min_voltage_level(intel_state));
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = cnl_calc_cdclk(0);
>>>> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>>>
>>>> intel_state->cdclk.actual.vco = vco;
>>>> @@ -2439,7 +2421,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>> intel_state->cdclk.logical.cdclk = cdclk;
>>>>
>>>> if (!intel_state->active_crtcs) {
>>>> - cdclk = icl_calc_cdclk(0, ref);
>>>> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>>>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>>>
>>>> intel_state->cdclk.actual.vco = vco;
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>> index 84ce66be88f2..7c369e15f193 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -12023,6 +12023,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>>>> return -EINVAL;
>>>> }
>>>>
>>>> + /* keep the current setting */
>>>> + if (!intel_state->modeset)
>>>> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
>>>> +
>>>> intel_state->modeset = true;
>>>> intel_state->active_crtcs = dev_priv->active_crtcs;
>>>> intel_state->cdclk.logical = dev_priv->cdclk.logical;
>>>> @@ -12118,7 +12122,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>>> struct drm_crtc *crtc;
>>>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>>>> int ret, i;
>>>> - bool any_ms = false;
>>>> + bool any_ms = intel_state->modeset;
>>>>
>>>> /* Catch I915_MODE_FLAG_INHERITED */
>>>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>>>> @@ -12666,6 +12670,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>>>> dev_priv->active_crtcs = intel_state->active_crtcs;
>>>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>>>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>>>> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
>>>> }
>>>>
>>>> drm_atomic_state_get(state);
>>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>>>> index 11a1932cde6e..79928505d0d0 100644
>>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>>> @@ -461,6 +461,7 @@ struct intel_atomic_state {
>>>> * state only when all crtc's are DPMS off.
>>>> */
>>>> struct intel_cdclk_state actual;
>>>> + int force_min_cdclk;
>>>> } cdclk;
>>>>
>>>> bool dpll_set, modeset;
>>>> --
>>>> 2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (5 preceding siblings ...)
2018-05-02 15:12 ` Ville Syrjälä
@ 2018-05-10 1:25 ` Abhay Kumar
2018-05-11 12:33 ` Ville Syrjälä
2018-06-12 7:17 ` [PATCH v3] " Abhay Kumar
2018-05-10 1:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) Patchwork
` (7 subsequent siblings)
14 siblings, 2 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-05-10 1:25 UTC (permalink / raw)
To: ville.syrjala; +Cc: jani.nikula, intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/intel_audio.c | 66 +++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_cdclk.c | 29 +++++-----------
drivers/gpu/drm/i915/intel_display.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 ++
5 files changed, 82 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24c5e4765afd..9c4ea767688a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1692,6 +1692,7 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ atomic_t get_put_refcount;
struct {
/*
@@ -1709,6 +1710,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..a1e2c4daae6e 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!connector->eld[0])
return;
-
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
connector->name,
@@ -713,14 +712,73 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+ * Protects dev_priv->cdclk.force_min_cdclk
+ * Need to lock this here in case we have no active pipes
+ * and thus wouldn't lock it during the commit otherwise.
+ */
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
- intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+ atomic_inc(&dev_priv->get_put_refcount);
+
+ /* Force cdclk to 2*BCLK during first time get power call */
+ if (atomic_read(&dev_priv->get_put_refcount) == 1)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
}
static void i915_audio_component_put_power(struct device *kdev)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ atomic_dec(&dev_priv->get_put_refcount);
+
+ /* Force required cdclk during last time put power call */
+ if (atomic_read(&dev_priv->get_put_refcount) == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
@@ -959,7 +1017,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
/* continue with reduced functionality */
return;
}
-
+ atomic_set(&dev_priv->get_put_refcount, 0);
dev_priv->audio_component_registered = true;
}
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 704ddb4d3ca7..a0c281a90ff4 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2143,19 +2143,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/*
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
- *
- * FIXME: Check the actual, not default, BCLK being used.
- *
- * FIXME: This does not depend on ->has_audio because the higher CDCLK
- * is required for audio probe, also when there are no audio capable
- * displays connected at probe time. This leads to unnecessarily high
- * CDCLK when audio is not required.
- *
- * FIXME: This limit is only applied when there are displays connected
- * at probe time. If we probe without displays, we'll still end up using
- * the platform minimum CDCLK, failing audio probe.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2195,7 +2184,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
intel_state->min_cdclk[i] = min_cdclk;
}
- min_cdclk = 0;
+ min_cdclk = intel_state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
@@ -2256,7 +2245,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
- cdclk = vlv_calc_cdclk(dev_priv, 0);
+ cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2289,7 +2278,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = bdw_calc_cdclk(0);
+ cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2361,7 +2350,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = skl_calc_cdclk(0, vco);
+ cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
@@ -2400,10 +2389,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
- cdclk = glk_calc_cdclk(0);
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = glk_de_pll_vco(dev_priv, cdclk);
} else {
- cdclk = bxt_calc_cdclk(0);
+ cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
@@ -2439,7 +2428,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = cnl_calc_cdclk(0);
+ cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
@@ -2472,7 +2461,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
if (!intel_state->active_crtcs) {
- cdclk = icl_calc_cdclk(0, ref);
+ cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cdfe0951d171..0b0e519fe844 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12041,6 +12041,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return -EINVAL;
}
+ /* keep the current setting */
+ if (!intel_state->modeset)
+ intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
intel_state->modeset = true;
intel_state->active_crtcs = dev_priv->active_crtcs;
intel_state->cdclk.logical = dev_priv->cdclk.logical;
@@ -12136,7 +12140,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *crtc_state;
int ret, i;
- bool any_ms = false;
+ bool any_ms = intel_state->modeset;
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -12684,6 +12688,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
+ dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 52337f487ebc..7b53f72d7242 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -461,6 +461,8 @@ struct intel_atomic_state {
* state only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
+
+ int force_min_cdclk;
} cdclk;
bool dpll_set, modeset;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (6 preceding siblings ...)
2018-05-10 1:25 ` [PATCH v2] " Abhay Kumar
@ 2018-05-10 1:54 ` Patchwork
2018-05-10 1:55 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-05-10 1:54 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
420c5e74238d drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_audio.c:716:
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
-:202: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 25)
#202: FILE: drivers/gpu/drm/i915/intel_cdclk.c:2391:
if (IS_GEMINILAKE(dev_priv)) {
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
total: 0 errors, 1 warnings, 1 checks, 218 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (7 preceding siblings ...)
2018-05-10 1:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) Patchwork
@ 2018-05-10 1:55 ` Patchwork
2018-05-10 2:14 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-05-10 1:55 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-O:drivers/gpu/drm/i915/intel_cdclk.c:2159:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2148:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2200:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2200:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2189:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2189:29: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3657:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (8 preceding siblings ...)
2018-05-10 1:55 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-05-10 2:14 ` Patchwork
2018-05-10 4:35 ` ✓ Fi.CI.IGT: " Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-05-10 2:14 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8969 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42459/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_8969 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-hsw-4200u: PASS -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: PASS -> FAIL (fdo#104008)
==== Possible fixes ====
igt@drv_module_reload@basic-reload-inject:
fi-glk-j4005: DMESG-WARN (fdo#106248) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-hsw-4770r: FAIL (fdo#100368) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
== Participating hosts (41 -> 37) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8969
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8969: 420c5e74238dfee3520f9f386e3257ff0a2b416e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Linux commits ==
420c5e74238d drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8969/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (9 preceding siblings ...)
2018-05-10 2:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-10 4:35 ` Patchwork
2018-06-12 7:28 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-05-10 4:35 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8969_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8969_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8969_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42459/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8969_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +2
igt@kms_force_connector_basic@force-connector-state:
shard-snb: PASS -> SKIP
igt@kms_properties@plane-properties-legacy:
shard-snb: SKIP -> PASS +4
== Known issues ==
Here are the changes found in Patchwork_8969_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@flip-vs-wf_vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105312)
igt@kms_frontbuffer_tracking@fbc-suspend:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +5
igt@kms_rotation_crc@primary-rotation-180:
shard-apl: PASS -> DMESG-WARN (fdo#105127)
==== Possible fixes ====
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: FAIL (fdo#106087) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL (fdo#105363, fdo#102887) -> PASS
shard-glk: FAIL (fdo#102887) -> PASS
igt@kms_flip@wf_vblank-ts-check-interruptible:
shard-apl: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#105127 https://bugs.freedesktop.org/show_bug.cgi?id=105127
fdo#105312 https://bugs.freedesktop.org/show_bug.cgi?id=105312
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (9 -> 9) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8969
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8969: 420c5e74238dfee3520f9f386e3257ff0a2b416e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8969/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-10 1:25 ` [PATCH v2] " Abhay Kumar
@ 2018-05-11 12:33 ` Ville Syrjälä
2018-05-11 22:04 ` Kumar, Abhay
2018-06-12 7:17 ` [PATCH v3] " Abhay Kumar
1 sibling, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2018-05-11 12:33 UTC (permalink / raw)
To: Abhay Kumar; +Cc: jani.nikula, intel-gfx, ville.syrjala
On Wed, May 09, 2018 at 06:25:32PM -0700, Abhay Kumar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> v2: Use atomic refcount for get_power, put_power so that we can
> call each once(Abhay).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/intel_audio.c | 66 +++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_cdclk.c | 29 +++++-----------
> drivers/gpu/drm/i915/intel_display.c | 7 +++-
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 5 files changed, 82 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 24c5e4765afd..9c4ea767688a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1692,6 +1692,7 @@ struct drm_i915_private {
> unsigned int hpll_freq;
> unsigned int fdi_pll_freq;
> unsigned int czclk_freq;
> + atomic_t get_put_refcount;
>
> struct {
> /*
> @@ -1709,6 +1710,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..a1e2c4daae6e 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>
> if (!connector->eld[0])
> return;
> -
> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
> connector->base.id,
> connector->name,
> @@ -713,14 +712,73 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(&ctx, 0);
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx = &ctx;
> +
> +retry:
> + to_intel_atomic_state(state)->modeset = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> static void i915_audio_component_get_power(struct device *kdev)
> {
> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +
> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> + atomic_inc(&dev_priv->get_put_refcount);
> +
> + /* Force cdclk to 2*BCLK during first time get power call */
> + if (atomic_read(&dev_priv->get_put_refcount) == 1)
If it needs to be atomic (ie. we have concurrent callers of get/put_power())
then you would also need to do the inc+check atomically. But that in itself
wouldn't help because only the first caller would do the cdclk change,
and the second call would just immediately proceed without waiting for the
cdclk to actually have been changed.
So the first question we should ask is whether we can even have
concurrent callers, or if there's some form of mutual exclusion
already on the caller side?
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, true);
> }
>
> static void i915_audio_component_put_power(struct device *kdev)
> {
> - intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +
> + atomic_dec(&dev_priv->get_put_refcount);
> +
> + /* Force required cdclk during last time put power call */
> + if (atomic_read(&dev_priv->get_put_refcount) == 0)
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, false);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
> }
>
> static void i915_audio_component_codec_wake_override(struct device *kdev,
> @@ -959,7 +1017,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
> /* continue with reduced functionality */
> return;
> }
> -
> + atomic_set(&dev_priv->get_put_refcount, 0);
> dev_priv->audio_component_registered = true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 704ddb4d3ca7..a0c281a90ff4 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2143,19 +2143,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /*
> * According to BSpec, "The CD clock frequency must be at least twice
> * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> - *
> - * FIXME: Check the actual, not default, BCLK being used.
> - *
> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> - * is required for audio probe, also when there are no audio capable
> - * displays connected at probe time. This leads to unnecessarily high
> - * CDCLK when audio is not required.
> - *
> - * FIXME: This limit is only applied when there are displays connected
> - * at probe time. If we probe without displays, we'll still end up using
> - * the platform minimum CDCLK, failing audio probe.
> */
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> min_cdclk = max(2 * 96000, min_cdclk);
>
> /*
> @@ -2195,7 +2184,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> intel_state->min_cdclk[i] = min_cdclk;
> }
>
> - min_cdclk = 0;
> + min_cdclk = intel_state->cdclk.force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>
> @@ -2256,7 +2245,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2289,7 +2278,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> bdw_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = bdw_calc_cdclk(0);
> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2361,7 +2350,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> skl_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = skl_calc_cdclk(0, vco);
> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> @@ -2400,10 +2389,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(0);
> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = glk_de_pll_vco(dev_priv, cdclk);
> } else {
> - cdclk = bxt_calc_cdclk(0);
> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = bxt_de_pll_vco(dev_priv, cdclk);
> }
>
> @@ -2439,7 +2428,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> - cdclk = cnl_calc_cdclk(0);
> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> @@ -2472,7 +2461,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> intel_state->cdclk.logical.cdclk = cdclk;
>
> if (!intel_state->active_crtcs) {
> - cdclk = icl_calc_cdclk(0, ref);
> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cdfe0951d171..0b0e519fe844 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12041,6 +12041,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> return -EINVAL;
> }
>
> + /* keep the current setting */
> + if (!intel_state->modeset)
> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
> +
> intel_state->modeset = true;
> intel_state->active_crtcs = dev_priv->active_crtcs;
> intel_state->cdclk.logical = dev_priv->cdclk.logical;
> @@ -12136,7 +12140,7 @@ static int intel_atomic_check(struct drm_device *dev,
> struct drm_crtc *crtc;
> struct drm_crtc_state *old_crtc_state, *crtc_state;
> int ret, i;
> - bool any_ms = false;
> + bool any_ms = intel_state->modeset;
>
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> @@ -12684,6 +12688,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> dev_priv->active_crtcs = intel_state->active_crtcs;
> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
> }
>
> drm_atomic_state_get(state);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 52337f487ebc..7b53f72d7242 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -461,6 +461,8 @@ struct intel_atomic_state {
> * state only when all crtc's are DPMS off.
> */
> struct intel_cdclk_state actual;
> +
> + int force_min_cdclk;
> } cdclk;
>
> bool dpll_set, modeset;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-11 12:33 ` Ville Syrjälä
@ 2018-05-11 22:04 ` Kumar, Abhay
2018-05-14 9:24 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Kumar, Abhay @ 2018-05-11 22:04 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx, Syrjala, Ville
On 5/11/2018 5:33 AM, Ville Syrjälä wrote:
> On Wed, May 09, 2018 at 06:25:32PM -0700, Abhay Kumar wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>> driver has to probe using this hook and increase the clock even in
>> absence of any display.
>>
>> v2: Use atomic refcount for get_power, put_power so that we can
>> call each once(Abhay).
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 3 ++
>> drivers/gpu/drm/i915/intel_audio.c | 66 +++++++++++++++++++++++++++++++++---
>> drivers/gpu/drm/i915/intel_cdclk.c | 29 +++++-----------
>> drivers/gpu/drm/i915/intel_display.c | 7 +++-
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 5 files changed, 82 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 24c5e4765afd..9c4ea767688a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1692,6 +1692,7 @@ struct drm_i915_private {
>> unsigned int hpll_freq;
>> unsigned int fdi_pll_freq;
>> unsigned int czclk_freq;
>> + atomic_t get_put_refcount;
>>
>> struct {
>> /*
>> @@ -1709,6 +1710,8 @@ struct drm_i915_private {
>> struct intel_cdclk_state actual;
>> /* The current hardware cdclk state */
>> struct intel_cdclk_state hw;
>> +
>> + int force_min_cdclk;
>> } cdclk;
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>> index 3ea566f99450..a1e2c4daae6e 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>>
>> if (!connector->eld[0])
>> return;
>> -
>> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>> connector->base.id,
>> connector->name,
>> @@ -713,14 +712,73 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>> }
>> }
>>
>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>> + bool enable)
>> +{
>> + struct drm_modeset_acquire_ctx ctx;
>> + struct drm_atomic_state *state;
>> + int ret;
>> +
>> + drm_modeset_acquire_init(&ctx, 0);
>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>> + if (WARN_ON(!state))
>> + return;
>> +
>> + state->acquire_ctx = &ctx;
>> +
>> +retry:
>> + to_intel_atomic_state(state)->modeset = true;
>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>> + enable ? 2 * 96000 : 0;
>> +
>> + /*
>> + * Protects dev_priv->cdclk.force_min_cdclk
>> + * Need to lock this here in case we have no active pipes
>> + * and thus wouldn't lock it during the commit otherwise.
>> + */
>> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
>> + if (!ret)
>> + ret = drm_atomic_commit(state);
>> +
>> + if (ret == -EDEADLK) {
>> + drm_atomic_state_clear(state);
>> + drm_modeset_backoff(&ctx);
>> + goto retry;
>> + }
>> +
>> + WARN_ON(ret);
>> +
>> + drm_atomic_state_put(state);
>> +
>> + drm_modeset_drop_locks(&ctx);
>> + drm_modeset_acquire_fini(&ctx);
>> +}
>> +
>> static void i915_audio_component_get_power(struct device *kdev)
>> {
>> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>> +
>> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
>> + atomic_inc(&dev_priv->get_put_refcount);
>> +
>> + /* Force cdclk to 2*BCLK during first time get power call */
>> + if (atomic_read(&dev_priv->get_put_refcount) == 1)
> If it needs to be atomic (ie. we have concurrent callers of get/put_power())
> then you would also need to do the inc+check atomically. But that in itself
> wouldn't help because only the first caller would do the cdclk change,
> and the second call would just immediately proceed without waiting for the
> cdclk to actually have been changed.
>
> So the first question we should ask is whether we can even have
> concurrent callers, or if there's some form of mutual exclusion
> already on the caller side?
As per my understanding I don't think we have any concurrent callers as
these calls will be in sequence.
Do you prefer to use static instead?
>
>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>> + glk_force_audio_cdclk(dev_priv, true);
>> }
>>
>> static void i915_audio_component_put_power(struct device *kdev)
>> {
>> - intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>> +
>> + atomic_dec(&dev_priv->get_put_refcount);
>> +
>> + /* Force required cdclk during last time put power call */
>> + if (atomic_read(&dev_priv->get_put_refcount) == 0)
>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>> + glk_force_audio_cdclk(dev_priv, false);
>> +
>> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
>> }
>>
>> static void i915_audio_component_codec_wake_override(struct device *kdev,
>> @@ -959,7 +1017,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
>> /* continue with reduced functionality */
>> return;
>> }
>> -
>> + atomic_set(&dev_priv->get_put_refcount, 0);
>> dev_priv->audio_component_registered = true;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> index 704ddb4d3ca7..a0c281a90ff4 100644
>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> @@ -2143,19 +2143,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> /*
>> * According to BSpec, "The CD clock frequency must be at least twice
>> * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>> - *
>> - * FIXME: Check the actual, not default, BCLK being used.
>> - *
>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>> - * is required for audio probe, also when there are no audio capable
>> - * displays connected at probe time. This leads to unnecessarily high
>> - * CDCLK when audio is not required.
>> - *
>> - * FIXME: This limit is only applied when there are displays connected
>> - * at probe time. If we probe without displays, we'll still end up using
>> - * the platform minimum CDCLK, failing audio probe.
>> */
>> - if (INTEL_GEN(dev_priv) >= 9)
>> + if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
>> min_cdclk = max(2 * 96000, min_cdclk);
>>
>> /*
>> @@ -2195,7 +2184,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
>> intel_state->min_cdclk[i] = min_cdclk;
>> }
>>
>> - min_cdclk = 0;
>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>> for_each_pipe(dev_priv, pipe)
>> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>>
>> @@ -2256,7 +2245,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>> vlv_calc_voltage_level(dev_priv, cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>>
>> intel_state->cdclk.actual.cdclk = cdclk;
>> intel_state->cdclk.actual.voltage_level =
>> @@ -2289,7 +2278,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
>> bdw_calc_voltage_level(cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = bdw_calc_cdclk(0);
>> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>
>> intel_state->cdclk.actual.cdclk = cdclk;
>> intel_state->cdclk.actual.voltage_level =
>> @@ -2361,7 +2350,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> skl_calc_voltage_level(cdclk);
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = skl_calc_cdclk(0, vco);
>> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>
>> intel_state->cdclk.actual.vco = vco;
>> intel_state->cdclk.actual.cdclk = cdclk;
>> @@ -2400,10 +2389,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>>
>> if (!intel_state->active_crtcs) {
>> if (IS_GEMINILAKE(dev_priv)) {
>> - cdclk = glk_calc_cdclk(0);
>> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = glk_de_pll_vco(dev_priv, cdclk);
>> } else {
>> - cdclk = bxt_calc_cdclk(0);
>> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>> }
>>
>> @@ -2439,7 +2428,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> cnl_compute_min_voltage_level(intel_state));
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = cnl_calc_cdclk(0);
>> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>
>> intel_state->cdclk.actual.vco = vco;
>> @@ -2472,7 +2461,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> intel_state->cdclk.logical.cdclk = cdclk;
>>
>> if (!intel_state->active_crtcs) {
>> - cdclk = icl_calc_cdclk(0, ref);
>> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>
>> intel_state->cdclk.actual.vco = vco;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index cdfe0951d171..0b0e519fe844 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -12041,6 +12041,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>> return -EINVAL;
>> }
>>
>> + /* keep the current setting */
>> + if (!intel_state->modeset)
>> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
>> +
>> intel_state->modeset = true;
>> intel_state->active_crtcs = dev_priv->active_crtcs;
>> intel_state->cdclk.logical = dev_priv->cdclk.logical;
>> @@ -12136,7 +12140,7 @@ static int intel_atomic_check(struct drm_device *dev,
>> struct drm_crtc *crtc;
>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>> int ret, i;
>> - bool any_ms = false;
>> + bool any_ms = intel_state->modeset;
>>
>> /* Catch I915_MODE_FLAG_INHERITED */
>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>> @@ -12684,6 +12688,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>> dev_priv->active_crtcs = intel_state->active_crtcs;
>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
>> }
>>
>> drm_atomic_state_get(state);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 52337f487ebc..7b53f72d7242 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -461,6 +461,8 @@ struct intel_atomic_state {
>> * state only when all crtc's are DPMS off.
>> */
>> struct intel_cdclk_state actual;
>> +
>> + int force_min_cdclk;
>> } cdclk;
>>
>> bool dpll_set, modeset;
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-11 22:04 ` Kumar, Abhay
@ 2018-05-14 9:24 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2018-05-14 9:24 UTC (permalink / raw)
To: Kumar, Abhay, Ville Syrjälä; +Cc: intel-gfx, Syrjala, Ville
On Fri, 11 May 2018, "Kumar, Abhay" <abhay.kumar@intel.com> wrote:
> On 5/11/2018 5:33 AM, Ville Syrjälä wrote:
>> On Wed, May 09, 2018 at 06:25:32PM -0700, Abhay Kumar wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>>> driver has to probe using this hook and increase the clock even in
>>> absence of any display.
>>>
>>> v2: Use atomic refcount for get_power, put_power so that we can
>>> call each once(Abhay).
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 3 ++
>>> drivers/gpu/drm/i915/intel_audio.c | 66 +++++++++++++++++++++++++++++++++---
>>> drivers/gpu/drm/i915/intel_cdclk.c | 29 +++++-----------
>>> drivers/gpu/drm/i915/intel_display.c | 7 +++-
>>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>>> 5 files changed, 82 insertions(+), 25 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 24c5e4765afd..9c4ea767688a 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1692,6 +1692,7 @@ struct drm_i915_private {
>>> unsigned int hpll_freq;
>>> unsigned int fdi_pll_freq;
>>> unsigned int czclk_freq;
>>> + atomic_t get_put_refcount;
>>>
>>> struct {
>>> /*
>>> @@ -1709,6 +1710,8 @@ struct drm_i915_private {
>>> struct intel_cdclk_state actual;
>>> /* The current hardware cdclk state */
>>> struct intel_cdclk_state hw;
>>> +
>>> + int force_min_cdclk;
>>> } cdclk;
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>>> index 3ea566f99450..a1e2c4daae6e 100644
>>> --- a/drivers/gpu/drm/i915/intel_audio.c
>>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>>> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>>>
>>> if (!connector->eld[0])
>>> return;
>>> -
>>> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>>> connector->base.id,
>>> connector->name,
>>> @@ -713,14 +712,73 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>>> }
>>> }
>>>
>>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>>> + bool enable)
>>> +{
>>> + struct drm_modeset_acquire_ctx ctx;
>>> + struct drm_atomic_state *state;
>>> + int ret;
>>> +
>>> + drm_modeset_acquire_init(&ctx, 0);
>>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>>> + if (WARN_ON(!state))
>>> + return;
>>> +
>>> + state->acquire_ctx = &ctx;
>>> +
>>> +retry:
>>> + to_intel_atomic_state(state)->modeset = true;
>>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>>> + enable ? 2 * 96000 : 0;
>>> +
>>> + /*
>>> + * Protects dev_priv->cdclk.force_min_cdclk
>>> + * Need to lock this here in case we have no active pipes
>>> + * and thus wouldn't lock it during the commit otherwise.
>>> + */
>>> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
>>> + if (!ret)
>>> + ret = drm_atomic_commit(state);
>>> +
>>> + if (ret == -EDEADLK) {
>>> + drm_atomic_state_clear(state);
>>> + drm_modeset_backoff(&ctx);
>>> + goto retry;
>>> + }
>>> +
>>> + WARN_ON(ret);
>>> +
>>> + drm_atomic_state_put(state);
>>> +
>>> + drm_modeset_drop_locks(&ctx);
>>> + drm_modeset_acquire_fini(&ctx);
>>> +}
>>> +
>>> static void i915_audio_component_get_power(struct device *kdev)
>>> {
>>> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>>> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>>> +
>>> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
>>> + atomic_inc(&dev_priv->get_put_refcount);
>>> +
>>> + /* Force cdclk to 2*BCLK during first time get power call */
>>> + if (atomic_read(&dev_priv->get_put_refcount) == 1)
>> If it needs to be atomic (ie. we have concurrent callers of get/put_power())
>> then you would also need to do the inc+check atomically. But that in itself
>> wouldn't help because only the first caller would do the cdclk change,
>> and the second call would just immediately proceed without waiting for the
>> cdclk to actually have been changed.
>>
>> So the first question we should ask is whether we can even have
>> concurrent callers, or if there's some form of mutual exclusion
>> already on the caller side?
> As per my understanding I don't think we have any concurrent callers as
> these calls will be in sequence.
> Do you prefer to use static instead?
Static what?
BR,
Jani.
>>
>>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>> + glk_force_audio_cdclk(dev_priv, true);
>>> }
>>>
>>> static void i915_audio_component_put_power(struct device *kdev)
>>> {
>>> - intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>>> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>>> +
>>> + atomic_dec(&dev_priv->get_put_refcount);
>>> +
>>> + /* Force required cdclk during last time put power call */
>>> + if (atomic_read(&dev_priv->get_put_refcount) == 0)
>>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>>> + glk_force_audio_cdclk(dev_priv, false);
>>> +
>>> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
>>> }
>>>
>>> static void i915_audio_component_codec_wake_override(struct device *kdev,
>>> @@ -959,7 +1017,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
>>> /* continue with reduced functionality */
>>> return;
>>> }
>>> -
>>> + atomic_set(&dev_priv->get_put_refcount, 0);
>>> dev_priv->audio_component_registered = true;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>>> index 704ddb4d3ca7..a0c281a90ff4 100644
>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>> @@ -2143,19 +2143,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>>> /*
>>> * According to BSpec, "The CD clock frequency must be at least twice
>>> * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>>> - *
>>> - * FIXME: Check the actual, not default, BCLK being used.
>>> - *
>>> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
>>> - * is required for audio probe, also when there are no audio capable
>>> - * displays connected at probe time. This leads to unnecessarily high
>>> - * CDCLK when audio is not required.
>>> - *
>>> - * FIXME: This limit is only applied when there are displays connected
>>> - * at probe time. If we probe without displays, we'll still end up using
>>> - * the platform minimum CDCLK, failing audio probe.
>>> */
>>> - if (INTEL_GEN(dev_priv) >= 9)
>>> + if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
>>> min_cdclk = max(2 * 96000, min_cdclk);
>>>
>>> /*
>>> @@ -2195,7 +2184,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
>>> intel_state->min_cdclk[i] = min_cdclk;
>>> }
>>>
>>> - min_cdclk = 0;
>>> + min_cdclk = intel_state->cdclk.force_min_cdclk;
>>> for_each_pipe(dev_priv, pipe)
>>> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>>>
>>> @@ -2256,7 +2245,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> vlv_calc_voltage_level(dev_priv, cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = vlv_calc_cdclk(dev_priv, 0);
>>> + cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
>>>
>>> intel_state->cdclk.actual.cdclk = cdclk;
>>> intel_state->cdclk.actual.voltage_level =
>>> @@ -2289,7 +2278,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> bdw_calc_voltage_level(cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = bdw_calc_cdclk(0);
>>> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>>
>>> intel_state->cdclk.actual.cdclk = cdclk;
>>> intel_state->cdclk.actual.voltage_level =
>>> @@ -2361,7 +2350,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> skl_calc_voltage_level(cdclk);
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = skl_calc_cdclk(0, vco);
>>> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>>>
>>> intel_state->cdclk.actual.vco = vco;
>>> intel_state->cdclk.actual.cdclk = cdclk;
>>> @@ -2400,10 +2389,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>>>
>>> if (!intel_state->active_crtcs) {
>>> if (IS_GEMINILAKE(dev_priv)) {
>>> - cdclk = glk_calc_cdclk(0);
>>> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = glk_de_pll_vco(dev_priv, cdclk);
>>> } else {
>>> - cdclk = bxt_calc_cdclk(0);
>>> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = bxt_de_pll_vco(dev_priv, cdclk);
>>> }
>>>
>>> @@ -2439,7 +2428,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> cnl_compute_min_voltage_level(intel_state));
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = cnl_calc_cdclk(0);
>>> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>>> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>>
>>> intel_state->cdclk.actual.vco = vco;
>>> @@ -2472,7 +2461,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> intel_state->cdclk.logical.cdclk = cdclk;
>>>
>>> if (!intel_state->active_crtcs) {
>>> - cdclk = icl_calc_cdclk(0, ref);
>>> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
>>> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>>>
>>> intel_state->cdclk.actual.vco = vco;
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index cdfe0951d171..0b0e519fe844 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -12041,6 +12041,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>>> return -EINVAL;
>>> }
>>>
>>> + /* keep the current setting */
>>> + if (!intel_state->modeset)
>>> + intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
>>> +
>>> intel_state->modeset = true;
>>> intel_state->active_crtcs = dev_priv->active_crtcs;
>>> intel_state->cdclk.logical = dev_priv->cdclk.logical;
>>> @@ -12136,7 +12140,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>> struct drm_crtc *crtc;
>>> struct drm_crtc_state *old_crtc_state, *crtc_state;
>>> int ret, i;
>>> - bool any_ms = false;
>>> + bool any_ms = intel_state->modeset;
>>>
>>> /* Catch I915_MODE_FLAG_INHERITED */
>>> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
>>> @@ -12684,6 +12688,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>>> dev_priv->active_crtcs = intel_state->active_crtcs;
>>> dev_priv->cdclk.logical = intel_state->cdclk.logical;
>>> dev_priv->cdclk.actual = intel_state->cdclk.actual;
>>> + dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
>>> }
>>>
>>> drm_atomic_state_get(state);
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>>> index 52337f487ebc..7b53f72d7242 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -461,6 +461,8 @@ struct intel_atomic_state {
>>> * state only when all crtc's are DPMS off.
>>> */
>>> struct intel_cdclk_state actual;
>>> +
>>> + int force_min_cdclk;
>>> } cdclk;
>>>
>>> bool dpll_set, modeset;
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-05-10 1:25 ` [PATCH v2] " Abhay Kumar
2018-05-11 12:33 ` Ville Syrjälä
@ 2018-06-12 7:17 ` Abhay Kumar
2018-06-12 12:13 ` Ville Syrjälä
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
1 sibling, 2 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-06-12 7:17 UTC (permalink / raw)
To: intel-gfx, ville.syrjala; +Cc: jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_audio.c | 87 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++--------
drivers/gpu/drm/i915/intel_display.c | 7 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
6 files changed, 107 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6104d7115054..a4a386a5db69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1702,6 +1702,7 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ u32 get_put_refcount;
struct {
/*
@@ -1719,6 +1720,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def26ce82..cef770184245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,10 @@ enum skl_power_gate {
* SKL Clocks
*/
+/* Power well 2 */
+#define POWER_WELL_2 _MMIO(0x45404)
+#define POWER_WELL_2_REQUEST (1<<31)
+
/* CDCLK_CTL */
#define CDCLK_CTL _MMIO(0x46000)
#define CDCLK_FREQ_SEL_MASK (3 << 26)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..1f5a9af13ef0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!connector->eld[0])
return;
-
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
connector->name,
@@ -713,14 +712,94 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+ * Protects dev_priv->cdclk.force_min_cdclk
+ * Need to lock this here in case we have no active pipes
+ * and thus wouldn't lock it during the commit otherwise.
+ */
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
- intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+ u32 tmp;
+
+ dev_priv->get_put_refcount++;
+
+ /* Force cdclk to 2*BCLK during first time get power call */
+ if (dev_priv->get_put_refcount == 1) {
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+
+ /*FIXME: Make sure there is no transaction
+ * on iDisp link while changing cdclk
+ */
+
+ /* Turn off power well 2*/
+ tmp = I915_READ(POWER_WELL_2);
+ tmp = tmp & ~POWER_WELL_2_REQUEST;
+ I915_WRITE(POWER_WELL_2, tmp);
+ tmp = I915_READ(POWER_WELL_2);
+
+ /* Turn on power well 2*/
+ tmp = I915_READ(POWER_WELL_2);
+ tmp = tmp | POWER_WELL_2_REQUEST;
+ I915_WRITE(POWER_WELL_2, tmp);
+ tmp = I915_READ(POWER_WELL_2);
+
+ glk_force_audio_cdclk(dev_priv, true);
+ }
+ }
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_put_power(struct device *kdev)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ dev_priv->get_put_refcount--;
+
+ /* Force required cdclk during last time put power call */
+ if (dev_priv->get_put_refcount == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
@@ -959,7 +1038,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
/* continue with reduced functionality */
return;
}
-
+ dev_priv->get_put_refcount = 0;
dev_priv->audio_component_registered = true;
}
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 8ed7bd052e46..0f0aea900ceb 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2153,19 +2153,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/*
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
- *
- * FIXME: Check the actual, not default, BCLK being used.
- *
- * FIXME: This does not depend on ->has_audio because the higher CDCLK
- * is required for audio probe, also when there are no audio capable
- * displays connected at probe time. This leads to unnecessarily high
- * CDCLK when audio is not required.
- *
- * FIXME: This limit is only applied when there are displays connected
- * at probe time. If we probe without displays, we'll still end up using
- * the platform minimum CDCLK, failing audio probe.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2205,7 +2194,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
intel_state->min_cdclk[i] = min_cdclk;
}
- min_cdclk = 0;
+ min_cdclk = intel_state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
@@ -2266,7 +2255,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
- cdclk = vlv_calc_cdclk(dev_priv, 0);
+ cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2299,7 +2288,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = bdw_calc_cdclk(0);
+ cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2371,7 +2360,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = skl_calc_cdclk(0, vco);
+ cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
@@ -2410,10 +2399,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
- cdclk = glk_calc_cdclk(0);
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = glk_de_pll_vco(dev_priv, cdclk);
} else {
- cdclk = bxt_calc_cdclk(0);
+ cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
@@ -2449,7 +2438,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = cnl_calc_cdclk(0);
+ cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
@@ -2482,7 +2471,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
if (!intel_state->active_crtcs) {
- cdclk = icl_calc_cdclk(0, ref);
+ cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 17c590b42fd7..3ee1c1f5419d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12162,6 +12162,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return -EINVAL;
}
+ /* keep the current setting */
+ if (!intel_state->modeset)
+ intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
intel_state->modeset = true;
intel_state->active_crtcs = dev_priv->active_crtcs;
intel_state->cdclk.logical = dev_priv->cdclk.logical;
@@ -12257,7 +12261,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *crtc_state;
int ret, i;
- bool any_ms = false;
+ bool any_ms = intel_state->modeset;
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -12805,6 +12809,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
+ dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8641583842be..0da17ad056ec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -459,6 +459,8 @@ struct intel_atomic_state {
* state only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
+
+ int force_min_cdclk;
} cdclk;
bool dpll_set, modeset;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (10 preceding siblings ...)
2018-05-10 4:35 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-06-12 7:28 ` Patchwork
2018-06-12 7:29 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-06-12 7:28 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7e66d7400ee9 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-:53: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#53: FILE: drivers/gpu/drm/i915/i915_reg.h:8874:
+#define POWER_WELL_2_REQUEST (1<<31)
^
-:75: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#75: FILE: drivers/gpu/drm/i915/intel_audio.c:716:
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
-:127: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#127: FILE: drivers/gpu/drm/i915/intel_audio.c:767:
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+
-:240: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 25)
#240: FILE: drivers/gpu/drm/i915/intel_cdclk.c:2401:
if (IS_GEMINILAKE(dev_priv)) {
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
total: 0 errors, 1 warnings, 3 checks, 249 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (11 preceding siblings ...)
2018-06-12 7:28 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) Patchwork
@ 2018-06-12 7:29 ` Patchwork
2018-06-12 7:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12 8:37 ` ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-06-12 7:29 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/42459/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
-O:drivers/gpu/drm/i915/intel_cdclk.c:2169:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2158:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2210:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_cdclk.c:2210:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2199:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_cdclk.c:2199:29: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3680:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (12 preceding siblings ...)
2018-06-12 7:29 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-06-12 7:48 ` Patchwork
2018-06-12 8:37 ` ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2018-06-12 7:48 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4304 -> Patchwork_9268 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9268 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9268, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42459/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9268:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9268 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_frontbuffer_tracking@basic:
fi-hsw-4200u: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-glk-j4005: PASS -> INCOMPLETE (fdo#103359, k.org#198133)
==== Possible fixes ====
igt@kms_flip@basic-plain-flip:
fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS +1
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (42 -> 38) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4304 -> Patchwork_9268
CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7e66d7400ee9 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (13 preceding siblings ...)
2018-06-12 7:48 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-06-12 8:37 ` Patchwork
2018-06-12 18:09 ` Saarinen, Jani
14 siblings, 1 reply; 36+ messages in thread
From: Patchwork @ 2018-06-12 8:37 UTC (permalink / raw)
To: Abhay Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
URL : https://patchwork.freedesktop.org/series/42459/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9268_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9268_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9268_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: PASS -> SKIP
igt@gem_exec_schedule@deep-vebox:
shard-kbl: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9268_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-hsw: PASS -> FAIL (fdo#102887)
igt@kms_setmode@basic:
shard-kbl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@drv_selftest@live_gtt:
shard-kbl: FAIL (fdo#105347) -> PASS
igt@drv_suspend@shrink:
shard-hsw: INCOMPLETE (fdo#103540) -> PASS
igt@kms_rotation_crc@sprite-rotation-180:
shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 4) ==
Missing (1): shard-glk
== Build changes ==
* Linux: CI_DRM_4304 -> Patchwork_9268
CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-06-12 7:17 ` [PATCH v3] " Abhay Kumar
@ 2018-06-12 12:13 ` Ville Syrjälä
2018-06-12 16:27 ` Kumar, Abhay
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
1 sibling, 1 reply; 36+ messages in thread
From: Ville Syrjälä @ 2018-06-12 12:13 UTC (permalink / raw)
To: Abhay Kumar; +Cc: jani.nikula, intel-gfx, ville.syrjala
On Tue, Jun 12, 2018 at 12:17:41AM -0700, Abhay Kumar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> v2: Use atomic refcount for get_power, put_power so that we can
> call each once(Abhay).
> v3: Reset power well 2 to avoid any transaction on iDisp link
> during cdclk change(Abhay).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> drivers/gpu/drm/i915/intel_audio.c | 87 ++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++--------
> drivers/gpu/drm/i915/intel_display.c | 7 ++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 6 files changed, 107 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6104d7115054..a4a386a5db69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1702,6 +1702,7 @@ struct drm_i915_private {
> unsigned int hpll_freq;
> unsigned int fdi_pll_freq;
> unsigned int czclk_freq;
> + u32 get_put_refcount;
>
> struct {
> /*
> @@ -1719,6 +1720,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 987def26ce82..cef770184245 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8869,6 +8869,10 @@ enum skl_power_gate {
> * SKL Clocks
> */
>
> +/* Power well 2 */
> +#define POWER_WELL_2 _MMIO(0x45404)
> +#define POWER_WELL_2_REQUEST (1<<31)
> +
> /* CDCLK_CTL */
> #define CDCLK_CTL _MMIO(0x46000)
> #define CDCLK_FREQ_SEL_MASK (3 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..1f5a9af13ef0 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>
> if (!connector->eld[0])
> return;
> -
> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
> connector->base.id,
> connector->name,
> @@ -713,14 +712,94 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(&ctx, 0);
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx = &ctx;
> +
> +retry:
> + to_intel_atomic_state(state)->modeset = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> static void i915_audio_component_get_power(struct device *kdev)
> {
> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> + u32 tmp;
> +
> + dev_priv->get_put_refcount++;
> +
> + /* Force cdclk to 2*BCLK during first time get power call */
> + if (dev_priv->get_put_refcount == 1) {
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> +
> + /*FIXME: Make sure there is no transaction
> + * on iDisp link while changing cdclk
> + */
> +
> + /* Turn off power well 2*/
> + tmp = I915_READ(POWER_WELL_2);
> + tmp = tmp & ~POWER_WELL_2_REQUEST;
> + I915_WRITE(POWER_WELL_2, tmp);
> + tmp = I915_READ(POWER_WELL_2);
> +
> + /* Turn on power well 2*/
> + tmp = I915_READ(POWER_WELL_2);
> + tmp = tmp | POWER_WELL_2_REQUEST;
> + I915_WRITE(POWER_WELL_2, tmp);
> + tmp = I915_READ(POWER_WELL_2);
You can't just shut down the power well like that.
Things may be using it.
> +
> + glk_force_audio_cdclk(dev_priv, true);
> + }
> + }
> +
> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> }
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-06-12 12:13 ` Ville Syrjälä
@ 2018-06-12 16:27 ` Kumar, Abhay
0 siblings, 0 replies; 36+ messages in thread
From: Kumar, Abhay @ 2018-06-12 16:27 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx, Syrjala, Ville
On 6/12/2018 5:13 AM, Ville Syrjälä wrote:
> On Tue, Jun 12, 2018 at 12:17:41AM -0700, Abhay Kumar wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> CDCLK has to be at least twice the BLCK regardless of audio. Audio
>> driver has to probe using this hook and increase the clock even in
>> absence of any display.
>>
>> v2: Use atomic refcount for get_power, put_power so that we can
>> call each once(Abhay).
>> v3: Reset power well 2 to avoid any transaction on iDisp link
>> during cdclk change(Abhay).
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 3 ++
>> drivers/gpu/drm/i915/i915_reg.h | 4 ++
>> drivers/gpu/drm/i915/intel_audio.c | 87 ++++++++++++++++++++++++++++++++++--
>> drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++--------
>> drivers/gpu/drm/i915/intel_display.c | 7 ++-
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 6 files changed, 107 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 6104d7115054..a4a386a5db69 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1702,6 +1702,7 @@ struct drm_i915_private {
>> unsigned int hpll_freq;
>> unsigned int fdi_pll_freq;
>> unsigned int czclk_freq;
>> + u32 get_put_refcount;
>>
>> struct {
>> /*
>> @@ -1719,6 +1720,8 @@ struct drm_i915_private {
>> struct intel_cdclk_state actual;
>> /* The current hardware cdclk state */
>> struct intel_cdclk_state hw;
>> +
>> + int force_min_cdclk;
>> } cdclk;
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 987def26ce82..cef770184245 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8869,6 +8869,10 @@ enum skl_power_gate {
>> * SKL Clocks
>> */
>>
>> +/* Power well 2 */
>> +#define POWER_WELL_2 _MMIO(0x45404)
>> +#define POWER_WELL_2_REQUEST (1<<31)
>> +
>> /* CDCLK_CTL */
>> #define CDCLK_CTL _MMIO(0x46000)
>> #define CDCLK_FREQ_SEL_MASK (3 << 26)
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>> index 3ea566f99450..1f5a9af13ef0 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>>
>> if (!connector->eld[0])
>> return;
>> -
>> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>> connector->base.id,
>> connector->name,
>> @@ -713,14 +712,94 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>> }
>> }
>>
>> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
>> + bool enable)
>> +{
>> + struct drm_modeset_acquire_ctx ctx;
>> + struct drm_atomic_state *state;
>> + int ret;
>> +
>> + drm_modeset_acquire_init(&ctx, 0);
>> + state = drm_atomic_state_alloc(&dev_priv->drm);
>> + if (WARN_ON(!state))
>> + return;
>> +
>> + state->acquire_ctx = &ctx;
>> +
>> +retry:
>> + to_intel_atomic_state(state)->modeset = true;
>> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
>> + enable ? 2 * 96000 : 0;
>> +
>> + /*
>> + * Protects dev_priv->cdclk.force_min_cdclk
>> + * Need to lock this here in case we have no active pipes
>> + * and thus wouldn't lock it during the commit otherwise.
>> + */
>> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
>> + if (!ret)
>> + ret = drm_atomic_commit(state);
>> +
>> + if (ret == -EDEADLK) {
>> + drm_atomic_state_clear(state);
>> + drm_modeset_backoff(&ctx);
>> + goto retry;
>> + }
>> +
>> + WARN_ON(ret);
>> +
>> + drm_atomic_state_put(state);
>> +
>> + drm_modeset_drop_locks(&ctx);
>> + drm_modeset_acquire_fini(&ctx);
>> +}
>> +
>> static void i915_audio_component_get_power(struct device *kdev)
>> {
>> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
>> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>> + u32 tmp;
>> +
>> + dev_priv->get_put_refcount++;
>> +
>> + /* Force cdclk to 2*BCLK during first time get power call */
>> + if (dev_priv->get_put_refcount == 1) {
>> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>> +
>> + /*FIXME: Make sure there is no transaction
>> + * on iDisp link while changing cdclk
>> + */
>> +
>> + /* Turn off power well 2*/
>> + tmp = I915_READ(POWER_WELL_2);
>> + tmp = tmp & ~POWER_WELL_2_REQUEST;
>> + I915_WRITE(POWER_WELL_2, tmp);
>> + tmp = I915_READ(POWER_WELL_2);
>> +
>> + /* Turn on power well 2*/
>> + tmp = I915_READ(POWER_WELL_2);
>> + tmp = tmp | POWER_WELL_2_REQUEST;
>> + I915_WRITE(POWER_WELL_2, tmp);
>> + tmp = I915_READ(POWER_WELL_2);
> You can't just shut down the power well like that.
> Things may be using it.
HI Ville,
I think then your other patch to reset pw2 with any cdclk change
only for glk should be good. Anyway when external monitor is connected
it will bump up clock to max and from then there is no cdclk chagne
so no chances of audio break ateast for GLK for which that patch is
applicable.
How about that way?
Thanks
Abhay
>
>> +
>> + glk_force_audio_cdclk(dev_priv, true);
>> + }
>> + }
>> +
>> + intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
>> }
_______________________________________________
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-06-12 8:37 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-06-12 18:09 ` Saarinen, Jani
2018-06-12 23:51 ` Kumar, Abhay
0 siblings, 1 reply; 36+ messages in thread
From: Saarinen, Jani @ 2018-06-12 18:09 UTC (permalink / raw)
To: intel-gfx, Kumar, Abhay, Sarvela, Tomi P
HI,
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Patchwork
> Sent: tiistai 12. kesäkuuta 2018 11.38
> To: Kumar, Abhay <abhay.kumar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on
> glk/cnl when audio power is enabled (rev3)
>
> == Series Details ==
>
> Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is
> enabled (rev3)
> URL : https://patchwork.freedesktop.org/series/42459/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full =
>
> == Summary - WARNING ==
>
> Minor unknown changes coming with Patchwork_9268_full need to be
> verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_9268_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in
> Patchwork_9268_full:
>
> === IGT changes ===
>
> ==== Warnings ====
>
> igt@gem_exec_schedule@deep-bsd2:
> shard-kbl: PASS -> SKIP
>
> igt@gem_exec_schedule@deep-vebox:
> shard-kbl: SKIP -> PASS
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_9268_full that come from known
> issues:
>
> === IGT changes ===
>
> ==== Issues hit ====
>
> igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
> shard-hsw: PASS -> FAIL (fdo#102887)
>
> igt@kms_setmode@basic:
> shard-kbl: PASS -> FAIL (fdo#99912)
>
>
> ==== Possible fixes ====
>
> igt@drv_selftest@live_gtt:
> shard-kbl: FAIL (fdo#105347) -> PASS
>
> igt@drv_suspend@shrink:
> shard-hsw: INCOMPLETE (fdo#103540) -> PASS
>
> igt@kms_rotation_crc@sprite-rotation-180:
> shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS
>
>
> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
> fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
> fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
> fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
> fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> == Participating hosts (5 -> 4) ==
>
> Missing (1): shard-glk
There glk's are but some issues:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk1/
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk2/run2.log
etc...
Worth to investigate...
+ Tomi too.
>
>
> == Build changes ==
>
> * Linux: CI_DRM_4304 -> Patchwork_9268
>
> CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_9268/shards.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK
2018-06-12 7:17 ` [PATCH v3] " Abhay Kumar
2018-06-12 12:13 ` Ville Syrjälä
@ 2018-06-12 21:58 ` Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
` (2 more replies)
1 sibling, 3 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-06-12 21:58 UTC (permalink / raw)
To: intel-gfx, ville.syrjala; +Cc: jani.nikula
Patches needed to change cdclk to 2*BCLK before accessing HDA Codec.
Ville Syrjälä (2):
drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
drm/i915: Shut off PW2 when changing cdclk on glk
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_audio.c | 67 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_cdclk.c | 43 +++++++++++----------
drivers/gpu/drm/i915/intel_display.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 7 ++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++
7 files changed, 140 insertions(+), 25 deletions(-)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
@ 2018-06-12 21:58 ` Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk Abhay Kumar
2018-06-13 12:27 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Ville Syrjälä
2 siblings, 0 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-06-12 21:58 UTC (permalink / raw)
To: intel-gfx, ville.syrjala; +Cc: jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
v4: Remove Power well 2 reset workaround(Ville).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_audio.c | 67 +++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_cdclk.c | 29 +++++-----------
drivers/gpu/drm/i915/intel_display.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 ++
6 files changed, 87 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6104d7115054..a4a386a5db69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1702,6 +1702,7 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ u32 get_put_refcount;
struct {
/*
@@ -1719,6 +1720,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def26ce82..cef770184245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,10 @@ enum skl_power_gate {
* SKL Clocks
*/
+/* Power well 2 */
+#define POWER_WELL_2 _MMIO(0x45404)
+#define POWER_WELL_2_REQUEST (1<<31)
+
/* CDCLK_CTL */
#define CDCLK_CTL _MMIO(0x46000)
#define CDCLK_FREQ_SEL_MASK (3 << 26)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..ca8f04c7cbb3 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!connector->eld[0])
return;
-
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
connector->name,
@@ -713,14 +712,74 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+ * Protects dev_priv->cdclk.force_min_cdclk
+ * Need to lock this here in case we have no active pipes
+ * and thus wouldn't lock it during the commit otherwise.
+ */
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
- intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ dev_priv->get_put_refcount++;
+
+ /* Force cdclk to 2*BCLK during first time get power call */
+ if (dev_priv->get_put_refcount == 1)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_put_power(struct device *kdev)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ dev_priv->get_put_refcount--;
+
+ /* Force required cdclk during last time put power call */
+ if (dev_priv->get_put_refcount == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
@@ -959,7 +1018,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
/* continue with reduced functionality */
return;
}
-
+ dev_priv->get_put_refcount = 0;
dev_priv->audio_component_registered = true;
}
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 8ed7bd052e46..0f0aea900ceb 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2153,19 +2153,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/*
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
- *
- * FIXME: Check the actual, not default, BCLK being used.
- *
- * FIXME: This does not depend on ->has_audio because the higher CDCLK
- * is required for audio probe, also when there are no audio capable
- * displays connected at probe time. This leads to unnecessarily high
- * CDCLK when audio is not required.
- *
- * FIXME: This limit is only applied when there are displays connected
- * at probe time. If we probe without displays, we'll still end up using
- * the platform minimum CDCLK, failing audio probe.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2205,7 +2194,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
intel_state->min_cdclk[i] = min_cdclk;
}
- min_cdclk = 0;
+ min_cdclk = intel_state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
@@ -2266,7 +2255,7 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
- cdclk = vlv_calc_cdclk(dev_priv, 0);
+ cdclk = vlv_calc_cdclk(dev_priv, intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2299,7 +2288,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = bdw_calc_cdclk(0);
+ cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2371,7 +2360,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = skl_calc_cdclk(0, vco);
+ cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
@@ -2410,10 +2399,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
- cdclk = glk_calc_cdclk(0);
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = glk_de_pll_vco(dev_priv, cdclk);
} else {
- cdclk = bxt_calc_cdclk(0);
+ cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
@@ -2449,7 +2438,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = cnl_calc_cdclk(0);
+ cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
@@ -2482,7 +2471,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
if (!intel_state->active_crtcs) {
- cdclk = icl_calc_cdclk(0, ref);
+ cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 17c590b42fd7..3ee1c1f5419d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12162,6 +12162,10 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return -EINVAL;
}
+ /* keep the current setting */
+ if (!intel_state->modeset)
+ intel_state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
+
intel_state->modeset = true;
intel_state->active_crtcs = dev_priv->active_crtcs;
intel_state->cdclk.logical = dev_priv->cdclk.logical;
@@ -12257,7 +12261,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *crtc_state;
int ret, i;
- bool any_ms = false;
+ bool any_ms = intel_state->modeset;
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -12805,6 +12809,7 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
+ dev_priv->cdclk.force_min_cdclk = intel_state->cdclk.force_min_cdclk;
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8641583842be..0da17ad056ec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -459,6 +459,8 @@ struct intel_atomic_state {
* state only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
+
+ int force_min_cdclk;
} cdclk;
bool dpll_set, modeset;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
@ 2018-06-12 21:58 ` Abhay Kumar
2018-06-13 12:27 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Ville Syrjälä
2 siblings, 0 replies; 36+ messages in thread
From: Abhay Kumar @ 2018-06-12 21:58 UTC (permalink / raw)
To: intel-gfx, ville.syrjala; +Cc: jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently the audio hardware gets confused if it's powered up when
change the cdclk frequency. Force PW2 (which is where audio lives)
off when we do the cdclk reprogramming.
This is a rather big hack. If something is using PW2 when we do this
things wil break. I don't think there should be anything active on
the display side since we've turned off all the pipes and we've locked
out gmbus and aux, but I may be overlooking something. The problem
is more on the audio side. If audio is active when we do this PW2
toggle I'm sure something "interesting" will happen. But presumably
something would also happen if we just changed cdclk without the PW2
toggle.
A better fix would involve somehow forcing everything to drop
their PW2 references, which isn't trivial. And to make the audio driver
participate in this scheme we'd definitely need some kind of pre/post
cdclk change notify hooks in the audio component so that i915 can
actually inform the audio driver that the cdclk is going to be changed.
Either that or the audio driver would have to promise never to touch
the hardware when the pipes are off (which is how the VLV/CHV LPE
audio driver works IIRC).
Even with this hacky scheme it would make more sense to me to have
the pre/post cdclk change hooks so that the audio driver is actually
informed when the cdclk change/pw2 toggle will occur. What the audio
driver would do to prepare itself I don't actually know.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 14 ++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 5 +++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++++++++++++++++++
3 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 0f0aea900ceb..6557f1e9cf9e 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1356,6 +1356,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
+ bool enable_pw2 = false;
u32 val, divider;
int ret;
@@ -1381,6 +1382,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
}
/*
+ * On GLK HDA apparently gets confused if
+ * cdclk is changed while PW2 is on
+ */
+ if (IS_GEMINILAKE(dev_priv))
+ enable_pw2 = intel_display_power_toggle_start(dev_priv,
+ SKL_DISP_PW_2);
+
+ /*
* Inform power controller of upcoming frequency change. BSpec
* requires us to wait up to 150usec, but that leads to timeouts;
* the 2ms used here is based on experiment.
@@ -1437,6 +1446,11 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
}
intel_update_cdclk(dev_priv);
+
+ if (IS_GEMINILAKE(dev_priv))
+ intel_display_power_toggle_end(dev_priv,
+ SKL_DISP_PW_2,
+ enable_pw2);
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0da17ad056ec..c4fc107ad8cd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1950,6 +1950,11 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+bool intel_display_power_toggle_start(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id);
+void intel_display_power_toggle_end(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id,
+ bool enable);
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 53a6eaa9671a..86a4b788e224 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2809,6 +2809,40 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
}
+bool intel_display_power_toggle_start(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *well = lookup_power_well(dev_priv, power_well_id);
+ bool was_enabled;
+
+ mutex_lock(&power_domains->lock);
+
+ was_enabled = well->hw_enabled;
+
+ if (was_enabled)
+ intel_power_well_disable(dev_priv, well);
+
+ return was_enabled;
+}
+
+void intel_display_power_toggle_end(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id,
+ bool enable)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *well = lookup_power_well(dev_priv, power_well_id);
+
+ lockdep_assert_held(&power_domains->lock);
+
+ if (enable) {
+ WARN_ON(well->hw_enabled);
+ intel_power_well_enable(dev_priv, well);
+ }
+
+ mutex_unlock(&power_domains->lock);
+}
+
void bxt_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
2018-06-12 18:09 ` Saarinen, Jani
@ 2018-06-12 23:51 ` Kumar, Abhay
0 siblings, 0 replies; 36+ messages in thread
From: Kumar, Abhay @ 2018-06-12 23:51 UTC (permalink / raw)
To: Saarinen, Jani, intel-gfx, Sarvela, Tomi P
On 6/12/2018 11:09 AM, Saarinen, Jani wrote:
> HI,
>
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Patchwork
>> Sent: tiistai 12. kesäkuuta 2018 11.38
>> To: Kumar, Abhay <abhay.kumar@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on
>> glk/cnl when audio power is enabled (rev3)
>>
>> == Series Details ==
>>
>> Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is
>> enabled (rev3)
>> URL : https://patchwork.freedesktop.org/series/42459/
>> State : success
>>
>> == Summary ==
>>
>> = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full =
>>
>> == Summary - WARNING ==
>>
>> Minor unknown changes coming with Patchwork_9268_full need to be
>> verified
>> manually.
>>
>> If you think the reported changes have nothing to do with the changes
>> introduced in Patchwork_9268_full, please notify your bug team to allow
>> them
>> to document this new failure mode, which will reduce false positives in CI.
>>
>>
>>
>> == Possible new issues ==
>>
>> Here are the unknown changes that may have been introduced in
>> Patchwork_9268_full:
>>
>> === IGT changes ===
>>
>> ==== Warnings ====
>>
>> igt@gem_exec_schedule@deep-bsd2:
>> shard-kbl: PASS -> SKIP
>>
>> igt@gem_exec_schedule@deep-vebox:
>> shard-kbl: SKIP -> PASS
>>
>>
>> == Known issues ==
>>
>> Here are the changes found in Patchwork_9268_full that come from known
>> issues:
>>
>> === IGT changes ===
>>
>> ==== Issues hit ====
>>
>> igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
>> shard-hsw: PASS -> FAIL (fdo#102887)
>>
>> igt@kms_setmode@basic:
>> shard-kbl: PASS -> FAIL (fdo#99912)
>>
>>
>> ==== Possible fixes ====
>>
>> igt@drv_selftest@live_gtt:
>> shard-kbl: FAIL (fdo#105347) -> PASS
>>
>> igt@drv_suspend@shrink:
>> shard-hsw: INCOMPLETE (fdo#103540) -> PASS
>>
>> igt@kms_rotation_crc@sprite-rotation-180:
>> shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS
>>
>>
>> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
>> fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
>> fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
>> fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
>> fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
>> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
>>
>>
>> == Participating hosts (5 -> 4) ==
>>
>> Missing (1): shard-glk
> There glk's are but some issues:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk1/
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk2/run2.log
> etc...
>
> Worth to investigate...
May be this is due to turning off and on Power well 2. Sent another
patchset where we restart power well2 for any cdclk change only for glk.
>
> + Tomi too.
>
>>
>> == Build changes ==
>>
>> * Linux: CI_DRM_4304 -> Patchwork_9268
>>
>> CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @
>> git://anongit.freedesktop.org/gfx-ci/linux
>> IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @
>> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>> Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @
>> git://anongit.freedesktop.org/gfx-ci/linux
>> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
>> git://anongit.freedesktop.org/piglit
>>
>> == Logs ==
>>
>> For more details see: https://intel-gfx-ci.01.org/tree/drm-
>> tip/Patchwork_9268/shards.html
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk Abhay Kumar
@ 2018-06-13 12:27 ` Ville Syrjälä
2 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2018-06-13 12:27 UTC (permalink / raw)
To: Abhay Kumar; +Cc: jani.nikula, intel-gfx, ville.syrjala
On Tue, Jun 12, 2018 at 02:58:45PM -0700, Abhay Kumar wrote:
> Patches needed to change cdclk to 2*BCLK before accessing HDA Codec.
>
> Ville Syrjälä (2):
> drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
> drm/i915: Shut off PW2 when changing cdclk on glk
Patchwork is probably totally confused by the threading here, so I
doubt you will get any testing report for this.
Also these two alone aren't sufficient. You'll need at least the
other two patches from the pw2 toggle branch.
>
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> drivers/gpu/drm/i915/intel_audio.c | 67 +++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_cdclk.c | 43 +++++++++++----------
> drivers/gpu/drm/i915/intel_display.c | 7 +++-
> drivers/gpu/drm/i915/intel_drv.h | 7 ++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++
> 7 files changed, 140 insertions(+), 25 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
2019-05-24 3:41 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Jian-Hong Pan
@ 2019-05-31 5:20 ` Jian-Hong Pan
0 siblings, 0 replies; 36+ messages in thread
From: Jian-Hong Pan @ 2019-05-31 5:20 UTC (permalink / raw)
To: stable
Cc: Linux Upstreaming Team, Takashi Iwai, Ville Syrjälä,
Abhay Kumar, Imre Deak, Clint Taylor
Jian-Hong Pan <jian-hong@endlessm.com> 於 2019年5月24日 週五 上午11:42寫道：
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> commit 905801fe72377b4dc53c6e13eea1a91c6a4aa0c4 upstream.
>
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> v2: Use atomic refcount for get_power, put_power so that we can
> call each once(Abhay).
> v3: Reset power well 2 to avoid any transaction on iDisp link
> during cdclk change(Abhay).
> v4: Remove Power well 2 reset workaround(Ville).
> v5: Remove unwanted Power well 2 register defined in v4(Abhay).
> v6:
> - Use a dedicated flag instead of state->modeset for min CDCLK changes
> - Make get/put audio power domain symmetric
> - Rebased on top of intel_wakeref tracking changes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> Tested-by: Abhay Kumar <abhay.kumar@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190320135439.12201-1-imre.deak@intel.com
> Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=203623
> Cc: <stable@vger.kernel.org> # 5.1.x: d31c85fc8642 snd/hda, drm/i915: Track the display_power_status using a cookie
> Cc: <stable@vger.kernel.org> # 5.1.x
> Signed-off-by: Jian-Hong Pan <jian-hong@endlessm.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/intel_audio.c | 64 +++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_cdclk.c | 30 +++++--------
> drivers/gpu/drm/i915/intel_display.c | 9 +++-
> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> 5 files changed, 86 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a67a63b5aa84..5c9bb1b2d1f3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1622,6 +1622,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> @@ -1741,6 +1743,7 @@ struct drm_i915_private {
> *
> */
> struct mutex av_mutex;
> + int audio_power_refcount;
>
> struct {
> struct mutex mutex;
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 502b57ce72ab..20324b0d34c7 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -741,18 +741,78 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(&ctx, 0);
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx = &ctx;
> +
> +retry:
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
> + &ctx);
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> static unsigned long i915_audio_component_get_power(struct device *kdev)
> {
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> + intel_wakeref_t ret;
> +
> /* Catch potential impedance mismatches before they occur! */
> BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
>
> - return intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> + ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> +
> + /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
> + if (dev_priv->audio_power_refcount++ == 0)
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, true);
> +
> + return ret;
> }
>
> static void i915_audio_component_put_power(struct device *kdev,
> unsigned long cookie)
> {
> - intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO, cookie);
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +
> + /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
> + if (--dev_priv->audio_power_refcount == 0)
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + glk_force_audio_cdclk(dev_priv, false);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
> }
>
> static void i915_audio_component_codec_wake_override(struct device *kdev,
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 15ba950dee00..553f57ff60f4 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2187,19 +2187,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /*
> * According to BSpec, "The CD clock frequency must be at least twice
> * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> - *
> - * FIXME: Check the actual, not default, BCLK being used.
> - *
> - * FIXME: This does not depend on ->has_audio because the higher CDCLK
> - * is required for audio probe, also when there are no audio capable
> - * displays connected at probe time. This leads to unnecessarily high
> - * CDCLK when audio is not required.
> - *
> - * FIXME: This limit is only applied when there are displays connected
> - * at probe time. If we probe without displays, we'll still end up using
> - * the platform minimum CDCLK, failing audio probe.
> */
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> min_cdclk = max(2 * 96000, min_cdclk);
>
> /*
> @@ -2239,7 +2228,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> intel_state->min_cdclk[i] = min_cdclk;
> }
>
> - min_cdclk = 0;
> + min_cdclk = intel_state->cdclk.force_min_cdclk;
> for_each_pipe(dev_priv, pipe)
> min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
>
> @@ -2300,7 +2289,8 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> vlv_calc_voltage_level(dev_priv, cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> + cdclk = vlv_calc_cdclk(dev_priv,
> + intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2333,7 +2323,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> bdw_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = bdw_calc_cdclk(0);
> + cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
>
> intel_state->cdclk.actual.cdclk = cdclk;
> intel_state->cdclk.actual.voltage_level =
> @@ -2405,7 +2395,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> skl_calc_voltage_level(cdclk);
>
> if (!intel_state->active_crtcs) {
> - cdclk = skl_calc_cdclk(0, vco);
> + cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> @@ -2444,10 +2434,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(0);
> + cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = glk_de_pll_vco(dev_priv, cdclk);
> } else {
> - cdclk = bxt_calc_cdclk(0);
> + cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = bxt_de_pll_vco(dev_priv, cdclk);
> }
>
> @@ -2483,7 +2473,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> - cdclk = cnl_calc_cdclk(0);
> + cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
> vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> @@ -2519,7 +2509,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
> cnl_compute_min_voltage_level(intel_state));
>
> if (!intel_state->active_crtcs) {
> - cdclk = icl_calc_cdclk(0, ref);
> + cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
> vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> intel_state->cdclk.actual.vco = vco;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 421aac80a838..ebbac873b8f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12769,6 +12769,11 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> return -EINVAL;
> }
>
> + /* keep the current setting */
> + if (!intel_state->cdclk.force_min_cdclk_changed)
> + intel_state->cdclk.force_min_cdclk =
> + dev_priv->cdclk.force_min_cdclk;
> +
> intel_state->modeset = true;
> intel_state->active_crtcs = dev_priv->active_crtcs;
> intel_state->cdclk.logical = dev_priv->cdclk.logical;
> @@ -12864,7 +12869,7 @@ static int intel_atomic_check(struct drm_device *dev,
> struct drm_crtc *crtc;
> struct drm_crtc_state *old_crtc_state, *crtc_state;
> int ret, i;
> - bool any_ms = false;
> + bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
>
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> @@ -13456,6 +13461,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> dev_priv->active_crtcs = intel_state->active_crtcs;
> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> + dev_priv->cdclk.force_min_cdclk =
> + intel_state->cdclk.force_min_cdclk;
> }
>
> drm_atomic_state_get(state);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d5660ac1b0d6..539caca05da4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -480,6 +480,9 @@ struct intel_atomic_state {
> * state only when all crtc's are DPMS off.
> */
> struct intel_cdclk_state actual;
> +
> + int force_min_cdclk;
> + bool force_min_cdclk_changed;
> } cdclk;
>
> bool dpll_set, modeset;
> --
> 2.21.0
>
Gentle ping for this patch on Linux stable 5.1.X
It fixes "The audio playback does not work anymore after suspend &
resume" on ASUS E406MA.
Any comment will be appreciated.
Jian-Hong Pan
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
@ 2019-05-24 3:41 Jian-Hong Pan
2019-05-31 5:20 ` Jian-Hong Pan
0 siblings, 1 reply; 36+ messages in thread
From: Jian-Hong Pan @ 2019-05-24 3:41 UTC (permalink / raw)
To: stable
Cc: linux, tiwai, Ville Syrjälä,
Abhay Kumar, Imre Deak, Clint Taylor, Jian-Hong Pan
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
commit 905801fe72377b4dc53c6e13eea1a91c6a4aa0c4 upstream.
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
v4: Remove Power well 2 reset workaround(Ville).
v5: Remove unwanted Power well 2 register defined in v4(Abhay).
v6:
- Use a dedicated flag instead of state->modeset for min CDCLK changes
- Make get/put audio power domain symmetric
- Rebased on top of intel_wakeref tracking changes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Tested-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190320135439.12201-1-imre.deak@intel.com
Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=203623
Cc: <stable@vger.kernel.org> # 5.1.x: d31c85fc8642 snd/hda, drm/i915: Track the display_power_status using a cookie
Cc: <stable@vger.kernel.org> # 5.1.x
Signed-off-by: Jian-Hong Pan <jian-hong@endlessm.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/intel_audio.c | 64 +++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_cdclk.c | 30 +++++--------
drivers/gpu/drm/i915/intel_display.c | 9 +++-
drivers/gpu/drm/i915/intel_drv.h | 3 ++
5 files changed, 86 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a67a63b5aa84..5c9bb1b2d1f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1622,6 +1622,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
@@ -1741,6 +1743,7 @@ struct drm_i915_private {
*
*/
struct mutex av_mutex;
+ int audio_power_refcount;
struct {
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 502b57ce72ab..20324b0d34c7 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -741,18 +741,78 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+ * Protects dev_priv->cdclk.force_min_cdclk
+ * Need to lock this here in case we have no active pipes
+ * and thus wouldn't lock it during the commit otherwise.
+ */
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
+ &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static unsigned long i915_audio_component_get_power(struct device *kdev)
{
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+ intel_wakeref_t ret;
+
/* Catch potential impedance mismatches before they occur! */
BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
- return intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+
+ /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
+ if (dev_priv->audio_power_refcount++ == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
+
+ return ret;
}
static void i915_audio_component_put_power(struct device *kdev,
unsigned long cookie)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO, cookie);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
+ if (--dev_priv->audio_power_refcount == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 15ba950dee00..553f57ff60f4 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2187,19 +2187,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/*
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
- *
- * FIXME: Check the actual, not default, BCLK being used.
- *
- * FIXME: This does not depend on ->has_audio because the higher CDCLK
- * is required for audio probe, also when there are no audio capable
- * displays connected at probe time. This leads to unnecessarily high
- * CDCLK when audio is not required.
- *
- * FIXME: This limit is only applied when there are displays connected
- * at probe time. If we probe without displays, we'll still end up using
- * the platform minimum CDCLK, failing audio probe.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2239,7 +2228,7 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
intel_state->min_cdclk[i] = min_cdclk;
}
- min_cdclk = 0;
+ min_cdclk = intel_state->cdclk.force_min_cdclk;
for_each_pipe(dev_priv, pipe)
min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
@@ -2300,7 +2289,8 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
vlv_calc_voltage_level(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
- cdclk = vlv_calc_cdclk(dev_priv, 0);
+ cdclk = vlv_calc_cdclk(dev_priv,
+ intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2333,7 +2323,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
bdw_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = bdw_calc_cdclk(0);
+ cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
intel_state->cdclk.actual.cdclk = cdclk;
intel_state->cdclk.actual.voltage_level =
@@ -2405,7 +2395,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
skl_calc_voltage_level(cdclk);
if (!intel_state->active_crtcs) {
- cdclk = skl_calc_cdclk(0, vco);
+ cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
intel_state->cdclk.actual.vco = vco;
intel_state->cdclk.actual.cdclk = cdclk;
@@ -2444,10 +2434,10 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
if (!intel_state->active_crtcs) {
if (IS_GEMINILAKE(dev_priv)) {
- cdclk = glk_calc_cdclk(0);
+ cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = glk_de_pll_vco(dev_priv, cdclk);
} else {
- cdclk = bxt_calc_cdclk(0);
+ cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = bxt_de_pll_vco(dev_priv, cdclk);
}
@@ -2483,7 +2473,7 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = cnl_calc_cdclk(0);
+ cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
@@ -2519,7 +2509,7 @@ static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
cnl_compute_min_voltage_level(intel_state));
if (!intel_state->active_crtcs) {
- cdclk = icl_calc_cdclk(0, ref);
+ cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
intel_state->cdclk.actual.vco = vco;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 421aac80a838..ebbac873b8f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12769,6 +12769,11 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return -EINVAL;
}
+ /* keep the current setting */
+ if (!intel_state->cdclk.force_min_cdclk_changed)
+ intel_state->cdclk.force_min_cdclk =
+ dev_priv->cdclk.force_min_cdclk;
+
intel_state->modeset = true;
intel_state->active_crtcs = dev_priv->active_crtcs;
intel_state->cdclk.logical = dev_priv->cdclk.logical;
@@ -12864,7 +12869,7 @@ static int intel_atomic_check(struct drm_device *dev,
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *crtc_state;
int ret, i;
- bool any_ms = false;
+ bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -13456,6 +13461,8 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->active_crtcs = intel_state->active_crtcs;
dev_priv->cdclk.logical = intel_state->cdclk.logical;
dev_priv->cdclk.actual = intel_state->cdclk.actual;
+ dev_priv->cdclk.force_min_cdclk =
+ intel_state->cdclk.force_min_cdclk;
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d5660ac1b0d6..539caca05da4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -480,6 +480,9 @@ struct intel_atomic_state {
* state only when all crtc's are DPMS off.
*/
struct intel_cdclk_state actual;
+
+ int force_min_cdclk;
+ bool force_min_cdclk_changed;
} cdclk;
bool dpll_set, modeset;
--
2.21.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
end of thread, other threads:[~2019-05-31 5:20 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-29 20:39 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-04-30 10:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-04-30 10:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-04-30 10:43 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-30 13:01 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-30 18:22 ` [PATCH] " Du,Wenkai
2018-05-01 9:15 ` Saarinen, Jani
2018-05-01 23:42 ` Kumar, Abhay
2018-05-01 23:47 ` Kumar, Abhay
2018-05-02 15:12 ` Ville Syrjälä
2018-05-02 16:57 ` Kumar, Abhay
2018-05-02 17:14 ` Ville Syrjälä
2018-05-02 18:47 ` Kumar, Abhay
2018-05-10 1:25 ` [PATCH v2] " Abhay Kumar
2018-05-11 12:33 ` Ville Syrjälä
2018-05-11 22:04 ` Kumar, Abhay
2018-05-14 9:24 ` Jani Nikula
2018-06-12 7:17 ` [PATCH v3] " Abhay Kumar
2018-06-12 12:13 ` Ville Syrjälä
2018-06-12 16:27 ` Kumar, Abhay
2018-06-12 21:58 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Abhay Kumar
2018-06-12 21:58 ` [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk Abhay Kumar
2018-06-13 12:27 ` [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK Ville Syrjälä
2018-05-10 1:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2) Patchwork
2018-05-10 1:55 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-10 2:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-10 4:35 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12 7:28 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) Patchwork
2018-06-12 7:29 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-12 7:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12 8:37 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12 18:09 ` Saarinen, Jani
2018-06-12 23:51 ` Kumar, Abhay
2019-05-24 3:41 [PATCH] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Jian-Hong Pan
2019-05-31 5:20 ` Jian-Hong Pan
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