All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alan Douglas <adouglas@cadence.com>
To: bhelgaas@google.com, kishon@ti.com, lorenzo.pieralisi@arm.com
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	robh+dt@kernel.org, Alan Douglas <adouglas@cadence.com>
Subject: [PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
Date: Mon, 25 Jun 2018 09:30:51 +0100	[thread overview]
Message-ID: <1529915453-4633-4-git-send-email-adouglas@cadence.com> (raw)
In-Reply-To: <1529915453-4633-1-git-send-email-adouglas@cadence.com>

Update DT documentation to include optional PHYs for cadence PCIe
host and endpoint controllers.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +++++
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..4a0475e 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,9 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 1).
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +22,6 @@ pcie@fc000000 {
 	reg-names = "reg", "mem";
 	cdns,max-outbound-regions = <16>;
 	max-functions = /bits/ 8 <8>;
+	phys = <&ep_phy0 &ep_phy1>;
+	phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..91de69c 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,9 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +60,7 @@ pcie@fb000000 {
 	interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
 	msi-parent = <&its_pci>;
+
+	phys = <&pcie_phy0>;
+	phy-names = "pcie-phy";
 };
-- 
1.7.1


WARNING: multiple messages have this Message-ID (diff)
From: Alan Douglas <adouglas@cadence.com>
To: <bhelgaas@google.com>, <kishon@ti.com>, <lorenzo.pieralisi@arm.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<robh+dt@kernel.org>, Alan Douglas <adouglas@cadence.com>
Subject: [PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
Date: Mon, 25 Jun 2018 09:30:51 +0100	[thread overview]
Message-ID: <1529915453-4633-4-git-send-email-adouglas@cadence.com> (raw)
In-Reply-To: <1529915453-4633-1-git-send-email-adouglas@cadence.com>

Update DT documentation to include optional PHYs for cadence PCIe
host and endpoint controllers.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt  |    5 +++++
 .../bindings/pci/cdns,cdns-pcie-host.txt           |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
index 9a30523..4a0475e 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -9,6 +9,9 @@ Required properties:
 
 Optional properties:
 - max-functions: Maximum number of functions that can be configured (default 1).
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -19,4 +22,6 @@ pcie@fc000000 {
 	reg-names = "reg", "mem";
 	cdns,max-outbound-regions = <16>;
 	max-functions = /bits/ 8 <8>;
+	phys = <&ep_phy0 &ep_phy1>;
+	phy-names = "pcie-lane0","pcie-lane1";
 };
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
index 20a33f3..91de69c 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -24,6 +24,9 @@ Optional properties:
   translations (default 32)
 - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
 - device-id: The PCI device ID (16 bits, default is design dependent)
+- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
+  than one in the list.  If only one PHY listed it must manage all lanes. 
+- phy-names:  List of names to identify the PHY.
 
 Example:
 
@@ -57,4 +60,7 @@ pcie@fb000000 {
 	interrupt-map-mask = <0x0 0x0 0x0  0x7>;
 
 	msi-parent = <&its_pci>;
+
+	phys = <&pcie_phy0>;
+	phy-names = "pcie-phy";
 };
-- 
1.7.1

  parent reply	other threads:[~2018-06-25  8:31 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-25  8:30 [PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management Alan Douglas
2018-06-25  8:30 ` Alan Douglas
2018-06-25  8:30 ` [PATCH 1/5] PCI: cadence: Update cdns_pcie_writel function signature Alan Douglas
2018-06-25  8:30   ` Alan Douglas
2018-06-25  8:30 ` [PATCH 2/5] PCI: cadence: Add generic PHY support to host and EP drivers Alan Douglas
2018-06-25  8:30   ` Alan Douglas
2018-06-25  8:30 ` Alan Douglas [this message]
2018-06-25  8:30   ` [PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs Alan Douglas
2018-07-03 21:01   ` Rob Herring
2018-06-25  8:30 ` [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP Alan Douglas
2018-06-25  8:30   ` Alan Douglas
2018-07-09 15:33   ` Lorenzo Pieralisi
2018-07-09 15:56     ` Alan Douglas
2018-07-09 15:56       ` Alan Douglas
2018-07-11 10:58       ` Lorenzo Pieralisi
2018-07-11 14:00         ` Alan Douglas
2018-07-11 14:00           ` Alan Douglas
2018-06-25  8:30 ` [PATCH 5/5] PCI: cadence: Add shutdown callback to host driver Alan Douglas
2018-06-25  8:30   ` Alan Douglas
2018-07-13 13:02 ` [PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1529915453-4633-4-git-send-email-adouglas@cadence.com \
    --to=adouglas@cadence.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=kishon@ti.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.