* [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
@ 2018-07-03 13:27 Zhao Yakui
2018-07-03 13:32 ` Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Zhao Yakui @ 2018-07-03 13:27 UTC (permalink / raw)
To: intel-gfx
On VGPU scenario the read/write operation of fence_reg will be trapped
by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
And the gvt-g takes care of updating the fence reg correctly for any
trapped value of fence reg.
So it is unnecessary to read/write fence reg several times. It is enough
that the fence reg is written only value in 64-bit mdoe. This will help
to reduce the redundantt trap of fence_reg mmio operation.
V1->V2: Fix one typo error of parameter when calling intel_vgpu_active.
V2->V3: Follow Chris Wilson and Daniel Vetter to add more descriptions.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d548ac0..7b10bf9 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
i915_reg_t fence_reg_lo, fence_reg_hi;
int fence_pitch_shift;
u64 val;
+ struct drm_i915_private *dev_priv = fence->i915;
if (INTEL_GEN(fence->i915) >= 6) {
fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
@@ -92,9 +93,17 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
val |= I965_FENCE_REG_VALID;
}
- if (!pipelined) {
- struct drm_i915_private *dev_priv = fence->i915;
-
+ if (intel_vgpu_active(dev_priv)) {
+ /* Use the 64-bit RW to write fence reg on VGPU mode.
+ * The GVT-g can trap the written val of VGPU to program the
+ * fence reg. And the fence write in gvt-g follows the
+ * sequence of off/read/double-write/read. This assures that
+ * the fence reg is configured correctly.
+ * At the same time the 64-bit op can help to reduce the num
+ * of VGPU trap for the fence reg.
+ */
+ I915_WRITE64_FW(fence_reg_lo, val);
+ } else {
/* To w/a incoherency with non-atomic 64-bit register updates,
* we split the 64-bit update into two 32-bit writes. In order
* for a partial fence not to be evaluated between writes, we
--
2.7.4
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
2018-07-03 13:27 [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU Zhao Yakui
@ 2018-07-03 13:32 ` Chris Wilson
2018-07-03 14:37 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-07-03 23:33 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2018-07-03 13:32 UTC (permalink / raw)
To: Zhao Yakui, intel-gfx
Quoting Zhao Yakui (2018-07-03 14:27:47)
> On VGPU scenario the read/write operation of fence_reg will be trapped
> by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
> And the gvt-g takes care of updating the fence reg correctly for any
> trapped value of fence reg.
>
> So it is unnecessary to read/write fence reg several times. It is enough
> that the fence reg is written only value in 64-bit mdoe. This will help
> to reduce the redundantt trap of fence_reg mmio operation.
>
> V1->V2: Fix one typo error of parameter when calling intel_vgpu_active.
> V2->V3: Follow Chris Wilson and Daniel Vetter to add more descriptions.
>
> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index d548ac0..7b10bf9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
> i915_reg_t fence_reg_lo, fence_reg_hi;
> int fence_pitch_shift;
> u64 val;
> + struct drm_i915_private *dev_priv = fence->i915;
>
> if (INTEL_GEN(fence->i915) >= 6) {
> fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
> @@ -92,9 +93,17 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
> val |= I965_FENCE_REG_VALID;
> }
>
> - if (!pipelined) {
> - struct drm_i915_private *dev_priv = fence->i915;
Ahem.
-Chris
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^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
2018-07-03 13:27 [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU Zhao Yakui
2018-07-03 13:32 ` Chris Wilson
@ 2018-07-03 14:37 ` Patchwork
2018-07-03 23:33 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-07-03 14:37 UTC (permalink / raw)
To: Zhao, Yakui; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
URL : https://patchwork.freedesktop.org/series/45841/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4423 -> Patchwork_9510 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/45841/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9510 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: NOTRUN -> INCOMPLETE (fdo#103927)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s3:
{fi-cfl-8109u}: INCOMPLETE -> PASS
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: FAIL (fdo#103841) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
== Participating hosts (45 -> 40) ==
Additional (1): fi-bxt-dsi
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4423 -> Patchwork_9510
CI_DRM_4423: 9b9b45349fe3a36d41586992426d03a238396531 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4533: 199220052af977598033d3810ffb4cc32d377522 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9510: 8f3afb60f04c05b46289401cc19d38451fbf2c70 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8f3afb60f04c drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9510/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
2018-07-03 13:27 [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU Zhao Yakui
2018-07-03 13:32 ` Chris Wilson
2018-07-03 14:37 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-07-03 23:33 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-07-03 23:33 UTC (permalink / raw)
To: Zhao, Yakui; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU
URL : https://patchwork.freedesktop.org/series/45841/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4423_full -> Patchwork_9510_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9510_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9510_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9510_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: PASS -> SKIP +2
== Known issues ==
Here are the changes found in Patchwork_9510_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_gtt:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
shard-glk: PASS -> FAIL (fdo#100368)
igt@kms_flip@dpms-vs-vblank-race-interruptible:
shard-hsw: PASS -> FAIL (fdo#103060)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
shard-kbl: PASS -> FAIL (fdo#99912)
igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
==== Possible fixes ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS
igt@kms_flip@2x-plain-flip-ts-check:
shard-glk: FAIL (fdo#100368) -> PASS +1
igt@kms_flip_tiling@flip-x-tiled:
shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS +1
igt@kms_vblank@pipe-a-ts-continuation-suspend:
shard-hsw: FAIL (fdo#104894) -> PASS
igt@perf@polling:
shard-hsw: FAIL (fdo#102252) -> PASS
==== Warnings ====
igt@drv_selftest@live_gtt:
shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> FAIL (fdo#105347)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#104894 https://bugs.freedesktop.org/show_bug.cgi?id=104894
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4423 -> Patchwork_9510
CI_DRM_4423: 9b9b45349fe3a36d41586992426d03a238396531 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4533: 199220052af977598033d3810ffb4cc32d377522 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9510: 8f3afb60f04c05b46289401cc19d38451fbf2c70 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9510/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-07-03 23:33 UTC | newest]
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-- links below jump to the message on this page --
2018-07-03 13:27 [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU Zhao Yakui
2018-07-03 13:32 ` Chris Wilson
2018-07-03 14:37 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-07-03 23:33 ` ✓ Fi.CI.IGT: " Patchwork
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