From: Patrick Delaunay <patrick.delaunay@st.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/6] stm32mp1: clk: update Ethernet clock gating
Date: Mon, 16 Jul 2018 10:41:44 +0200 [thread overview]
Message-ID: <1531730506-18633-4-git-send-email-patrick.delaunay@st.com> (raw)
In-Reply-To: <1531730506-18633-1-git-send-email-patrick.delaunay@st.com>
Alignment with kernel clock driver
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---
drivers/clk/clk_stm32mp1.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 6202ebe..0641dfa 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -542,10 +542,9 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
--
2.7.4
next prev parent reply other threads:[~2018-07-16 8:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-16 8:41 [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Patrick Delaunay
2018-07-16 8:41 ` [U-Boot] [PATCH 2/6] stm32mp1: clk: add common function pll_get_fvco Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 3/6] stm32mp1: clk: add LDTC and DSI clock support Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
2018-07-16 8:41 ` Patrick Delaunay [this message]
2018-07-20 22:36 ` [U-Boot] [U-Boot, 4/6] stm32mp1: clk: update Ethernet clock gating Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 5/6] stm32mp1: clk: add ADC " Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot,5/6] " Tom Rini
2018-07-16 8:41 ` [U-Boot] [PATCH 6/6] stm32mp1: clk: support digital bypass Patrick Delaunay
2018-07-20 22:36 ` [U-Boot] [U-Boot,6/6] " Tom Rini
2018-07-16 18:30 ` [U-Boot] [PATCH 1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro Vikas Manocha
2018-07-20 22:36 ` [U-Boot] [U-Boot, " Tom Rini
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