[PATCH 0/2] Add HDMI support to the iwg23s

[PATCH 0/2] Add HDMI support to the iwg23s

[Fabrizio Castro]

Dear All,

this series adds HDMI support to the iwg23s board.

Thanks,
Fab

Fabrizio Castro (2):
  ARM: dts: r8a77470: Add DU support
  ARM: dts: iwg23s-sbc: Add HDMI support

 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 79 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a77470.dtsi           | 32 +++++++++++++
 2 files changed, 111 insertions(+)

-- 
2.7.4

[PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Fabrizio Castro]

This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index f4e232b..493cf2b 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -643,6 +643,38 @@
 			resets = <&cpg 408>;
 		};
 
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a77470";
+			reg = <0 0xfeb00000 0 0x40000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 724>,
+				 <&cpg CPG_MOD 723>;
+			clock-names = "du.0", "du.1";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_rgb0: endpoint {
+					};
+				};
+				port@1 {
+					reg = <1>;
+					du_out_rgb1: endpoint {
+					};
+				};
+				port@2 {
+					reg = <2>;
+					du_out_lvds0: endpoint {
+					};
+				};
+			};
+		};
+
 		prr: chipid@ff000044 {
 			compatible = "renesas,prr";
 			reg = <0 0xff000044 0 4>;
-- 
2.7.4

[PATCH 2/2] ARM: dts: iwg23s-sbc: Add HDMI support

[Fabrizio Castro]

This patch adds HDMI video output support to the iwg23s board
from iWave. Due to a problem with the bootloader not dealing
with the configuration of one of the pins correctly, we have
to use a gpio-hog for the interrupt line to make sure the pin
is configured as GPIO-input when requesting the interrupt.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 79 +++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 77d1824..9f9eb15 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -22,6 +22,17 @@
 		stdout-path = "serial1:115200n8";
 	};
 
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x20000000>;
@@ -80,10 +91,34 @@
 	status = "okay";
 };
 
+&du {
+	pinctrl-0 = <&du0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &extal_clk {
 	clock-frequency = <20000000>;
 };
 
+&gpio2 {
+	interrupt-fixup {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_HIGH>;
+		line-name = "hdmi-hpd-int";
+		input;
+	};
+};
+
 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
@@ -97,12 +132,56 @@
 	};
 };
 
+&i2c4 {
+	pinctrl-0 = <&i2c4_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <100000>;
+
+	hdmi@39 {
+		compatible = "sil,sii9022";
+		reg = <0x39>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				bridge_in: endpoint {
+					remote-endpoint = <&du_out_rgb0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				bridge_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
 &pfc {
 	avb_pins: avb {
 		groups = "avb_mdio", "avb_gmii_tx_rx";
 		function = "avb";
 	};
 
+	du0_pins: du0 {
+		groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+		function = "du0";
+	};
+
+	i2c4_pins: i2c4 {
+		groups = "i2c4_e";
+		function = "i2c4";
+	};
+
 	i2c3_pins: i2c3 {
 		groups = "i2c3_c";
 		function = "i2c3";
-- 
2.7.4

Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Simon Horman]

On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> specific device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> index f4e232b..493cf2b 100644
> --- a/arch/arm/boot/dts/r8a77470.dtsi
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -643,6 +643,38 @@
>  			resets = <&cpg 408>;
>  		};
>  
> +		du: display@feb00000 {
> +			compatible = "renesas,du-r8a77470";
> +			reg = <0 0xfeb00000 0 0x40000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 724>,
> +				 <&cpg CPG_MOD 723>;

I do not see MSTP 7 bit 23 documented as used by DU
in the User's Manual: Hardware v1.00 Oct 13, 2017.

Do you have more recent documentation or some insight in this area?

> +			clock-names = "du.0", "du.1";
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					du_out_rgb0: endpoint {
> +					};
> +				};
> +				port@1 {
> +					reg = <1>;
> +					du_out_rgb1: endpoint {
> +					};
> +				};
> +				port@2 {
> +					reg = <2>;
> +					du_out_lvds0: endpoint {
> +					};
> +				};
> +			};
> +		};
> +
>  		prr: chipid@ff000044 {
>  			compatible = "renesas,prr";
>  			reg = <0 0xff000044 0 4>;
> -- 
> 2.7.4
> 

RE: [PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 22 March 2019 10:47
> Subject: Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support
> 
> On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> > This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> > specific device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > index f4e232b..493cf2b 100644
> > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -643,6 +643,38 @@
> >  			resets = <&cpg 408>;
> >  		};
> >
> > +		du: display@feb00000 {
> > +			compatible = "renesas,du-r8a77470";
> > +			reg = <0 0xfeb00000 0 0x40000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cpg CPG_MOD 724>,
> > +				 <&cpg CPG_MOD 723>;
> 
> I do not see MSTP 7 bit 23 documented as used by DU
> in the User's Manual: Hardware v1.00 Oct 13, 2017.
> 
> Do you have more recent documentation or some insight in this area?

I have the same document, and I can see the bit defined in page 7A-16.
Perhaps you checked the Software Reset Register?

Thanks,
Fab

> 
> > +			clock-names = "du.0", "du.1";
> > +			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +					du_out_rgb0: endpoint {
> > +					};
> > +				};
> > +				port@1 {
> > +					reg = <1>;
> > +					du_out_rgb1: endpoint {
> > +					};
> > +				};
> > +				port@2 {
> > +					reg = <2>;
> > +					du_out_lvds0: endpoint {
> > +					};
> > +				};
> > +			};
> > +		};
> > +
> >  		prr: chipid@ff000044 {
> >  			compatible = "renesas,prr";
> >  			reg = <0 0xff000044 0 4>;
> > --
> > 2.7.4
> >

RE: [PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 22 March 2019 10:47
> Subject: Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support
> 
> On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> > This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> > specific device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > index f4e232b..493cf2b 100644
> > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -643,6 +643,38 @@
> >  			resets = <&cpg 408>;
> >  		};
> >
> > +		du: display@feb00000 {
> > +			compatible = "renesas,du-r8a77470";
> > +			reg = <0 0xfeb00000 0 0x40000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cpg CPG_MOD 724>,
> > +				 <&cpg CPG_MOD 723>;
> 
> I do not see MSTP 7 bit 23 documented as used by DU
> in the User's Manual: Hardware v1.00 Oct 13, 2017.
> 
> Do you have more recent documentation or some insight in this area?

I have the same document, and I can see the bit defined in page 7A-16.
Perhaps you checked the Software Reset Register?

Thanks,
Fab

> 
> > +			clock-names = "du.0", "du.1";
> > +			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +					du_out_rgb0: endpoint {
> > +					};
> > +				};
> > +				port@1 {
> > +					reg = <1>;
> > +					du_out_rgb1: endpoint {
> > +					};
> > +				};
> > +				port@2 {
> > +					reg = <2>;
> > +					du_out_lvds0: endpoint {
> > +					};
> > +				};
> > +			};
> > +		};
> > +
> >  		prr: chipid@ff000044 {
> >  			compatible = "renesas,prr";
> >  			reg = <0 0xff000044 0 4>;
> > --
> > 2.7.4
> >

Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Simon Horman]

On Fri, Mar 22, 2019 at 10:53:16AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 22 March 2019 10:47
> > Subject: Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support
> > 
> > On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> > > This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> > > specific device tree.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > >  arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
> > >  1 file changed, 32 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > index f4e232b..493cf2b 100644
> > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > @@ -643,6 +643,38 @@
> > >  			resets = <&cpg 408>;
> > >  		};
> > >
> > > +		du: display@feb00000 {
> > > +			compatible = "renesas,du-r8a77470";
> > > +			reg = <0 0xfeb00000 0 0x40000>;
> > > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > > +				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > > +			clocks = <&cpg CPG_MOD 724>,
> > > +				 <&cpg CPG_MOD 723>;
> > 
> > I do not see MSTP 7 bit 23 documented as used by DU
> > in the User's Manual: Hardware v1.00 Oct 13, 2017.
> > 
> > Do you have more recent documentation or some insight in this area?
> 
> I have the same document, and I can see the bit defined in page 7A-16.
> Perhaps you checked the Software Reset Register?

Thanks,

I think its likely that was my mistake.
And I now see the field described on page 7A-16.

I have gone ahead and applied this patch for inclusion in v5.2.

> 
> Thanks,
> Fab
> 
> > 
> > > +			clock-names = "du.0", "du.1";
> > > +			status = "disabled";
> > > +
> > > +			ports {
> > > +				#address-cells = <1>;
> > > +				#size-cells = <0>;
> > > +
> > > +				port@0 {
> > > +					reg = <0>;
> > > +					du_out_rgb0: endpoint {
> > > +					};
> > > +				};
> > > +				port@1 {
> > > +					reg = <1>;
> > > +					du_out_rgb1: endpoint {
> > > +					};
> > > +				};
> > > +				port@2 {
> > > +					reg = <2>;
> > > +					du_out_lvds0: endpoint {
> > > +					};
> > > +				};
> > > +			};
> > > +		};
> > > +
> > >  		prr: chipid@ff000044 {
> > >  			compatible = "renesas,prr";
> > >  			reg = <0 0xff000044 0 4>;
> > > --
> > > 2.7.4
> > >
> 

Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support

[Simon Horman]

On Fri, Mar 22, 2019 at 10:53:16AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 22 March 2019 10:47
> > Subject: Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support
> > 
> > On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> > > This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> > > specific device tree.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > >  arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
> > >  1 file changed, 32 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > index f4e232b..493cf2b 100644
> > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > @@ -643,6 +643,38 @@
> > >  			resets = <&cpg 408>;
> > >  		};
> > >
> > > +		du: display@feb00000 {
> > > +			compatible = "renesas,du-r8a77470";
> > > +			reg = <0 0xfeb00000 0 0x40000>;
> > > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > > +				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > > +			clocks = <&cpg CPG_MOD 724>,
> > > +				 <&cpg CPG_MOD 723>;
> > 
> > I do not see MSTP 7 bit 23 documented as used by DU
> > in the User's Manual: Hardware v1.00 Oct 13, 2017.
> > 
> > Do you have more recent documentation or some insight in this area?
> 
> I have the same document, and I can see the bit defined in page 7A-16.
> Perhaps you checked the Software Reset Register?

Thanks,

I think its likely that was my mistake.
And I now see the field described on page 7A-16.

I have gone ahead and applied this patch for inclusion in v5.2.

> 
> Thanks,
> Fab
> 
> > 
> > > +			clock-names = "du.0", "du.1";
> > > +			status = "disabled";
> > > +
> > > +			ports {
> > > +				#address-cells = <1>;
> > > +				#size-cells = <0>;
> > > +
> > > +				port@0 {
> > > +					reg = <0>;
> > > +					du_out_rgb0: endpoint {
> > > +					};
> > > +				};
> > > +				port@1 {
> > > +					reg = <1>;
> > > +					du_out_rgb1: endpoint {
> > > +					};
> > > +				};
> > > +				port@2 {
> > > +					reg = <2>;
> > > +					du_out_lvds0: endpoint {
> > > +					};
> > > +				};
> > > +			};
> > > +		};
> > > +
> > >  		prr: chipid@ff000044 {
> > >  			compatible = "renesas,prr";
> > >  			reg = <0 0xff000044 0 4>;
> > > --
> > > 2.7.4
> > >
> 

Re: [PATCH 2/2] ARM: dts: iwg23s-sbc: Add HDMI support

[Simon Horman]

On Tue, Mar 19, 2019 at 12:21:39PM +0000, Fabrizio Castro wrote:
> This patch adds HDMI video output support to the iwg23s board
> from iWave. Due to a problem with the bootloader not dealing
> with the configuration of one of the pins correctly, we have
> to use a gpio-hog for the interrupt line to make sure the pin
> is configured as GPIO-input when requesting the interrupt.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Thanks Fabrizio, applied for v5.2.