[U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Ley Foon Tan]

This patchset fix issues in Intel FPGA PCIe driver.
- Fix TLP polling timeout
- Fix enumerating mult-function PCIe device issue
- Fix PCIe switch read config register issue

Ley Foon Tan (3):
  pci: intel: Increase TLP polling counter
  pci: intel: Fix error when enumerating multi-function PCIe device
  pci: intel: Fix configuration type based on secondary number

 drivers/pci/pcie_intel_fpga.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

-- 
2.19.0

[U-Boot] [PATCH 1/3] pci: intel: Increase TLP polling counter

[Ley Foon Tan]

Some PCIe devices require longer time to response.
Increase polling counter to 20000 (~100ms).

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 drivers/pci/pcie_intel_fpga.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 3cdf05b314..e74b35ac16 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -56,7 +56,7 @@
 #define TLP_COMP_STATUS(s)		(((s) >> 13) & 7)
 #define TLP_BYTE_COUNT(s)		(((s) >> 0) & 0xfff)
 #define TLP_HDR_SIZE			3
-#define TLP_LOOP			500
+#define TLP_LOOP			20000
 #define DWORD_MASK			3
 
 #define IS_ROOT_PORT(pcie, bdf)				\
-- 
2.19.0

[U-Boot] [PATCH 2/3] pci: intel: Fix error when enumerating multi-function PCIe device

[Ley Foon Tan]

Hardware return completion status non-zero when read from non exist
function in multi-function PCIe device. Return error will cause PCIe
enumeration fail.

Change it to return 0 and return value 0xffffffff when error.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 drivers/pci/pcie_intel_fpga.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index e74b35ac16..a096d1c697 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -161,8 +161,10 @@ static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
 			dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
 			if (ctrl & RP_RXCPL_EOP) {
 				comp_status = TLP_COMP_STATUS(dw[1]);
-				if (comp_status)
-					return -EFAULT;
+				if (comp_status) {
+					*value = pci_get_ff(PCI_SIZE_32);
+					return 0;
+				}
 
 				if (value &&
 				    TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
-- 
2.19.0

[U-Boot] [PATCH 3/3] pci: intel: Fix configuration type based on secondary number

[Ley Foon Tan]

This fix issue when access config from PCIe switch.

The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.

The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 drivers/pci/pcie_intel_fpga.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index a096d1c697..a5ea4888f3 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -36,16 +36,18 @@
 
 #define RP_CFG_ADDR(pcie, reg)						\
 		((pcie->hip_base) + (reg) + (1 << 20))
+#define RP_SECONDARY(pcie)						\
+	readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
 #define TLP_REQ_ID(bus, devfn)		(((bus) << 8) | (devfn))
 
 #define TLP_CFGRD_DW0(pcie, bus)					\
-	((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0		\
-				      : TLP_FMTTYPE_CFGRD1) << 24) |	\
+	((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1		\
+				      : TLP_FMTTYPE_CFGRD0) << 24) |	\
 					TLP_PAYLOAD_SIZE)
 
 #define TLP_CFGWR_DW0(pcie, bus)					\
-	((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0		\
-				      : TLP_FMTTYPE_CFGWR1) << 24) |	\
+	((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1		\
+				      : TLP_FMTTYPE_CFGWR0) << 24) |	\
 					TLP_PAYLOAD_SIZE)
 
 #define TLP_CFG_DW1(pcie, tag, be)					\
-- 
2.19.0

[U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Ley Foon Tan]

On Fri, May 24, 2019 at 10:30 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> This patchset fix issues in Intel FPGA PCIe driver.
> - Fix TLP polling timeout
> - Fix enumerating mult-function PCIe device issue
> - Fix PCIe switch read config register issue
>
> Ley Foon Tan (3):
>   pci: intel: Increase TLP polling counter
>   pci: intel: Fix error when enumerating multi-function PCIe device
>   pci: intel: Fix configuration type based on secondary number
>
>  drivers/pci/pcie_intel_fpga.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
Any comment on these patches?

Thanks

Regards
Ley Foon

[U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Ley Foon Tan]

On Tue, Jun 11, 2019 at 8:30 AM Ley Foon Tan <lftan.linux@gmail.com> wrote:
>
> On Fri, May 24, 2019 at 10:30 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> >
> > This patchset fix issues in Intel FPGA PCIe driver.
> > - Fix TLP polling timeout
> > - Fix enumerating mult-function PCIe device issue
> > - Fix PCIe switch read config register issue
> >
> > Ley Foon Tan (3):
> >   pci: intel: Increase TLP polling counter
> >   pci: intel: Fix error when enumerating multi-function PCIe device
> >   pci: intel: Fix configuration type based on secondary number
> >
> >  drivers/pci/pcie_intel_fpga.c | 18 +++++++++++-------
> >  1 file changed, 11 insertions(+), 7 deletions(-)
> Any comment on these patches?
>
> Thanks
Hi Tom and Michal

Can you help to merge these patches?

Thanks.

Regards
Ley Foon

[U-Boot] [PATCH 0/3] Intel FPGA PCIe fixes

[Tom Rini]

On Fri, Aug 09, 2019 at 05:04:43PM +0800, Ley Foon Tan wrote:
> On Tue, Jun 11, 2019 at 8:30 AM Ley Foon Tan <lftan.linux@gmail.com> wrote:
> >
> > On Fri, May 24, 2019 at 10:30 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> > >
> > > This patchset fix issues in Intel FPGA PCIe driver.
> > > - Fix TLP polling timeout
> > > - Fix enumerating mult-function PCIe device issue
> > > - Fix PCIe switch read config register issue
> > >
> > > Ley Foon Tan (3):
> > >   pci: intel: Increase TLP polling counter
> > >   pci: intel: Fix error when enumerating multi-function PCIe device
> > >   pci: intel: Fix configuration type based on secondary number
> > >
> > >  drivers/pci/pcie_intel_fpga.c | 18 +++++++++++-------
> > >  1 file changed, 11 insertions(+), 7 deletions(-)
> > Any comment on these patches?
> >
> > Thanks
> Hi Tom and Michal
> 
> Can you help to merge these patches?

I saw these as "FPGA" and gave them to Michal, in patchwork.  And I know
he's digging out from a vacation backlog.  Looking at the patches
themselves, I can see they're more "PCI" than anything else, I'll put
them in my queue.  Thanks for the reminder!

-- 
Tom
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[U-Boot] [PATCH 1/3] pci: intel: Increase TLP polling counter

[Tom Rini]

On Fri, May 24, 2019 at 10:29:58AM +0800, Ley Foon Tan wrote:

> Some PCIe devices require longer time to response.
> Increase polling counter to 20000 (~100ms).
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH 2/3] pci: intel: Fix error when enumerating multi-function PCIe device

[Tom Rini]

On Fri, May 24, 2019 at 10:29:59AM +0800, Ley Foon Tan wrote:

> Hardware return completion status non-zero when read from non exist
> function in multi-function PCIe device. Return error will cause PCIe
> enumeration fail.
> 
> Change it to return 0 and return value 0xffffffff when error.
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH 3/3] pci: intel: Fix configuration type based on secondary number

[Tom Rini]

On Fri, May 24, 2019 at 10:30:00AM +0800, Ley Foon Tan wrote:

> This fix issue when access config from PCIe switch.
> 
> The PCIe controller need to send Type 0 config TLP if the targeting bus
> matches with the secondary bus number, which is when the TLP is targeting
> the immediate device on the link.
> 
> The PCIe controller send Type 1 config TLP if the targeting bus is
> larger than the secondary bus, which is when the TLP is targeting the
> device not immediate on the link.
> 
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Applied to u-boot/master, thanks!

-- 
Tom
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