[PATCH v6 0/8] i915 vgpu PV to improve vgpu performance

[PATCH v6 0/8] i915 vgpu PV to improve vgpu performance

[Xiaolin Zhang]

To improve vgpu performance, it could implement some PV optimization
such as to reduce the mmio access trap numbers or eliminate certain piece
of HW emulation within guest driver to reduce vm exit/vm enter cost.

the solutions in this patch set are implemented two PV optimizations based
on the shared memory region between guest and GVTg for data communication.
The shared memory region is allocated by guest driver and this
region's memory guest physical address will be passed to GVTg through
PVINFO register and later GVTg can access this region directly without
trap cost to achieve data exchange purpose between guest and GVTg.

in this patch set, 2 kind of PV optimization implemented controlled by
pv_caps PVINO register with different pv bit.
1. workload PV submission (context submission): reduce 4 traps to 1 trap
and eliminated execlists HW behaviour emulation.
2. ppgtt PV update: eliminate the cost of ppgtt write protection.

based on the experiment, for small workloads, specifally, glxgears with
vblank_mode off, the average performance gain on single vgpu is 30~50%.
for large workload such as media and 3D, the average performance gain
is about 4%. 

based on the PV mechanism, it could achive more vgpu feature optimization
such as globle GTT update, display plane and water mark update.

v0: RFC patch set
v1: addressed RFC review comments
v2: addressed v1 review comments, added pv callbacks for pv operations
v3:
1. addressed v2 review comments, removed pv callbacks code duplication in
v2 and unified pv calls under g2v notification register. different g2v pv
notifications defined.
2. dropped pv master irq feature due to hard conflict with recnet i915
change and take time to rework.
v4:
1. addressed v3 review comments.
2. extended workload PV submission by skip execlists HW behaviour emulation
and context switch interrupt injection.  
v5:
1. addressed v4 review comments from Chris for pv submission.
2. per-engine communication between PV guest and host.
v6:
1. addressed v5 review comment from Chris for pv submission.
2. addressed v5 review comment from Zhenyu for PV version support.

Xiaolin Zhang (8):
  drm/i915: introduced vgpu pv capability
  drm/i915: vgpu shared memory setup for pv optimization
  drm/i915: vgpu ppgtt update pv optimization
  drm/i915: vgpu context submission pv optimization
  drm/i915/gvt: GVTg handle pv_caps PVINFO register
  drm/i915/gvt: GVTg handle shared_page setup
  drm/i915/gvt: GVTg support ppgtt pv optimization
  drm/i915/gvt: GVTg support context submission pv optimization

 drivers/gpu/drm/i915/Makefile              |   2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c        |   8 +-
 drivers/gpu/drm/i915/gvt/execlist.c        |   6 +
 drivers/gpu/drm/i915/gvt/gtt.c             | 317 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h             |   9 +
 drivers/gpu/drm/i915/gvt/gvt.h             |  12 +-
 drivers/gpu/drm/i915/gvt/handlers.c        |  65 +++++-
 drivers/gpu/drm/i915/gvt/vgpu.c            |  50 +++++
 drivers/gpu/drm/i915/i915_drv.h            |   5 +-
 drivers/gpu/drm/i915/i915_gem.c            |   3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        |   9 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h        |   8 +
 drivers/gpu/drm/i915/i915_pvinfo.h         |  12 +-
 drivers/gpu/drm/i915/i915_vgpu.c           | 182 ++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.h           |  59 ++++++
 drivers/gpu/drm/i915/intel_pv_submission.c | 166 +++++++++++++++
 16 files changed, 900 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_pv_submission.c

-- 
2.7.4

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[PATCH v6 1/8] drm/i915: introduced vgpu pv capability

[Xiaolin Zhang]

pv capability for vgpu was introduced by pv_caps in struct
i915_virtual_gpu and a new pv_caps register for host GVT
was defined in struct vgt_if for vgpu pv optimization.

both of them are used to control different feature pv optimization
supported and implemented by both guest and host.

These fields are default zero, no any pv feature enabled.

it also adds VGT_CAPS_PV capability BIT for guest to check GVTg
can support PV feature or not.

v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v2: rebase.
v3: distinct pv caps from guest and host. renamed enable_pvmmio to
pvmmio_caps which is used for host pv caps.
v4: consolidated all pv related functons into a single file i915_vgpu.c
and renamed pvmmio to pv_caps.
v5: rebase.
v6: rebase.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  2 ++
 drivers/gpu/drm/i915/i915_pvinfo.h |  5 ++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 44 +++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.h   |  8 +++++++
 4 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76f2bf9..2bb38b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -90,6 +90,7 @@
 #include "i915_vma.h"
 
 #include "intel_gvt.h"
+#include "i915_pvinfo.h"
 
 /* General customization:
  */
@@ -1242,6 +1243,7 @@ struct i915_frontbuffer_tracking {
 struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
+	u32 pv_caps;
 };
 
 /* used in computing the new watermarks state */
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 969e514..619305a 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -55,6 +55,7 @@ enum vgt_g2v_type {
 #define VGT_CAPS_FULL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
+#define VGT_CAPS_PV		BIT(5)
 
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
@@ -107,7 +108,9 @@ struct vgt_if {
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
 
-	u32  rsv7[0x200 - 24];    /* pad to one page */
+	u32 pv_caps;
+
+	u32  rsv7[0x200 - 25];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992..bb9f988 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -79,7 +79,14 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
 
 	dev_priv->vgpu.active = true;
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+	if (!intel_vgpu_check_pv_caps(dev_priv)) {
+		DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+		return;
+	}
+
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n",
+			dev_priv->vgpu.pv_caps);
 }
 
 bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
@@ -274,3 +281,38 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
 	DRM_ERROR("VGT balloon fail\n");
 	return ret;
 }
+
+/*
+ * i915 vgpu PV support for Linux
+ */
+
+/**
+ * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
+ * @dev_priv: i915 device private
+ *
+ * This function is called at the initialization stage, to detect VGPU
+ * PV capabilities
+ *
+ * If guest wants to enable pv_caps, it needs to config it explicitly
+ * through vgt_if interface from gvt layer.
+ */
+bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	u32 gvt_pvcaps;
+	u32 pvcaps = 0;
+
+	if (!intel_vgpu_has_pv_caps(dev_priv))
+		return false;
+
+	/* PV capability negotiation between PV guest and GVT */
+	gvt_pvcaps = __raw_uncore_read32(uncore, vgtif_reg(pv_caps));
+	pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps;
+	dev_priv->vgpu.pv_caps = pvcaps;
+	__raw_uncore_write32(uncore, vgtif_reg(pv_caps), pvcaps);
+
+	if (!pvcaps)
+		return false;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7b..91010fc 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,15 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
 }
 
+static inline bool
+intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv)
+{
+	return dev_priv->vgpu.caps & VGT_CAPS_PV;
+}
+
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 
+/* i915 vgpu pv related functions */
+bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv);
 #endif /* _I915_VGPU_H_ */
-- 
2.7.4

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[PATCH v6 2/8] drm/i915: vgpu shared memory setup for pv optimization

[Xiaolin Zhang]

To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.

guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page meory without any trap cost with the
help form hyperviser's read guest gpa functionality.

guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT
once shared memory setup finished.

the layout of the shared_page also defined as well in this patch which
is used for pv features implementation.

v0: RFC.
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure.
v2: packed i915_virtual_gpu structure.
v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c.
v5: per engine desc data in shared memory.
v6: added version support in shared memory (Zhenyu).

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  3 ++-
 drivers/gpu/drm/i915/i915_pvinfo.h |  5 +++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 48 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_vgpu.h   | 31 ++++++++++++++++++++++++
 4 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2bb38b4..9ccf37b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1244,7 +1244,8 @@ struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
-};
+	struct gvt_shared_page *shared_page;
+} __packed;
 
 /* used in computing the new watermarks state */
 struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 619305a..4657bf7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,7 @@ enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_SHARED_PAGE_SETUP,
 	VGT_G2V_MAX,
 };
 
@@ -110,7 +111,9 @@ struct vgt_if {
 
 	u32 pv_caps;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u64 shared_page_gpa;
+
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index bb9f988..6020515 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -135,6 +135,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
 
 	for (i = 0; i < 4; i++)
 		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+
+	if (dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -286,6 +289,46 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
  * i915 vgpu PV support for Linux
  */
 
+/*
+ * shared_page setup for VGPU PV features
+ */
+static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	struct gvt_shared_page *shared_page;
+	u64 gpa;
+	u16 ver_maj, ver_min;
+
+	shared_page =  (struct gvt_shared_page *)get_zeroed_page(GFP_KERNEL);
+	if (!shared_page) {
+		DRM_INFO("out of memory for shared page memory\n");
+		return -ENOMEM;
+	}
+
+	/* pass guest memory pa address to GVT and then read back to verify */
+	gpa = __pa(shared_page);
+	__raw_uncore_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
+	if (gpa != __raw_uncore_read64(uncore, vgtif_reg(shared_page_gpa))) {
+		DRM_INFO("vgpu: passed shared_page_gpa failed\n");
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
+		return -EIO;
+	}
+
+	__raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+			VGT_G2V_SHARED_PAGE_SETUP);
+	ver_maj = shared_page->ver_major;
+	ver_min = shared_page->ver_minor;
+	DRM_INFO("vgpu PV ver major %d and minor %d\n", ver_maj, ver_min);
+	if (ver_maj != PV_MAJOR || ver_min != PV_MINOR) {
+		DRM_INFO("vgpu: shared_page format incompatible\n");
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
+		return -EIO;
+	}
+
+	dev_priv->vgpu.shared_page = shared_page;
+	return 0;
+}
+
 /**
  * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
  * @dev_priv: i915 device private
@@ -305,9 +348,14 @@ bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
 	if (!intel_vgpu_has_pv_caps(dev_priv))
 		return false;
 
+	if (intel_vgpu_setup_shared_page(dev_priv))
+		goto err;
+
 	/* PV capability negotiation between PV guest and GVT */
 	gvt_pvcaps = __raw_uncore_read32(uncore, vgtif_reg(pv_caps));
 	pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps;
+
+err:
 	dev_priv->vgpu.pv_caps = pvcaps;
 	__raw_uncore_write32(uncore, vgtif_reg(pv_caps), pvcaps);
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 91010fc..1030f5a 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -26,6 +26,37 @@
 
 #include "i915_pvinfo.h"
 
+/*
+ * A shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a fixed location in PCI bar 0 region
+ */
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+struct pv_submission {
+	u64 descs[EXECLIST_MAX_PORTS];
+};
+
+#define PV_MAX_ENGINES_NUM (VECS1_HW + 1)
+#define PV_MAJOR		1
+#define PV_MINOR		0
+
+struct pv_buffer_desc {
+	struct pv_ppgtt_update pv_ppgtt;
+	struct pv_submission pv_elsp[PV_MAX_ENGINES_NUM];
+	bool submitted[PV_MAX_ENGINES_NUM];
+} __packed;
+
+struct gvt_shared_page {
+	u16 ver_major;
+	u16 ver_minor;
+	struct pv_buffer_desc buf;
+};
+
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
-- 
2.7.4

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[PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization

[Xiaolin Zhang]

This patch extends vgpu ppgtt g2v notification to notify host
GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4
and insert_4lvl.

These updates use the shared memory page to pass struct pv_ppgtt_update
from guest to GVT which is used for pv optimiation implemeation within
host GVT side.

This patch also add one new pv_caps level to control ppgtt update.

Use PV_PPGTT_UPDATE to control this level of pv optimization.

v0: RFC.
v1: rebased.
v2: added pv callbacks for vm.{allocate_va_range, insert_entries,
clear_range} within ppgtt.
v3: rebased, disable huge page ppgtt support when using PVMMIO ppgtt
update due to complex and performance impact.
v4: moved alloc/insert/clear_4lvl pv callbacks into i915_vgpu_pv.c and
added a single intel_vgpu_config_pv_caps() for vgpu pv callbacks setup.
v5: rebase.
v6: rebase.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c     |  3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c |  9 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.h |  8 ++++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  3 ++
 drivers/gpu/drm/i915/i915_vgpu.c    | 84 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_vgpu.h    | 17 ++++++++
 6 files changed, 120 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4739a630..975c784 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1507,7 +1507,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 	int ret;
 
 	/* We need to fallback to 4K pages if host doesn't support huge gtt. */
-	if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+	if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+		|| intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE))
 		mkwrite_device_info(dev_priv)->page_sizes =
 			I915_GTT_PAGE_SIZE_4K;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ca8a69e..480e8f4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -926,7 +926,7 @@ static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
  * This is the top-level structure in 4-level page tables used on gen8+.
  * Empty entries are always scratch pml4e.
  */
-static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 				  u64 start, u64 length)
 {
 	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1165,7 +1165,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
 	} while (iter->sg);
 }
 
-static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 				   struct i915_vma *vma,
 				   enum i915_cache_level cache_level,
 				   u32 flags)
@@ -1447,7 +1447,7 @@ static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
 				    &i915_vm_to_ppgtt(vm)->pdp, start, length);
 }
 
-static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 				 u64 start, u64 length)
 {
 	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1579,6 +1579,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+
+		if (intel_vgpu_active(i915))
+			intel_vgpu_config_pv_caps(i915, PV_PPGTT_UPDATE, ppgtt);
 	} else {
 		err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
 		if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 73b6608..2372f03 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -646,6 +646,14 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
 void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
 
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+		u64 start, u64 length);
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+		struct i915_vma *vma,
+		enum i915_cache_level cache_level, u32 flags);
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+		u64 start, u64 length);
+
 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 4657bf7..2408a9d 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -47,6 +47,9 @@ enum vgt_g2v_type {
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
 	VGT_G2V_SHARED_PAGE_SETUP,
+	VGT_G2V_PPGTT_L4_ALLOC,
+	VGT_G2V_PPGTT_L4_CLEAR,
+	VGT_G2V_PPGTT_L4_INSERT,
 	VGT_G2V_MAX,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 6020515..418582c 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -80,6 +80,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	dev_priv->vgpu.active = true;
 
+	/* guest driver PV capability */
+	dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE;
+
 	if (!intel_vgpu_check_pv_caps(dev_priv)) {
 		DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 		return;
@@ -289,6 +292,87 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
  * i915 vgpu PV support for Linux
  */
 
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->buf.pv_ppgtt;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	gen8_ppgtt_clear_4lvl(vm, start, length);
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
+}
+
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+				   struct i915_vma *vma,
+				   enum i915_cache_level cache_level,
+				   u32 flags)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->buf.pv_ppgtt;
+
+	gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
+
+	pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+	pv_ppgtt->start = vma->node.start;
+	pv_ppgtt->length = vma->node.size;
+	pv_ppgtt->cache_level = cache_level;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
+}
+
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+				 u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->buf.pv_ppgtt;
+	int ret;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	ret = gen8_ppgtt_alloc_4lvl(vm, start, length);
+	if (ret)
+		return ret;
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+
+	return 0;
+}
+
+/*
+ * config guest driver PV ops for different PV features
+ */
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap, void *data)
+{
+	struct i915_hw_ppgtt *ppgtt;
+
+	if (!intel_vgpu_enabled_pv_caps(dev_priv, cap))
+		return;
+
+	if (cap == PV_PPGTT_UPDATE) {
+		ppgtt = (struct i915_hw_ppgtt *)data;
+		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv;
+		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
+		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
+	}
+}
+
 /*
  * shared_page setup for VGPU PV features
  */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 1030f5a..7a39748 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -27,6 +27,13 @@
 #include "i915_pvinfo.h"
 
 /*
+ * define different capabilities of PV optimization
+ */
+enum pv_caps {
+	PV_PPGTT_UPDATE = 0x1,
+};
+
+/*
  * A shared page(4KB) between gvt and VM, could be allocated by guest driver
  * or a fixed location in PCI bar 0 region
  */
@@ -79,9 +86,19 @@ intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_PV;
 }
 
+static inline bool
+intel_vgpu_enabled_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap)
+{
+	return intel_vgpu_active(dev_priv) && intel_vgpu_has_pv_caps(dev_priv)
+			&& (dev_priv->vgpu.pv_caps & cap);
+}
+
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 
 /* i915 vgpu pv related functions */
 bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv);
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap, void *data);
 #endif /* _I915_VGPU_H_ */
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 4/8] drm/i915: vgpu context submission pv optimization

[Xiaolin Zhang]

It is performance optimization to override the actual submisison backend
in order to eliminate execlists csb process and reduce mmio trap numbers
for workload submission without context switch interrupt by talking with
GVT via PV submisison notification mechanism between guest and GVT.

Use PV_SUBMISSION to control this level of pv optimization.

v0: RFC.
v1: rebase.
v2: added pv ops for pv context submission. to maximize code resuse,
introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of
submit_ports and preempt_context implemented.
v3:
1. to reduce more code duplication, code refactor and replaced 2 ops
"submit_ports & preempt_contex" from v2 by 1 ops "write_desc"
in engine structure. pv version of write_des implemented.
2. added VGT_G2V_ELSP_SUBMIT for g2v pv notification.
v4: implemented pv elsp submission tasklet as the backend workload
submisison by talking to GVT with PV notificaiton mechanism and renamed
VGT_G2V_ELSP_SUBMIT to VGT_G2V_PV_SUBMISIION.
v5: addressed v4 comments from Chris, intel_pv_submission.c added.
v6: addressed v5 comments from Chris, replaced engine id by hw_id.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/Makefile              |   2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c        |   8 +-
 drivers/gpu/drm/i915/i915_pvinfo.h         |   1 +
 drivers/gpu/drm/i915/i915_vgpu.c           |   8 +-
 drivers/gpu/drm/i915/i915_vgpu.h           |   3 +
 drivers/gpu/drm/i915/intel_pv_submission.c | 166 +++++++++++++++++++++++++++++
 6 files changed, 184 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_pv_submission.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7850bb..86d11ba 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -215,7 +215,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
 	selftests/igt_spinner.o
 
 # virtual gpu code
-i915-y += i915_vgpu.o
+i915-y += i915_vgpu.o intel_pv_submission.o
 
 # perf code
 i915-y += i915_perf.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fed7048..86f46dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2644,11 +2644,15 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
 	engine->unpark = NULL;
 
 	engine->flags |= I915_ENGINE_SUPPORTS_STATS;
-	if (!intel_vgpu_active(engine->i915))
-		engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+	engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
 	if (engine->preempt_context &&
 	    HAS_LOGICAL_RING_PREEMPTION(engine->i915))
 		engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+
+	if (intel_vgpu_active(engine->i915)) {
+		engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
+		intel_vgpu_config_pv_caps(engine->i915,	PV_SUBMISSION, engine);
+	}
 }
 
 static void execlists_destroy(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 2408a9d..362d898 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -50,6 +50,7 @@ enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_ALLOC,
 	VGT_G2V_PPGTT_L4_CLEAR,
 	VGT_G2V_PPGTT_L4_INSERT,
+	VGT_G2V_PV_SUBMISSION,
 	VGT_G2V_MAX,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 418582c..723aa80 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,7 +81,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	dev_priv->vgpu.active = true;
 
 	/* guest driver PV capability */
-	dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE;
+	dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE | PV_SUBMISSION;
 
 	if (!intel_vgpu_check_pv_caps(dev_priv)) {
 		DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
@@ -361,6 +361,7 @@ void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
 		enum pv_caps cap, void *data)
 {
 	struct i915_hw_ppgtt *ppgtt;
+	struct intel_engine_cs *engine;
 
 	if (!intel_vgpu_enabled_pv_caps(dev_priv, cap))
 		return;
@@ -371,6 +372,11 @@ void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
 	}
+
+	if (cap == PV_SUBMISSION) {
+		engine = (struct intel_engine_cs *)data;
+		vgpu_set_pv_submission(engine);
+	}
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 7a39748..c5b1c33 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -31,6 +31,7 @@
  */
 enum pv_caps {
 	PV_PPGTT_UPDATE = 0x1,
+	PV_SUBMISSION = 0x2,
 };
 
 /*
@@ -101,4 +102,6 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv);
 void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
 		enum pv_caps cap, void *data);
+void vgpu_set_pv_submission(struct intel_engine_cs *engine);
+
 #endif /* _I915_VGPU_H_ */
diff --git a/drivers/gpu/drm/i915/intel_pv_submission.c b/drivers/gpu/drm/i915/intel_pv_submission.c
new file mode 100644
index 0000000..9036fd4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_pv_submission.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "intel_drv.h"
+#include "i915_vgpu.h"
+#include "gt/intel_lrc_reg.h"
+#include "gt/intel_engine_pm.h"
+
+static u64 execlists_update_context(struct i915_request *rq)
+{
+	struct intel_context *ce = rq->hw_context;
+	u32 *reg_state = ce->lrc_reg_state;
+
+	reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
+
+	return ce->lrc_desc;
+}
+
+static inline struct i915_priolist *to_priolist(struct rb_node *rb)
+{
+	return rb_entry(rb, struct i915_priolist, node);
+}
+
+static void pv_submit(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
+	unsigned int n;
+	struct gvt_shared_page *shared_page = engine->i915->vgpu.shared_page;
+	u64 descs[2];
+
+	for (n = 0; n < execlists_num_ports(execlists); n++) {
+		struct i915_request *rq;
+		unsigned int count = 0;
+
+		descs[n] = 0;
+		rq = port_unpack(&port[n], &count);
+		if (rq && count == 0) {
+			port_set(&port[n], port_pack(rq, ++count));
+			descs[n] = execlists_update_context(rq);
+		}
+	}
+
+	for (n = 0; n < execlists_num_ports(execlists); n++)
+		shared_page->buf.pv_elsp[engine->hw_id].descs[n] = descs[n];
+
+	writel(VGT_G2V_PV_SUBMISSION, execlists->submit_reg);
+	if (shared_page->buf.submitted[engine->hw_id])
+		shared_page->buf.submitted[engine->hw_id] = false;
+	else
+		DRM_ERROR("engine(%s) pv submission failed\n", engine->name);
+}
+
+static void pv_dequeue(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
+	struct i915_request *last = NULL;
+	bool submit = false;
+	struct rb_node *rb;
+
+	lockdep_assert_held(&engine->timeline.lock);
+
+	while ((rb = rb_first_cached(&execlists->queue))) {
+		struct i915_priolist *p = to_priolist(rb);
+		struct i915_request *rq, *rn;
+		int i;
+
+		priolist_for_each_request_consume(rq, rn, p, i) {
+			if (last && rq->hw_context != last->hw_context)
+				goto done;
+
+			list_del_init(&rq->sched.link);
+
+			__i915_request_submit(rq);
+			trace_i915_request_in(rq, port_index(port, execlists));
+
+			last = rq;
+			submit = true;
+		}
+
+		rb_erase_cached(&p->node, &execlists->queue);
+		i915_priolist_free(p);
+	}
+done:
+	execlists->queue_priority_hint =
+			rb ? to_priolist(rb)->priority : INT_MIN;
+	if (submit) {
+		port_set(port, i915_request_get(last));
+		pv_submit(engine);
+	}
+	if (last)
+		execlists_user_begin(execlists, execlists->port);
+
+	/* We must always keep the beast fed if we have work piled up */
+	GEM_BUG_ON(port_isset(execlists->port) &&
+		   !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
+	GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
+		   !port_isset(execlists->port));
+}
+
+static void vgpu_pv_submission_tasklet(unsigned long data)
+{
+	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
+	struct intel_engine_execlists * const execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
+	struct i915_request *rq;
+	unsigned long flags;
+
+	spin_lock_irqsave(&engine->timeline.lock, flags);
+
+	rq = port_request(port);
+	while (rq && i915_request_completed(rq)) {
+		trace_i915_request_out(rq);
+		i915_request_put(rq);
+
+		port = execlists_port_complete(execlists, port);
+		if (port_isset(port)) {
+			execlists_user_begin(execlists, port);
+			rq = port_request(port);
+		} else {
+			execlists_user_end(execlists);
+			rq = NULL;
+		}
+	}
+
+	if (!rq)
+		pv_dequeue(engine);
+
+	spin_unlock_irqrestore(&engine->timeline.lock, flags);
+}
+
+static void vgpu_pv_submission_park(struct intel_engine_cs *engine)
+{
+	intel_engine_park(engine);
+	intel_engine_unpin_breadcrumbs_irq(engine);
+	engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+}
+
+static void vgpu_pv_submission_unpark(struct intel_engine_cs *engine)
+{
+	engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+	intel_engine_pin_breadcrumbs_irq(engine);
+}
+
+void vgpu_set_pv_submission(struct intel_engine_cs *engine)
+{
+	/*
+	 * We inherit a bunch of functions from execlists that we'd like
+	 * to keep using:
+	 *
+	 *    engine->submit_request = execlists_submit_request;
+	 *    engine->cancel_requests = execlists_cancel_requests;
+	 *    engine->schedule = execlists_schedule;
+	 *
+	 * But we need to override the actual submission backend in order
+	 * to talk to the GVT with PV notification message.
+	 */
+
+	engine->execlists.tasklet.func = vgpu_pv_submission_tasklet;
+
+	engine->park = vgpu_pv_submission_park;
+	engine->unpark = vgpu_pv_submission_unpark;
+}
-- 
2.7.4

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 5/8] drm/i915/gvt: GVTg handle pv_caps PVINFO register

[Xiaolin Zhang]

implement pv_caps PVINFO register handler in GVTg to
control different level pv optimization within guest.

report VGT_CAPS_PV capability in pvinfo page for guest.

v0: RFC.
v1: rebase.
v2: rebase.
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
v4: renamed pvmmio_caps to pv_caps.
v5: rebase.
v6: rebase.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 4 ++++
 drivers/gpu/drm/i915/gvt/vgpu.c     | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7732caa..fd2f72c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1194,6 +1194,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 		break;
 	case 0x78010:	/* vgt_caps */
 	case 0x7881c:
+	case _vgtif_reg(pv_caps):
 		break;
 	default:
 		invalid_read = true;
@@ -1267,6 +1268,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	case _vgtif_reg(g2v_notify):
 		ret = handle_g2v_notification(vgpu, data);
 		break;
+	case _vgtif_reg(pv_caps):
+		DRM_INFO("vgpu id=%d pv caps =0x%x\n", vgpu->id, data);
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 44ce3c2..3ecc45a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -47,6 +47,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PV;
 
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
@@ -531,6 +532,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
 	struct intel_gvt *gvt = vgpu->gvt;
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 	intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
+	int pv_caps = vgpu_vreg_t(vgpu, vgtif_reg(pv_caps));
 
 	gvt_dbg_core("------------------------------------------\n");
 	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -562,6 +564,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
 
 		intel_vgpu_reset_mmio(vgpu, dmlr);
 		populate_pvinfo_page(vgpu);
+		vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = pv_caps;
 		intel_vgpu_reset_display(vgpu);
 
 		if (dmlr) {
-- 
2.7.4

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 6/8] drm/i915/gvt: GVTg handle shared_page setup

[Xiaolin Zhang]

GVTg implemented shared_page setup operation and read_shared_page
functionality based on hypervisor_read_gpa().

the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.

v0: RFC.
v1: rebase.
v2: rebase.
v3: added shared_page_gpa check and if read_gpa failure, return zero
memory and handle VGT_G2V_SHARED_PAGE_SETUP g2v notification
v4: rebase.
v5: rebase.
v6: rebase, added PV version support.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gvt.h      |  8 ++++++-
 drivers/gpu/drm/i915/gvt/handlers.c | 20 +++++++++++++++++
 drivers/gpu/drm/i915/gvt/vgpu.c     | 43 +++++++++++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index b54f2bd..1efbf68 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -49,6 +49,7 @@
 #include "fb_decoder.h"
 #include "dmabuf.h"
 #include "page_track.h"
+#include "i915_vgpu.h"
 
 #define GVT_MAX_VGPU 8
 
@@ -229,6 +230,8 @@ struct intel_vgpu {
 	struct completion vblank_done;
 
 	u32 scan_nonprivbb;
+	u64 shared_page_gpa;
+	bool shared_page_enabled;
 };
 
 /* validating GM healthy status*/
@@ -686,7 +689,10 @@ int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
 int intel_gvt_debugfs_init(struct intel_gvt *gvt);
 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
-
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);
 
 #include "trace.h"
 #include "mpt.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index fd2f72c..79679da 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1195,6 +1195,8 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 	case 0x78010:	/* vgt_caps */
 	case 0x7881c:
 	case _vgtif_reg(pv_caps):
+	case _vgtif_reg(shared_page_gpa):
+	case _vgtif_reg(shared_page_gpa) + 4:
 		break;
 	default:
 		invalid_read = true;
@@ -1212,6 +1214,9 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
 	struct intel_vgpu_mm *mm;
 	u64 *pdps;
+	unsigned long gpa, gfn;
+	u16 ver_major = PV_MAJOR;
+	u16 ver_minor = PV_MINOR;
 
 	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
 
@@ -1225,6 +1230,19 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
 	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
 		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
+	case VGT_G2V_SHARED_PAGE_SETUP:
+		gpa = vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa));
+		gfn = gpa >> PAGE_SHIFT;
+		if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
+			vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = 0;
+			return 0;
+		}
+		vgpu->shared_page_gpa = gpa;
+		vgpu->shared_page_enabled = true;
+
+		intel_gvt_write_shared_page(vgpu, 0, &ver_major, 2);
+		intel_gvt_write_shared_page(vgpu, 2, &ver_minor, 2);
+		break;
 	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
 	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
 	case 1:	/* Remove this in guest driver. */
@@ -1284,6 +1302,8 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	case _vgtif_reg(pdp[3].hi):
 	case _vgtif_reg(execlist_context_descriptor_lo):
 	case _vgtif_reg(execlist_context_descriptor_hi):
+	case _vgtif_reg(shared_page_gpa):
+	case _vgtif_reg(shared_page_gpa) + 4:
 		break;
 	case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
 		enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 3ecc45a..8cba30d 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -63,6 +63,8 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
 
+	vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa)) = 0;
+
 	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
 	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
 		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
@@ -593,3 +595,44 @@ void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
 	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
 	mutex_unlock(&vgpu->vgpu_lock);
 }
+
+/**
+ * intel_gvt_read_shared_page - read content from shared page
+ */
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)
+{
+	int ret = -EINVAL;
+	unsigned long gpa;
+
+	if (offset >= sizeof(struct gvt_shared_page))
+		goto err;
+
+	gpa = vgpu->shared_page_gpa + offset;
+	ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa, buf, len);
+	if (!ret)
+		return ret;
+err:
+	gvt_vgpu_err("read shared page (offset %x) failed", offset);
+	memset(buf, 0, len);
+	return ret;
+}
+
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)
+{
+	int ret = -EINVAL;
+	unsigned long gpa;
+
+	if (offset >= sizeof(struct gvt_shared_page))
+		goto err;
+
+	gpa = vgpu->shared_page_gpa + offset;
+	ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa, buf, len);
+	if (!ret)
+		return ret;
+err:
+	gvt_vgpu_err("write shared page (offset %x) failed", offset);
+	memset(buf, 0, len);
+	return ret;
+}
-- 
2.7.4

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[PATCH v6 7/8] drm/i915/gvt: GVTg support ppgtt pv optimization

[Xiaolin Zhang]

This patch handles ppgtt update from g2v notification.

It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.

It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and removes the cost of write
protection from the original shadow page mechansim.

v0: RFC.
v1: rebase.
v2: rebase.
v3: report pv pggtt cap to guest.
v4: renamed VGPU_PVMMIO with VGPU_PVCAP for name consistance, no PV
support if gfx vtd enabled.
v5: rebase.
v6: rebase.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c      | 317 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h      |   9 +
 drivers/gpu/drm/i915/gvt/gvt.h      |   4 +
 drivers/gpu/drm/i915/gvt/handlers.c |  12 +-
 drivers/gpu/drm/i915/gvt/vgpu.c     |   3 +
 5 files changed, 344 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index d767c45..b78b872 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1761,6 +1761,25 @@ static int ppgtt_handle_guest_write_page_table_bytes(
 	return 0;
 }
 
+static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
+{
+	struct intel_vgpu *vgpu = mm->vgpu;
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt *gtt = &gvt->gtt;
+	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+	struct intel_gvt_gtt_entry se;
+
+	i915_ppgtt_put(mm->ppgtt);
+
+	ppgtt_get_shadow_root_entry(mm, &se, 0);
+	if (!ops->test_present(&se))
+		return;
+	se.val64 = 0;
+	ppgtt_set_shadow_root_entry(mm, &se, 0);
+
+	mm->ppgtt_mm.shadowed  = false;
+}
+
 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 {
 	struct intel_vgpu *vgpu = mm->vgpu;
@@ -1773,6 +1792,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 	if (!mm->ppgtt_mm.shadowed)
 		return;
 
+	if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE)) {
+		invalidate_mm_pv(mm);
+		return;
+	}
+
 	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
 		ppgtt_get_shadow_root_entry(mm, &se, index);
 
@@ -1790,6 +1814,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 	mm->ppgtt_mm.shadowed = false;
 }
 
+static int shadow_mm_pv(struct intel_vgpu_mm *mm)
+{
+	struct intel_vgpu *vgpu = mm->vgpu;
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt_entry se;
+
+	mm->ppgtt = i915_ppgtt_create(gvt->dev_priv);
+	if (IS_ERR(mm->ppgtt)) {
+		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+				px_dma(&mm->ppgtt->pml4));
+		return PTR_ERR(mm->ppgtt);
+	}
+
+	se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
+	se.val64 = px_dma(&mm->ppgtt->pml4);
+	ppgtt_set_shadow_root_entry(mm, &se, 0);
+	mm->ppgtt_mm.shadowed  = true;
+
+	return 0;
+}
 
 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
 {
@@ -1804,6 +1848,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
 	if (mm->ppgtt_mm.shadowed)
 		return 0;
 
+	if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE))
+		return shadow_mm_pv(mm);
+
 	mm->ppgtt_mm.shadowed = true;
 
 	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
@@ -2806,3 +2853,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
 	intel_vgpu_destroy_all_ppgtt_mm(vgpu);
 	intel_vgpu_reset_ggtt(vgpu, true);
 }
+
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	int ret = 0;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, buf.pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+	if (!mm) {
+		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+		ret = -EINVAL;
+	} else {
+		ret = mm->ppgtt->vm.allocate_va_range(&mm->ppgtt->vm,
+			pv_ppgtt.start, pv_ppgtt.length);
+		if (ret)
+			gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
+	}
+
+	return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	int ret = 0;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, buf.pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+	if (!mm) {
+		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+		ret = -EINVAL;
+	} else {
+		mm->ppgtt->vm.clear_range(&mm->ppgtt->vm,
+			pv_ppgtt.start, pv_ppgtt.length);
+	}
+
+	return ret;
+}
+
+#define GEN8_PML4E_SIZE		(1UL << GEN8_PML4E_SHIFT)
+#define GEN8_PML4E_SIZE_MASK	(~(GEN8_PML4E_SIZE - 1))
+#define GEN8_PDPE_SIZE		(1UL << GEN8_PDPE_SHIFT)
+#define GEN8_PDPE_SIZE_MASK	(~(GEN8_PDPE_SIZE - 1))
+#define GEN8_PDE_SIZE		(1UL << GEN8_PDE_SHIFT)
+#define GEN8_PDE_SIZE_MASK	(~(GEN8_PDE_SIZE - 1))
+
+#define pml4_addr_end(addr, end)					\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+#define pdp_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+#define pd_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+struct ppgtt_walk {
+	unsigned long *mfns;
+	int mfn_index;
+	unsigned long *pt;
+};
+
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long start_index, end_index;
+	int ret;
+	int i;
+	unsigned long mfn, gfn;
+
+	start_index = gma_ops->gma_to_pte_index(start);
+	end_index = ((end - start) >> PAGE_SHIFT) + start_index;
+
+	ret = intel_gvt_hypervisor_read_gpa(vgpu,
+		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
+		walk->pt + start_index,
+		(end_index - start_index) << info->gtt_entry_size_shift);
+	if (ret) {
+		gvt_vgpu_err("fail to read gpa %llx\n", pt);
+		return ret;
+	}
+
+	for (i = start_index; i < end_index; i++) {
+		gfn = walk->pt[i] >> PAGE_SHIFT;
+		mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
+		if (mfn == INTEL_GVT_INVALID_ADDR) {
+			gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
+			return -ENXIO;
+		}
+		walk->mfns[walk->mfn_index++] = mfn << PAGE_SHIFT;
+	}
+
+	return 0;
+}
+
+
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pt, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_pde_index(start);
+
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pd & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pt, 8);
+		if (ret)
+			return ret;
+		next = pd_addr_end(start, end);
+		walk_pt_range(vgpu, pt, start, next, walk);
+
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+				  u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pd, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_l4_pdp_index(start);
+
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pdp & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pd, 8);
+		if (ret)
+			return ret;
+		next = pdp_addr_end(start, end);
+		walk_pd_range(vgpu, pd, start, next, walk);
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pdp, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_pml4_index(start);
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pml4 & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pdp, 8);
+		if (ret)
+			return ret;
+		next = pml4_addr_end(start, end);
+		walk_pdp_range(vgpu, pdp, start, next, walk);
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	u64 pml4, start, length;
+	u32 cache_level;
+	int ret = 0;
+	struct sg_table st;
+	struct scatterlist *sg = NULL;
+	int num_pages;
+	struct i915_vma vma;
+	struct ppgtt_walk walk;
+	int i;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, buf.pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+	pml4 = pv_ppgtt.pdp;
+	start = pv_ppgtt.start;
+	length = pv_ppgtt.length;
+	cache_level = pv_ppgtt.cache_level;
+	num_pages = length >> PAGE_SHIFT;
+
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pml4);
+	if (!mm) {
+		gvt_vgpu_err("fail to find mm for pml4 0x%llx\n", pml4);
+		return -EINVAL;
+	}
+
+	walk.mfn_index = 0;
+	walk.mfns = NULL;
+	walk.pt = NULL;
+
+	walk.mfns = kmalloc_array(num_pages,
+			sizeof(unsigned long), GFP_KERNEL);
+	if (!walk.mfns) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	walk.pt = (unsigned long *)__get_free_pages(GFP_KERNEL, 0);
+	if (!walk.pt) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	if (sg_alloc_table(&st, num_pages, GFP_KERNEL)) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	ret = walk_pml4_range(vgpu, pml4, start, start + length, &walk);
+	if (ret)
+		goto fail_free_sg;
+
+	WARN_ON(num_pages != walk.mfn_index);
+
+	for_each_sg(st.sgl, sg, num_pages, i) {
+		sg->offset = 0;
+		sg->length = PAGE_SIZE;
+		sg_dma_address(sg) = walk.mfns[i];
+		sg_dma_len(sg) = PAGE_SIZE;
+	}
+
+	memset(&vma, 0, sizeof(vma));
+	vma.node.start = start;
+	vma.pages = &st;
+	mm->ppgtt->vm.insert_entries(&mm->ppgtt->vm, &vma, cache_level, 0);
+
+fail_free_sg:
+	sg_free_table(&st);
+fail:
+	kfree(walk.mfns);
+	free_page((unsigned long)walk.pt);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 42d0394..31926ca 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -141,6 +141,7 @@ struct intel_gvt_partial_pte {
 
 struct intel_vgpu_mm {
 	enum intel_gvt_mm_type type;
+	struct i915_hw_ppgtt *ppgtt;
 	struct intel_vgpu *vgpu;
 
 	struct kref ref;
@@ -277,4 +278,12 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
 	unsigned int off, void *p_data, unsigned int bytes);
 
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
+
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
 #endif /* _GVT_GTT_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 1efbf68..ba05bc4 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -53,6 +53,10 @@
 
 #define GVT_MAX_VGPU 8
 
+#define VGPU_PVCAP(vgpu, cap)	\
+	((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \
+			&& vgpu->shared_page_enabled)
+
 struct intel_gvt_host {
 	struct device *dev;
 	bool initialized;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 79679da..1e09c23 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1217,6 +1217,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	unsigned long gpa, gfn;
 	u16 ver_major = PV_MAJOR;
 	u16 ver_minor = PV_MINOR;
+	int ret = 0;
 
 	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
 
@@ -1243,6 +1244,15 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 		intel_gvt_write_shared_page(vgpu, 0, &ver_major, 2);
 		intel_gvt_write_shared_page(vgpu, 2, &ver_minor, 2);
 		break;
+	case VGT_G2V_PPGTT_L4_ALLOC:
+		ret = intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(vgpu, pdps);
+			break;
+	case VGT_G2V_PPGTT_L4_INSERT:
+		ret = intel_vgpu_g2v_pv_ppgtt_insert_4lvl(vgpu, pdps);
+		break;
+	case VGT_G2V_PPGTT_L4_CLEAR:
+		ret = intel_vgpu_g2v_pv_ppgtt_clear_4lvl(vgpu, pdps);
+		break;
 	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
 	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
 	case 1:	/* Remove this in guest driver. */
@@ -1250,7 +1260,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	default:
 		gvt_vgpu_err("Invalid PV notification %d\n", notification);
 	}
-	return 0;
+	return ret;
 }
 
 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 8cba30d..57eaf56 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -49,6 +49,9 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PV;
 
+	if (!intel_vtd_active())
+		vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = PV_PPGTT_UPDATE;
+
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 8/8] drm/i915/gvt: GVTg support context submission pv optimization

[Xiaolin Zhang]

implemented context submission pv optimizaiton within GVTg.

GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost and eliminate execlist HW behavior emulation
without injecting context switch interrupt to guest under PV
submisison mechanism.

v0: RFC.
v1: rebase.
v2: rebase.
v3: report pv context submission cap and handle VGT_G2V_ELSP_SUBMIT
g2v pv notification.
v4: eliminate execlist HW emulation and don't inject context switch
interrupt to guest under PV submisison mechanism.
v5: rebase.
v6: rebase.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/execlist.c |  6 ++++++
 drivers/gpu/drm/i915/gvt/handlers.c | 29 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/gvt/vgpu.c     |  1 +
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index f21b8fb..e52bfd6 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -382,6 +382,9 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
 	int ring_id = workload->ring_id;
 	int ret;
 
+	if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+		return 0;
+
 	if (!workload->emulate_schedule_in)
 		return 0;
 
@@ -429,6 +432,9 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
 		goto out;
 	}
 
+	if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+		goto out;
+
 	ret = emulate_execlist_ctx_schedule_out(execlist, &workload->ctx_desc);
 out:
 	intel_vgpu_unpin_mm(workload->shadow_mm);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 1e09c23..9cff9396 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1692,6 +1692,31 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
 }
 
+static int handle_pv_submission(struct intel_vgpu *vgpu, int ring_id)
+{
+	struct intel_vgpu_execlist *execlist;
+	u32 hw_id = vgpu->gvt->dev_priv->engine[ring_id]->hw_id;
+	u32 pv_elsp_off = offsetof(struct gvt_shared_page, buf.pv_elsp);
+	u32 submitted_off = offsetof(struct gvt_shared_page, buf.submitted);
+	bool submitted = true;
+	int ret;
+
+	execlist = &vgpu->submission.execlist[ring_id];
+
+	pv_elsp_off += hw_id * sizeof(struct pv_submission);
+	if (intel_gvt_read_shared_page(vgpu, pv_elsp_off,
+		&execlist->elsp_dwords.data, sizeof(struct pv_submission)))
+		return -EINVAL;
+
+	ret = intel_vgpu_submit_execlist(vgpu, ring_id);
+	if (ret)
+		submitted = false;
+
+	submitted_off += hw_id;
+	ret = intel_gvt_write_shared_page(vgpu, submitted_off, &submitted, 1);
+	return ret;
+}
+
 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
 {
@@ -1703,8 +1728,10 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
 		return -EINVAL;
 
-	execlist = &vgpu->submission.execlist[ring_id];
+	if (VGPU_PVCAP(vgpu, PV_SUBMISSION) && VGT_G2V_PV_SUBMISSION == data)
+		return handle_pv_submission(vgpu, ring_id);
 
+	execlist = &vgpu->submission.execlist[ring_id];
 	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
 	if (execlist->elsp_dwords.index == 3) {
 		ret = intel_vgpu_submit_execlist(vgpu, ring_id);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 57eaf56..debdb88 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -51,6 +51,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 
 	if (!intel_vtd_active())
 		vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = PV_PPGTT_UPDATE;
+	vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) |= PV_SUBMISSION;
 
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for i915 vgpu PV to improve vgpu performance

[Patchwork]

== Series Details ==

Series: i915 vgpu PV to improve vgpu performance
URL   : https://patchwork.freedesktop.org/series/61493/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b84d8b472a53 drm/i915: introduced vgpu pv capability
-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/i915_vgpu.c:89:
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n",
+			dev_priv->vgpu.pv_caps);

total: 0 errors, 0 warnings, 1 checks, 99 lines checked
8f6296420e40 drm/i915: vgpu shared memory setup for pv optimization
-:113: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#113: FILE: drivers/gpu/drm/i915/i915_vgpu.c:318:
+	__raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+			VGT_G2V_SHARED_PAGE_SETUP);

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
61bce586be7a drm/i915: vgpu ppgtt update pv optimization
-:41: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#41: FILE: drivers/gpu/drm/i915/i915_gem.c:1511:
+	if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+		|| intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE))

-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:930:
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 				  u64 start, u64 length)

-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#64: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1169:
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 				   struct i915_vma *vma,

-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1451:
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 				 u64 start, u64 length)

-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:650:
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+		u64 start, u64 length);

-:97: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#97: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:652:
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+		struct i915_vma *vma,

-:100: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#100: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:655:
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+		u64 start, u64 length);

-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/i915_vgpu.c:296:
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+				  u64 start, u64 length)

-:157: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#157: FILE: drivers/gpu/drm/i915/i915_vgpu.c:315:
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+				   struct i915_vma *vma,

-:176: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#176: FILE: drivers/gpu/drm/i915/i915_vgpu.c:334:
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+				 u64 start, u64 length)

-:203: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#203: FILE: drivers/gpu/drm/i915/i915_vgpu.c:361:
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap, void *data)

-:245: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#245: FILE: drivers/gpu/drm/i915/i915_vgpu.h:91:
+intel_vgpu_enabled_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap)

-:248: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#248: FILE: drivers/gpu/drm/i915/i915_vgpu.h:94:
+	return intel_vgpu_active(dev_priv) && intel_vgpu_has_pv_caps(dev_priv)
+			&& (dev_priv->vgpu.pv_caps & cap);

-:257: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#257: FILE: drivers/gpu/drm/i915/i915_vgpu.h:103:
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+		enum pv_caps cap, void *data);

total: 0 errors, 0 warnings, 14 checks, 193 lines checked
f1b3f498ebea drm/i915: vgpu context submission pv optimization
-:132: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#132: 
new file mode 100644

-:152: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#152: FILE: drivers/gpu/drm/i915/intel_pv_submission.c:16:
+	reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
 	                       ^

total: 0 errors, 1 warnings, 1 checks, 237 lines checked
40ce001e1ce8 drm/i915/gvt: GVTg handle pv_caps PVINFO register
4becca4775d1 drm/i915/gvt: GVTg handle shared_page setup
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/gvt/gvt.h:693:
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);

-:52: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#52: FILE: drivers/gpu/drm/i915/gvt/gvt.h:695:
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);

-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:603:
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)

-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:622:
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)

total: 0 errors, 0 warnings, 4 checks, 122 lines checked
3626e6547796 drm/i915/gvt: GVTg support ppgtt pv optimization
-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/gvt/gtt.c:1826:
+		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+				px_dma(&mm->ppgtt->pml4));

-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2858:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2883:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:165: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#165: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2911:
+#define pml4_addr_end(addr, end)					\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:171: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#171: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2917:
+#define pdp_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:177: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#177: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2923:
+#define pd_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2936:
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:203: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#203: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2949:
+	ret = intel_gvt_hypervisor_read_gpa(vgpu,
+		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),

-:224: CHECK:LINE_SPACING: Please don't use multiple blank lines
#224: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2970:
+
+

-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2972:
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:238: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#238: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2984:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pd & PAGE_MASK) + (index <<

-:251: CHECK:LINE_SPACING: Please don't use multiple blank lines
#251: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2997:
+
+

-:253: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#253: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2999:
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+				  u64 start, u64 end, struct ppgtt_walk *walk)

-:265: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#265: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3011:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pdp & PAGE_MASK) + (index <<

-:277: CHECK:LINE_SPACING: Please don't use multiple blank lines
#277: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3023:
+
+

-:279: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#279: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3025:
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:290: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#290: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3036:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pml4 & PAGE_MASK) + (index <<

-:303: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#303: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3049:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:337: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#337: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3083:
+	walk.mfns = kmalloc_array(num_pages,
+			sizeof(unsigned long), GFP_KERNEL);

-:397: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#397: FILE: drivers/gpu/drm/i915/gvt/gtt.h:282:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

-:400: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#400: FILE: drivers/gpu/drm/i915/gvt/gtt.h:285:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

-:403: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#403: FILE: drivers/gpu/drm/i915/gvt/gtt.h:288:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

-:413: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vgpu' - possible side-effects?
#413: FILE: drivers/gpu/drm/i915/gvt/gvt.h:56:
+#define VGPU_PVCAP(vgpu, cap)	\
+	((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \
+			&& vgpu->shared_page_enabled)

-:415: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#415: FILE: drivers/gpu/drm/i915/gvt/gvt.h:58:
+	((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \
+			&& vgpu->shared_page_enabled)

total: 0 errors, 0 warnings, 24 checks, 412 lines checked
fa6226cbb013 drm/i915/gvt: GVTg support context submission pv optimization
-:70: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#70: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1708:
+	if (intel_gvt_read_shared_page(vgpu, pv_elsp_off,
+		&execlist->elsp_dwords.data, sizeof(struct pv_submission)))

total: 0 errors, 0 warnings, 1 checks, 67 lines checked

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for i915 vgpu PV to improve vgpu performance

[Patchwork]

== Series Details ==

Series: i915 vgpu PV to improve vgpu performance
URL   : https://patchwork.freedesktop.org/series/61493/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: introduced vgpu pv capability
Okay!

Commit: drm/i915: vgpu shared memory setup for pv optimization
Okay!

Commit: drm/i915: vgpu ppgtt update pv optimization
Okay!

Commit: drm/i915: vgpu context submission pv optimization
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)

Commit: drm/i915/gvt: GVTg handle pv_caps PVINFO register
Okay!

Commit: drm/i915/gvt: GVTg handle shared_page setup
Okay!

Commit: drm/i915/gvt: GVTg support ppgtt pv optimization
+./include/linux/slab.h:666:13: error: undefined identifier '__builtin_mul_overflow'
+./include/linux/slab.h:666:13: warning: call with no type!

Commit: drm/i915/gvt: GVTg support context submission pv optimization
Okay!

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for i915 vgpu PV to improve vgpu performance

[Patchwork]

== Series Details ==

Series: i915 vgpu PV to improve vgpu performance
URL   : https://patchwork.freedesktop.org/series/61493/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6179 -> Patchwork_13156
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/

Known issues
------------

  Here are the changes found in Patchwork_13156 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_basic@bad-close:
    - fi-icl-u2:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-icl-u2/igt@gem_basic@bad-close.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-icl-u2/igt@gem_basic@bad-close.html

  * igt@gem_ctx_exec@basic:
    - fi-icl-y:           [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-icl-y/igt@gem_ctx_exec@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-icl-y/igt@gem_ctx_exec@basic.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [PASS][5] -> [FAIL][6] ([fdo#103167])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_basic@create-close:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-icl-u3/igt@gem_basic@create-close.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-icl-u3/igt@gem_basic@create-close.html

  * {igt@i915_selftest@live_blt}:
    - fi-skl-iommu:       [INCOMPLETE][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-skl-iommu/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-skl-iommu/igt@i915_selftest@live_blt.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-bxt-dsi:         [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/fi-bxt-dsi/igt@kms_flip@basic-flip-vs-modeset.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/fi-bxt-dsi/igt@kms_flip@basic-flip-vs-modeset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724


Participating hosts (51 -> 46)
------------------------------

  Additional (2): fi-bsw-n3050 fi-pnv-d510 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-byt-clapper fi-kbl-7560u fi-icl-dsi fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6179 -> Patchwork_13156

  CI_DRM_6179: 9a30aa526df5b04037ec56abbe568efed126d7e6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5026: 4108c74c3b15460de25ab989f4e2031594559dfc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13156: fa6226cbb01317edd7fc30b64ab414f092c05ef3 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fa6226cbb013 drm/i915/gvt: GVTg support context submission pv optimization
3626e6547796 drm/i915/gvt: GVTg support ppgtt pv optimization
4becca4775d1 drm/i915/gvt: GVTg handle shared_page setup
40ce001e1ce8 drm/i915/gvt: GVTg handle pv_caps PVINFO register
f1b3f498ebea drm/i915: vgpu context submission pv optimization
61bce586be7a drm/i915: vgpu ppgtt update pv optimization
8f6296420e40 drm/i915: vgpu shared memory setup for pv optimization
b84d8b472a53 drm/i915: introduced vgpu pv capability

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for i915 vgpu PV to improve vgpu performance

[Patchwork]

== Series Details ==

Series: i915 vgpu PV to improve vgpu performance
URL   : https://patchwork.freedesktop.org/series/61493/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6179_full -> Patchwork_13156_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13156_full:

### Piglit changes ###

#### Possible regressions ####

  * spec@glsl-1.30@execution@tex-miplevel-selection texturelod 1d (NEW):
    - {pig-snb-2600}:     NOTRUN -> [FAIL][1]
   [1]: None

  
New tests
---------

  New tests have been introduced between CI_DRM_6179_full and Patchwork_13156_full:

### New Piglit tests (1) ###

  * spec@glsl-1.30@execution@tex-miplevel-selection texturelod 1d:
    - Statuses : 1 fail(s)
    - Exec time: [7.69] s

  

Known issues
------------

  Here are the changes found in Patchwork_13156_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +5 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-iclb:         [PASS][4] -> [FAIL][5] ([fdo#108686])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb3/igt@gem_tiled_swapping@non-threaded.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb1/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-hsw:          [PASS][6] -> [SKIP][7] ([fdo#109271]) +16 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-hsw4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-hsw1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][8] -> [FAIL][9] ([fdo#103167]) +5 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
    - shard-skl:          [PASS][10] -> [FAIL][11] ([fdo#108040])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([fdo#103167])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][16] -> [FAIL][17] ([fdo#108145])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([fdo#108341])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb6/igt@kms_psr@no_drrs.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][20] -> [SKIP][21] ([fdo#109441]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb6/igt@kms_psr@psr2_no_drrs.html

  * igt@perf_pmu@rc6-runtime-pm-long:
    - shard-kbl:          [PASS][22] -> [FAIL][23] ([fdo#105010])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl2/igt@perf_pmu@rc6-runtime-pm-long.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-kbl3/igt@perf_pmu@rc6-runtime-pm-long.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][24] ([fdo#108566]) -> [PASS][25] +6 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-apl7/igt@gem_ctx_isolation@bcs0-s3.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_mmap_gtt@forked-medium-copy-xy:
    - shard-iclb:         [INCOMPLETE][26] ([fdo#107713] / [fdo#109100]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb3/igt@gem_mmap_gtt@forked-medium-copy-xy.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb1/igt@gem_mmap_gtt@forked-medium-copy-xy.html

  * igt@i915_pm_rpm@universal-planes-dpms:
    - shard-iclb:         [INCOMPLETE][28] ([fdo#107713] / [fdo#108840]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb7/igt@i915_pm_rpm@universal-planes-dpms.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb8/igt@i915_pm_rpm@universal-planes-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][30] ([fdo#108566]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][32] ([fdo#102887] / [fdo#105363]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [FAIL][34] ([fdo#103167]) -> [PASS][35] +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][36] ([fdo#109441]) -> [PASS][37] +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][38] ([fdo#99912]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl2/igt@kms_setmode@basic.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-kbl1/igt@kms_setmode@basic.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][40] -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl1/igt@perf@polling.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-skl7/igt@perf@polling.html

  
#### Warnings ####

  * igt@gem_mmap_gtt@forked-big-copy-xy:
    - shard-iclb:         [TIMEOUT][42] ([fdo#109673]) -> [INCOMPLETE][43] ([fdo#107713] / [fdo#109100])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb4/igt@gem_mmap_gtt@forked-big-copy-xy.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-iclb7/igt@gem_mmap_gtt@forked-big-copy-xy.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-hsw:          [INCOMPLETE][44] ([fdo#103540]) -> [FAIL][45] ([fdo#108686])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-hsw2/igt@gem_tiled_swapping@non-threaded.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 11)
------------------------------

  Additional (1): pig-snb-2600 


Build changes
-------------

  * Linux: CI_DRM_6179 -> Patchwork_13156

  CI_DRM_6179: 9a30aa526df5b04037ec56abbe568efed126d7e6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5026: 4108c74c3b15460de25ab989f4e2031594559dfc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13156: fa6226cbb01317edd7fc30b64ab414f092c05ef3 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13156/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization

[Chris Wilson]

Quoting Xiaolin Zhang (2019-06-03 07:02:44)
> +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
> +                                 u64 start, u64 length)
> +{
> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> +       struct i915_pml4 *pml4 = &ppgtt->pml4;
> +       struct drm_i915_private *dev_priv = vm->i915;
> +       struct pv_ppgtt_update *pv_ppgtt =
> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
> +       u64 orig_start = start;
> +       u64 orig_length = length;
> +
> +       gen8_ppgtt_clear_4lvl(vm, start, length);
> +
> +       pv_ppgtt->pdp = px_dma(pml4);
> +       pv_ppgtt->start = orig_start;
> +       pv_ppgtt->length = orig_length;
> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
> +}
> +
> +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
> +                                  struct i915_vma *vma,
> +                                  enum i915_cache_level cache_level,
> +                                  u32 flags)
> +{
> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> +       struct drm_i915_private *dev_priv = vm->i915;
> +       struct pv_ppgtt_update *pv_ppgtt =
> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
> +
> +       gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
> +
> +       pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
> +       pv_ppgtt->start = vma->node.start;
> +       pv_ppgtt->length = vma->node.size;
> +       pv_ppgtt->cache_level = cache_level;
> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
> +}

For this to work, a vgpu mmio write must be trapped and suspend the
client while the host processes the trap. Otherwise, we would be
overwriting the side-channel before the host processes the command.

That sounds horrible.
-Chris
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Re: [PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization

[Zhang, Xiaolin]

On 06/04/2019 05:01 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-06-03 07:02:44)
>> +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
>> +                                 u64 start, u64 length)
>> +{
>> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>> +       struct i915_pml4 *pml4 = &ppgtt->pml4;
>> +       struct drm_i915_private *dev_priv = vm->i915;
>> +       struct pv_ppgtt_update *pv_ppgtt =
>> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
>> +       u64 orig_start = start;
>> +       u64 orig_length = length;
>> +
>> +       gen8_ppgtt_clear_4lvl(vm, start, length);
>> +
>> +       pv_ppgtt->pdp = px_dma(pml4);
>> +       pv_ppgtt->start = orig_start;
>> +       pv_ppgtt->length = orig_length;
>> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
>> +}
>> +
>> +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
>> +                                  struct i915_vma *vma,
>> +                                  enum i915_cache_level cache_level,
>> +                                  u32 flags)
>> +{
>> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>> +       struct drm_i915_private *dev_priv = vm->i915;
>> +       struct pv_ppgtt_update *pv_ppgtt =
>> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
>> +
>> +       gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
>> +
>> +       pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
>> +       pv_ppgtt->start = vma->node.start;
>> +       pv_ppgtt->length = vma->node.size;
>> +       pv_ppgtt->cache_level = cache_level;
>> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
>> +}
> For this to work, a vgpu mmio write must be trapped and suspend the
> client while the host processes the trap. Otherwise, we would be
> overwriting the side-channel before the host processes the command.
>
> That sounds horrible.
> -Chris
Chris, thanks your comment. do you think is the spin_lock to protect
this VGPU MMIO write enough to eliminate the side-channel effect?
Xiaolin


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Re: [PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization

[Chris Wilson]

Quoting Zhang, Xiaolin (2019-06-10 02:32:18)
> On 06/04/2019 05:01 PM, Chris Wilson wrote:
> > Quoting Xiaolin Zhang (2019-06-03 07:02:44)
> >> +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
> >> +                                 u64 start, u64 length)
> >> +{
> >> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> >> +       struct i915_pml4 *pml4 = &ppgtt->pml4;
> >> +       struct drm_i915_private *dev_priv = vm->i915;
> >> +       struct pv_ppgtt_update *pv_ppgtt =
> >> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
> >> +       u64 orig_start = start;
> >> +       u64 orig_length = length;
> >> +
> >> +       gen8_ppgtt_clear_4lvl(vm, start, length);
> >> +
> >> +       pv_ppgtt->pdp = px_dma(pml4);
> >> +       pv_ppgtt->start = orig_start;
> >> +       pv_ppgtt->length = orig_length;
> >> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
> >> +}
> >> +
> >> +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
> >> +                                  struct i915_vma *vma,
> >> +                                  enum i915_cache_level cache_level,
> >> +                                  u32 flags)
> >> +{
> >> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> >> +       struct drm_i915_private *dev_priv = vm->i915;
> >> +       struct pv_ppgtt_update *pv_ppgtt =
> >> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
> >> +
> >> +       gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
> >> +
> >> +       pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
> >> +       pv_ppgtt->start = vma->node.start;
> >> +       pv_ppgtt->length = vma->node.size;
> >> +       pv_ppgtt->cache_level = cache_level;
> >> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
> >> +}
> > For this to work, a vgpu mmio write must be trapped and suspend the
> > client while the host processes the trap. Otherwise, we would be
> > overwriting the side-channel before the host processes the command.
> >
> > That sounds horrible.
> > -Chris
> Chris, thanks your comment. do you think is the spin_lock to protect
> this VGPU MMIO write enough to eliminate the side-channel effect?

I would suggest you consider using a pair of command/response rings.
-Chris
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Re: [PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization

[Zhang, Xiaolin]

On 06/10/2019 03:44 PM, Chris Wilson wrote:
> Quoting Zhang, Xiaolin (2019-06-10 02:32:18)
>> On 06/04/2019 05:01 PM, Chris Wilson wrote:
>>> Quoting Xiaolin Zhang (2019-06-03 07:02:44)
>>>> +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
>>>> +                                 u64 start, u64 length)
>>>> +{
>>>> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>>>> +       struct i915_pml4 *pml4 = &ppgtt->pml4;
>>>> +       struct drm_i915_private *dev_priv = vm->i915;
>>>> +       struct pv_ppgtt_update *pv_ppgtt =
>>>> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
>>>> +       u64 orig_start = start;
>>>> +       u64 orig_length = length;
>>>> +
>>>> +       gen8_ppgtt_clear_4lvl(vm, start, length);
>>>> +
>>>> +       pv_ppgtt->pdp = px_dma(pml4);
>>>> +       pv_ppgtt->start = orig_start;
>>>> +       pv_ppgtt->length = orig_length;
>>>> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
>>>> +}
>>>> +
>>>> +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
>>>> +                                  struct i915_vma *vma,
>>>> +                                  enum i915_cache_level cache_level,
>>>> +                                  u32 flags)
>>>> +{
>>>> +       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>>>> +       struct drm_i915_private *dev_priv = vm->i915;
>>>> +       struct pv_ppgtt_update *pv_ppgtt =
>>>> +                       &dev_priv->vgpu.shared_page->buf.pv_ppgtt;
>>>> +
>>>> +       gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
>>>> +
>>>> +       pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
>>>> +       pv_ppgtt->start = vma->node.start;
>>>> +       pv_ppgtt->length = vma->node.size;
>>>> +       pv_ppgtt->cache_level = cache_level;
>>>> +       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
>>>> +}
>>> For this to work, a vgpu mmio write must be trapped and suspend the
>>> client while the host processes the trap. Otherwise, we would be
>>> overwriting the side-channel before the host processes the command.
>>>
>>> That sounds horrible.
>>> -Chris
>> Chris, thanks your comment. do you think is the spin_lock to protect
>> this VGPU MMIO write enough to eliminate the side-channel effect?
> I would suggest you consider using a pair of command/response rings.
> -Chris
>
Chris, Thanks your suggestion and prompt response. I will rework them
for that direction.
BRs, Xiaolin


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