* [PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
@ 2020-08-27 10:02 haibo.chen at nxp.com
2020-08-28 5:38 ` Peng Fan
0 siblings, 1 reply; 2+ messages in thread
From: haibo.chen at nxp.com @ 2020-08-27 10:02 UTC (permalink / raw)
To: u-boot
From: Haibo Chen <haibo.chen@nxp.com>
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/mmc/fsl_esdhc_imx.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 788677984b..8f7ac5b7a3 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -36,6 +36,7 @@
#include <dt-structs.h>
#include <mapmem.h>
#include <dm/ofnode.h>
+#include <linux/iopoll.h>
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
+ u32 tmp;
+ int ret;
#ifdef ARCH_MXC
#ifdef CONFIG_MX53
/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
@@ -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
+ ret = readl_poll_timeout(®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
+ if (ret)
+ pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
2020-08-27 10:02 [PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate haibo.chen at nxp.com
@ 2020-08-28 5:38 ` Peng Fan
0 siblings, 0 replies; 2+ messages in thread
From: Peng Fan @ 2020-08-28 5:38 UTC (permalink / raw)
To: u-boot
> Subject: [PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after
> config the clock rate.
>
> From: Haibo Chen <haibo.chen@nxp.com>
>
> Currently, after config the clock rate, delay 10ms, this is quite a rough method.
> Check the clock stable status in the present status register is enough.
>
> Tested-by: Ji Luo <ji.luo@nxp.com>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/mmc/fsl_esdhc_imx.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> index 788677984b..8f7ac5b7a3 100644
> --- a/drivers/mmc/fsl_esdhc_imx.c
> +++ b/drivers/mmc/fsl_esdhc_imx.c
> @@ -36,6 +36,7 @@
> #include <dt-structs.h>
> #include <mapmem.h>
> #include <dm/ofnode.h>
> +#include <linux/iopoll.h>
>
> #if !CONFIG_IS_ENABLED(BLK)
> #include "mmc_private.h"
> @@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv,
> struct mmc *mmc, uint clock) {
> struct fsl_esdhc *regs = priv->esdhc_regs;
> int div = 1;
> + u32 tmp;
> + int ret;
> #ifdef ARCH_MXC
> #ifdef CONFIG_MX53
> /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ @@
> -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct
> mmc *mmc, uint clock)
>
> esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
>
> - udelay(10000);
> + ret = readl_poll_timeout(®s->prsstat, tmp, tmp & PRSSTAT_SDSTB,
To avoid breaking others, not i.MX, please add access io.
Thanks,
Peng.
> 100);
> + if (ret)
> + pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
>
> #ifdef CONFIG_FSL_USDHC
> esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
> VENDORSPEC_CKEN);
> --
> 2.17.1
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2020-08-27 10:02 [PATCH v2] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate haibo.chen at nxp.com
2020-08-28 5:38 ` Peng Fan
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