* [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel
@ 2020-10-23 3:18 Ashutosh Dixit
2020-10-23 4:06 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: sync i915_pciids.h with kernel (rev8) Patchwork
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Ashutosh Dixit @ 2020-10-23 3:18 UTC (permalink / raw)
To: igt-dev; +Cc: petri.latvala
Align with kernel commits:
605f9c290c1a2 ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f5 ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681d ("drm/i915: Sort CFL PCI IDs")
df3478af1d73c ("drm/i915: Sort CML PCI IDs")
cd988984cbea0 ("drm/i915: Sort KBL PCI IDs")
b04d36f737712 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b5 ("drm/i915: Sort HSW PCI IDs")
79033a0a78984 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae25 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd20 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08cc ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed0 ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7dd ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d8 ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739c ("drm/i915/dg1: add more PCI ids")
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
lib/i915_pciids.h | 141 ++++++++++++++++++++++++----------------------
1 file changed, 75 insertions(+), 66 deletions(-)
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 7eeecb07c9..3b5ed1e4f3 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -170,9 +170,9 @@
#define INTEL_HSW_ULT_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
- INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
+ INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
#define INTEL_HSW_ULX_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
@@ -181,26 +181,26 @@
INTEL_HSW_ULT_GT1_IDS(info), \
INTEL_HSW_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
+ INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
#define INTEL_HSW_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
+ INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
#define INTEL_HSW_ULX_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
@@ -209,45 +209,45 @@
INTEL_HSW_ULT_GT2_IDS(info), \
INTEL_HSW_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
+ INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
#define INTEL_HSW_ULT_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
#define INTEL_HSW_GT3_IDS(info) \
INTEL_HSW_ULT_GT3_IDS(info), \
INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
- INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+ INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
+ INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
+ INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
#define INTEL_HSW_IDS(info) \
INTEL_HSW_GT1_IDS(info), \
@@ -329,17 +329,20 @@
INTEL_VGA_DEVICE(0x22b3, info)
#define INTEL_SKL_ULT_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
+ INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
#define INTEL_SKL_ULX_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
+ INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
#define INTEL_SKL_GT1_IDS(info) \
INTEL_SKL_ULT_GT1_IDS(info), \
INTEL_SKL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+ INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */
#define INTEL_SKL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
@@ -352,26 +355,26 @@
INTEL_SKL_ULT_GT2_IDS(info), \
INTEL_SKL_ULX_GT2_IDS(info), \
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
#define INTEL_SKL_ULT_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
+ INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
+ INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */
#define INTEL_SKL_GT3_IDS(info) \
INTEL_SKL_ULT_GT3_IDS(info), \
- INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
- INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
+ INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
+ INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */
#define INTEL_SKL_GT4_IDS(info) \
INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
- INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
- INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
- INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
- INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
+ INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
+ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
+ INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
#define INTEL_SKL_IDS(info) \
INTEL_SKL_GT1_IDS(info), \
@@ -403,8 +406,8 @@
INTEL_KBL_ULX_GT1_IDS(info), \
INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+ INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
#define INTEL_KBL_ULT_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
@@ -416,10 +419,10 @@
#define INTEL_KBL_GT2_IDS(info) \
INTEL_KBL_ULT_GT2_IDS(info), \
INTEL_KBL_ULX_GT2_IDS(info), \
- INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
#define INTEL_KBL_ULT_GT3_IDS(info) \
@@ -444,10 +447,10 @@
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x9BA5, info), \
- INTEL_VGA_DEVICE(0x9BA8, info), \
+ INTEL_VGA_DEVICE(0x9BA2, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
- INTEL_VGA_DEVICE(0x9BA2, info)
+ INTEL_VGA_DEVICE(0x9BA5, info), \
+ INTEL_VGA_DEVICE(0x9BA8, info)
#define INTEL_CML_U_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9B21, info), \
@@ -456,11 +459,11 @@
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x9BC5, info), \
- INTEL_VGA_DEVICE(0x9BC8, info), \
- INTEL_VGA_DEVICE(0x9BC4, info), \
INTEL_VGA_DEVICE(0x9BC2, info), \
+ INTEL_VGA_DEVICE(0x9BC4, info), \
+ INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC6, info), \
+ INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BE6, info), \
INTEL_VGA_DEVICE(0x9BF6, info)
@@ -494,8 +497,8 @@
INTEL_VGA_DEVICE(0x3E9C, info)
#define INTEL_CFL_H_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+ INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
/* CFL U GT2 */
#define INTEL_CFL_U_GT2_IDS(info) \
@@ -540,54 +543,57 @@
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
- INTEL_VGA_DEVICE(0x5A54, info), \
- INTEL_VGA_DEVICE(0x5A5C, info), \
INTEL_VGA_DEVICE(0x5A44, info), \
- INTEL_VGA_DEVICE(0x5A4C, info)
+ INTEL_VGA_DEVICE(0x5A4C, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info)
#define INTEL_CNL_IDS(info) \
INTEL_CNL_PORT_F_IDS(info), \
- INTEL_VGA_DEVICE(0x5A51, info), \
- INTEL_VGA_DEVICE(0x5A59, info), \
+ INTEL_VGA_DEVICE(0x5A40, info), \
INTEL_VGA_DEVICE(0x5A41, info), \
- INTEL_VGA_DEVICE(0x5A49, info), \
- INTEL_VGA_DEVICE(0x5A52, info), \
- INTEL_VGA_DEVICE(0x5A5A, info), \
INTEL_VGA_DEVICE(0x5A42, info), \
+ INTEL_VGA_DEVICE(0x5A49, info), \
INTEL_VGA_DEVICE(0x5A4A, info), \
INTEL_VGA_DEVICE(0x5A50, info), \
- INTEL_VGA_DEVICE(0x5A40, info)
+ INTEL_VGA_DEVICE(0x5A51, info), \
+ INTEL_VGA_DEVICE(0x5A52, info), \
+ INTEL_VGA_DEVICE(0x5A59, info), \
+ INTEL_VGA_DEVICE(0x5A5A, info)
/* ICL */
#define INTEL_ICL_PORT_F_IDS(info) \
INTEL_VGA_DEVICE(0x8A50, info), \
- INTEL_VGA_DEVICE(0x8A5C, info), \
- INTEL_VGA_DEVICE(0x8A59, info), \
- INTEL_VGA_DEVICE(0x8A58, info), \
INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A53, info), \
+ INTEL_VGA_DEVICE(0x8A54, info), \
+ INTEL_VGA_DEVICE(0x8A56, info), \
+ INTEL_VGA_DEVICE(0x8A57, info), \
+ INTEL_VGA_DEVICE(0x8A58, info), \
+ INTEL_VGA_DEVICE(0x8A59, info), \
INTEL_VGA_DEVICE(0x8A5A, info), \
INTEL_VGA_DEVICE(0x8A5B, info), \
- INTEL_VGA_DEVICE(0x8A57, info), \
- INTEL_VGA_DEVICE(0x8A56, info), \
- INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
INTEL_VGA_DEVICE(0x8A70, info), \
- INTEL_VGA_DEVICE(0x8A53, info), \
- INTEL_VGA_DEVICE(0x8A54, info)
+ INTEL_VGA_DEVICE(0x8A71, info)
#define INTEL_ICL_11_IDS(info) \
INTEL_ICL_PORT_F_IDS(info), \
INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5D, info)
-/* EHL/JSL */
+/* EHL */
#define INTEL_EHL_IDS(info) \
INTEL_VGA_DEVICE(0x4500, info), \
INTEL_VGA_DEVICE(0x4571, info), \
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info), \
- INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4557, info), \
- INTEL_VGA_DEVICE(0x4555, info), \
+ INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E57, info), \
INTEL_VGA_DEVICE(0x4E55, info), \
@@ -624,6 +630,9 @@
/* DG1 */
#define INTEL_DG1_IDS(info) \
- INTEL_VGA_DEVICE(0x4905, info)
+ INTEL_VGA_DEVICE(0x4905, info), \
+ INTEL_VGA_DEVICE(0x4906, info), \
+ INTEL_VGA_DEVICE(0x4907, info), \
+ INTEL_VGA_DEVICE(0x4908, info)
#endif /* _I915_PCIIDS_H */
--
2.26.2.108.g048abe1751
_______________________________________________
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igt-dev@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib: sync i915_pciids.h with kernel (rev8)
2020-10-23 3:18 [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Ashutosh Dixit
@ 2020-10-23 4:06 ` Patchwork
2020-10-23 5:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2020-10-23 7:59 ` [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Petri Latvala
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-10-23 4:06 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 5081 bytes --]
== Series Details ==
Series: lib: sync i915_pciids.h with kernel (rev8)
URL : https://patchwork.freedesktop.org/series/50957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9187 -> IGTPW_5087
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
Known issues
------------
Here are the changes found in IGTPW_5087 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1635])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-apl-guc/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-apl-guc/igt@gem_close_race@basic-threads.html
* igt@i915_module_load@reload:
- fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-bxt-dsi/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-bxt-dsi/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][7] -> [INCOMPLETE][8] ([i915#2276])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-icl-y/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-icl-y/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-byt-j1900/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-byt-j1900/igt@i915_module_load@reload.html
- fi-icl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-icl-y/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-icl-y/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][19] ([i915#2203]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/fi-skl-guc/igt@vgem_basic@unload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/fi-skl-guc/igt@vgem_basic@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
Participating hosts (46 -> 39)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5822 -> IGTPW_5087
CI-20190529: 20190529
CI_DRM_9187: e11ff28a7d8e3881b55292f504ed63372167b591 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5087: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
[-- Attachment #1.2: Type: text/html, Size: 6396 bytes --]
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for lib: sync i915_pciids.h with kernel (rev8)
2020-10-23 3:18 [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Ashutosh Dixit
2020-10-23 4:06 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: sync i915_pciids.h with kernel (rev8) Patchwork
@ 2020-10-23 5:06 ` Patchwork
2020-10-23 7:59 ` [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Petri Latvala
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2020-10-23 5:06 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 16983 bytes --]
== Series Details ==
Series: lib: sync i915_pciids.h with kernel (rev8)
URL : https://patchwork.freedesktop.org/series/50957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9187_full -> IGTPW_5087_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_5087_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5087_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5087_full:
### IGT changes ###
#### Warnings ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-hsw: [WARN][1] ([i915#2283]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-hsw1/igt@core_hotunplug@hotrebind-lateclose.html
Known issues
------------
Here are the changes found in IGTPW_5087_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-snb: [PASS][3] -> [FAIL][4] ([i915#2389])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-snb4/igt@gem_exec_reloc@basic-many-active@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-snb5/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk7/igt@gem_exec_reloc@basic-many-active@vecs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][7] -> [FAIL][8] ([i915#96])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@perf@i915-ref-count:
- shard-hsw: [PASS][17] -> [SKIP][18] ([fdo#109271])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-hsw4/igt@perf@i915-ref-count.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-hsw8/igt@perf@i915-ref-count.html
- shard-iclb: [PASS][19] -> [SKIP][20] ([i915#1354])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-iclb1/igt@perf@i915-ref-count.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-iclb7/igt@perf@i915-ref-count.html
- shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271] / [i915#1354])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl4/igt@perf@i915-ref-count.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl1/igt@perf@i915-ref-count.html
- shard-apl: [PASS][23] -> [SKIP][24] ([fdo#109271] / [i915#1354] / [i915#1635])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl4/igt@perf@i915-ref-count.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl4/igt@perf@i915-ref-count.html
- shard-glk: [PASS][25] -> [SKIP][26] ([fdo#109271] / [i915#1354])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk3/igt@perf@i915-ref-count.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk3/igt@perf@i915-ref-count.html
- shard-tglb: [PASS][27] -> [SKIP][28] ([i915#1354])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-tglb2/igt@perf@i915-ref-count.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-tglb2/igt@perf@i915-ref-count.html
#### Possible fixes ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-snb: [INCOMPLETE][29] ([i915#82]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-snb2/igt@core_hotunplug@hotrebind-lateclose.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-snb2/igt@core_hotunplug@hotrebind-lateclose.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][31] ([i915#1635] / [i915#2389]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl1/igt@gem_exec_reloc@basic-many-active@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl6/igt@gem_exec_reloc@basic-many-active@rcs0.html
- shard-glk: [FAIL][33] ([i915#2389]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk7/igt@gem_exec_reloc@basic-many-active@rcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk6/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk6/igt@gem_exec_whisper@basic-forked-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk5/igt@gem_exec_whisper@basic-forked-all.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [INCOMPLETE][37] ([i915#155]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl2/igt@i915_suspend@debugfs-reader.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl1/igt@i915_suspend@debugfs-reader.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-glk: [FAIL][39] ([i915#2521]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk7/igt@kms_async_flips@async-flip-with-page-flip-events.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk8/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-apl: [DMESG-WARN][41] ([i915#1635] / [i915#1982]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl2/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl6/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
- shard-glk: [FAIL][45] ([i915#54]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk8/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk5/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
- shard-apl: [FAIL][47] ([i915#1635] / [i915#54]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
- shard-kbl: [FAIL][49] ([i915#54]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding.html
* igt@kms_flip@blocking-wf_vblank@a-edp1:
- shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-tglb2/igt@kms_flip@blocking-wf_vblank@a-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-tglb7/igt@kms_flip@blocking-wf_vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk8/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][57] ([i915#1635] / [i915#31]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl3/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl4/igt@kms_setmode@basic.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-kbl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl4/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
* igt@perf@polling:
- shard-glk: [SKIP][61] ([fdo#109271] / [i915#1354]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk5/igt@perf@polling.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk9/igt@perf@polling.html
- shard-tglb: [SKIP][63] ([i915#1354]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-tglb3/igt@perf@polling.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-tglb5/igt@perf@polling.html
- shard-apl: [SKIP][65] ([fdo#109271] / [i915#1354] / [i915#1635]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl7/igt@perf@polling.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl6/igt@perf@polling.html
- shard-kbl: [SKIP][67] ([fdo#109271] / [i915#1354]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-kbl6/igt@perf@polling.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-kbl1/igt@perf@polling.html
- shard-hsw: [SKIP][69] ([fdo#109271]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-hsw1/igt@perf@polling.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-hsw4/igt@perf@polling.html
- shard-iclb: [SKIP][71] ([i915#1354]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-iclb2/igt@perf@polling.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-iclb3/igt@perf@polling.html
* igt@prime_vgem@coherency-blt:
- shard-hsw: [FAIL][73] -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-hsw1/igt@prime_vgem@coherency-blt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-hsw4/igt@prime_vgem@coherency-blt.html
#### Warnings ####
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-glk: [FAIL][75] ([i915#1888]) -> [DMESG-WARN][76] ([i915#118] / [i915#95])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-glk5/igt@gem_exec_whisper@basic-queues-priority-all.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-glk6/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@kms_content_protection@atomic:
- shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [FAIL][78] ([fdo#110321] / [fdo#110336] / [i915#1635]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-apl1/igt@kms_content_protection@atomic.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-apl3/igt@kms_content_protection@atomic.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-tglb: [DMESG-WARN][79] ([i915#2411]) -> [INCOMPLETE][80] ([i915#1436] / [i915#1982])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9187/shard-tglb1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (11 -> 8)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5822 -> IGTPW_5087
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_9187: e11ff28a7d8e3881b55292f504ed63372167b591 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5087: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5087/index.html
[-- Attachment #1.2: Type: text/html, Size: 21033 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel
2020-10-23 3:18 [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Ashutosh Dixit
2020-10-23 4:06 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: sync i915_pciids.h with kernel (rev8) Patchwork
2020-10-23 5:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2020-10-23 7:59 ` Petri Latvala
2020-10-23 8:03 ` Petri Latvala
2 siblings, 1 reply; 7+ messages in thread
From: Petri Latvala @ 2020-10-23 7:59 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: igt-dev
On Thu, Oct 22, 2020 at 08:18:59PM -0700, Ashutosh Dixit wrote:
> Align with kernel commits:
>
> 605f9c290c1a2 ("drm/i915: Sort ICL PCI IDs")
> 514dc424ce4f5 ("drm/i915: Sort CNL PCI IDs")
> 32d4ec9a1681d ("drm/i915: Sort CFL PCI IDs")
> df3478af1d73c ("drm/i915: Sort CML PCI IDs")
> cd988984cbea0 ("drm/i915: Sort KBL PCI IDs")
> b04d36f737712 ("drm/i915: Sort SKL PCI IDs")
> 9c0b2d30441b5 ("drm/i915: Sort HSW PCI IDs")
> 79033a0a78984 ("drm/i915: Ocd the HSW PCI ID hex numbers")
> cfb3db8fdae25 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
> 03e399020cd20 ("drm/i915: Add SKL GT1.5 PCI IDs")
> 812f044df08cc ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
> 194909a32aed0 ("drm/i915: Reclassify SKL 0x192a as GT3")
> 82e84284ab7dd ("drm/i915: Update Haswell PCI IDs")
> 24ea098b7c0d8 ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
> b50b7991b739c ("drm/i915/dg1: add more PCI ids")
>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
I get really confused by commit messages like this. Which commit is
this now copied from, and which repo has that commit?
--
Petri Latvala
> lib/i915_pciids.h | 141 ++++++++++++++++++++++++----------------------
> 1 file changed, 75 insertions(+), 66 deletions(-)
>
> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> index 7eeecb07c9..3b5ed1e4f3 100644
> --- a/lib/i915_pciids.h
> +++ b/lib/i915_pciids.h
> @@ -170,9 +170,9 @@
>
> #define INTEL_HSW_ULT_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
> + INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
>
> #define INTEL_HSW_ULX_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
> @@ -181,26 +181,26 @@
> INTEL_HSW_ULT_GT1_IDS(info), \
> INTEL_HSW_ULX_GT1_IDS(info), \
> INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
> INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
> + INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
>
> #define INTEL_HSW_ULT_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
> + INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
>
> #define INTEL_HSW_ULX_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
> @@ -209,45 +209,45 @@
> INTEL_HSW_ULT_GT2_IDS(info), \
> INTEL_HSW_ULX_GT2_IDS(info), \
> INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
> INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
> + INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
>
> #define INTEL_HSW_ULT_GT3_IDS(info) \
> INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
>
> #define INTEL_HSW_GT3_IDS(info) \
> INTEL_HSW_ULT_GT3_IDS(info), \
> INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> + INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
> INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
>
> #define INTEL_HSW_IDS(info) \
> INTEL_HSW_GT1_IDS(info), \
> @@ -329,17 +329,20 @@
> INTEL_VGA_DEVICE(0x22b3, info)
>
> #define INTEL_SKL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
> + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
>
> #define INTEL_SKL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
> + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
>
> #define INTEL_SKL_GT1_IDS(info) \
> INTEL_SKL_ULT_GT1_IDS(info), \
> INTEL_SKL_ULX_GT1_IDS(info), \
> INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> + INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */
>
> #define INTEL_SKL_ULT_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> @@ -352,26 +355,26 @@
> INTEL_SKL_ULT_GT2_IDS(info), \
> INTEL_SKL_ULX_GT2_IDS(info), \
> INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
>
> #define INTEL_SKL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
> + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
> + INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */
>
> #define INTEL_SKL_GT3_IDS(info) \
> INTEL_SKL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
> + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
> + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
> + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */
>
> #define INTEL_SKL_GT4_IDS(info) \
> INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
> - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
> + INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
> + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> + INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
>
> #define INTEL_SKL_IDS(info) \
> INTEL_SKL_GT1_IDS(info), \
> @@ -403,8 +406,8 @@
> INTEL_KBL_ULX_GT1_IDS(info), \
> INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> + INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
> + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
>
> #define INTEL_KBL_ULT_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> @@ -416,10 +419,10 @@
> #define INTEL_KBL_GT2_IDS(info) \
> INTEL_KBL_ULT_GT2_IDS(info), \
> INTEL_KBL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
>
> #define INTEL_KBL_ULT_GT3_IDS(info) \
> @@ -444,10 +447,10 @@
>
> /* CML GT1 */
> #define INTEL_CML_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BA5, info), \
> - INTEL_VGA_DEVICE(0x9BA8, info), \
> + INTEL_VGA_DEVICE(0x9BA2, info), \
> INTEL_VGA_DEVICE(0x9BA4, info), \
> - INTEL_VGA_DEVICE(0x9BA2, info)
> + INTEL_VGA_DEVICE(0x9BA5, info), \
> + INTEL_VGA_DEVICE(0x9BA8, info)
>
> #define INTEL_CML_U_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x9B21, info), \
> @@ -456,11 +459,11 @@
>
> /* CML GT2 */
> #define INTEL_CML_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BC5, info), \
> - INTEL_VGA_DEVICE(0x9BC8, info), \
> - INTEL_VGA_DEVICE(0x9BC4, info), \
> INTEL_VGA_DEVICE(0x9BC2, info), \
> + INTEL_VGA_DEVICE(0x9BC4, info), \
> + INTEL_VGA_DEVICE(0x9BC5, info), \
> INTEL_VGA_DEVICE(0x9BC6, info), \
> + INTEL_VGA_DEVICE(0x9BC8, info), \
> INTEL_VGA_DEVICE(0x9BE6, info), \
> INTEL_VGA_DEVICE(0x9BF6, info)
>
> @@ -494,8 +497,8 @@
> INTEL_VGA_DEVICE(0x3E9C, info)
>
> #define INTEL_CFL_H_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
> + INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
>
> /* CFL U GT2 */
> #define INTEL_CFL_U_GT2_IDS(info) \
> @@ -540,54 +543,57 @@
>
> /* CNL */
> #define INTEL_CNL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A54, info), \
> - INTEL_VGA_DEVICE(0x5A5C, info), \
> INTEL_VGA_DEVICE(0x5A44, info), \
> - INTEL_VGA_DEVICE(0x5A4C, info)
> + INTEL_VGA_DEVICE(0x5A4C, info), \
> + INTEL_VGA_DEVICE(0x5A54, info), \
> + INTEL_VGA_DEVICE(0x5A5C, info)
>
> #define INTEL_CNL_IDS(info) \
> INTEL_CNL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x5A51, info), \
> - INTEL_VGA_DEVICE(0x5A59, info), \
> + INTEL_VGA_DEVICE(0x5A40, info), \
> INTEL_VGA_DEVICE(0x5A41, info), \
> - INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info), \
> INTEL_VGA_DEVICE(0x5A42, info), \
> + INTEL_VGA_DEVICE(0x5A49, info), \
> INTEL_VGA_DEVICE(0x5A4A, info), \
> INTEL_VGA_DEVICE(0x5A50, info), \
> - INTEL_VGA_DEVICE(0x5A40, info)
> + INTEL_VGA_DEVICE(0x5A51, info), \
> + INTEL_VGA_DEVICE(0x5A52, info), \
> + INTEL_VGA_DEVICE(0x5A59, info), \
> + INTEL_VGA_DEVICE(0x5A5A, info)
>
> /* ICL */
> #define INTEL_ICL_PORT_F_IDS(info) \
> INTEL_VGA_DEVICE(0x8A50, info), \
> - INTEL_VGA_DEVICE(0x8A5C, info), \
> - INTEL_VGA_DEVICE(0x8A59, info), \
> - INTEL_VGA_DEVICE(0x8A58, info), \
> INTEL_VGA_DEVICE(0x8A52, info), \
> + INTEL_VGA_DEVICE(0x8A53, info), \
> + INTEL_VGA_DEVICE(0x8A54, info), \
> + INTEL_VGA_DEVICE(0x8A56, info), \
> + INTEL_VGA_DEVICE(0x8A57, info), \
> + INTEL_VGA_DEVICE(0x8A58, info), \
> + INTEL_VGA_DEVICE(0x8A59, info), \
> INTEL_VGA_DEVICE(0x8A5A, info), \
> INTEL_VGA_DEVICE(0x8A5B, info), \
> - INTEL_VGA_DEVICE(0x8A57, info), \
> - INTEL_VGA_DEVICE(0x8A56, info), \
> - INTEL_VGA_DEVICE(0x8A71, info), \
> + INTEL_VGA_DEVICE(0x8A5C, info), \
> INTEL_VGA_DEVICE(0x8A70, info), \
> - INTEL_VGA_DEVICE(0x8A53, info), \
> - INTEL_VGA_DEVICE(0x8A54, info)
> + INTEL_VGA_DEVICE(0x8A71, info)
>
> #define INTEL_ICL_11_IDS(info) \
> INTEL_ICL_PORT_F_IDS(info), \
> INTEL_VGA_DEVICE(0x8A51, info), \
> INTEL_VGA_DEVICE(0x8A5D, info)
>
> -/* EHL/JSL */
> +/* EHL */
> #define INTEL_EHL_IDS(info) \
> INTEL_VGA_DEVICE(0x4500, info), \
> INTEL_VGA_DEVICE(0x4571, info), \
> INTEL_VGA_DEVICE(0x4551, info), \
> INTEL_VGA_DEVICE(0x4541, info), \
> - INTEL_VGA_DEVICE(0x4E71, info), \
> INTEL_VGA_DEVICE(0x4557, info), \
> - INTEL_VGA_DEVICE(0x4555, info), \
> + INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> + INTEL_VGA_DEVICE(0x4E71, info), \
> INTEL_VGA_DEVICE(0x4E61, info), \
> INTEL_VGA_DEVICE(0x4E57, info), \
> INTEL_VGA_DEVICE(0x4E55, info), \
> @@ -624,6 +630,9 @@
>
> /* DG1 */
> #define INTEL_DG1_IDS(info) \
> - INTEL_VGA_DEVICE(0x4905, info)
> + INTEL_VGA_DEVICE(0x4905, info), \
> + INTEL_VGA_DEVICE(0x4906, info), \
> + INTEL_VGA_DEVICE(0x4907, info), \
> + INTEL_VGA_DEVICE(0x4908, info)
>
> #endif /* _I915_PCIIDS_H */
> --
> 2.26.2.108.g048abe1751
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel
2020-10-23 7:59 ` [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Petri Latvala
@ 2020-10-23 8:03 ` Petri Latvala
2020-10-23 15:55 ` Dixit, Ashutosh
0 siblings, 1 reply; 7+ messages in thread
From: Petri Latvala @ 2020-10-23 8:03 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: igt-dev
On Fri, Oct 23, 2020 at 10:59:27AM +0300, Petri Latvala wrote:
> On Thu, Oct 22, 2020 at 08:18:59PM -0700, Ashutosh Dixit wrote:
> > Align with kernel commits:
> >
> > 605f9c290c1a2 ("drm/i915: Sort ICL PCI IDs")
> > 514dc424ce4f5 ("drm/i915: Sort CNL PCI IDs")
> > 32d4ec9a1681d ("drm/i915: Sort CFL PCI IDs")
> > df3478af1d73c ("drm/i915: Sort CML PCI IDs")
> > cd988984cbea0 ("drm/i915: Sort KBL PCI IDs")
> > b04d36f737712 ("drm/i915: Sort SKL PCI IDs")
> > 9c0b2d30441b5 ("drm/i915: Sort HSW PCI IDs")
> > 79033a0a78984 ("drm/i915: Ocd the HSW PCI ID hex numbers")
> > cfb3db8fdae25 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
> > 03e399020cd20 ("drm/i915: Add SKL GT1.5 PCI IDs")
> > 812f044df08cc ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
> > 194909a32aed0 ("drm/i915: Reclassify SKL 0x192a as GT3")
> > 82e84284ab7dd ("drm/i915: Update Haswell PCI IDs")
> > 24ea098b7c0d8 ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
> > b50b7991b739c ("drm/i915/dg1: add more PCI ids")
> >
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
>
> I get really confused by commit messages like this. Which commit is
> this now copied from, and which repo has that commit?
Regardless of that confusion, the file matches what's in drm-tip so
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
>
>
> --
> Petri Latvala
>
>
>
> > lib/i915_pciids.h | 141 ++++++++++++++++++++++++----------------------
> > 1 file changed, 75 insertions(+), 66 deletions(-)
> >
> > diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> > index 7eeecb07c9..3b5ed1e4f3 100644
> > --- a/lib/i915_pciids.h
> > +++ b/lib/i915_pciids.h
> > @@ -170,9 +170,9 @@
> >
> > #define INTEL_HSW_ULT_GT1_IDS(info) \
> > INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> > + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> > INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> > - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> > - INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
> > + INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
> >
> > #define INTEL_HSW_ULX_GT1_IDS(info) \
> > INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
> > @@ -181,26 +181,26 @@
> > INTEL_HSW_ULT_GT1_IDS(info), \
> > INTEL_HSW_ULX_GT1_IDS(info), \
> > INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> > - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> > + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> > + INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
> > INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> > INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> > INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> > + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> > INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> > INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> > INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> > INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> > + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> > INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> > INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> > - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> > - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> > - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> > - INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
> > + INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
> >
> > #define INTEL_HSW_ULT_GT2_IDS(info) \
> > INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> > + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> > INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> > - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> > - INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
> > + INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
> >
> > #define INTEL_HSW_ULX_GT2_IDS(info) \
> > INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
> > @@ -209,45 +209,45 @@
> > INTEL_HSW_ULT_GT2_IDS(info), \
> > INTEL_HSW_ULX_GT2_IDS(info), \
> > INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> > - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> > + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> > + INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
> > INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> > INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> > INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> > + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> > INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> > INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> > INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> > INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> > + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> > INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> > INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> > - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> > - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> > - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> > - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> > - INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
> > + INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
> >
> > #define INTEL_HSW_ULT_GT3_IDS(info) \
> > INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> > + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> > INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> > INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> > - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> > INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
> >
> > #define INTEL_HSW_GT3_IDS(info) \
> > INTEL_HSW_ULT_GT3_IDS(info), \
> > INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> > - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> > + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> > + INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
> > INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> > INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> > INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> > + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> > INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> > INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> > INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> > INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> > + INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
> > INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> > INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> > - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
> > - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> > - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> > + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
> >
> > #define INTEL_HSW_IDS(info) \
> > INTEL_HSW_GT1_IDS(info), \
> > @@ -329,17 +329,20 @@
> > INTEL_VGA_DEVICE(0x22b3, info)
> >
> > #define INTEL_SKL_ULT_GT1_IDS(info) \
> > - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
> > + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> > + INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
> >
> > #define INTEL_SKL_ULX_GT1_IDS(info) \
> > - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
> > + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> > + INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
> >
> > #define INTEL_SKL_GT1_IDS(info) \
> > INTEL_SKL_ULT_GT1_IDS(info), \
> > INTEL_SKL_ULX_GT1_IDS(info), \
> > INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> > + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> > INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> > - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> > + INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */
> >
> > #define INTEL_SKL_ULT_GT2_IDS(info) \
> > INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> > @@ -352,26 +355,26 @@
> > INTEL_SKL_ULT_GT2_IDS(info), \
> > INTEL_SKL_ULX_GT2_IDS(info), \
> > INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> > - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> > INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> > + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> > INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> >
> > #define INTEL_SKL_ULT_GT3_IDS(info) \
> > - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
> > + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> > + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
> > + INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */
> >
> > #define INTEL_SKL_GT3_IDS(info) \
> > INTEL_SKL_ULT_GT3_IDS(info), \
> > - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> > - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> > - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> > - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
> > + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
> > + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
> > + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */
> >
> > #define INTEL_SKL_GT4_IDS(info) \
> > INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> > - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> > - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> > - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
> > - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
> > + INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
> > + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> > + INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
> >
> > #define INTEL_SKL_IDS(info) \
> > INTEL_SKL_GT1_IDS(info), \
> > @@ -403,8 +406,8 @@
> > INTEL_KBL_ULX_GT1_IDS(info), \
> > INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> > INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> > - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> > - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> > + INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
> > + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
> >
> > #define INTEL_KBL_ULT_GT2_IDS(info) \
> > INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> > @@ -416,10 +419,10 @@
> > #define INTEL_KBL_GT2_IDS(info) \
> > INTEL_KBL_ULT_GT2_IDS(info), \
> > INTEL_KBL_ULX_GT2_IDS(info), \
> > - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> > INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> > - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> > + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> > INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> > + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> > INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> >
> > #define INTEL_KBL_ULT_GT3_IDS(info) \
> > @@ -444,10 +447,10 @@
> >
> > /* CML GT1 */
> > #define INTEL_CML_GT1_IDS(info) \
> > - INTEL_VGA_DEVICE(0x9BA5, info), \
> > - INTEL_VGA_DEVICE(0x9BA8, info), \
> > + INTEL_VGA_DEVICE(0x9BA2, info), \
> > INTEL_VGA_DEVICE(0x9BA4, info), \
> > - INTEL_VGA_DEVICE(0x9BA2, info)
> > + INTEL_VGA_DEVICE(0x9BA5, info), \
> > + INTEL_VGA_DEVICE(0x9BA8, info)
> >
> > #define INTEL_CML_U_GT1_IDS(info) \
> > INTEL_VGA_DEVICE(0x9B21, info), \
> > @@ -456,11 +459,11 @@
> >
> > /* CML GT2 */
> > #define INTEL_CML_GT2_IDS(info) \
> > - INTEL_VGA_DEVICE(0x9BC5, info), \
> > - INTEL_VGA_DEVICE(0x9BC8, info), \
> > - INTEL_VGA_DEVICE(0x9BC4, info), \
> > INTEL_VGA_DEVICE(0x9BC2, info), \
> > + INTEL_VGA_DEVICE(0x9BC4, info), \
> > + INTEL_VGA_DEVICE(0x9BC5, info), \
> > INTEL_VGA_DEVICE(0x9BC6, info), \
> > + INTEL_VGA_DEVICE(0x9BC8, info), \
> > INTEL_VGA_DEVICE(0x9BE6, info), \
> > INTEL_VGA_DEVICE(0x9BF6, info)
> >
> > @@ -494,8 +497,8 @@
> > INTEL_VGA_DEVICE(0x3E9C, info)
> >
> > #define INTEL_CFL_H_GT2_IDS(info) \
> > - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> > - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
> > + INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \
> > + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
> >
> > /* CFL U GT2 */
> > #define INTEL_CFL_U_GT2_IDS(info) \
> > @@ -540,54 +543,57 @@
> >
> > /* CNL */
> > #define INTEL_CNL_PORT_F_IDS(info) \
> > - INTEL_VGA_DEVICE(0x5A54, info), \
> > - INTEL_VGA_DEVICE(0x5A5C, info), \
> > INTEL_VGA_DEVICE(0x5A44, info), \
> > - INTEL_VGA_DEVICE(0x5A4C, info)
> > + INTEL_VGA_DEVICE(0x5A4C, info), \
> > + INTEL_VGA_DEVICE(0x5A54, info), \
> > + INTEL_VGA_DEVICE(0x5A5C, info)
> >
> > #define INTEL_CNL_IDS(info) \
> > INTEL_CNL_PORT_F_IDS(info), \
> > - INTEL_VGA_DEVICE(0x5A51, info), \
> > - INTEL_VGA_DEVICE(0x5A59, info), \
> > + INTEL_VGA_DEVICE(0x5A40, info), \
> > INTEL_VGA_DEVICE(0x5A41, info), \
> > - INTEL_VGA_DEVICE(0x5A49, info), \
> > - INTEL_VGA_DEVICE(0x5A52, info), \
> > - INTEL_VGA_DEVICE(0x5A5A, info), \
> > INTEL_VGA_DEVICE(0x5A42, info), \
> > + INTEL_VGA_DEVICE(0x5A49, info), \
> > INTEL_VGA_DEVICE(0x5A4A, info), \
> > INTEL_VGA_DEVICE(0x5A50, info), \
> > - INTEL_VGA_DEVICE(0x5A40, info)
> > + INTEL_VGA_DEVICE(0x5A51, info), \
> > + INTEL_VGA_DEVICE(0x5A52, info), \
> > + INTEL_VGA_DEVICE(0x5A59, info), \
> > + INTEL_VGA_DEVICE(0x5A5A, info)
> >
> > /* ICL */
> > #define INTEL_ICL_PORT_F_IDS(info) \
> > INTEL_VGA_DEVICE(0x8A50, info), \
> > - INTEL_VGA_DEVICE(0x8A5C, info), \
> > - INTEL_VGA_DEVICE(0x8A59, info), \
> > - INTEL_VGA_DEVICE(0x8A58, info), \
> > INTEL_VGA_DEVICE(0x8A52, info), \
> > + INTEL_VGA_DEVICE(0x8A53, info), \
> > + INTEL_VGA_DEVICE(0x8A54, info), \
> > + INTEL_VGA_DEVICE(0x8A56, info), \
> > + INTEL_VGA_DEVICE(0x8A57, info), \
> > + INTEL_VGA_DEVICE(0x8A58, info), \
> > + INTEL_VGA_DEVICE(0x8A59, info), \
> > INTEL_VGA_DEVICE(0x8A5A, info), \
> > INTEL_VGA_DEVICE(0x8A5B, info), \
> > - INTEL_VGA_DEVICE(0x8A57, info), \
> > - INTEL_VGA_DEVICE(0x8A56, info), \
> > - INTEL_VGA_DEVICE(0x8A71, info), \
> > + INTEL_VGA_DEVICE(0x8A5C, info), \
> > INTEL_VGA_DEVICE(0x8A70, info), \
> > - INTEL_VGA_DEVICE(0x8A53, info), \
> > - INTEL_VGA_DEVICE(0x8A54, info)
> > + INTEL_VGA_DEVICE(0x8A71, info)
> >
> > #define INTEL_ICL_11_IDS(info) \
> > INTEL_ICL_PORT_F_IDS(info), \
> > INTEL_VGA_DEVICE(0x8A51, info), \
> > INTEL_VGA_DEVICE(0x8A5D, info)
> >
> > -/* EHL/JSL */
> > +/* EHL */
> > #define INTEL_EHL_IDS(info) \
> > INTEL_VGA_DEVICE(0x4500, info), \
> > INTEL_VGA_DEVICE(0x4571, info), \
> > INTEL_VGA_DEVICE(0x4551, info), \
> > INTEL_VGA_DEVICE(0x4541, info), \
> > - INTEL_VGA_DEVICE(0x4E71, info), \
> > INTEL_VGA_DEVICE(0x4557, info), \
> > - INTEL_VGA_DEVICE(0x4555, info), \
> > + INTEL_VGA_DEVICE(0x4555, info)
> > +
> > +/* JSL */
> > +#define INTEL_JSL_IDS(info) \
> > + INTEL_VGA_DEVICE(0x4E71, info), \
> > INTEL_VGA_DEVICE(0x4E61, info), \
> > INTEL_VGA_DEVICE(0x4E57, info), \
> > INTEL_VGA_DEVICE(0x4E55, info), \
> > @@ -624,6 +630,9 @@
> >
> > /* DG1 */
> > #define INTEL_DG1_IDS(info) \
> > - INTEL_VGA_DEVICE(0x4905, info)
> > + INTEL_VGA_DEVICE(0x4905, info), \
> > + INTEL_VGA_DEVICE(0x4906, info), \
> > + INTEL_VGA_DEVICE(0x4907, info), \
> > + INTEL_VGA_DEVICE(0x4908, info)
> >
> > #endif /* _I915_PCIIDS_H */
> > --
> > 2.26.2.108.g048abe1751
> >
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel
2020-10-23 8:03 ` Petri Latvala
@ 2020-10-23 15:55 ` Dixit, Ashutosh
2020-10-26 8:30 ` Petri Latvala
0 siblings, 1 reply; 7+ messages in thread
From: Dixit, Ashutosh @ 2020-10-23 15:55 UTC (permalink / raw)
To: Petri Latvala; +Cc: igt-dev
On Fri, 23 Oct 2020 01:03:24 -0700, Petri Latvala wrote:
>
> On Fri, Oct 23, 2020 at 10:59:27AM +0300, Petri Latvala wrote:
> > On Thu, Oct 22, 2020 at 08:18:59PM -0700, Ashutosh Dixit wrote:
> > > Align with kernel commits:
> > >
> > > 605f9c290c1a2 ("drm/i915: Sort ICL PCI IDs")
> > > 514dc424ce4f5 ("drm/i915: Sort CNL PCI IDs")
> > > 32d4ec9a1681d ("drm/i915: Sort CFL PCI IDs")
> > > df3478af1d73c ("drm/i915: Sort CML PCI IDs")
> > > cd988984cbea0 ("drm/i915: Sort KBL PCI IDs")
> > > b04d36f737712 ("drm/i915: Sort SKL PCI IDs")
> > > 9c0b2d30441b5 ("drm/i915: Sort HSW PCI IDs")
> > > 79033a0a78984 ("drm/i915: Ocd the HSW PCI ID hex numbers")
> > > cfb3db8fdae25 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
> > > 03e399020cd20 ("drm/i915: Add SKL GT1.5 PCI IDs")
> > > 812f044df08cc ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
> > > 194909a32aed0 ("drm/i915: Reclassify SKL 0x192a as GT3")
> > > 82e84284ab7dd ("drm/i915: Update Haswell PCI IDs")
> > > 24ea098b7c0d8 ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
> > > b50b7991b739c ("drm/i915/dg1: add more PCI ids")
> > >
> > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > ---
> >
> > I get really confused by commit messages like this. Which commit is
> > this now copied from, and which repo has that commit?
Hi Petri, yes I wasn't happy either doing this since it appears a simple
commit message like "Sync i915_pciids.h with the drm-tip kernel as of
today" should have been sufficient. But the previous git log for the file
has followed this format for the commit message. The format is the same as
that for "git log --oneline" for include/drm/i915_pciids.h on drm-tip,
newest commits on top.
But yes, I should have said it's the drm-tip kernel.
> Regardless of that confusion, the file matches what's in drm-tip so
>
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Thanks.
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel
2020-10-23 15:55 ` Dixit, Ashutosh
@ 2020-10-26 8:30 ` Petri Latvala
0 siblings, 0 replies; 7+ messages in thread
From: Petri Latvala @ 2020-10-26 8:30 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: igt-dev
On Fri, Oct 23, 2020 at 08:55:58AM -0700, Dixit, Ashutosh wrote:
> On Fri, 23 Oct 2020 01:03:24 -0700, Petri Latvala wrote:
> >
> > On Fri, Oct 23, 2020 at 10:59:27AM +0300, Petri Latvala wrote:
> > > On Thu, Oct 22, 2020 at 08:18:59PM -0700, Ashutosh Dixit wrote:
> > > > Align with kernel commits:
> > > >
> > > > 605f9c290c1a2 ("drm/i915: Sort ICL PCI IDs")
> > > > 514dc424ce4f5 ("drm/i915: Sort CNL PCI IDs")
> > > > 32d4ec9a1681d ("drm/i915: Sort CFL PCI IDs")
> > > > df3478af1d73c ("drm/i915: Sort CML PCI IDs")
> > > > cd988984cbea0 ("drm/i915: Sort KBL PCI IDs")
> > > > b04d36f737712 ("drm/i915: Sort SKL PCI IDs")
> > > > 9c0b2d30441b5 ("drm/i915: Sort HSW PCI IDs")
> > > > 79033a0a78984 ("drm/i915: Ocd the HSW PCI ID hex numbers")
> > > > cfb3db8fdae25 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
> > > > 03e399020cd20 ("drm/i915: Add SKL GT1.5 PCI IDs")
> > > > 812f044df08cc ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
> > > > 194909a32aed0 ("drm/i915: Reclassify SKL 0x192a as GT3")
> > > > 82e84284ab7dd ("drm/i915: Update Haswell PCI IDs")
> > > > 24ea098b7c0d8 ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
> > > > b50b7991b739c ("drm/i915/dg1: add more PCI ids")
> > > >
> > > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > > ---
> > >
> > > I get really confused by commit messages like this. Which commit is
> > > this now copied from, and which repo has that commit?
>
> Hi Petri, yes I wasn't happy either doing this since it appears a simple
> commit message like "Sync i915_pciids.h with the drm-tip kernel as of
> today" should have been sufficient. But the previous git log for the file
> has followed this format for the commit message. The format is the same as
> that for "git log --oneline" for include/drm/i915_pciids.h on drm-tip,
> newest commits on top.
>
> But yes, I should have said it's the drm-tip kernel.
The main thing I'm looking for is if this version of the header is in
drm-next already or is it only in dinq. Not a dealbreaker, but useful
information.
--
Petri Latvala
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-10-26 8:30 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-23 3:18 [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Ashutosh Dixit
2020-10-23 4:06 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: sync i915_pciids.h with kernel (rev8) Patchwork
2020-10-23 5:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2020-10-23 7:59 ` [igt-dev] [PATCH i-g-t] lib: sync i915_pciids.h with kernel Petri Latvala
2020-10-23 8:03 ` Petri Latvala
2020-10-23 15:55 ` Dixit, Ashutosh
2020-10-26 8:30 ` Petri Latvala
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