* [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
@ 2021-06-18 10:51 ` Alexandru Elisei
0 siblings, 0 replies; 6+ messages in thread
From: Alexandru Elisei @ 2021-06-18 10:51 UTC (permalink / raw)
To: maz, linux-arm-kernel, kvmarm
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:
"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."
Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
Found by code inspection.
Entertained the idea of restricting the number of bits in
for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
treats the cycle count register as the 32nd event counter. Settled on this
approach because I think it's clearer.
arch/arm64/kvm/pmu-emul.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index fd167d4f4215..ecc0d19c8cc1 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
if (val & ARMV8_PMU_PMCR_P) {
+ mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
for_each_set_bit(i, &mask, 32)
kvm_pmu_set_counter_value(vcpu, i, 0);
}
--
2.32.0
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
@ 2021-06-18 10:51 ` Alexandru Elisei
0 siblings, 0 replies; 6+ messages in thread
From: Alexandru Elisei @ 2021-06-18 10:51 UTC (permalink / raw)
To: maz, linux-arm-kernel, kvmarm; +Cc: james.morse, suzuki.poulose
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:
"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."
Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
Found by code inspection.
Entertained the idea of restricting the number of bits in
for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
treats the cycle count register as the 32nd event counter. Settled on this
approach because I think it's clearer.
arch/arm64/kvm/pmu-emul.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index fd167d4f4215..ecc0d19c8cc1 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
if (val & ARMV8_PMU_PMCR_P) {
+ mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
for_each_set_bit(i, &mask, 32)
kvm_pmu_set_counter_value(vcpu, i, 0);
}
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
2021-06-18 10:51 ` Alexandru Elisei
@ 2021-06-18 11:16 ` Alexandru Elisei
-1 siblings, 0 replies; 6+ messages in thread
From: Alexandru Elisei @ 2021-06-18 11:16 UTC (permalink / raw)
To: maz, linux-arm-kernel, kvmarm
Argh, forgot to CC Eric.
On 6/18/21 11:51 AM, Alexandru Elisei wrote:
> According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
> 1 has the following effect:
>
> "Reset all event counters accessible in the current Exception level, not
> including PMCCNTR_EL0, to zero."
>
> Similar behaviour is described for AArch32 on page G8-7022. Make it so.
>
> Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
> Found by code inspection.
>
> Entertained the idea of restricting the number of bits in
> for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
> treats the cycle count register as the 32nd event counter. Settled on this
> approach because I think it's clearer.
>
> arch/arm64/kvm/pmu-emul.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index fd167d4f4215..ecc0d19c8cc1 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
> kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
>
> if (val & ARMV8_PMU_PMCR_P) {
> + mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
> for_each_set_bit(i, &mask, 32)
> kvm_pmu_set_counter_value(vcpu, i, 0);
> }
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
@ 2021-06-18 11:16 ` Alexandru Elisei
0 siblings, 0 replies; 6+ messages in thread
From: Alexandru Elisei @ 2021-06-18 11:16 UTC (permalink / raw)
To: maz, linux-arm-kernel, kvmarm; +Cc: Auger Eric
Argh, forgot to CC Eric.
On 6/18/21 11:51 AM, Alexandru Elisei wrote:
> According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
> 1 has the following effect:
>
> "Reset all event counters accessible in the current Exception level, not
> including PMCCNTR_EL0, to zero."
>
> Similar behaviour is described for AArch32 on page G8-7022. Make it so.
>
> Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> ---
> Found by code inspection.
>
> Entertained the idea of restricting the number of bits in
> for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
> treats the cycle count register as the 32nd event counter. Settled on this
> approach because I think it's clearer.
>
> arch/arm64/kvm/pmu-emul.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index fd167d4f4215..ecc0d19c8cc1 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
> kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
>
> if (val & ARMV8_PMU_PMCR_P) {
> + mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
> for_each_set_bit(i, &mask, 32)
> kvm_pmu_set_counter_value(vcpu, i, 0);
> }
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
2021-06-18 10:51 ` Alexandru Elisei
@ 2021-06-18 13:21 ` Marc Zyngier
-1 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2021-06-18 13:21 UTC (permalink / raw)
To: linux-arm-kernel, Alexandru Elisei, kvmarm
On Fri, 18 Jun 2021 11:51:39 +0100, Alexandru Elisei wrote:
> According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
> 1 has the following effect:
>
> "Reset all event counters accessible in the current Exception level, not
> including PMCCNTR_EL0, to zero."
>
> Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Applied to kvm-arm64/pmu-fixes, thanks!
[1/1] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
commit: 2a71fabf6a1bc9162a84e18d6ab991230ca4d588
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
@ 2021-06-18 13:21 ` Marc Zyngier
0 siblings, 0 replies; 6+ messages in thread
From: Marc Zyngier @ 2021-06-18 13:21 UTC (permalink / raw)
To: linux-arm-kernel, Alexandru Elisei, kvmarm
On Fri, 18 Jun 2021 11:51:39 +0100, Alexandru Elisei wrote:
> According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
> 1 has the following effect:
>
> "Reset all event counters accessible in the current Exception level, not
> including PMCCNTR_EL0, to zero."
>
> Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Applied to kvm-arm64/pmu-fixes, thanks!
[1/1] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
commit: 2a71fabf6a1bc9162a84e18d6ab991230ca4d588
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-18 13:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18 10:51 [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set Alexandru Elisei
2021-06-18 10:51 ` Alexandru Elisei
2021-06-18 11:16 ` Alexandru Elisei
2021-06-18 11:16 ` Alexandru Elisei
2021-06-18 13:21 ` Marc Zyngier
2021-06-18 13:21 ` Marc Zyngier
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.