* [PATCH v2 1/2] recipes-devtools/qemu: Add RISC-V support
@ 2018-06-21 21:26 Alistair Francis
2018-06-21 21:26 ` [PATCH v2 2/2] recipes-support/nspr: " Alistair Francis
0 siblings, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2018-06-21 21:26 UTC (permalink / raw)
To: openembedded-core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
meta/recipes-devtools/qemu/qemu.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc
index 094a975177..b05c1cee9e 100644
--- a/meta/recipes-devtools/qemu/qemu.inc
+++ b/meta/recipes-devtools/qemu/qemu.inc
@@ -9,7 +9,7 @@ inherit pkgconfig bluetooth
BBCLASSEXTEND = "native nativesdk"
# QEMU_TARGETS is overridable variable
-QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel mips64 mips64el ppc sh4 x86_64"
+QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel mips64 mips64el ppc riscv32 riscv64 sh4 x86_64"
EXTRA_OECONF = " \
--prefix=${prefix} \
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 2/2] recipes-support/nspr: Add RISC-V support
2018-06-21 21:26 [PATCH v2 1/2] recipes-devtools/qemu: Add RISC-V support Alistair Francis
@ 2018-06-21 21:26 ` Alistair Francis
2018-06-22 5:12 ` Martin Hundebøll
0 siblings, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2018-06-21 21:26 UTC (permalink / raw)
To: openembedded-core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
...initions-for-the-RISC-V-architecture.patch | 150 ++++++++++++++++++
meta/recipes-support/nspr/nspr_4.19.bb | 1 +
2 files changed, 151 insertions(+)
create mode 100644 meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
diff --git a/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
new file mode 100644
index 0000000000..aa32908d13
--- /dev/null
+++ b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
@@ -0,0 +1,150 @@
+# HG changeset patch
+# User Karsten Merker <merker@debian.org>
+# Date 1523974333 -7200
+# Node ID f47871e2aeb16b39d4f516690e25c81b04d6d05a
+# Parent 776db96f834cb86e8863052201d55f60a2da91cb
+Bug 1308584, Add type definitions for the RISC-V architecture, r=kaie
+
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+[ Changes by AF:
+ - Rebase on other Yocto patches
+]
+Upstream-Status: Merged [ https://hg.mozilla.org/projects/nspr/rev/f47871e2aeb1 ]
+
+diff --git a/pr/include/md/_linux.cfg b/pr/include/md/_linux.cfg
+--- a/pr/include/md/_linux.cfg
++++ b/pr/include/md/_linux.cfg
+@@ -1015,16 +1015,108 @@
+ #define PR_ALIGN_OF_FLOAT 4
+ #define PR_ALIGN_OF_DOUBLE 4
+ #define PR_ALIGN_OF_POINTER 4
+ #define PR_ALIGN_OF_WORD 4
+
+ #define PR_BYTES_PER_WORD_LOG2 2
+ #define PR_BYTES_PER_DWORD_LOG2 3
+
++#elif defined(__riscv) && (__riscv_xlen == 32)
++
++#undef IS_BIG_ENDIAN
++#define IS_LITTLE_ENDIAN 1
++#undef IS_64
++
++#define PR_BYTES_PER_BYTE 1
++#define PR_BYTES_PER_SHORT 2
++#define PR_BYTES_PER_INT 4
++#define PR_BYTES_PER_INT64 8
++#define PR_BYTES_PER_LONG 4
++#define PR_BYTES_PER_FLOAT 4
++#define PR_BYTES_PER_DOUBLE 8
++#define PR_BYTES_PER_WORD 4
++#define PR_BYTES_PER_DWORD 8
++
++#define PR_BITS_PER_BYTE 8
++#define PR_BITS_PER_SHORT 16
++#define PR_BITS_PER_INT 32
++#define PR_BITS_PER_INT64 64
++#define PR_BITS_PER_LONG 32
++#define PR_BITS_PER_FLOAT 32
++#define PR_BITS_PER_DOUBLE 64
++#define PR_BITS_PER_WORD 32
++
++#define PR_BITS_PER_BYTE_LOG2 3
++#define PR_BITS_PER_SHORT_LOG2 4
++#define PR_BITS_PER_INT_LOG2 5
++#define PR_BITS_PER_INT64_LOG2 6
++#define PR_BITS_PER_LONG_LOG2 5
++#define PR_BITS_PER_FLOAT_LOG2 5
++#define PR_BITS_PER_DOUBLE_LOG2 6
++#define PR_BITS_PER_WORD_LOG2 5
++
++#define PR_ALIGN_OF_SHORT 2
++#define PR_ALIGN_OF_INT 4
++#define PR_ALIGN_OF_LONG 4
++#define PR_ALIGN_OF_INT64 8
++#define PR_ALIGN_OF_FLOAT 4
++#define PR_ALIGN_OF_DOUBLE 8
++#define PR_ALIGN_OF_POINTER 4
++#define PR_ALIGN_OF_WORD 4
++
++#define PR_BYTES_PER_WORD_LOG2 2
++#define PR_BYTES_PER_DWORD_LOG2 3
++
++#elif defined(__riscv) && (__riscv_xlen == 64)
++
++#undef IS_BIG_ENDIAN
++#define IS_LITTLE_ENDIAN 1
++#define IS_64
++
++#define PR_BYTES_PER_BYTE 1
++#define PR_BYTES_PER_SHORT 2
++#define PR_BYTES_PER_INT 4
++#define PR_BYTES_PER_INT64 8
++#define PR_BYTES_PER_LONG 8
++#define PR_BYTES_PER_FLOAT 4
++#define PR_BYTES_PER_DOUBLE 8
++#define PR_BYTES_PER_WORD 8
++#define PR_BYTES_PER_DWORD 8
++
++#define PR_BITS_PER_BYTE 8
++#define PR_BITS_PER_SHORT 16
++#define PR_BITS_PER_INT 32
++#define PR_BITS_PER_INT64 64
++#define PR_BITS_PER_LONG 64
++#define PR_BITS_PER_FLOAT 32
++#define PR_BITS_PER_DOUBLE 64
++#define PR_BITS_PER_WORD 64
++
++#define PR_BITS_PER_BYTE_LOG2 3
++#define PR_BITS_PER_SHORT_LOG2 4
++#define PR_BITS_PER_INT_LOG2 5
++#define PR_BITS_PER_INT64_LOG2 6
++#define PR_BITS_PER_LONG_LOG2 6
++#define PR_BITS_PER_FLOAT_LOG2 5
++#define PR_BITS_PER_DOUBLE_LOG2 6
++#define PR_BITS_PER_WORD_LOG2 6
++
++#define PR_ALIGN_OF_SHORT 2
++#define PR_ALIGN_OF_INT 4
++#define PR_ALIGN_OF_LONG 8
++#define PR_ALIGN_OF_INT64 8
++#define PR_ALIGN_OF_FLOAT 4
++#define PR_ALIGN_OF_DOUBLE 8
++#define PR_ALIGN_OF_POINTER 8
++#define PR_ALIGN_OF_WORD 8
++
++#define PR_BYTES_PER_WORD_LOG2 3
++#define PR_BYTES_PER_DWORD_LOG2 3
++
+ #else
+
+ #error "Unknown CPU architecture"
+
+ #endif
+
+ #ifndef HAVE_LONG_LONG
+ #define HAVE_LONG_LONG
+diff --git a/pr/include/md/_linux.h b/pr/include/md/_linux.h
+--- a/pr/include/md/_linux.h
++++ b/pr/include/md/_linux.h
+@@ -54,16 +54,20 @@
+ #elif defined(__avr32__)
+ #define _PR_SI_ARCHITECTURE "avr32"
+ #elif defined(__m32r__)
+ #define _PR_SI_ARCHITECTURE "m32r"
+ #elif defined(__nios2__)
+ #define _PR_SI_ARCHITECTURE "nios2"
+ #elif defined(__or1k__)
+ #define _PR_SI_ARCHITECTURE "or1k"
++#elif defined(__riscv) && (__riscv_xlen == 32)
++#define _PR_SI_ARCHITECTURE "riscv32"
++#elif defined(__riscv) && (__riscv_xlen == 64)
++#define _PR_SI_ARCHITECTURE "riscv64"
+ #else
+ #error "Unknown CPU architecture"
+ #endif
+ #define PR_DLL_SUFFIX ".so"
+
+ #define _PR_VMBASE 0x30000000
+ #define _PR_STACK_VMBASE 0x50000000
+ #define _MD_DEFAULT_STACK_SIZE 65536L
+
diff --git a/meta/recipes-support/nspr/nspr_4.19.bb b/meta/recipes-support/nspr/nspr_4.19.bb
index de2c87131f..b43c78081d 100644
--- a/meta/recipes-support/nspr/nspr_4.19.bb
+++ b/meta/recipes-support/nspr/nspr_4.19.bb
@@ -11,6 +11,7 @@ SRC_URI = "http://ftp.mozilla.org/pub/nspr/releases/v${PV}/src/nspr-${PV}.tar.gz
file://remove-srcdir-from-configure-in.patch \
file://0002-Add-nios2-support.patch \
file://0001-md-Fix-build-with-musl.patch \
+ file://0003-Add-type-definitions-for-the-RISC-V-architecture.patch \
file://nspr.pc.in \
"
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2 2/2] recipes-support/nspr: Add RISC-V support
2018-06-21 21:26 ` [PATCH v2 2/2] recipes-support/nspr: " Alistair Francis
@ 2018-06-22 5:12 ` Martin Hundebøll
2018-06-22 18:18 ` Alistair Francis
0 siblings, 1 reply; 4+ messages in thread
From: Martin Hundebøll @ 2018-06-22 5:12 UTC (permalink / raw)
To: Alistair Francis, openembedded-core
On 2018-06-21 23:26, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> ...initions-for-the-RISC-V-architecture.patch | 150 ++++++++++++++++++
> meta/recipes-support/nspr/nspr_4.19.bb | 1 +
> 2 files changed, 151 insertions(+)
> create mode 100644 meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
>
> diff --git a/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
> new file mode 100644
> index 0000000000..aa32908d13
> --- /dev/null
> +++ b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
> @@ -0,0 +1,150 @@
> +# HG changeset patch
> +# User Karsten Merker <merker@debian.org>
> +# Date 1523974333 -7200
> +# Node ID f47871e2aeb16b39d4f516690e25c81b04d6d05a
> +# Parent 776db96f834cb86e8863052201d55f60a2da91cb
> +Bug 1308584, Add type definitions for the RISC-V architecture, r=kaie
> +
> +Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> +[ Changes by AF:
> + - Rebase on other Yocto patches
> +]
> +Upstream-Status: Merged [ https://hg.mozilla.org/projects/nspr/rev/f47871e2aeb1 ]
I don't think "merged" is a proper upstream status. Should be "backport"
instead:
https://www.openembedded.org/wiki/Commit_Patch_Message_Guidelines#Patch_Header_Recommendations:_Upstream-Status
> +
> +diff --git a/pr/include/md/_linux.cfg b/pr/include/md/_linux.cfg
> +--- a/pr/include/md/_linux.cfg
> ++++ b/pr/include/md/_linux.cfg
> +@@ -1015,16 +1015,108 @@
> + #define PR_ALIGN_OF_FLOAT 4
> + #define PR_ALIGN_OF_DOUBLE 4
> + #define PR_ALIGN_OF_POINTER 4
> + #define PR_ALIGN_OF_WORD 4
> +
> + #define PR_BYTES_PER_WORD_LOG2 2
> + #define PR_BYTES_PER_DWORD_LOG2 3
> +
> ++#elif defined(__riscv) && (__riscv_xlen == 32)
> ++
> ++#undef IS_BIG_ENDIAN
> ++#define IS_LITTLE_ENDIAN 1
> ++#undef IS_64
> ++
> ++#define PR_BYTES_PER_BYTE 1
> ++#define PR_BYTES_PER_SHORT 2
> ++#define PR_BYTES_PER_INT 4
> ++#define PR_BYTES_PER_INT64 8
> ++#define PR_BYTES_PER_LONG 4
> ++#define PR_BYTES_PER_FLOAT 4
> ++#define PR_BYTES_PER_DOUBLE 8
> ++#define PR_BYTES_PER_WORD 4
> ++#define PR_BYTES_PER_DWORD 8
> ++
> ++#define PR_BITS_PER_BYTE 8
> ++#define PR_BITS_PER_SHORT 16
> ++#define PR_BITS_PER_INT 32
> ++#define PR_BITS_PER_INT64 64
> ++#define PR_BITS_PER_LONG 32
> ++#define PR_BITS_PER_FLOAT 32
> ++#define PR_BITS_PER_DOUBLE 64
> ++#define PR_BITS_PER_WORD 32
> ++
> ++#define PR_BITS_PER_BYTE_LOG2 3
> ++#define PR_BITS_PER_SHORT_LOG2 4
> ++#define PR_BITS_PER_INT_LOG2 5
> ++#define PR_BITS_PER_INT64_LOG2 6
> ++#define PR_BITS_PER_LONG_LOG2 5
> ++#define PR_BITS_PER_FLOAT_LOG2 5
> ++#define PR_BITS_PER_DOUBLE_LOG2 6
> ++#define PR_BITS_PER_WORD_LOG2 5
> ++
> ++#define PR_ALIGN_OF_SHORT 2
> ++#define PR_ALIGN_OF_INT 4
> ++#define PR_ALIGN_OF_LONG 4
> ++#define PR_ALIGN_OF_INT64 8
> ++#define PR_ALIGN_OF_FLOAT 4
> ++#define PR_ALIGN_OF_DOUBLE 8
> ++#define PR_ALIGN_OF_POINTER 4
> ++#define PR_ALIGN_OF_WORD 4
> ++
> ++#define PR_BYTES_PER_WORD_LOG2 2
> ++#define PR_BYTES_PER_DWORD_LOG2 3
> ++
> ++#elif defined(__riscv) && (__riscv_xlen == 64)
> ++
> ++#undef IS_BIG_ENDIAN
> ++#define IS_LITTLE_ENDIAN 1
> ++#define IS_64
> ++
> ++#define PR_BYTES_PER_BYTE 1
> ++#define PR_BYTES_PER_SHORT 2
> ++#define PR_BYTES_PER_INT 4
> ++#define PR_BYTES_PER_INT64 8
> ++#define PR_BYTES_PER_LONG 8
> ++#define PR_BYTES_PER_FLOAT 4
> ++#define PR_BYTES_PER_DOUBLE 8
> ++#define PR_BYTES_PER_WORD 8
> ++#define PR_BYTES_PER_DWORD 8
> ++
> ++#define PR_BITS_PER_BYTE 8
> ++#define PR_BITS_PER_SHORT 16
> ++#define PR_BITS_PER_INT 32
> ++#define PR_BITS_PER_INT64 64
> ++#define PR_BITS_PER_LONG 64
> ++#define PR_BITS_PER_FLOAT 32
> ++#define PR_BITS_PER_DOUBLE 64
> ++#define PR_BITS_PER_WORD 64
> ++
> ++#define PR_BITS_PER_BYTE_LOG2 3
> ++#define PR_BITS_PER_SHORT_LOG2 4
> ++#define PR_BITS_PER_INT_LOG2 5
> ++#define PR_BITS_PER_INT64_LOG2 6
> ++#define PR_BITS_PER_LONG_LOG2 6
> ++#define PR_BITS_PER_FLOAT_LOG2 5
> ++#define PR_BITS_PER_DOUBLE_LOG2 6
> ++#define PR_BITS_PER_WORD_LOG2 6
> ++
> ++#define PR_ALIGN_OF_SHORT 2
> ++#define PR_ALIGN_OF_INT 4
> ++#define PR_ALIGN_OF_LONG 8
> ++#define PR_ALIGN_OF_INT64 8
> ++#define PR_ALIGN_OF_FLOAT 4
> ++#define PR_ALIGN_OF_DOUBLE 8
> ++#define PR_ALIGN_OF_POINTER 8
> ++#define PR_ALIGN_OF_WORD 8
> ++
> ++#define PR_BYTES_PER_WORD_LOG2 3
> ++#define PR_BYTES_PER_DWORD_LOG2 3
> ++
> + #else
> +
> + #error "Unknown CPU architecture"
> +
> + #endif
> +
> + #ifndef HAVE_LONG_LONG
> + #define HAVE_LONG_LONG
> +diff --git a/pr/include/md/_linux.h b/pr/include/md/_linux.h
> +--- a/pr/include/md/_linux.h
> ++++ b/pr/include/md/_linux.h
> +@@ -54,16 +54,20 @@
> + #elif defined(__avr32__)
> + #define _PR_SI_ARCHITECTURE "avr32"
> + #elif defined(__m32r__)
> + #define _PR_SI_ARCHITECTURE "m32r"
> + #elif defined(__nios2__)
> + #define _PR_SI_ARCHITECTURE "nios2"
> + #elif defined(__or1k__)
> + #define _PR_SI_ARCHITECTURE "or1k"
> ++#elif defined(__riscv) && (__riscv_xlen == 32)
> ++#define _PR_SI_ARCHITECTURE "riscv32"
> ++#elif defined(__riscv) && (__riscv_xlen == 64)
> ++#define _PR_SI_ARCHITECTURE "riscv64"
> + #else
> + #error "Unknown CPU architecture"
> + #endif
> + #define PR_DLL_SUFFIX ".so"
> +
> + #define _PR_VMBASE 0x30000000
> + #define _PR_STACK_VMBASE 0x50000000
> + #define _MD_DEFAULT_STACK_SIZE 65536L
> +
> diff --git a/meta/recipes-support/nspr/nspr_4.19.bb b/meta/recipes-support/nspr/nspr_4.19.bb
> index de2c87131f..b43c78081d 100644
> --- a/meta/recipes-support/nspr/nspr_4.19.bb
> +++ b/meta/recipes-support/nspr/nspr_4.19.bb
> @@ -11,6 +11,7 @@ SRC_URI = "http://ftp.mozilla.org/pub/nspr/releases/v${PV}/src/nspr-${PV}.tar.gz
> file://remove-srcdir-from-configure-in.patch \
> file://0002-Add-nios2-support.patch \
> file://0001-md-Fix-build-with-musl.patch \
> + file://0003-Add-type-definitions-for-the-RISC-V-architecture.patch \
> file://nspr.pc.in \
> "
>
>
--
Kind regards,
Martin Hundebøll
Embedded Linux Consultant
+45 61 65 54 61
martin@geanix.com
Geanix IVS
DK39600706
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2 2/2] recipes-support/nspr: Add RISC-V support
2018-06-22 5:12 ` Martin Hundebøll
@ 2018-06-22 18:18 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2018-06-22 18:18 UTC (permalink / raw)
To: Martin Hundebøll; +Cc: OE-core
On Thu, Jun 21, 2018 at 10:12 PM, Martin Hundebøll <martin@geanix.com> wrote:
>
>
> On 2018-06-21 23:26, Alistair Francis wrote:
>>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> ...initions-for-the-RISC-V-architecture.patch | 150 ++++++++++++++++++
>> meta/recipes-support/nspr/nspr_4.19.bb | 1 +
>> 2 files changed, 151 insertions(+)
>> create mode 100644
>> meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
>>
>> diff --git
>> a/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
>> b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
>> new file mode 100644
>> index 0000000000..aa32908d13
>> --- /dev/null
>> +++
>> b/meta/recipes-support/nspr/nspr/0003-Add-type-definitions-for-the-RISC-V-architecture.patch
>> @@ -0,0 +1,150 @@
>> +# HG changeset patch
>> +# User Karsten Merker <merker@debian.org>
>> +# Date 1523974333 -7200
>> +# Node ID f47871e2aeb16b39d4f516690e25c81b04d6d05a
>> +# Parent 776db96f834cb86e8863052201d55f60a2da91cb
>> +Bug 1308584, Add type definitions for the RISC-V architecture, r=kaie
>> +
>> +Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> +[ Changes by AF:
>> + - Rebase on other Yocto patches
>> +]
>> +Upstream-Status: Merged [
>> https://hg.mozilla.org/projects/nspr/rev/f47871e2aeb1 ]
>
>
> I don't think "merged" is a proper upstream status. Should be "backport"
> instead:
> https://www.openembedded.org/wiki/Commit_Patch_Message_Guidelines#Patch_Header_Recommendations:_Upstream-Status
Ah, this is handy, I always forget the status messages. I'll fix in v3.
Alistair
>
>
>> +
>> +diff --git a/pr/include/md/_linux.cfg b/pr/include/md/_linux.cfg
>> +--- a/pr/include/md/_linux.cfg
>> ++++ b/pr/include/md/_linux.cfg
>> +@@ -1015,16 +1015,108 @@
>> + #define PR_ALIGN_OF_FLOAT 4
>> + #define PR_ALIGN_OF_DOUBLE 4
>> + #define PR_ALIGN_OF_POINTER 4
>> + #define PR_ALIGN_OF_WORD 4
>> +
>> + #define PR_BYTES_PER_WORD_LOG2 2
>> + #define PR_BYTES_PER_DWORD_LOG2 3
>> +
>> ++#elif defined(__riscv) && (__riscv_xlen == 32)
>> ++
>> ++#undef IS_BIG_ENDIAN
>> ++#define IS_LITTLE_ENDIAN 1
>> ++#undef IS_64
>> ++
>> ++#define PR_BYTES_PER_BYTE 1
>> ++#define PR_BYTES_PER_SHORT 2
>> ++#define PR_BYTES_PER_INT 4
>> ++#define PR_BYTES_PER_INT64 8
>> ++#define PR_BYTES_PER_LONG 4
>> ++#define PR_BYTES_PER_FLOAT 4
>> ++#define PR_BYTES_PER_DOUBLE 8
>> ++#define PR_BYTES_PER_WORD 4
>> ++#define PR_BYTES_PER_DWORD 8
>> ++
>> ++#define PR_BITS_PER_BYTE 8
>> ++#define PR_BITS_PER_SHORT 16
>> ++#define PR_BITS_PER_INT 32
>> ++#define PR_BITS_PER_INT64 64
>> ++#define PR_BITS_PER_LONG 32
>> ++#define PR_BITS_PER_FLOAT 32
>> ++#define PR_BITS_PER_DOUBLE 64
>> ++#define PR_BITS_PER_WORD 32
>> ++
>> ++#define PR_BITS_PER_BYTE_LOG2 3
>> ++#define PR_BITS_PER_SHORT_LOG2 4
>> ++#define PR_BITS_PER_INT_LOG2 5
>> ++#define PR_BITS_PER_INT64_LOG2 6
>> ++#define PR_BITS_PER_LONG_LOG2 5
>> ++#define PR_BITS_PER_FLOAT_LOG2 5
>> ++#define PR_BITS_PER_DOUBLE_LOG2 6
>> ++#define PR_BITS_PER_WORD_LOG2 5
>> ++
>> ++#define PR_ALIGN_OF_SHORT 2
>> ++#define PR_ALIGN_OF_INT 4
>> ++#define PR_ALIGN_OF_LONG 4
>> ++#define PR_ALIGN_OF_INT64 8
>> ++#define PR_ALIGN_OF_FLOAT 4
>> ++#define PR_ALIGN_OF_DOUBLE 8
>> ++#define PR_ALIGN_OF_POINTER 4
>> ++#define PR_ALIGN_OF_WORD 4
>> ++
>> ++#define PR_BYTES_PER_WORD_LOG2 2
>> ++#define PR_BYTES_PER_DWORD_LOG2 3
>> ++
>> ++#elif defined(__riscv) && (__riscv_xlen == 64)
>> ++
>> ++#undef IS_BIG_ENDIAN
>> ++#define IS_LITTLE_ENDIAN 1
>> ++#define IS_64
>> ++
>> ++#define PR_BYTES_PER_BYTE 1
>> ++#define PR_BYTES_PER_SHORT 2
>> ++#define PR_BYTES_PER_INT 4
>> ++#define PR_BYTES_PER_INT64 8
>> ++#define PR_BYTES_PER_LONG 8
>> ++#define PR_BYTES_PER_FLOAT 4
>> ++#define PR_BYTES_PER_DOUBLE 8
>> ++#define PR_BYTES_PER_WORD 8
>> ++#define PR_BYTES_PER_DWORD 8
>> ++
>> ++#define PR_BITS_PER_BYTE 8
>> ++#define PR_BITS_PER_SHORT 16
>> ++#define PR_BITS_PER_INT 32
>> ++#define PR_BITS_PER_INT64 64
>> ++#define PR_BITS_PER_LONG 64
>> ++#define PR_BITS_PER_FLOAT 32
>> ++#define PR_BITS_PER_DOUBLE 64
>> ++#define PR_BITS_PER_WORD 64
>> ++
>> ++#define PR_BITS_PER_BYTE_LOG2 3
>> ++#define PR_BITS_PER_SHORT_LOG2 4
>> ++#define PR_BITS_PER_INT_LOG2 5
>> ++#define PR_BITS_PER_INT64_LOG2 6
>> ++#define PR_BITS_PER_LONG_LOG2 6
>> ++#define PR_BITS_PER_FLOAT_LOG2 5
>> ++#define PR_BITS_PER_DOUBLE_LOG2 6
>> ++#define PR_BITS_PER_WORD_LOG2 6
>> ++
>> ++#define PR_ALIGN_OF_SHORT 2
>> ++#define PR_ALIGN_OF_INT 4
>> ++#define PR_ALIGN_OF_LONG 8
>> ++#define PR_ALIGN_OF_INT64 8
>> ++#define PR_ALIGN_OF_FLOAT 4
>> ++#define PR_ALIGN_OF_DOUBLE 8
>> ++#define PR_ALIGN_OF_POINTER 8
>> ++#define PR_ALIGN_OF_WORD 8
>> ++
>> ++#define PR_BYTES_PER_WORD_LOG2 3
>> ++#define PR_BYTES_PER_DWORD_LOG2 3
>> ++
>> + #else
>> +
>> + #error "Unknown CPU architecture"
>> +
>> + #endif
>> +
>> + #ifndef HAVE_LONG_LONG
>> + #define HAVE_LONG_LONG
>> +diff --git a/pr/include/md/_linux.h b/pr/include/md/_linux.h
>> +--- a/pr/include/md/_linux.h
>> ++++ b/pr/include/md/_linux.h
>> +@@ -54,16 +54,20 @@
>> + #elif defined(__avr32__)
>> + #define _PR_SI_ARCHITECTURE "avr32"
>> + #elif defined(__m32r__)
>> + #define _PR_SI_ARCHITECTURE "m32r"
>> + #elif defined(__nios2__)
>> + #define _PR_SI_ARCHITECTURE "nios2"
>> + #elif defined(__or1k__)
>> + #define _PR_SI_ARCHITECTURE "or1k"
>> ++#elif defined(__riscv) && (__riscv_xlen == 32)
>> ++#define _PR_SI_ARCHITECTURE "riscv32"
>> ++#elif defined(__riscv) && (__riscv_xlen == 64)
>> ++#define _PR_SI_ARCHITECTURE "riscv64"
>> + #else
>> + #error "Unknown CPU architecture"
>> + #endif
>> + #define PR_DLL_SUFFIX ".so"
>> +
>> + #define _PR_VMBASE 0x30000000
>> + #define _PR_STACK_VMBASE 0x50000000
>> + #define _MD_DEFAULT_STACK_SIZE 65536L
>> +
>> diff --git a/meta/recipes-support/nspr/nspr_4.19.bb
>> b/meta/recipes-support/nspr/nspr_4.19.bb
>> index de2c87131f..b43c78081d 100644
>> --- a/meta/recipes-support/nspr/nspr_4.19.bb
>> +++ b/meta/recipes-support/nspr/nspr_4.19.bb
>> @@ -11,6 +11,7 @@ SRC_URI =
>> "http://ftp.mozilla.org/pub/nspr/releases/v${PV}/src/nspr-${PV}.tar.gz
>> file://remove-srcdir-from-configure-in.patch \
>> file://0002-Add-nios2-support.patch \
>> file://0001-md-Fix-build-with-musl.patch \
>> +
>> file://0003-Add-type-definitions-for-the-RISC-V-architecture.patch \
>> file://nspr.pc.in \
>> "
>>
>
>
> --
> Kind regards,
> Martin Hundebøll
> Embedded Linux Consultant
>
> +45 61 65 54 61
> martin@geanix.com
>
> Geanix IVS
> DK39600706
> --
> _______________________________________________
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.openembedded.org/mailman/listinfo/openembedded-core
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-06-22 18:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-21 21:26 [PATCH v2 1/2] recipes-devtools/qemu: Add RISC-V support Alistair Francis
2018-06-21 21:26 ` [PATCH v2 2/2] recipes-support/nspr: " Alistair Francis
2018-06-22 5:12 ` Martin Hundebøll
2018-06-22 18:18 ` Alistair Francis
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