* [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
@ 2011-07-12 5:59 Naga Chumbalkar
2011-07-12 7:05 ` Cyrill Gorcunov
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Naga Chumbalkar @ 2011-07-12 5:59 UTC (permalink / raw)
To: x86; +Cc: Naga Chumbalkar, suresh.b.siddha, linux-kernel, hpa, mingo, tglx
If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.
The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8..f7b0c7a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1429,7 +1429,7 @@ void enable_x2apic(void)
rdmsr(MSR_IA32_APICBASE, msr, msr2);
if (!(msr & X2APIC_ENABLE)) {
printk_once(KERN_INFO "Enabling x2apic\n");
- wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+ wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
}
}
#endif /* CONFIG_X86_X2APIC */
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 5:59 [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR Naga Chumbalkar
@ 2011-07-12 7:05 ` Cyrill Gorcunov
2011-07-12 17:29 ` Suresh Siddha
2011-07-13 3:06 ` [tip:x86/apic] " tip-bot for Naga Chumbalkar
2 siblings, 0 replies; 7+ messages in thread
From: Cyrill Gorcunov @ 2011-07-12 7:05 UTC (permalink / raw)
To: Naga Chumbalkar; +Cc: x86, suresh.b.siddha, linux-kernel, hpa, mingo, tglx
On Tue, Jul 12, 2011 at 05:59:07AM +0000, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
>
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
>
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
>
Looks like a good idea for me. I've reviewed some additional specs
and even some updates, nothing interesting found.
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 5:59 [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR Naga Chumbalkar
2011-07-12 7:05 ` Cyrill Gorcunov
@ 2011-07-12 17:29 ` Suresh Siddha
2011-07-12 18:21 ` H. Peter Anvin
2011-07-13 3:06 ` [tip:x86/apic] " tip-bot for Naga Chumbalkar
2 siblings, 1 reply; 7+ messages in thread
From: Suresh Siddha @ 2011-07-12 17:29 UTC (permalink / raw)
To: Naga Chumbalkar; +Cc: x86, linux-kernel, hpa, mingo, tglx
On Mon, 2011-07-11 at 22:59 -0700, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
>
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
>
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index b9338b8..f7b0c7a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1429,7 +1429,7 @@ void enable_x2apic(void)
> rdmsr(MSR_IA32_APICBASE, msr, msr2);
> if (!(msr & X2APIC_ENABLE)) {
> printk_once(KERN_INFO "Enabling x2apic\n");
> - wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
> + wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
> }
> }
> #endif /* CONFIG_X86_X2APIC */
yeah, I don't think it was intentional.
Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 17:29 ` Suresh Siddha
@ 2011-07-12 18:21 ` H. Peter Anvin
2011-07-12 18:36 ` Suresh Siddha
0 siblings, 1 reply; 7+ messages in thread
From: H. Peter Anvin @ 2011-07-12 18:21 UTC (permalink / raw)
To: Suresh Siddha; +Cc: Naga Chumbalkar, x86, linux-kernel, mingo, tglx
On 07/12/2011 10:29 AM, Suresh Siddha wrote:
>
> yeah, I don't think it was intentional.
>
> Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
>
This isn't 3.0 material, though (no manifest error), correct?
-hpa
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 18:21 ` H. Peter Anvin
@ 2011-07-12 18:36 ` Suresh Siddha
2011-07-12 18:43 ` Chumbalkar, Nagananda
0 siblings, 1 reply; 7+ messages in thread
From: Suresh Siddha @ 2011-07-12 18:36 UTC (permalink / raw)
To: H. Peter Anvin; +Cc: Naga Chumbalkar, x86, linux-kernel, mingo, tglx
On Tue, 2011-07-12 at 11:21 -0700, H. Peter Anvin wrote:
> On 07/12/2011 10:29 AM, Suresh Siddha wrote:
> >
> > yeah, I don't think it was intentional.
> >
> > Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
> >
>
> This isn't 3.0 material, though (no manifest error), correct?
Yep. Right Naga?
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 18:36 ` Suresh Siddha
@ 2011-07-12 18:43 ` Chumbalkar, Nagananda
0 siblings, 0 replies; 7+ messages in thread
From: Chumbalkar, Nagananda @ 2011-07-12 18:43 UTC (permalink / raw)
To: Suresh Siddha, H. Peter Anvin; +Cc: x86, linux-kernel, mingo, tglx
>-----Original Message-----
>From: Suresh Siddha [mailto:suresh.b.siddha@intel.com]
>Sent: Tuesday, July 12, 2011 1:36 PM
>To: H. Peter Anvin
>Cc: Chumbalkar, Nagananda; x86@kernel.org; linux-kernel@vger.kernel.org;
>mingo@elte.hu; tglx@linutronix.de
>Subject: Re: [PATCH] x86, x2apic: Preserve high 32-bits of
>IA32_APIC_BASE MSR
>
>On Tue, 2011-07-12 at 11:21 -0700, H. Peter Anvin wrote:
>> On 07/12/2011 10:29 AM, Suresh Siddha wrote:
>> >
>> > yeah, I don't think it was intentional.
>> >
>> > Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
>> >
>>
>> This isn't 3.0 material, though (no manifest error), correct?
>
>Yep. Right Naga?
That's correct. No manifest errors. This patch can wait.
- naga -
^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:x86/apic] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
2011-07-12 5:59 [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR Naga Chumbalkar
2011-07-12 7:05 ` Cyrill Gorcunov
2011-07-12 17:29 ` Suresh Siddha
@ 2011-07-13 3:06 ` tip-bot for Naga Chumbalkar
2 siblings, 0 replies; 7+ messages in thread
From: tip-bot for Naga Chumbalkar @ 2011-07-13 3:06 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, gorcunov, suresh.b.siddha,
nagananda.chumbalkar, tglx, hpa
Commit-ID: 25970852280c9d5fb2de899769880d3e97332baa
Gitweb: http://git.kernel.org/tip/25970852280c9d5fb2de899769880d3e97332baa
Author: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
AuthorDate: Tue, 12 Jul 2011 05:59:07 +0000
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 12 Jul 2011 14:33:49 -0700
x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.
The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Link: http://lkml.kernel.org/r/20110712055831.2498.78521.sendpatchset@nchumbalkar.americas.cpqcorp.net
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/kernel/apic/apic.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b9338b8..f7b0c7a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1429,7 +1429,7 @@ void enable_x2apic(void)
rdmsr(MSR_IA32_APICBASE, msr, msr2);
if (!(msr & X2APIC_ENABLE)) {
printk_once(KERN_INFO "Enabling x2apic\n");
- wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+ wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
}
}
#endif /* CONFIG_X86_X2APIC */
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-07-13 3:07 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-07-12 5:59 [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR Naga Chumbalkar
2011-07-12 7:05 ` Cyrill Gorcunov
2011-07-12 17:29 ` Suresh Siddha
2011-07-12 18:21 ` H. Peter Anvin
2011-07-12 18:36 ` Suresh Siddha
2011-07-12 18:43 ` Chumbalkar, Nagananda
2011-07-13 3:06 ` [tip:x86/apic] " tip-bot for Naga Chumbalkar
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