[PATCH] drm/i915: Improve HiZ throughput on Cherryview.

[PATCH] drm/i915: Improve HiZ throughput on Cherryview.

[Kenneth Graunke]

Found by reading the HIZ_CHICKEN documentation.

Improves performance in a HiZ microbenchmark by around 50%.
Improves performance in OglZBuffer by around 18%.

Thanks to Chris Wilson for helping me figure out where to put this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f32fd1a..a39bb03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5202,6 +5202,9 @@ enum punit_power_well {
 #define COMMON_SLICE_CHICKEN2			0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
 
+#define HIZ_CHICKEN				0x7018
+# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
+
 #define GEN7_L3SQCREG1				0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12a36f0..dabc1d8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -836,6 +836,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
 			  HDC_FORCE_NON_COHERENT |
 			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
 
+	/* Improve HiZ throughput on CHV. */
+	WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
+
 	return 0;
 }
 
-- 
2.2.1

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Re: [PATCH] drm/i915: Improve HiZ throughput on Cherryview.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  354/354              354/354
ILK                                  201/201              201/201
SNB              +2-2              401/424              401/424
IVB                                  488/488              488/488
BYT                                  278/278              278/278
HSW                 -1              529/529              528/529
BDW                 -1              405/405              404/405
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_kms_flip_event_leak      NSPT(3, M35)      PASS(1, M35)
 SNB  igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible      NSPT(1, M35)PASS(2, M35)      PASS(1, M35)
*SNB  igt_kms_flip_tiling_flip-changes-tiling      PASS(2, M35)      TIMEOUT(1, M35)
*SNB  igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible      PASS(3, M35)      DMESG_WARN(1, M35)
 HSW  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(2, M40)PASS(1, M20)      DMESG_WARN(1, M40)
*BDW  igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible      PASS(2, M30)      DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Improve HiZ throughput on Cherryview.

[Ville Syrjälä]

On Sat, Jan 10, 2015 at 06:02:22PM -0800, Kenneth Graunke wrote:
> Found by reading the HIZ_CHICKEN documentation.
> 
> Improves performance in a HiZ microbenchmark by around 50%.
> Improves performance in OglZBuffer by around 18%.
> 
> Thanks to Chris Wilson for helping me figure out where to put this.
> 
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f32fd1a..a39bb03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5202,6 +5202,9 @@ enum punit_power_well {
>  #define COMMON_SLICE_CHICKEN2			0x7014
>  # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>  
> +#define HIZ_CHICKEN				0x7018
> +# define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
> +
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 12a36f0..dabc1d8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -836,6 +836,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  			  HDC_FORCE_NON_COHERENT |
>  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>  
> +	/* Improve HiZ throughput on CHV. */
> +	WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
> +

Nothing much in bspec about this bit. Can't see anything suspicious
in the w/a database either. So I guess we can assume it's safe.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

But I do wonder a bit if there's any relationship with the WIZ hashing
mode. Looks like we've not brought the 16x4 WIZ hashing mode change
over to CHV (or BYT for that matter), so I guess we're still using the
default 8x8 on these platforms. Might be interesting to see if there
are any gains to be had by changing it.

>  	return 0;
>  }
>  
> -- 
> 2.2.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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