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From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Salter <msalter@redhat.com>
Cc: Will Deacon <will.deacon@arm.com>,
	Matt Fleming <matt.fleming@intel.com>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	linux-kernel@vger.kernel.org, Hanjun Guo <hanjun.guo@linaro.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: support ACPI tables outside of kernel RAM
Date: Mon, 18 May 2015 12:11:44 +0100	[thread overview]
Message-ID: <20150518111143.GC21251@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1431613373-10928-1-git-send-email-msalter@redhat.com>

On Thu, May 14, 2015 at 10:22:53AM -0400, Mark Salter wrote:
> There is no guarantee that ACPI tables will be located in RAM linearly
> mapped by the kernel. This could be because UEFI placed them below the
> kernel image or because mem= places them beyond the reach of the linear
> kernel mapping. Even though these tables are outside the linear mapped
> RAM, they still need to be accessed as normal memory in order to support
> unaligned accesses from ACPI code. In this case, the page_is_ram() test
> in acpi_os_ioremap() is not sufficient.

And can we not simply add the rest of the RAM to the resource list as
"System RAM" without being part of memblock?

> Additionally, if the table spans multiple pages, it may fall partially
> within the linear map and partially without. If the table overlaps the
> end of the linear map, the test for whether or not to use the existing
> mapping in ioremap_cache() could lead to a panic when ACPI code tries
> to access the part beyond the end of the linear map. This patch
> attempts to address these problems.

That's a problem with ioremap_cache() that should be fixed independently.

Ideally, I'd like to see the ACPI code use different APIs to distinguish
between table access in RAM and device access, so that we don't have to
guess whether the page is RAM or not.

-- 
Catalin

WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: support ACPI tables outside of kernel RAM
Date: Mon, 18 May 2015 12:11:44 +0100	[thread overview]
Message-ID: <20150518111143.GC21251@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1431613373-10928-1-git-send-email-msalter@redhat.com>

On Thu, May 14, 2015 at 10:22:53AM -0400, Mark Salter wrote:
> There is no guarantee that ACPI tables will be located in RAM linearly
> mapped by the kernel. This could be because UEFI placed them below the
> kernel image or because mem= places them beyond the reach of the linear
> kernel mapping. Even though these tables are outside the linear mapped
> RAM, they still need to be accessed as normal memory in order to support
> unaligned accesses from ACPI code. In this case, the page_is_ram() test
> in acpi_os_ioremap() is not sufficient.

And can we not simply add the rest of the RAM to the resource list as
"System RAM" without being part of memblock?

> Additionally, if the table spans multiple pages, it may fall partially
> within the linear map and partially without. If the table overlaps the
> end of the linear map, the test for whether or not to use the existing
> mapping in ioremap_cache() could lead to a panic when ACPI code tries
> to access the part beyond the end of the linear map. This patch
> attempts to address these problems.

That's a problem with ioremap_cache() that should be fixed independently.

Ideally, I'd like to see the ACPI code use different APIs to distinguish
between table access in RAM and device access, so that we don't have to
guess whether the page is RAM or not.

-- 
Catalin

  parent reply	other threads:[~2015-05-18 11:11 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-14 14:22 [PATCH] arm64: support ACPI tables outside of kernel RAM Mark Salter
2015-05-14 14:22 ` Mark Salter
2015-05-14 14:50 ` Ard Biesheuvel
2015-05-14 14:50   ` Ard Biesheuvel
2015-05-15 13:58   ` Mark Salter
2015-05-15 13:58     ` Mark Salter
2015-05-18 11:11 ` Catalin Marinas [this message]
2015-05-18 11:11   ` Catalin Marinas
2015-05-18 13:58   ` Mark Salter
2015-05-18 13:58     ` Mark Salter
2015-05-18 16:41     ` Catalin Marinas
2015-05-18 16:41       ` Catalin Marinas
2015-05-18 16:49       ` Ard Biesheuvel
2015-05-18 16:49         ` Ard Biesheuvel
2015-05-22 10:34         ` Catalin Marinas
2015-05-22 10:34           ` Catalin Marinas
2015-05-22 12:46           ` Mark Salter
2015-05-22 12:46             ` Mark Salter
2015-05-22 12:53             ` Catalin Marinas
2015-05-22 12:53               ` Catalin Marinas
2015-05-22 13:13               ` Mark Salter
2015-05-22 13:13                 ` Mark Salter
2015-05-22 13:49           ` Mark Salter
2015-05-22 13:49             ` Mark Salter

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