Re: [RFC 7/8] fpga-region: add sysfs interface

From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
To: Alan Tull <delicious.quinoa@gmail.com>
Cc: Moritz Fischer <moritz.fischer@ettus.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-fpga@vger.kernel.org
Subject: Re: [RFC 7/8] fpga-region: add sysfs interface
Date: Wed, 15 Feb 2017 16:07:00 -0700	[thread overview]
Message-ID: <20170215230700.GA17067@obsidianresearch.com> (raw)
In-Reply-To: <CANk1AXQiCy6ySx_LVs9Oi6BT_T-hQPWX_ckakQ-UTE9PKh-7PA@mail.gmail.com>

On Wed, Feb 15, 2017 at 04:49:58PM -0600, Alan Tull wrote:

> So this script takes the bitfile and its build logs as input, parses
> the build logs for image information, does some manipulations on bit
> order as needed, and adds the header.  So it's really doing (at least)
> two things: adding header info and doing bitorder changes where needed
> so that the kernel won't need to do it.

Yes. This mangling is basically mandatory for Zynq due to how DevCfg
works, what Xilinx tools emit, and the desire to avoid copying the
bitfile.

Other cases are less essential, eg a gpio driver could do the
bit-reversal internally. We did the swap when writing the image
because the speed up was very noticable when the programming hardware
was a < 100MHz CPU.

It would be trivial to add Altera support, it really just needs a
similar build log parser for Altera's format to extract similar
information.

Jason