From: Palmer Dabbelt <palmer@dabbelt.com> To: linux-arch@vger.kernel.org To: linux-kernel@vger.kernel.org To: Arnd Bergmann <arnd@arndb.de> To: olof@lixom.net Cc: albert@sifive.com Cc: patches@groups.riscv.org Cc: Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Date: Tue, 6 Jun 2017 16:00:01 -0700 [thread overview] Message-ID: <20170606230007.19101-12-palmer@dabbelt.com> (raw) In-Reply-To: <20170606230007.19101-1-palmer@dabbelt.com> This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt controller). Per-hart local interrupt controllers are found on all RISC-V systems. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> --- drivers/irqchip/Kconfig | 14 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 239 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-intc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 2906d63934ef..dfde170e5886 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -313,3 +313,17 @@ config RISCV_PLIC interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC. If you don't know what to do here, say Y. + +config RISCV_INTC + def_bool y if RISCV + #bool "RISC-V Interrupt Controller" + depends on RISCV + default y + help + This enables support for the local interrupt controller found in + standard RISC-V systems. The local interrupt controller handles + timer interrupts, software interrupts, and hardware interrupts. + Without a local interrupt controller the system will be unable to + handle any interrupts, including those passed via the PLIC. + + If you don't know what to do here, say Y. diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index bed94cc89146..bc9a6b45903b 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_RISCV_PLIC) += irq-riscv-plic.o +obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c new file mode 100644 index 000000000000..8150a035aada --- /dev/null +++ b/drivers/irqchip/irq-riscv-intc.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> +#include <linux/interrupt.h> +#include <linux/ftrace.h> +#include <linux/of.h> +#include <linux/seq_file.h> + +#include <asm/ptrace.h> +#include <asm/sbi.h> +#include <asm/smp.h> + +struct riscv_irq_data { + struct irq_chip chip; + struct irq_domain *domain; + int hart; + char name[20]; +}; +DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data); +DEFINE_PER_CPU(atomic_long_t, riscv_early_sie); + +static void riscv_software_interrupt(void) +{ +#ifdef CONFIG_SMP + irqreturn_t ret; + + ret = handle_ipi(); + if (ret != IRQ_NONE) + return; +#endif + + BUG(); +} + +asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs) +{ + struct pt_regs *old_regs = set_irq_regs(regs); + struct irq_domain *domain; + + irq_enter(); + + /* There are three classes of interrupt: timer, software, and + * external devices. We dispatch between them here. External + * device interrupts use the generic IRQ mechanisms. + */ + switch (cause) { + case INTERRUPT_CAUSE_TIMER: + riscv_timer_interrupt(); + break; + case INTERRUPT_CAUSE_SOFTWARE: + riscv_software_interrupt(); + break; + default: + domain = per_cpu(riscv_irq_data, smp_processor_id()).domain; + generic_handle_irq(irq_find_mapping(domain, cause)); + break; + } + + irq_exit(); + set_irq_regs(old_regs); +} + +static int riscv_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct riscv_irq_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &data->chip, handle_simple_irq); + irq_set_chip_data(irq, data); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops riscv_irqdomain_ops = { + .map = riscv_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +static void riscv_irq_mask(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + BUG_ON(smp_processor_id() != data->hart); + csr_clear(sie, 1 << (long)d->hwirq); +} + +static void riscv_irq_unmask(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + BUG_ON(smp_processor_id() != data->hart); + csr_set(sie, 1 << (long)d->hwirq); +} + +static void riscv_irq_enable_helper(void *d) +{ + riscv_irq_unmask(d); +} + +static void riscv_irq_enable(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + /* There are two phases to setting up an interrupt: first we set a bit + * in this bookkeeping structure, which is used by trap_init to + * initialize SIE for each hart as it comes up. + */ + atomic_long_or((1 << (long)d->hwirq), + &per_cpu(riscv_early_sie, data->hart)); + + /* The CPU is usually online, so here we just attempt to enable the + * interrupt by writing SIE directly. We need to write SIE on the + * correct hart, which might be another hart. + */ + if (data->hart == smp_processor_id()) + riscv_irq_unmask(d); + else if (cpu_online(data->hart)) + smp_call_function_single(data->hart, + riscv_irq_enable_helper, + d, + true); +} + +static void riscv_irq_disable_helper(void *d) +{ + riscv_irq_mask(d); +} + +static void riscv_irq_disable(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + /* This is the mirror of riscv_irq_enable. */ + atomic_long_and(~(1 << (long)d->hwirq), + &per_cpu(riscv_early_sie, data->hart)); + if (data->hart == smp_processor_id()) + riscv_irq_mask(d); + else if (cpu_online(data->hart)) + smp_call_function_single(data->hart, + riscv_irq_disable_helper, + d, + true); +} + +static void riscv_irq_mask_noop(struct irq_data *d) { } + +static void riscv_irq_unmask_noop(struct irq_data *d) { } + +static void riscv_irq_enable_noop(struct irq_data *d) +{ + struct device_node *data = irq_data_get_irq_chip_data(d); + u32 hart; + + if (!of_property_read_u32(data, "reg", &hart)) + printk( + KERN_WARNING "enabled interrupt %d for missing hart %d (this interrupt has no handler)\n", + (int)d->hwirq, hart); +} + +static struct irq_chip riscv_noop_chip = { + .name = "riscv,cpu-intc,noop", + .irq_mask = riscv_irq_mask_noop, + .irq_unmask = riscv_irq_unmask_noop, + .irq_enable = riscv_irq_enable_noop, +}; + +static int riscv_irqdomain_map_noop(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct device_node *data = d->host_data; + + irq_set_chip_and_handler(irq, &riscv_noop_chip, handle_simple_irq); + irq_set_chip_data(irq, data); + return 0; +} + +static const struct irq_domain_ops riscv_irqdomain_ops_noop = { + .map = riscv_irqdomain_map_noop, + .xlate = irq_domain_xlate_onecell, +}; + +static int riscv_intc_init(struct device_node *node, struct device_node *parent) +{ + int hart; + struct riscv_irq_data *data; + + if (parent) + return 0; + + hart = riscv_of_processor_hart(node->parent); + if (hart < 0) { + /* If a hart is disabled, create a no-op irq domain. Devices + * may still have interrupts connected to those harts. This is + * not wrong... unless they actually load a driver that needs + * it! + */ + irq_domain_add_linear( + node, + 8*sizeof(uintptr_t), + &riscv_irqdomain_ops_noop, + node->parent); + return 0; + } + + data = &per_cpu(riscv_irq_data, hart); + snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart); + data->hart = hart; + data->chip.name = data->name; + data->chip.irq_mask = riscv_irq_mask; + data->chip.irq_unmask = riscv_irq_unmask; + data->chip.irq_enable = riscv_irq_enable; + data->chip.irq_disable = riscv_irq_disable; + data->domain = irq_domain_add_linear( + node, + 8*sizeof(uintptr_t), + &riscv_irqdomain_ops, + data); + WARN_ON(!data->domain); + printk(KERN_INFO "%s: %d local interrupts mapped\n", + data->name, 8*(int)sizeof(uintptr_t)); + return 0; +} + +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); -- 2.13.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com> To: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>, olof@lixom.net Cc: albert@sifive.com, patches@groups.riscv.org, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Date: Tue, 6 Jun 2017 16:00:01 -0700 [thread overview] Message-ID: <20170606230007.19101-12-palmer@dabbelt.com> (raw) In-Reply-To: <20170606230007.19101-1-palmer@dabbelt.com> This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform level interrupt controller). Per-hart local interrupt controllers are found on all RISC-V systems. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> --- drivers/irqchip/Kconfig | 14 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 239 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-intc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 2906d63934ef..dfde170e5886 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -313,3 +313,17 @@ config RISCV_PLIC interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC. If you don't know what to do here, say Y. + +config RISCV_INTC + def_bool y if RISCV + #bool "RISC-V Interrupt Controller" + depends on RISCV + default y + help + This enables support for the local interrupt controller found in + standard RISC-V systems. The local interrupt controller handles + timer interrupts, software interrupts, and hardware interrupts. + Without a local interrupt controller the system will be unable to + handle any interrupts, including those passed via the PLIC. + + If you don't know what to do here, say Y. diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index bed94cc89146..bc9a6b45903b 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_RISCV_PLIC) += irq-riscv-plic.o +obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c new file mode 100644 index 000000000000..8150a035aada --- /dev/null +++ b/drivers/irqchip/irq-riscv-intc.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> +#include <linux/interrupt.h> +#include <linux/ftrace.h> +#include <linux/of.h> +#include <linux/seq_file.h> + +#include <asm/ptrace.h> +#include <asm/sbi.h> +#include <asm/smp.h> + +struct riscv_irq_data { + struct irq_chip chip; + struct irq_domain *domain; + int hart; + char name[20]; +}; +DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data); +DEFINE_PER_CPU(atomic_long_t, riscv_early_sie); + +static void riscv_software_interrupt(void) +{ +#ifdef CONFIG_SMP + irqreturn_t ret; + + ret = handle_ipi(); + if (ret != IRQ_NONE) + return; +#endif + + BUG(); +} + +asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs) +{ + struct pt_regs *old_regs = set_irq_regs(regs); + struct irq_domain *domain; + + irq_enter(); + + /* There are three classes of interrupt: timer, software, and + * external devices. We dispatch between them here. External + * device interrupts use the generic IRQ mechanisms. + */ + switch (cause) { + case INTERRUPT_CAUSE_TIMER: + riscv_timer_interrupt(); + break; + case INTERRUPT_CAUSE_SOFTWARE: + riscv_software_interrupt(); + break; + default: + domain = per_cpu(riscv_irq_data, smp_processor_id()).domain; + generic_handle_irq(irq_find_mapping(domain, cause)); + break; + } + + irq_exit(); + set_irq_regs(old_regs); +} + +static int riscv_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct riscv_irq_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &data->chip, handle_simple_irq); + irq_set_chip_data(irq, data); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops riscv_irqdomain_ops = { + .map = riscv_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +static void riscv_irq_mask(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + BUG_ON(smp_processor_id() != data->hart); + csr_clear(sie, 1 << (long)d->hwirq); +} + +static void riscv_irq_unmask(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + BUG_ON(smp_processor_id() != data->hart); + csr_set(sie, 1 << (long)d->hwirq); +} + +static void riscv_irq_enable_helper(void *d) +{ + riscv_irq_unmask(d); +} + +static void riscv_irq_enable(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + /* There are two phases to setting up an interrupt: first we set a bit + * in this bookkeeping structure, which is used by trap_init to + * initialize SIE for each hart as it comes up. + */ + atomic_long_or((1 << (long)d->hwirq), + &per_cpu(riscv_early_sie, data->hart)); + + /* The CPU is usually online, so here we just attempt to enable the + * interrupt by writing SIE directly. We need to write SIE on the + * correct hart, which might be another hart. + */ + if (data->hart == smp_processor_id()) + riscv_irq_unmask(d); + else if (cpu_online(data->hart)) + smp_call_function_single(data->hart, + riscv_irq_enable_helper, + d, + true); +} + +static void riscv_irq_disable_helper(void *d) +{ + riscv_irq_mask(d); +} + +static void riscv_irq_disable(struct irq_data *d) +{ + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d); + + /* This is the mirror of riscv_irq_enable. */ + atomic_long_and(~(1 << (long)d->hwirq), + &per_cpu(riscv_early_sie, data->hart)); + if (data->hart == smp_processor_id()) + riscv_irq_mask(d); + else if (cpu_online(data->hart)) + smp_call_function_single(data->hart, + riscv_irq_disable_helper, + d, + true); +} + +static void riscv_irq_mask_noop(struct irq_data *d) { } + +static void riscv_irq_unmask_noop(struct irq_data *d) { } + +static void riscv_irq_enable_noop(struct irq_data *d) +{ + struct device_node *data = irq_data_get_irq_chip_data(d); + u32 hart; + + if (!of_property_read_u32(data, "reg", &hart)) + printk( + KERN_WARNING "enabled interrupt %d for missing hart %d (this interrupt has no handler)\n", + (int)d->hwirq, hart); +} + +static struct irq_chip riscv_noop_chip = { + .name = "riscv,cpu-intc,noop", + .irq_mask = riscv_irq_mask_noop, + .irq_unmask = riscv_irq_unmask_noop, + .irq_enable = riscv_irq_enable_noop, +}; + +static int riscv_irqdomain_map_noop(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct device_node *data = d->host_data; + + irq_set_chip_and_handler(irq, &riscv_noop_chip, handle_simple_irq); + irq_set_chip_data(irq, data); + return 0; +} + +static const struct irq_domain_ops riscv_irqdomain_ops_noop = { + .map = riscv_irqdomain_map_noop, + .xlate = irq_domain_xlate_onecell, +}; + +static int riscv_intc_init(struct device_node *node, struct device_node *parent) +{ + int hart; + struct riscv_irq_data *data; + + if (parent) + return 0; + + hart = riscv_of_processor_hart(node->parent); + if (hart < 0) { + /* If a hart is disabled, create a no-op irq domain. Devices + * may still have interrupts connected to those harts. This is + * not wrong... unless they actually load a driver that needs + * it! + */ + irq_domain_add_linear( + node, + 8*sizeof(uintptr_t), + &riscv_irqdomain_ops_noop, + node->parent); + return 0; + } + + data = &per_cpu(riscv_irq_data, hart); + snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart); + data->hart = hart; + data->chip.name = data->name; + data->chip.irq_mask = riscv_irq_mask; + data->chip.irq_unmask = riscv_irq_unmask; + data->chip.irq_enable = riscv_irq_enable; + data->chip.irq_disable = riscv_irq_disable; + data->domain = irq_domain_add_linear( + node, + 8*sizeof(uintptr_t), + &riscv_irqdomain_ops, + data); + WARN_ON(!data->domain); + printk(KERN_INFO "%s: %d local interrupts mapped\n", + data->name, 8*(int)sizeof(uintptr_t)); + return 0; +} + +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); -- 2.13.0
next prev parent reply other threads:[~2017-06-06 23:04 UTC|newest] Thread overview: 281+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-23 0:41 RISC-V Linux Port v1 Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64} Palmer Dabbelt 2017-05-23 11:30 ` Arnd Bergmann 2017-05-27 0:57 ` Palmer Dabbelt 2017-05-29 10:50 ` Arnd Bergmann 2017-06-06 4:56 ` Palmer Dabbelt 2017-06-06 17:39 ` Karsten Merker 2017-06-06 17:57 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt 2017-05-23 1:27 ` Olof Johansson 2017-05-23 1:31 ` Randy Dunlap 2017-05-23 4:49 ` Palmer Dabbelt 2017-05-23 4:49 ` Palmer Dabbelt 2017-05-23 5:16 ` [patches] " Olof Johansson 2017-05-23 21:07 ` Benjamin Herrenschmidt 2017-05-23 5:23 ` Olof Johansson 2017-05-23 15:29 ` Palmer Dabbelt 2017-05-23 10:51 ` Geert Uytterhoeven 2017-05-25 1:59 ` Palmer Dabbelt 2017-05-23 11:46 ` Arnd Bergmann 2017-05-27 0:57 ` Palmer Dabbelt 2017-05-29 11:17 ` Arnd Bergmann 2017-06-06 4:56 ` Palmer Dabbelt 2017-06-06 9:20 ` Arnd Bergmann 2017-06-06 20:38 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 3/7] RISC-V: Device Tree Documentation Palmer Dabbelt 2017-05-23 12:03 ` Arnd Bergmann 2017-05-27 0:57 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 4/7] RISC-V: arch/riscv/include Palmer Dabbelt 2017-05-23 12:55 ` Arnd Bergmann 2017-05-23 21:23 ` Benjamin Herrenschmidt 2017-06-03 2:00 ` Palmer Dabbelt 2017-06-01 0:56 ` Palmer Dabbelt 2017-06-01 9:00 ` Arnd Bergmann 2017-06-06 4:56 ` Palmer Dabbelt 2017-06-06 8:54 ` Arnd Bergmann 2017-06-06 19:07 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt 2017-05-23 10:47 ` Geert Uytterhoeven 2017-05-23 22:07 ` Palmer Dabbelt 2017-05-23 11:19 ` Arnd Bergmann 2017-05-25 1:59 ` Palmer Dabbelt 2017-05-26 9:06 ` Arnd Bergmann 2017-06-06 4:56 ` Palmer Dabbelt 2017-06-06 9:31 ` Arnd Bergmann 2017-06-06 20:53 ` Palmer Dabbelt 2017-06-07 7:35 ` Arnd Bergmann 2017-06-23 23:24 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 6/7] RISC-V: arch/riscv/kernel Palmer Dabbelt 2017-05-23 2:11 ` Olof Johansson 2017-05-25 1:59 ` Palmer Dabbelt 2017-05-25 19:51 ` Arnd Bergmann 2017-06-06 4:56 ` Palmer Dabbelt 2017-06-06 9:03 ` Arnd Bergmann 2017-06-06 20:38 ` Palmer Dabbelt 2017-05-23 13:35 ` Arnd Bergmann 2017-06-02 23:56 ` Palmer Dabbelt 2017-06-06 9:01 ` Arnd Bergmann 2017-06-06 20:37 ` Palmer Dabbelt 2017-05-25 17:05 ` Pavel Machek 2017-06-03 3:32 ` Palmer Dabbelt 2017-05-23 0:41 ` [PATCH 7/7] RISC-V: arch/riscv/mm Palmer Dabbelt 2017-05-23 1:28 ` Randy Dunlap 2017-05-23 2:17 ` Olof Johansson 2017-05-23 3:36 ` Palmer Dabbelt 2017-05-23 1:16 ` RISC-V Linux Port v1 Olof Johansson 2017-05-23 1:25 ` Randy Dunlap 2017-05-23 3:36 ` Palmer Dabbelt 2017-05-23 3:36 ` Palmer Dabbelt 2017-05-23 6:45 ` Tobias Klauser 2017-05-23 15:44 ` Palmer Dabbelt 2017-05-23 2:16 ` Randy Dunlap 2017-05-23 4:49 ` Palmer Dabbelt 2017-06-06 22:59 ` RISC-V Linux Port v2 Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 01/17] drivers: support PCIe in RISCV Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:17 ` Geert Uytterhoeven 2017-06-07 14:25 ` Christoph Hellwig [not found] ` <CAMgXwTjXZ5dsxmJ2FyWhCRWo-3nyvKUDfhfV0nNC+oakF=AEsA@mail.gmail.com> 2017-06-07 17:40 ` Olof Johansson 2017-06-23 21:47 ` [patches] " Palmer Dabbelt 2017-06-23 21:47 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 02/17] pcie-xilinx: add missing 5th legacy interrupt Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:18 ` Geert Uytterhoeven 2017-06-07 9:24 ` Marc Zyngier 2017-06-07 19:03 ` Wesley Terpstra 2017-06-06 22:59 ` [PATCH 03/17] base: fix order of OF initialization Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:07 ` Geert Uytterhoeven 2017-06-07 9:35 ` Mark Rutland 2017-06-07 9:35 ` Mark Rutland 2017-06-07 18:39 ` Wesley Terpstra 2017-06-07 21:10 ` Benjamin Herrenschmidt 2017-06-08 3:49 ` Frank Rowand 2017-06-08 9:05 ` Mark Rutland 2017-06-08 9:05 ` Mark Rutland 2017-06-08 9:05 ` Mark Rutland 2017-06-09 0:37 ` Frank Rowand 2017-06-06 22:59 ` [PATCH 04/17] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:19 ` Geert Uytterhoeven 2017-06-07 9:20 ` Will Deacon 2017-06-06 22:59 ` [PATCH 05/17] MAINTAINERS: Add RISC-V Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 06/17] pci: Add generic pcibios_{fixup_bus,align_resource} Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:19 ` Geert Uytterhoeven 2017-06-07 8:01 ` Arnd Bergmann 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-08 8:12 ` Christoph Hellwig 2017-06-08 8:35 ` Arnd Bergmann 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 07/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 08/17] dts: include documentation for the RISC-V interrupt controllers Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:11 ` Geert Uytterhoeven 2017-06-07 10:13 ` Mark Rutland 2017-06-07 18:57 ` Wesley Terpstra 2017-06-07 19:57 ` Rob Herring 2017-06-07 20:31 ` Wesley Terpstra 2017-06-08 10:52 ` Mark Rutland 2017-06-09 21:46 ` Wesley Terpstra 2017-06-09 21:46 ` Wesley Terpstra 2017-06-09 21:58 ` Wesley Terpstra 2017-06-19 14:30 ` Mark Rutland 2017-06-07 22:27 ` Luis R. Rodriguez 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-06 22:59 ` [PATCH 09/17] clocksource/timer-riscv: New RISC-V Clocksource Palmer Dabbelt 2017-06-06 22:59 ` Palmer Dabbelt 2017-06-07 7:12 ` Geert Uytterhoeven 2017-06-07 7:25 ` Arnd Bergmann 2017-06-23 23:24 ` Palmer Dabbelt 2017-06-23 23:24 ` Palmer Dabbelt 2017-06-07 9:43 ` Marc Zyngier 2017-06-24 2:02 ` Palmer Dabbelt 2017-06-24 2:02 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 10/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-07 7:13 ` Geert Uytterhoeven 2017-06-07 7:55 ` Arnd Bergmann 2017-06-24 0:45 ` Palmer Dabbelt 2017-06-24 0:45 ` Palmer Dabbelt 2017-06-07 10:52 ` Marc Zyngier 2017-06-09 13:47 ` Will Deacon 2017-06-27 1:09 ` Palmer Dabbelt 2017-06-27 1:09 ` Palmer Dabbelt 2017-06-25 20:49 ` Palmer Dabbelt 2017-06-25 20:49 ` Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt [this message] 2017-06-06 23:00 ` [PATCH 11/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt 2017-06-07 7:14 ` Geert Uytterhoeven 2017-06-06 23:00 ` [PATCH 12/17] tty: New RISC-V SBI Console Driver Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-07 7:15 ` Geert Uytterhoeven 2017-06-07 7:58 ` Arnd Bergmann 2017-06-24 0:45 ` Palmer Dabbelt 2017-06-24 0:45 ` Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 13/17] RISC-V: Add include subdirectory Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-07 8:12 ` Arnd Bergmann 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-24 2:01 ` Palmer Dabbelt 2017-06-24 15:42 ` Benjamin Herrenschmidt 2017-06-24 21:32 ` [patches] " Palmer Dabbelt 2017-06-24 21:32 ` Palmer Dabbelt 2017-06-25 3:01 ` Benjamin Herrenschmidt 2017-06-07 11:54 ` Peter Zijlstra 2017-06-07 12:25 ` Peter Zijlstra 2017-06-07 12:06 ` Peter Zijlstra 2017-06-07 12:18 ` Peter Zijlstra 2017-06-07 12:36 ` Peter Zijlstra 2017-06-07 12:58 ` Peter Zijlstra 2017-06-07 13:16 ` Will Deacon 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-27 0:07 ` Daniel Lustig 2017-06-27 8:48 ` Will Deacon 2017-06-07 16:35 ` Peter Zijlstra 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-07 12:42 ` Peter Zijlstra 2017-06-07 13:17 ` Peter Zijlstra 2017-06-09 8:16 ` Peter Zijlstra 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-26 20:07 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 14/17] RISC-V: lib files Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 15/17] RISC-V: Add mm subdirectory Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 16/17] RISC-V: Add kernel subdirectory Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` [PATCH 17/17] RISC-V: Makefile and Kconfig Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-06 23:00 ` Palmer Dabbelt 2017-06-07 9:23 ` RISC-V Linux Port v2 Will Deacon 2017-06-07 21:54 ` Palmer Dabbelt 2017-06-07 21:54 ` Palmer Dabbelt 2017-06-08 10:26 ` Will Deacon 2017-06-08 18:16 ` Palmer Dabbelt 2017-06-08 18:16 ` Palmer Dabbelt 2017-06-28 18:55 ` RISC-V Linux Port v3 Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-29 9:44 ` Geert Uytterhoeven 2017-06-29 9:44 ` Geert Uytterhoeven 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 2/9] RISC-V: Atomic and Locking Code Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 3/9] RISC-V: Generic library routines and assembly Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 23:32 ` James Hogan 2017-06-28 23:32 ` James Hogan 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-29 8:22 ` Tobias Klauser 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-29 8:39 ` Tobias Klauser 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-29 22:52 ` Palmer Dabbelt 2017-06-30 7:57 ` Tobias Klauser 2017-06-28 18:55 ` [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 23:09 ` James Hogan 2017-06-28 23:09 ` James Hogan 2017-06-29 22:11 ` Palmer Dabbelt 2017-06-29 22:11 ` Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 21:49 ` Thomas Gleixner 2017-06-28 21:52 ` Thomas Gleixner 2017-06-29 17:22 ` Palmer Dabbelt 2017-06-29 17:22 ` Palmer Dabbelt 2017-06-28 22:42 ` James Hogan 2017-06-28 22:42 ` James Hogan 2017-06-29 21:42 ` Palmer Dabbelt 2017-06-29 21:42 ` Palmer Dabbelt 2017-07-03 23:06 ` James Hogan 2017-07-03 23:06 ` James Hogan 2017-07-05 16:49 ` Palmer Dabbelt 2017-07-05 16:49 ` Palmer Dabbelt 2017-06-28 18:55 ` [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt 2017-06-28 18:55 ` Palmer Dabbelt 2017-06-28 21:05 ` Karsten Merker 2017-06-28 21:13 ` Palmer Dabbelt 2017-06-28 21:13 ` Palmer Dabbelt 2017-06-28 21:25 ` James Hogan 2017-06-28 21:25 ` James Hogan 2017-06-29 16:29 ` Palmer Dabbelt 2017-06-29 16:29 ` Palmer Dabbelt 2017-06-28 22:54 ` James Hogan 2017-06-28 22:54 ` James Hogan 2017-06-29 22:11 ` Palmer Dabbelt 2017-06-29 22:11 ` Palmer Dabbelt 2017-06-06 22:59 ` RISC-V Linux Port v2 Palmer Dabbelt 2017-06-07 7:29 ` David Howells 2017-06-07 21:54 ` Palmer Dabbelt 2017-06-07 21:54 ` Palmer Dabbelt 2017-06-07 21:54 ` Palmer Dabbelt
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