[PATCHv4 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[PATCHv4 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Drop the change for qcom pcie driver's fixup from 9/9, it seems qcom
pcie controller did not implement the register MISC_CONTROL_1_OFF.

Hou Zhiqiang (9):
  PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init
  PCI: layerscape: move STRFMR1 access out from the DBI write-enable
    bracket
  PCI: layerscape: add class code and multifunction fixups for ls1021a
  PCI: layerscape: refactor the host_init function
  PCI: layerscape: Disable the outbound windows configured by bootloader
  PCI: designware: add accessors for write permission of DBI read-only
    registers
  PCI: layerscape: use accessors to enable/disable DBI RO registers'
    write permission
  PCI: designware: enable write permission before updating DBI RO
    registers
  PCI: dwc: remove the obsolete fixups

 drivers/pci/dwc/pci-layerscape.c       | 90 ++++++++++++++++++----------------
 drivers/pci/dwc/pcie-artpec6.c         |  6 ---
 drivers/pci/dwc/pcie-designware-host.c |  6 +++
 drivers/pci/dwc/pcie-designware.h      | 25 ++++++++++
 4 files changed, 80 insertions(+), 47 deletions(-)

-- 
2.14.1

[PATCHv4 1/9] PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This function has been added to ls1021a host init function, but lost to
add to layerscape common host init, so other platforms still use the
setups from bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 7581490f007c..aebefb42377a 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -165,6 +165,8 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	ls_pcie_drop_msg_tlp(pcie);
 	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 
+	dw_pcie_setup_rc(pp);
+
 	return 0;
 }
 
-- 
2.14.1

[PATCHv4 2/9] PCI: layerscape: move STRFMR1 access out from the DBI write-enable bracket

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The STRFMR1 is not a DBI read-only register, so move it out from the
write-enable bracket.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index aebefb42377a..c16940044ed6 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -162,9 +162,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-	ls_pcie_drop_msg_tlp(pcie);
 	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 
+	ls_pcie_drop_msg_tlp(pcie);
+
 	dw_pcie_setup_rc(pp);
 
 	return 0;
-- 
2.14.1

[PATCHv4 3/9] PCI: layerscape: add class code and multifunction fixups for ls1021a

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The current code depends on these 2 fixups implemented in bootloader,
this patch is to resolve the dependence.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index c16940044ed6..3aa34214643c 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -134,6 +134,11 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
 
 	dw_pcie_setup_rc(pp);
 
+	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	ls_pcie_fix_class(pcie);
+	ls_pcie_clear_multifunction(pcie);
+	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+
 	ls_pcie_drop_msg_tlp(pcie);
 
 	return 0;
-- 
2.14.1

[PATCHv4 4/9] PCI: layerscape: refactor the host_init function

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Make the ls1021a's host_init reuse layerscape platform's common
host_init function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 65 ++++++++++++++++++----------------------
 1 file changed, 29 insertions(+), 36 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 3aa34214643c..57b86a0cd2c8 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -108,42 +108,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
 	return 1;
 }
 
-static int ls1021_pcie_host_init(struct pcie_port *pp)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-	struct ls_pcie *pcie = to_ls_pcie(pci);
-	struct device *dev = pci->dev;
-	u32 index[2];
-	int ret;
-
-	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
-						     "fsl,pcie-scfg");
-	if (IS_ERR(pcie->scfg)) {
-		ret = PTR_ERR(pcie->scfg);
-		dev_err(dev, "No syscfg phandle specified\n");
-		pcie->scfg = NULL;
-		return ret;
-	}
-
-	if (of_property_read_u32_array(dev->of_node,
-				       "fsl,pcie-scfg", index, 2)) {
-		pcie->scfg = NULL;
-		return -EINVAL;
-	}
-	pcie->index = index[1];
-
-	dw_pcie_setup_rc(pp);
-
-	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
-	ls_pcie_fix_class(pcie);
-	ls_pcie_clear_multifunction(pcie);
-	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
-
-	ls_pcie_drop_msg_tlp(pcie);
-
-	return 0;
-}
-
 static int ls_pcie_link_up(struct dw_pcie *pci)
 {
 	struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -176,6 +140,35 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	return 0;
 }
 
+static int ls1021_pcie_host_init(struct pcie_port *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	struct device *dev = pci->dev;
+	u32 index[2];
+	int ret;
+
+	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
+						     "fsl,pcie-scfg");
+	if (IS_ERR(pcie->scfg)) {
+		ret = PTR_ERR(pcie->scfg);
+		dev_err(dev, "No syscfg phandle specified\n");
+		pcie->scfg = NULL;
+		return ret;
+	}
+
+	if (of_property_read_u32_array(dev->of_node,
+				       "fsl,pcie-scfg", index, 2)) {
+		pcie->scfg = NULL;
+		return -EINVAL;
+	}
+	pcie->index = index[1];
+
+	ls_pcie_host_init(pp);
+
+	return 0;
+}
+
 static int ls_pcie_msi_host_init(struct pcie_port *pp,
 				 struct msi_controller *chip)
 {
-- 
2.14.1

[PATCHv4 5/9] PCI: layerscape: Disable the outbound windows configured by bootloader

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disable all the outbound windows to avoid one transaction hitting
multiple outbound windows, because the function dw_pcie_setup_rc
will re-configure the outbound windows which maybe confict with
the bootloader configured.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 57b86a0cd2c8..44a603db217a 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -35,6 +35,8 @@
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
 #define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
 
+#define PCIE_IATU_NUM		6
+
 struct ls_pcie_drvdata {
 	u32 lut_offset;
 	u32 ltssm_shift;
@@ -91,6 +93,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
 }
 
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+	int i;
+
+	for (i = 0; i < PCIE_IATU_NUM; i++)
+		dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+}
+
 static int ls1021_pcie_link_up(struct dw_pcie *pci)
 {
 	u32 state;
@@ -128,6 +138,13 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct ls_pcie *pcie = to_ls_pcie(pci);
 
+	/*
+	 * Disable the outbound windows configured by bootloader to avoid
+	 * one transaction hitting multiple outbound windows and the function
+	 * dw_pcie_setup_rc will re-configure the outbound windows.
+	 */
+	ls_pcie_disable_outbound_atus(pcie);
+
 	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-- 
2.14.1

[PATCHv4 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
---
V4:
 - no change

 drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 7366c8167404..0c5f874345f6 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
+#define PCIE_MISC_CONTROL_1_OFF		0x8BC
+#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
+
 /*
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
 	return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
 }
 
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+	u32 reg;
+	u32 val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dw_pcie_readl_dbi(pci, reg);
+	val |= PCIE_DBI_RO_WR_EN;
+	dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+	u32 reg;
+	u32 val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dw_pcie_readl_dbi(pci, reg);
+	val &= ~PCIE_DBI_RO_WR_EN;
+	dw_pcie_writel_dbi(pci, reg, val);
+}
+
 #ifdef CONFIG_PCIE_DW_HOST
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
-- 
2.14.1

[PATCHv4 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Use the accessors instead accessing the DBI read-only write enable
register directly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
---
V4:
 - no change

 drivers/pci/dwc/pci-layerscape.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 44a603db217a..0c1330fce01d 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -33,7 +33,6 @@
 
 /* PEX Internal Configuration Registers */
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
 
 #define PCIE_IATU_NUM		6
 
@@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	 */
 	ls_pcie_disable_outbound_atus(pcie);
 
-	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_en(pci);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	ls_pcie_drop_msg_tlp(pcie);
 
-- 
2.14.1

[PATCHv4 8/9] PCI: designware: enable write permission before updating DBI RO registers

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The existing fix doesn't actually work because the Class register and
interrupt PIN register are read-only, so it must enable the write
permission before writing the correct value to these registers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
---
V4:
 - no change

 drivers/pci/dwc/pcie-designware-host.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 157621175147..582f5cc3cd96 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -597,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
 
 	/* setup interrupt pins */
+	dw_pcie_dbi_ro_wr_en(pci);
 	val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
 	val &= 0xffff00ff;
 	val |= 0x00000100;
 	dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	/* setup bus numbers */
 	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -637,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
+	/* Enable write permission for the DBI read-only register */
+	dw_pcie_dbi_ro_wr_en(pci);
 	/* program correct class for RC */
 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+	/* Better disable write permission right after the update */
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
-- 
2.14.1

[PATCHv4 9/9] PCI: dwc: remove the obsolete fixups

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Now, the dw_pcie_setup_rc() works well, so remove the obsolete fixups:
Remove the Class field fix code from layerscape pcie driver.
Remove the line to enable write permission of DBI RO register from
artpec6 pcie driver.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - Drop the change for qcom pcie driver's fixup

 drivers/pci/dwc/pci-layerscape.c | 9 ---------
 drivers/pci/dwc/pcie-artpec6.c   | 6 ------
 2 files changed, 15 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 0c1330fce01d..d22ed57dcc6f 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
 	iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
 }
 
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
-	struct dw_pcie *pci = pcie->pci;
-
-	iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
-}
-
 /* Drop MSG TLP except for Vendor MSG */
 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 {
@@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	ls_pcie_disable_outbound_atus(pcie);
 
 	dw_pcie_dbi_ro_wr_en(pci);
-	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
 	dw_pcie_dbi_ro_wr_dis(pci);
 
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5d81f1d884e3..d153491f600f 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
 	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 	usleep_range(100, 200);
 
-	/*
-	 * Enable writing to config regs. This is required as the Synopsys
-	 * driver changes the class code. That register needs DBI write enable.
-	 */
-	dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
-
 	/* setup root complex */
 	dw_pcie_setup_rc(pp);
 
-- 
2.14.1

Re: [PATCHv4 4/9] PCI: layerscape: refactor the host_init function

[Bjorn Helgaas]

On Wed, Aug 23, 2017 at 02:08:51PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Make the ls1021a's host_init reuse layerscape platform's common
> host_init function.

This patch does two things:

  1) Moves ls1021_pcie_host_init() to a different place in the file
  2) Calls ls_pcie_host_init() instead of repeating that code in
     ls1021_pcie_host_init()

Those should be separate patches so they're easier to review.

Or if you don't really need to move ls1021_pcie_host_init() to a different
place, that would be even easier.

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
>  - no change
> 
>  drivers/pci/dwc/pci-layerscape.c | 65 ++++++++++++++++++----------------------
>  1 file changed, 29 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 3aa34214643c..57b86a0cd2c8 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -108,42 +108,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
>  	return 1;
>  }
>  
> -static int ls1021_pcie_host_init(struct pcie_port *pp)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> -	struct ls_pcie *pcie = to_ls_pcie(pci);
> -	struct device *dev = pci->dev;
> -	u32 index[2];
> -	int ret;
> -
> -	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> -						     "fsl,pcie-scfg");
> -	if (IS_ERR(pcie->scfg)) {
> -		ret = PTR_ERR(pcie->scfg);
> -		dev_err(dev, "No syscfg phandle specified\n");
> -		pcie->scfg = NULL;
> -		return ret;
> -	}
> -
> -	if (of_property_read_u32_array(dev->of_node,
> -				       "fsl,pcie-scfg", index, 2)) {
> -		pcie->scfg = NULL;
> -		return -EINVAL;
> -	}
> -	pcie->index = index[1];
> -
> -	dw_pcie_setup_rc(pp);
> -
> -	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> -	ls_pcie_fix_class(pcie);
> -	ls_pcie_clear_multifunction(pcie);
> -	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> -
> -	ls_pcie_drop_msg_tlp(pcie);
> -
> -	return 0;
> -}
> -
>  static int ls_pcie_link_up(struct dw_pcie *pci)
>  {
>  	struct ls_pcie *pcie = to_ls_pcie(pci);
> @@ -176,6 +140,35 @@ static int ls_pcie_host_init(struct pcie_port *pp)
>  	return 0;
>  }
>  
> +static int ls1021_pcie_host_init(struct pcie_port *pp)
> +{
> +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +	struct ls_pcie *pcie = to_ls_pcie(pci);
> +	struct device *dev = pci->dev;
> +	u32 index[2];
> +	int ret;
> +
> +	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> +						     "fsl,pcie-scfg");
> +	if (IS_ERR(pcie->scfg)) {
> +		ret = PTR_ERR(pcie->scfg);
> +		dev_err(dev, "No syscfg phandle specified\n");
> +		pcie->scfg = NULL;
> +		return ret;
> +	}
> +
> +	if (of_property_read_u32_array(dev->of_node,
> +				       "fsl,pcie-scfg", index, 2)) {
> +		pcie->scfg = NULL;
> +		return -EINVAL;
> +	}
> +	pcie->index = index[1];
> +
> +	ls_pcie_host_init(pp);
> +
> +	return 0;
> +}
> +
>  static int ls_pcie_msi_host_init(struct pcie_port *pp,
>  				 struct msi_controller *chip)
>  {
> -- 
> 2.14.1
> 

Re: [PATCHv4 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission

[Bjorn Helgaas]

On Wed, Aug 23, 2017 at 02:08:54PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Use the accessors instead accessing the DBI read-only write enable
> register directly.

This patch and the previous one (that added dw_pcie_dbi_ro_wr_en())
should be squashed together.  That way it's obvious that the new code
here is equivalent to the old code

> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Acked-By: Joao Pinto <jpinto@synopsys.com>
> ---
> V4:
>  - no change
> 
>  drivers/pci/dwc/pci-layerscape.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 44a603db217a..0c1330fce01d 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -33,7 +33,6 @@
>  
>  /* PEX Internal Configuration Registers */
>  #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
> -#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
>  
>  #define PCIE_IATU_NUM		6
>  
> @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
>  	 */
>  	ls_pcie_disable_outbound_atus(pcie);
>  
> -	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> +	dw_pcie_dbi_ro_wr_en(pci);
>  	ls_pcie_fix_class(pcie);
>  	ls_pcie_clear_multifunction(pcie);
> -	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> +	dw_pcie_dbi_ro_wr_dis(pci);
>  
>  	ls_pcie_drop_msg_tlp(pcie);
>  
> -- 
> 2.14.1
> 

Re: [PATCHv4 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[Bjorn Helgaas]

On Wed, Aug 23, 2017 at 02:08:47PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Drop the change for qcom pcie driver's fixup from 9/9, it seems qcom
> pcie controller did not implement the register MISC_CONTROL_1_OFF.
> 
> Hou Zhiqiang (9):
>   PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init
>   PCI: layerscape: move STRFMR1 access out from the DBI write-enable
>     bracket
>   PCI: layerscape: add class code and multifunction fixups for ls1021a
>   PCI: layerscape: refactor the host_init function
>   PCI: layerscape: Disable the outbound windows configured by bootloader
>   PCI: designware: add accessors for write permission of DBI read-only
>     registers
>   PCI: layerscape: use accessors to enable/disable DBI RO registers'
>     write permission
>   PCI: designware: enable write permission before updating DBI RO
>     registers
>   PCI: dwc: remove the obsolete fixups
> 
>  drivers/pci/dwc/pci-layerscape.c       | 90 ++++++++++++++++++----------------
>  drivers/pci/dwc/pcie-artpec6.c         |  6 ---
>  drivers/pci/dwc/pcie-designware-host.c |  6 +++
>  drivers/pci/dwc/pcie-designware.h      | 25 ++++++++++
>  4 files changed, 80 insertions(+), 47 deletions(-)

I had a couple minor comments on these, but mostly looks very nice.

I'll be looking for an ack from Minghuan, Mingkai, or Roy for all the
layerscape changes.  And from Niklas or Jesper for the artpec6 ones.

Thanks, Joao, for already looking at all the designware stuff!

Re: [PATCHv4 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[Roy Zang]

On 08/24/2017 12:17 PM, Bjorn Helgaas wrote:=0A=
> On Wed, Aug 23, 2017 at 02:08:47PM +0800, Zhiqiang Hou wrote:=0A=
>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>=0A=
>>=0A=
>> Drop the change for qcom pcie driver's fixup from 9/9, it seems qcom=0A=
>> pcie controller did not implement the register MISC_CONTROL_1_OFF.=0A=
>>=0A=
>> Hou Zhiqiang (9):=0A=
>>   PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init=0A=
>>   PCI: layerscape: move STRFMR1 access out from the DBI write-enable=0A=
>>     bracket=0A=
>>   PCI: layerscape: add class code and multifunction fixups for ls1021a=
=0A=
>>   PCI: layerscape: refactor the host_init function=0A=
>>   PCI: layerscape: Disable the outbound windows configured by bootloader=
=0A=
>>   PCI: designware: add accessors for write permission of DBI read-only=
=0A=
>>     registers=0A=
>>   PCI: layerscape: use accessors to enable/disable DBI RO registers'=0A=
>>     write permission=0A=
>>   PCI: designware: enable write permission before updating DBI RO=0A=
>>     registers=0A=
>>   PCI: dwc: remove the obsolete fixups=0A=
>>=0A=
>>  drivers/pci/dwc/pci-layerscape.c       | 90 ++++++++++++++++++---------=
-------=0A=
>>  drivers/pci/dwc/pcie-artpec6.c         |  6 ---=0A=
>>  drivers/pci/dwc/pcie-designware-host.c |  6 +++=0A=
>>  drivers/pci/dwc/pcie-designware.h      | 25 ++++++++++=0A=
>>  4 files changed, 80 insertions(+), 47 deletions(-)=0A=
> I had a couple minor comments on these, but mostly looks very nice.=0A=
>=0A=
> I'll be looking for an ack from Minghuan, Mingkai, or Roy for all the=0A=
> layerscape changes.  And from Niklas or Jesper for the artpec6 ones.=0A=
>=0A=
> Thanks, Joao, for already looking at all the designware stuff!=0A=
>=0A=
Bjorn,=0A=
=0A=
thanks.=0A=
=0A=
 Acked-by: Roy Zang <tie-fei.zang@freescale.com>=0A=
=0A=
Roy=0A=
=0A=
=0A=
=0A=

RE: [PATCHv4 4/9] PCI: layerscape: refactor the host_init function

[Z.q. Hou]

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RE: [PATCHv4 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission

[Z.q. Hou]

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Re: [PATCHv4 4/9] PCI: layerscape: refactor the host_init function

[Bjorn Helgaas]

On Fri, Aug 25, 2017 at 03:16:36AM +0000, Z.q. Hou wrote:
> Hi Bjorn,
> 
> Thanks a lot for your comments!
> 
> > -----Original Message-----
> > From: Bjorn Helgaas [mailto:helgaas@kernel.org]
> > Sent: 2017年8月25日 1:12
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: linux-pci@vger.kernel.org; bhelgaas@google.com;
> > jingoohan1@gmail.com; Joao.Pinto@synopsys.com; M.h. Lian
> > <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang
> > <roy.zang@nxp.com>; svarbanov@mm-sol.com; niklas.cassel@axis.com;
> > jesper.nilsson@axis.com
> > Subject: Re: [PATCHv4 4/9] PCI: layerscape: refactor the host_init function
> > 
> > On Wed, Aug 23, 2017 at 02:08:51PM +0800, Zhiqiang Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Make the ls1021a's host_init reuse layerscape platform's common
> > > host_init function.
> > 
> > This patch does two things:
> > 
> >   1) Moves ls1021_pcie_host_init() to a different place in the file
> >   2) Calls ls_pcie_host_init() instead of repeating that code in
> >      ls1021_pcie_host_init()
> > 
> > Those should be separate patches so they're easier to review.
> > 
> > Or if you don't really need to move ls1021_pcie_host_init() to a different place,
> > that would be even easier.
> 
> Moved ls1021_pcie_host_init() to this place behand the func ls_pcie_host_init is to call ls_pcie_host_init without adding a declaration of it. Is it necessary to separate it?

Yes, please.  I want to see one patch that *only* moves the function
(and mentions why you're moving it) and another that *only* calls
ls_pcie_host_init() instead of repeating that code in
ls1021_pcie_host_init().  That way, both patches are trivial to
review.  The combined one is not trivial to review.

> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > > V4:
> > >  - no change
> > >
> > >  drivers/pci/dwc/pci-layerscape.c | 65
> > > ++++++++++++++++++----------------------
> > >  1 file changed, 29 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/drivers/pci/dwc/pci-layerscape.c
> > > b/drivers/pci/dwc/pci-layerscape.c
> > > index 3aa34214643c..57b86a0cd2c8 100644
> > > --- a/drivers/pci/dwc/pci-layerscape.c
> > > +++ b/drivers/pci/dwc/pci-layerscape.c
> > > @@ -108,42 +108,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
> > >  	return 1;
> > >  }
> > >
> > > -static int ls1021_pcie_host_init(struct pcie_port *pp) -{
> > > -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > -	struct ls_pcie *pcie = to_ls_pcie(pci);
> > > -	struct device *dev = pci->dev;
> > > -	u32 index[2];
> > > -	int ret;
> > > -
> > > -	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> > > -						     "fsl,pcie-scfg");
> > > -	if (IS_ERR(pcie->scfg)) {
> > > -		ret = PTR_ERR(pcie->scfg);
> > > -		dev_err(dev, "No syscfg phandle specified\n");
> > > -		pcie->scfg = NULL;
> > > -		return ret;
> > > -	}
> > > -
> > > -	if (of_property_read_u32_array(dev->of_node,
> > > -				       "fsl,pcie-scfg", index, 2)) {
> > > -		pcie->scfg = NULL;
> > > -		return -EINVAL;
> > > -	}
> > > -	pcie->index = index[1];
> > > -
> > > -	dw_pcie_setup_rc(pp);
> > > -
> > > -	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> > > -	ls_pcie_fix_class(pcie);
> > > -	ls_pcie_clear_multifunction(pcie);
> > > -	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> > > -
> > > -	ls_pcie_drop_msg_tlp(pcie);
> > > -
> > > -	return 0;
> > > -}
> > > -
> > >  static int ls_pcie_link_up(struct dw_pcie *pci)  {
> > >  	struct ls_pcie *pcie = to_ls_pcie(pci); @@ -176,6 +140,35 @@ static
> > > int ls_pcie_host_init(struct pcie_port *pp)
> > >  	return 0;
> > >  }
> > >
> > > +static int ls1021_pcie_host_init(struct pcie_port *pp) {
> > > +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > +	struct ls_pcie *pcie = to_ls_pcie(pci);
> > > +	struct device *dev = pci->dev;
> > > +	u32 index[2];
> > > +	int ret;
> > > +
> > > +	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> > > +						     "fsl,pcie-scfg");
> > > +	if (IS_ERR(pcie->scfg)) {
> > > +		ret = PTR_ERR(pcie->scfg);
> > > +		dev_err(dev, "No syscfg phandle specified\n");
> > > +		pcie->scfg = NULL;
> > > +		return ret;
> > > +	}
> > > +
> > > +	if (of_property_read_u32_array(dev->of_node,
> > > +				       "fsl,pcie-scfg", index, 2)) {
> > > +		pcie->scfg = NULL;
> > > +		return -EINVAL;
> > > +	}
> > > +	pcie->index = index[1];
> > > +
> > > +	ls_pcie_host_init(pp);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static int ls_pcie_msi_host_init(struct pcie_port *pp,
> > >  				 struct msi_controller *chip)
> > >  {
> > > --
> > > 2.14.1
> > >
> 
> Thanks,
> Zhiqiang
> 

RE: [PATCHv4 4/9] PCI: layerscape: refactor the host_init function

[Z.q. Hou]

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