From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: <dianders@chromium.org>, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, <jeffy.chen@rock-chips.com>, Marc Zyngier <marc.zyngier@arm.com>, <linux-kernel@vger.kernel.org>, <linux-mips@linux-mips.org>, <tfiga@chromium.org>, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Date: Thu, 7 Sep 2017 16:25:41 -0700 [thread overview] Message-ID: <20170907232542.20589-9-paul.burton@imgtec.com> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> The MIPS timer, fast debug channel (FDC) & performance counter overflow interrupts are all really percpu interrupts. However up until now the users of these interrupt haven't used the percpu interrupt APIs to configure & control them; instead using the regular non-percpu APIs such as request_irq(), enable_irq() etc. This has required hacks elsewhere, and generally does not fit well with the fact that the interrupts are actually percpu. The users of these interrupts are now prepared for them to be used with the percpu interrupt APIs, so set them up as percpu_devid interrupts in order to allow these users to begin using the percpu interrupt APIs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 66f97fde13d8..8f7de01f6f35 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -166,7 +166,14 @@ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, if (cpu_has_vint) set_vi_handler(hw, plat_irq_dispatch); - irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + if ((irq == cp0_compare_irq) || + (irq == cp0_fdc_irq) || + (irq == cp0_perfcount_irq)) { + irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq); + irq_set_percpu_devid(irq); + } else { + irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + } return 0; } -- 2.14.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: dianders@chromium.org, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, jeffy.chen@rock-chips.com, Marc Zyngier <marc.zyngier@arm.com>, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, tfiga@chromium.org, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Date: Thu, 7 Sep 2017 16:25:41 -0700 [thread overview] Message-ID: <20170907232542.20589-9-paul.burton@imgtec.com> (raw) Message-ID: <20170907232541.Bqd85clgV54l0H2wZdl-T3kDcl0WF3D6LEapfAk5z4M@z> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> The MIPS timer, fast debug channel (FDC) & performance counter overflow interrupts are all really percpu interrupts. However up until now the users of these interrupt haven't used the percpu interrupt APIs to configure & control them; instead using the regular non-percpu APIs such as request_irq(), enable_irq() etc. This has required hacks elsewhere, and generally does not fit well with the fact that the interrupts are actually percpu. The users of these interrupts are now prepared for them to be used with the percpu interrupt APIs, so set them up as percpu_devid interrupts in order to allow these users to begin using the percpu interrupt APIs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 66f97fde13d8..8f7de01f6f35 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -166,7 +166,14 @@ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, if (cpu_has_vint) set_vi_handler(hw, plat_irq_dispatch); - irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + if ((irq == cp0_compare_irq) || + (irq == cp0_fdc_irq) || + (irq == cp0_perfcount_irq)) { + irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq); + irq_set_percpu_devid(irq); + } else { + irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + } return 0; } -- 2.14.1
next prev parent reply other threads:[~2017-09-07 23:28 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-31 9:58 [patch 0/2] genirq: Handle NOAUTOEN interrupts correctly Thomas Gleixner 2017-05-31 9:58 ` [patch 1/2] genirq: Handle NOAUTOEN interrupt setup proper Thomas Gleixner 2017-05-31 13:54 ` Marc Zyngier 2017-05-31 15:18 ` Thomas Gleixner 2017-06-04 12:47 ` [tip:irq/core] " tip-bot for Thomas Gleixner 2017-05-31 9:58 ` [patch 2/2] genirq: Warn when IRQ_NOAUTOEN is used with shared interrupts Thomas Gleixner 2017-06-04 12:48 ` [tip:irq/core] " tip-bot for Thomas Gleixner 2017-09-06 6:00 ` [2/2] " Paul Burton 2017-09-06 8:16 ` Thomas Gleixner 2017-09-06 14:01 ` Paul Burton 2017-09-06 14:14 ` Thomas Gleixner 2017-09-07 1:18 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 0/9] Support shared percpu interrupts; clean up MIPS hacks Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 1/9] genirq: Allow shared interrupt users to opt into IRQ_NOAUTOEN Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 2/9] genirq: Support shared per_cpu_devid interrupts Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-25 21:06 ` Thomas Gleixner 2017-09-26 12:00 ` Thomas Gleixner 2017-10-19 14:08 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 3/9] genirq: Introduce irq_is_percpu_devid() Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 4/9] MIPS: Remove perf_irq interrupt sharing fallback Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 5/9] MIPS: Remove perf_irq Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 6/9] MIPS: perf: percpu_devid interrupt support Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-10-19 14:12 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 7/9] MIPS: cevt-r4k: " Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` Paul Burton [this message] 2017-09-07 23:25 ` [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 9/9] irqchip: mips-gic: Remove gic_all_vpes_local_irq_controller Paul Burton 2017-09-07 23:25 ` Paul Burton
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