From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH v2 3/8] drm/i915: Use cdclk_state->voltage on VLV/CHV
Date: Thu, 19 Oct 2017 20:43:29 +0300 [thread overview]
Message-ID: <20171019174329.30912-1-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20171018204825.2500-4-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Store the punit DSPFREQUAR value into cdclk_state->voltage on
VLV/CHV. Since we can actually read that out from the hardware
this can give us a bit more cross checking between the hardware
and software state.
v2: Don't break waiting for cdclk change on VLV/CHV
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 66 +++++++++++++++++++++++++++++---------
1 file changed, 50 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 522222f8bb50..9cc4374797eb 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -437,13 +437,45 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
return 200000;
}
+static u8 vlv_calc_voltage(struct drm_i915_private *dev_priv, int cdclk)
+{
+ if (IS_VALLEYVIEW(dev_priv)) {
+ if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
+ return 2;
+ else if (cdclk >= 266667)
+ return 1;
+ else
+ return 0;
+ } else {
+ /*
+ * Specs are full of misinformation, but testing on actual
+ * hardware has shown that we just need to write the desired
+ * CCK divider into the Punit register.
+ */
+ return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+ }
+}
+
static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state)
{
+ u32 val;
+
cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_state->vco);
+
+ mutex_lock(&dev_priv->pcu_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+ mutex_unlock(&dev_priv->pcu_lock);
+
+ if (IS_VALLEYVIEW(dev_priv))
+ cdclk_state->voltage = (val & DSPFREQGUAR_MASK) >>
+ DSPFREQGUAR_SHIFT;
+ else
+ cdclk_state->voltage = (val & DSPFREQGUAR_MASK_CHV) >>
+ DSPFREQGUAR_SHIFT_CHV;
}
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
@@ -486,7 +518,19 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- u32 val, cmd;
+ u32 val, cmd = cdclk_state->voltage;
+
+ switch (cdclk) {
+ case 400000:
+ case 333333:
+ case 320000:
+ case 266667:
+ case 200000:
+ break;
+ default:
+ MISSING_CASE(cdclk);
+ return;
+ }
/* There are cases where we can end up here with power domains
* off and a CDCLK frequency other than the minimum, like when
@@ -496,13 +540,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
- cmd = 2;
- else if (cdclk == 266667)
- cmd = 1;
- else
- cmd = 0;
-
mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK;
@@ -562,7 +599,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state)
{
int cdclk = cdclk_state->cdclk;
- u32 val, cmd;
+ u32 val, cmd = cdclk_state->voltage;
switch (cdclk) {
case 333333:
@@ -583,13 +620,6 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- /*
- * Specs are full of misinformation, but testing on actual
- * hardware has shown that we just need to write the desired
- * CCK divider into the Punit register.
- */
- cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
-
mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
val &= ~DSPFREQGUAR_MASK_CHV;
@@ -1859,11 +1889,15 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage =
+ vlv_calc_voltage(dev_priv, cdclk);
if (!intel_state->active_crtcs) {
cdclk = vlv_calc_cdclk(dev_priv, 0);
intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage =
+ vlv_calc_voltage(dev_priv, cdclk);
} else {
intel_state->cdclk.actual =
intel_state->cdclk.logical;
--
2.13.6
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next prev parent reply other threads:[~2017-10-19 17:43 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-18 20:48 [PATCH 0/8] drm/i915: CNL DVFS thing Ville Syrjala
2017-10-18 20:48 ` [PATCH 1/8] drm/i915: Clean up some cdclk switch statements Ville Syrjala
2017-10-19 7:20 ` Mika Kahola
2017-10-18 20:48 ` [PATCH 2/8] drm/i915: Start tracking voltage level in the cdclk state Ville Syrjala
2017-10-19 23:32 ` Rodrigo Vivi
2017-10-20 14:01 ` Ville Syrjälä
2017-10-20 20:43 ` Rodrigo Vivi
2017-10-23 12:13 ` Ville Syrjälä
2017-10-23 17:14 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 3/8] drm/i915: USe cdclk_state->voltage on VLV/CHV Ville Syrjala
2017-10-19 17:43 ` Ville Syrjala [this message]
2017-10-19 23:42 ` [PATCH v2 3/8] drm/i915: Use " Rodrigo Vivi
2017-10-20 16:20 ` Ville Syrjälä
2017-10-20 17:03 ` [PATCH v3 " Ville Syrjala
2017-10-18 20:48 ` [PATCH 4/8] drm/i915: Use cdclk_state->voltage on BDW Ville Syrjala
2017-10-19 23:44 ` Rodrigo Vivi
2017-10-20 16:14 ` Ville Syrjälä
2017-10-20 17:03 ` [PATCH v2 " Ville Syrjala
2017-10-20 20:47 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 5/8] drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL Ville Syrjala
2017-10-19 23:47 ` Rodrigo Vivi
2017-10-20 11:18 ` Ville Syrjälä
2017-10-20 20:45 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 6/8] drm/i915: Use cdclk_state->voltage on BXT/GLK Ville Syrjala
2017-10-20 20:51 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 7/8] drm/i915: Use cdclk_state->voltage on CNL Ville Syrjala
2017-10-18 21:50 ` Rodrigo Vivi
2017-10-18 22:43 ` Rodrigo Vivi
2017-10-19 10:48 ` Ville Syrjälä
2017-10-19 10:56 ` Mika Kahola
2017-10-19 12:19 ` Ville Syrjälä
2017-10-19 23:52 ` Rodrigo Vivi
2017-10-23 18:29 ` Rodrigo Vivi
2017-10-18 20:48 ` [PATCH 8/8] drm/i915: Adjust system agent voltage on CNL if required by DDI ports Ville Syrjala
2017-10-19 23:54 ` Rodrigo Vivi
2017-10-20 11:11 ` Ville Syrjälä
2017-10-20 17:48 ` Runyan, Arthur J
2017-10-20 20:07 ` Ville Syrjälä
2017-10-20 20:36 ` Rodrigo Vivi
2017-10-20 21:44 ` Runyan, Arthur J
2017-10-23 12:03 ` Ville Syrjälä
2017-10-23 11:48 ` Ville Syrjälä
2017-10-20 14:18 ` Ville Syrjälä
2017-10-20 16:11 ` Ville Syrjälä
2017-10-20 16:09 ` [PATCH v2 " Ville Syrjala
2017-10-20 16:52 ` Ville Syrjälä
2017-10-20 17:05 ` [PATCH v3 " Ville Syrjala
2017-10-23 18:39 ` Rodrigo Vivi
2017-10-18 21:07 ` ✗ Fi.CI.BAT: warning for drm/i915: CNL DVFS thing Patchwork
2017-10-19 17:31 ` Ville Syrjälä
2017-10-19 18:17 ` ✗ Fi.CI.BAT: failure for drm/i915: CNL DVFS thing (rev2) Patchwork
2017-10-19 18:52 ` Patchwork
2017-10-19 20:07 ` ✗ Fi.CI.BAT: warning " Patchwork
2017-10-19 23:27 ` ✓ Fi.CI.BAT: success " Patchwork
2017-10-20 0:22 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-20 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: CNL DVFS thing (rev3) Patchwork
2017-10-20 17:48 ` ✓ Fi.CI.BAT: success for drm/i915: CNL DVFS thing (rev6) Patchwork
2017-10-20 19:19 ` ✓ Fi.CI.IGT: " Patchwork
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