From: Wu Hao <hao.wu@intel.com> To: Alan Tull <atull@kernel.org> Cc: Moritz Fischer <mdf@kernel.org>, linux-fpga@vger.kernel.org, linux-kernel <linux-kernel@vger.kernel.org>, linux-api@vger.kernel.org, "Kang, Luwei" <luwei.kang@intel.com>, "Zhang, Yi Z" <yi.z.zhang@intel.com>, Tim Whisonant <tim.whisonant@intel.com>, Enno Luebbers <enno.luebbers@intel.com>, Shiva Rao <shiva.rao@intel.com>, Christopher Rauer <christopher.rauer@intel.com>, Xiao Guangrong <guangrong.xiao@linux.intel.com> Subject: Re: [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Date: Tue, 13 Feb 2018 11:44:31 +0800 [thread overview] Message-ID: <20180213034431.GB10936@hao-dev> (raw) In-Reply-To: <CANk1AXR2Q4M4c1TOQhR2J_Mz5MjwZWbR0JUXCR5jFVL_kZtcag@mail.gmail.com> On Mon, Feb 12, 2018 at 10:51:44AM -0600, Alan Tull wrote: > On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao <hao.wu@intel.com> wrote: > > From: Kang Luwei <luwei.kang@intel.com> > > > > The header register set is always present for FPGA Management Engine (FME), > > this patch implements init and uinit function for header sub feature and > > introduce several read-only sysfs interfaces for the capability and status. > > > > Sysfs interfaces: > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/ports_num > > Read-only. Number of ports implemented > > > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/bitstream_id > > Read-only. Blue Bitstream (static FPGA region) identifier number > > > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/bitstream_metadata > > Read-only. Blue Bitstream (static FPGA region) meta data > > Please document the meta data. I don't see anywhere that describes it > or how it differs from the bitstream_id. So it could be useful to > document it in this header a bit, and in the code, in the sysfs > document, and in the Documentation/fpga so that people don't have to > go hunting. Hi Alan Thanks a lot for the review. The Blue Bitstream (static FPGA region) meta data contains information like synthesis date and seed. The Blue Bitstream (static FPGA region) id contains version information like major, minor, patch number (e.g version 6.4.0)and etc. I used bitstream_id a lot, but bitstream_metadata is useful in some cases as well. I will add more descriptions for them. Thanks Hao > > We discussed elsewhere the static region bitstream_id verses the other > interface_ids, so that's been discussed. > > Besides that, this patch looks good and straightforward. > > Thanks, > Alan > > > > > Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> > > Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> > > Signed-off-by: Shiva Rao <shiva.rao@intel.com> > > Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> > > Signed-off-by: Kang Luwei <luwei.kang@intel.com> > > Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> > > Signed-off-by: Wu Hao <hao.wu@intel.com> > > ---- > > v2: add sysfs documentation > > v3: rename driver to fpga-dfl-fme. > > improve sysfs doc and commit description. > > replace bitfield. > > --- > > .../ABI/testing/sysfs-platform-fpga-dfl-fme | 21 ++++++++ > > drivers/fpga/dfl-fme-main.c | 60 ++++++++++++++++++++++ > > 2 files changed, 81 insertions(+) > > create mode 100644 Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > > > diff --git a/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > new file mode 100644 > > index 0000000..6b32799 > > --- /dev/null > > +++ b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > @@ -0,0 +1,21 @@ > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/ports_num > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu@intel.com> > > +Description: Read-only. One DFL FPGA device may have more than 1 > > + port/Accelerator Function Unit (AFU). It returns the > > + number of ports on the FPGA device when read it. > > + > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_id > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu@intel.com> > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > > + identifier number. > > + > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_meta > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu@intel.com> > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > > + meta data. > > diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c > > index f7b5f7d..d17c66a 100644 > > --- a/drivers/fpga/dfl-fme-main.c > > +++ b/drivers/fpga/dfl-fme-main.c > > @@ -21,9 +21,68 @@ > > > > #include "fpga-dfl.h" > > > > +static ssize_t ports_num_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_CAP); > > + > > + return scnprintf(buf, PAGE_SIZE, "%u\n", > > + (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v)); > > +} > > +static DEVICE_ATTR_RO(ports_num); > > + > > +static ssize_t bitstream_id_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_BITSTREAM_ID); > > + > > + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); > > +} > > +static DEVICE_ATTR_RO(bitstream_id); > > + > > +static ssize_t bitstream_metadata_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_BITSTREAM_MD); > > + > > + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); > > +} > > +static DEVICE_ATTR_RO(bitstream_metadata); > > + > > +static const struct attribute *fme_hdr_attrs[] = { > > + &dev_attr_ports_num.attr, > > + &dev_attr_bitstream_id.attr, > > + &dev_attr_bitstream_metadata.attr, > > + NULL, > > +}; > > + > > static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) > > { > > + void __iomem *base = feature->ioaddr; > > + int ret; > > + > > dev_dbg(&pdev->dev, "FME HDR Init.\n"); > > + dev_dbg(&pdev->dev, "FME cap %llx.\n", > > + (unsigned long long)readq(base + FME_HDR_CAP)); > > + > > + ret = sysfs_create_files(&pdev->dev.kobj, fme_hdr_attrs); > > + if (ret) > > + return ret; > > > > return 0; > > } > > @@ -31,6 +90,7 @@ static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) > > static void fme_hdr_uinit(struct platform_device *pdev, struct feature *feature) > > { > > dev_dbg(&pdev->dev, "FME HDR UInit.\n"); > > + sysfs_remove_files(&pdev->dev.kobj, fme_hdr_attrs); > > } > > > > static const struct feature_ops fme_hdr_ops = { > > -- > > 1.8.3.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> To: Alan Tull <atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Cc: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "Kang, Luwei" <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Zhang, Yi Z" <yi.z.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Tim Whisonant <tim.whisonant-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Enno Luebbers <enno.luebbers-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Shiva Rao <shiva.rao-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Christopher Rauer <christopher.rauer-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Subject: Re: [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Date: Tue, 13 Feb 2018 11:44:31 +0800 [thread overview] Message-ID: <20180213034431.GB10936@hao-dev> (raw) In-Reply-To: <CANk1AXR2Q4M4c1TOQhR2J_Mz5MjwZWbR0JUXCR5jFVL_kZtcag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> On Mon, Feb 12, 2018 at 10:51:44AM -0600, Alan Tull wrote: > On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> wrote: > > From: Kang Luwei <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > > > The header register set is always present for FPGA Management Engine (FME), > > this patch implements init and uinit function for header sub feature and > > introduce several read-only sysfs interfaces for the capability and status. > > > > Sysfs interfaces: > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/ports_num > > Read-only. Number of ports implemented > > > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/bitstream_id > > Read-only. Blue Bitstream (static FPGA region) identifier number > > > > * /sys/class/fpga_region/<regionX>/<fpga-dfl-fme.x>/bitstream_metadata > > Read-only. Blue Bitstream (static FPGA region) meta data > > Please document the meta data. I don't see anywhere that describes it > or how it differs from the bitstream_id. So it could be useful to > document it in this header a bit, and in the code, in the sysfs > document, and in the Documentation/fpga so that people don't have to > go hunting. Hi Alan Thanks a lot for the review. The Blue Bitstream (static FPGA region) meta data contains information like synthesis date and seed. The Blue Bitstream (static FPGA region) id contains version information like major, minor, patch number (e.g version 6.4.0)and etc. I used bitstream_id a lot, but bitstream_metadata is useful in some cases as well. I will add more descriptions for them. Thanks Hao > > We discussed elsewhere the static region bitstream_id verses the other > interface_ids, so that's been discussed. > > Besides that, this patch looks good and straightforward. > > Thanks, > Alan > > > > > Signed-off-by: Tim Whisonant <tim.whisonant-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > Signed-off-by: Enno Luebbers <enno.luebbers-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > Signed-off-by: Shiva Rao <shiva.rao-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > Signed-off-by: Christopher Rauer <christopher.rauer-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > Signed-off-by: Kang Luwei <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > Signed-off-by: Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> > > Signed-off-by: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > ---- > > v2: add sysfs documentation > > v3: rename driver to fpga-dfl-fme. > > improve sysfs doc and commit description. > > replace bitfield. > > --- > > .../ABI/testing/sysfs-platform-fpga-dfl-fme | 21 ++++++++ > > drivers/fpga/dfl-fme-main.c | 60 ++++++++++++++++++++++ > > 2 files changed, 81 insertions(+) > > create mode 100644 Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > > > diff --git a/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > new file mode 100644 > > index 0000000..6b32799 > > --- /dev/null > > +++ b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme > > @@ -0,0 +1,21 @@ > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/ports_num > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > +Description: Read-only. One DFL FPGA device may have more than 1 > > + port/Accelerator Function Unit (AFU). It returns the > > + number of ports on the FPGA device when read it. > > + > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_id > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > > + identifier number. > > + > > +What: /sys/bus/platform/devices/fpga-dfl-fme.0/bitstream_meta > > +Date: November 2017 > > +KernelVersion: 4.15 > > +Contact: Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> > > +Description: Read-only. It returns Blue Bitstream (static FPGA region) > > + meta data. > > diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c > > index f7b5f7d..d17c66a 100644 > > --- a/drivers/fpga/dfl-fme-main.c > > +++ b/drivers/fpga/dfl-fme-main.c > > @@ -21,9 +21,68 @@ > > > > #include "fpga-dfl.h" > > > > +static ssize_t ports_num_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_CAP); > > + > > + return scnprintf(buf, PAGE_SIZE, "%u\n", > > + (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v)); > > +} > > +static DEVICE_ATTR_RO(ports_num); > > + > > +static ssize_t bitstream_id_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_BITSTREAM_ID); > > + > > + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); > > +} > > +static DEVICE_ATTR_RO(bitstream_id); > > + > > +static ssize_t bitstream_metadata_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + void __iomem *base; > > + u64 v; > > + > > + base = get_feature_ioaddr_by_index(dev, FME_FEATURE_ID_HEADER); > > + > > + v = readq(base + FME_HDR_BITSTREAM_MD); > > + > > + return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v); > > +} > > +static DEVICE_ATTR_RO(bitstream_metadata); > > + > > +static const struct attribute *fme_hdr_attrs[] = { > > + &dev_attr_ports_num.attr, > > + &dev_attr_bitstream_id.attr, > > + &dev_attr_bitstream_metadata.attr, > > + NULL, > > +}; > > + > > static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) > > { > > + void __iomem *base = feature->ioaddr; > > + int ret; > > + > > dev_dbg(&pdev->dev, "FME HDR Init.\n"); > > + dev_dbg(&pdev->dev, "FME cap %llx.\n", > > + (unsigned long long)readq(base + FME_HDR_CAP)); > > + > > + ret = sysfs_create_files(&pdev->dev.kobj, fme_hdr_attrs); > > + if (ret) > > + return ret; > > > > return 0; > > } > > @@ -31,6 +90,7 @@ static int fme_hdr_init(struct platform_device *pdev, struct feature *feature) > > static void fme_hdr_uinit(struct platform_device *pdev, struct feature *feature) > > { > > dev_dbg(&pdev->dev, "FME HDR UInit.\n"); > > + sysfs_remove_files(&pdev->dev.kobj, fme_hdr_attrs); > > } > > > > static const struct feature_ops fme_hdr_ops = { > > -- > > 1.8.3.1 > >
next prev parent reply other threads:[~2018-02-13 3:54 UTC|newest] Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-11-27 6:42 [PATCH v3 00/21] Intel FPGA Device Drivers Wu Hao 2017-11-27 6:42 ` [PATCH v3 01/21] docs: fpga: add a document for Intel FPGA driver overview Wu Hao 2017-11-27 6:42 ` Wu Hao 2017-12-04 19:55 ` Alan Tull 2017-12-05 3:57 ` Wu Hao 2017-12-05 3:57 ` Wu Hao 2017-12-06 10:04 ` David Laight 2017-12-20 22:31 ` Alan Tull 2017-12-20 22:31 ` Alan Tull 2017-12-21 6:02 ` Wu Hao 2017-12-21 6:02 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 02/21] fpga: mgr: add region_id to fpga_image_info Wu Hao 2017-11-29 6:11 ` Moritz Fischer 2017-11-29 6:11 ` Moritz Fischer 2017-12-04 20:26 ` Alan Tull 2017-12-05 3:36 ` Wu Hao 2017-12-05 3:36 ` Wu Hao 2018-01-31 15:35 ` Alan Tull 2018-01-31 15:35 ` Alan Tull 2018-02-01 5:05 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 03/21] fpga: mgr: add status for fpga-manager Wu Hao 2017-12-04 20:55 ` Alan Tull 2017-12-04 20:55 ` Alan Tull 2017-12-05 4:08 ` Wu Hao 2017-12-05 4:08 ` Wu Hao 2017-12-12 18:18 ` Alan Tull 2017-12-13 4:48 ` Wu Hao 2017-12-13 4:48 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 04/21] fpga: add device feature list support Wu Hao 2017-11-27 6:42 ` Wu Hao 2017-11-29 6:07 ` Moritz Fischer 2017-11-29 6:07 ` Moritz Fischer 2017-11-30 5:59 ` Wu Hao 2017-12-20 22:29 ` Alan Tull 2017-12-21 0:58 ` Alan Tull 2017-12-21 7:22 ` Wu Hao 2017-12-21 7:22 ` Wu Hao 2017-12-22 8:45 ` Wu Hao 2018-01-31 23:22 ` Alan Tull 2018-01-31 23:22 ` Alan Tull 2017-11-27 6:42 ` [PATCH v3 05/21] fpga: dfl: add chardev support for feature devices Wu Hao 2017-11-27 6:42 ` [PATCH v3 06/21] fpga: dfl: adds fpga_cdev_find_port Wu Hao 2018-02-05 22:08 ` Alan Tull 2018-02-06 2:37 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 07/21] fpga: dfl: add feature device infrastructure Wu Hao 2017-11-27 6:42 ` [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Wu Hao 2017-11-27 10:28 ` David Laight 2017-11-27 10:28 ` David Laight 2017-11-28 3:15 ` Wu Hao 2017-11-28 3:15 ` Wu Hao 2017-12-04 19:46 ` Alan Tull 2017-12-04 19:46 ` Alan Tull 2017-12-05 3:33 ` Wu Hao 2017-12-05 3:33 ` Wu Hao 2017-12-05 17:00 ` Alan Tull 2017-12-06 5:30 ` Wu Hao 2017-12-06 9:44 ` David Laight 2017-12-06 9:44 ` David Laight 2017-12-06 15:29 ` Alan Tull 2017-12-06 15:29 ` Alan Tull 2017-12-06 16:28 ` David Laight 2017-12-06 16:28 ` David Laight 2017-12-06 16:28 ` David Laight 2017-12-06 22:39 ` Alan Tull 2018-02-01 21:59 ` Alan Tull 2018-02-01 21:59 ` Alan Tull 2018-02-13 9:36 ` Wu Hao 2017-12-06 9:34 ` David Laight 2017-12-06 9:34 ` David Laight 2017-12-07 3:47 ` Wu Hao 2017-12-07 3:47 ` Wu Hao 2017-12-06 9:31 ` David Laight 2017-12-06 9:31 ` David Laight 2017-12-06 9:31 ` David Laight 2017-11-27 6:42 ` [PATCH v3 09/21] fpga: intel-dfl-pci: add enumeration for feature devices Wu Hao 2017-12-07 21:41 ` Alan Tull 2017-12-07 21:41 ` Alan Tull 2017-12-08 9:25 ` Wu Hao 2017-12-08 9:25 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 10/21] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao 2017-11-27 6:42 ` [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Wu Hao 2018-02-12 16:51 ` Alan Tull 2018-02-12 16:51 ` Alan Tull 2018-02-13 3:44 ` Wu Hao [this message] 2018-02-13 3:44 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 12/21] fpga: dfl: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao 2018-01-31 15:31 ` Alan Tull 2018-01-31 15:31 ` Alan Tull 2018-02-01 5:11 ` Wu Hao 2018-02-01 15:11 ` Moritz Fischer 2017-11-27 6:42 ` [PATCH v3 13/21] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao 2017-11-27 6:42 ` [PATCH v3 14/21] fpga: dfl: add fpga manager platform driver for FME Wu Hao 2018-02-01 22:00 ` Alan Tull 2018-02-01 22:00 ` Alan Tull 2018-02-02 9:42 ` Wu Hao 2018-02-03 0:26 ` Luebbers, Enno 2018-02-03 0:26 ` Luebbers, Enno 2018-02-03 10:41 ` Moritz Fischer 2018-02-04 10:05 ` Wu Hao 2018-02-04 10:05 ` Wu Hao 2018-02-05 17:21 ` Alan Tull 2018-02-05 17:21 ` Alan Tull 2018-02-06 2:17 ` Wu Hao 2018-02-06 2:17 ` Wu Hao 2018-02-06 4:25 ` Alan Tull 2018-02-06 5:23 ` Wu Hao 2018-02-06 5:23 ` Wu Hao 2018-02-06 6:44 ` Moritz Fischer 2018-02-06 6:44 ` Moritz Fischer 2018-02-04 9:37 ` Wu Hao 2018-02-04 9:37 ` Wu Hao 2018-02-05 18:36 ` Luebbers, Enno 2018-02-05 18:36 ` Luebbers, Enno 2018-02-06 1:47 ` Wu Hao 2018-02-06 1:47 ` Wu Hao 2018-02-06 4:25 ` Alan Tull 2018-02-06 4:25 ` Alan Tull 2018-02-06 6:47 ` Wu Hao 2018-02-06 6:47 ` Wu Hao 2018-02-06 18:53 ` Alan Tull 2018-02-06 18:53 ` Alan Tull 2018-02-07 4:52 ` Wu Hao 2018-02-07 22:37 ` Alan Tull 2018-02-07 22:37 ` Alan Tull 2017-11-27 6:42 ` [PATCH v3 15/21] fpga: dfl: add fpga bridge " Wu Hao 2018-01-31 15:16 ` Alan Tull 2018-01-31 15:16 ` Alan Tull 2018-02-01 5:15 ` Wu Hao 2018-02-01 15:11 ` Moritz Fischer 2018-02-01 15:11 ` Moritz Fischer 2017-11-27 6:42 ` [PATCH v3 16/21] fpga: dfl: add fpga region " Wu Hao 2018-01-31 20:46 ` Alan Tull 2018-02-01 5:23 ` Wu Hao 2018-02-01 15:13 ` Moritz Fischer 2017-11-27 6:42 ` [PATCH v3 17/21] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao 2017-11-27 6:42 ` [PATCH v3 18/21] fpga: dfl: afu: add header sub feature support Wu Hao 2018-02-12 17:43 ` Alan Tull 2018-02-12 17:43 ` Alan Tull 2018-02-13 3:33 ` Wu Hao 2018-02-13 3:33 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 19/21] fpga: dfl: afu: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao 2018-01-31 14:52 ` Alan Tull 2018-01-31 14:52 ` Alan Tull 2018-02-01 5:16 ` Wu Hao 2018-02-01 15:13 ` Moritz Fischer 2018-02-02 9:08 ` Wu Hao 2018-02-02 9:08 ` Wu Hao 2017-11-27 6:42 ` [PATCH v3 20/21] fpga: dfl: afu: add user afu sub feature support Wu Hao 2017-11-27 6:42 ` [PATCH v3 21/21] fpga: dfl: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao 2017-11-27 21:26 ` [PATCH v3 00/21] Intel FPGA Device Drivers Alan Tull 2017-11-27 21:26 ` Alan Tull
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