* [PATCH v3 0/2] ARM: dts: renesas: Correct mask for GIC PPI interrupts
@ 2018-05-07 13:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Liviu Dudau, linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Hi Simon, Magnus,
R-Car H2 and R-Mobile APE6 contain four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
can be delivered to all 8 processor cores.
This brings the predecessors of R-Car Gen3 in line with what we're doing
on other big.LITTLE SoCs, like R-Car H3 and M3-W.
Changes compared to v2:
- Change one-line summary prefix to match current arm-soc practices,
- Fast-forward by 3 years,
- Rebase.
Changes compared to v1:
- Drop RFC status after receiving confirmation from Liviu Dudau.
Thanks for applying!
P.S. Feel free to take a ride on your unicorn, to test on a legendary
system that boots all 8 cores.
Geert Uytterhoeven (2):
ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 0/2] ARM: dts: renesas: Correct mask for GIC PPI interrupts
@ 2018-05-07 13:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon, Magnus,
R-Car H2 and R-Mobile APE6 contain four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
can be delivered to all 8 processor cores.
This brings the predecessors of R-Car Gen3 in line with what we're doing
on other big.LITTLE SoCs, like R-Car H3 and M3-W.
Changes compared to v2:
- Change one-line summary prefix to match current arm-soc practices,
- Fast-forward by 3 years,
- Rebase.
Changes compared to v1:
- Drop RFC status after receiving confirmation from Liviu Dudau.
Thanks for applying!
P.S. Feel free to take a ride on your unicorn, to test on a legendary
system that boots all 8 cores.
Geert Uytterhoeven (2):
ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
2018-05-07 13:19 ` Geert Uytterhoeven
@ 2018-05-07 13:19 ` Geert Uytterhoeven
-1 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Liviu Dudau, linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
can be delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Change one-line summary prefix to match current arm-soc practices,
- Rebase,
v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.
---
arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index b66a18af28f1659a..47a51cd71434e7d2 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1554,7 +1554,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1810,10 +1810,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] ARM: dts: r8a7790: Correct mask for GIC PPI interrupts
@ 2018-05-07 13:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: linux-arm-kernel
R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
can be delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Change one-line summary prefix to match current arm-soc practices,
- Rebase,
v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.
---
arch/arm/boot/dts/r8a7790.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index b66a18af28f1659a..47a51cd71434e7d2 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1554,7 +1554,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1810,10 +1810,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
2018-05-07 13:19 ` Geert Uytterhoeven
@ 2018-05-07 13:19 ` Geert Uytterhoeven
-1 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: Simon Horman, Magnus Damm
Cc: Liviu Dudau, linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are
delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Change one-line summary prefix to match current arm-soc practices,
- Rebased,
v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.
---
arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 8e48090e4fdc1412..080d037f5733a8c3 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -57,10 +57,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
dbsc1: memory-controller@e6790000 {
@@ -464,7 +464,7 @@
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&pd_c4>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
@ 2018-05-07 13:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-05-07 13:19 UTC (permalink / raw)
To: linux-arm-kernel
R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are
delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
- Change one-line summary prefix to match current arm-soc practices,
- Rebased,
v2:
- Drop RFC status after receiving confirmation from Liviu Dudau.
---
arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 8e48090e4fdc1412..080d037f5733a8c3 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -57,10 +57,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
dbsc1: memory-controller at e6790000 {
@@ -464,7 +464,7 @@
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&pd_c4>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/2] ARM: dts: renesas: Correct mask for GIC PPI interrupts
2018-05-07 13:19 ` Geert Uytterhoeven
@ 2018-05-08 13:35 ` Simon Horman
-1 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2018-05-08 13:35 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Liviu Dudau, linux-renesas-soc, linux-arm-kernel
On Mon, May 07, 2018 at 03:19:51PM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> R-Car H2 and R-Mobile APE6 contain four Cortex-A15 and four Cortex-A7
> cores, hence the second interrupt specifier cell for Private Peripheral
> Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
> can be delivered to all 8 processor cores.
>
> This brings the predecessors of R-Car Gen3 in line with what we're doing
> on other big.LITTLE SoCs, like R-Car H3 and M3-W.
Thanks, applied.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 0/2] ARM: dts: renesas: Correct mask for GIC PPI interrupts
@ 2018-05-08 13:35 ` Simon Horman
0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2018-05-08 13:35 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, May 07, 2018 at 03:19:51PM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> R-Car H2 and R-Mobile APE6 contain four Cortex-A15 and four Cortex-A7
> cores, hence the second interrupt specifier cell for Private Peripheral
> Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
> can be delivered to all 8 processor cores.
>
> This brings the predecessors of R-Car Gen3 in line with what we're doing
> on other big.LITTLE SoCs, like R-Car H3 and M3-W.
Thanks, applied.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-05-08 13:35 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-07 13:19 [PATCH v3 0/2] ARM: dts: renesas: Correct mask for GIC PPI interrupts Geert Uytterhoeven
2018-05-07 13:19 ` Geert Uytterhoeven
2018-05-07 13:19 ` [PATCH v3 1/2] ARM: dts: r8a7790: " Geert Uytterhoeven
2018-05-07 13:19 ` Geert Uytterhoeven
2018-05-07 13:19 ` [PATCH v3 2/2] ARM: dts: r8a73a4: " Geert Uytterhoeven
2018-05-07 13:19 ` Geert Uytterhoeven
2018-05-08 13:35 ` [PATCH v3 0/2] ARM: dts: renesas: " Simon Horman
2018-05-08 13:35 ` Simon Horman
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