* [v2] drm/i915: Enable hw workaround to bypass alpha
@ 2018-06-21 15:13 Vandita Kulkarni
2018-06-21 16:02 ` ✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Vandita Kulkarni @ 2018-06-21 15:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Vandita Kulkarni, maarten.lankhorst
Alpha blending with alpha 0 and 0xff passes through
alpha math and rounding logic causing differences
compared to fully transparent or opaque plane,resulting
in CRC mismatch.
This WA on icl and above enables hardware to bypass alpha
math and rounding for per pixel alpha values of 00 and 0xff
v2: Fix patchwork checkpatch warnings.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4bfd7a9..b66ec9b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7366,6 +7366,14 @@ enum {
#define BDW_SCRATCH1 _MMIO(0xb11c)
#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
+/*GEN11 chicken */
+#define _PIPEA_CHICKEN 0x70038
+#define _PIPEB_CHICKEN 0x71038
+#define _PIPEC_CHICKEN 0x72038
+#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
+ _PIPEB_CHICKEN)
+
/* PCH */
/* south display engine interrupt: IBX */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c8fef3..3d849ec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
bool psl_clkgate_wa;
+ u32 pipe_chicken;
if (WARN_ON(intel_crtc->active))
return;
@@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
*/
intel_color_load_luts(&pipe_config->base);
+ /*
+ * Display WA #1153: enable hardware to bypass the alpha math
+ * and rounding for per-pixel values 00 and 0xff
+ */
+ if (INTEL_GEN(dev_priv) >= 11) {
+ pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
+ if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
+ I915_WRITE_FW(PIPE_CHICKEN(pipe),
+ pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
+ }
+
intel_ddi_set_pipe_settings(pipe_config);
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) 2018-06-21 15:13 [v2] drm/i915: Enable hw workaround to bypass alpha Vandita Kulkarni @ 2018-06-21 16:02 ` Patchwork 2018-06-21 21:09 ` [v2] drm/i915: Enable hw workaround to bypass alpha Radhakrishna Sripada 2018-06-21 22:22 ` ✓ Fi.CI.IGT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-06-21 16:02 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx == Series Details == Series: drm/i915: Enable hw workaround to bypass alpha (rev2) URL : https://patchwork.freedesktop.org/series/45173/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4359 -> Patchwork_9384 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/45173/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_9384 that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) ==== Possible fixes ==== igt@gem_ctx_create@basic-files: fi-skl-gvtdvm: INCOMPLETE (fdo#105600, fdo#106988) -> PASS fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#106988 https://bugs.freedesktop.org/show_bug.cgi?id=106988 == Participating hosts (42 -> 37) == Missing (5): fi-byt-squawks fi-kbl-x1275 fi-ilk-m540 fi-glk-dsi fi-hsw-4200u == Build changes == * Linux: CI_DRM_4359 -> Patchwork_9384 CI_DRM_4359: fe0300c16bff0f9c82050e56cdbc3880f87e39bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4527: 04afec3ccfcb35e994f2e78254ff499f6b94f097 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9384: d054ad3f8cdffbdfdc964839b966b1304a761439 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d054ad3f8cdf drm/i915: Enable hw workaround to bypass alpha == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9384/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [v2] drm/i915: Enable hw workaround to bypass alpha 2018-06-21 15:13 [v2] drm/i915: Enable hw workaround to bypass alpha Vandita Kulkarni 2018-06-21 16:02 ` ✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork @ 2018-06-21 21:09 ` Radhakrishna Sripada 2018-06-22 7:37 ` Kulkarni, Vandita 2018-06-22 8:42 ` Lankhorst, Maarten 2018-06-21 22:22 ` ✓ Fi.CI.IGT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork 2 siblings, 2 replies; 6+ messages in thread From: Radhakrishna Sripada @ 2018-06-21 21:09 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx, maarten.lankhorst On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > Alpha blending with alpha 0 and 0xff passes through > alpha math and rounding logic causing differences > compared to fully transparent or opaque plane,resulting > in CRC mismatch. > This WA on icl and above enables hardware to bypass alpha > math and rounding for per pixel alpha values of 00 and 0xff > > v2: Fix patchwork checkpatch warnings. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4bfd7a9..b66ec9b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7366,6 +7366,14 @@ enum { > #define BDW_SCRATCH1 _MMIO(0xb11c) > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > +/*GEN11 chicken */ > +#define _PIPEA_CHICKEN 0x70038 > +#define _PIPEB_CHICKEN 0x71038 > +#define _PIPEC_CHICKEN 0x72038 > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ > + _PIPEB_CHICKEN) > + > /* PCH */ > > /* south display engine interrupt: IBX */ > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 2c8fef3..3d849ec 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > bool psl_clkgate_wa; > + u32 pipe_chicken; > > if (WARN_ON(intel_crtc->active)) > return; > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > */ > intel_color_load_luts(&pipe_config->base); > > + /* > + * Display WA #1153: enable hardware to bypass the alpha math > + * and rounding for per-pixel values 00 and 0xff > + */ > + if (INTEL_GEN(dev_priv) >= 11) { > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > + pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); > + } This would enable the wa by default for gen > 11. Would this impact for non 00, 0xff alpha cases? In other words, should we enable the wa only when alpha is 00/0xff and not enable for other values? Thanks, Radhakrishna(RK) Sripada > + > intel_ddi_set_pipe_settings(pipe_config); > if (!transcoder_is_dsi(cpu_transcoder)) > intel_ddi_enable_transcoder_func(pipe_config); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [v2] drm/i915: Enable hw workaround to bypass alpha 2018-06-21 21:09 ` [v2] drm/i915: Enable hw workaround to bypass alpha Radhakrishna Sripada @ 2018-06-22 7:37 ` Kulkarni, Vandita 2018-06-22 8:42 ` Lankhorst, Maarten 1 sibling, 0 replies; 6+ messages in thread From: Kulkarni, Vandita @ 2018-06-22 7:37 UTC (permalink / raw) To: Sripada, Radhakrishna; +Cc: intel-gfx, Lankhorst, Maarten > -----Original Message----- > From: Sripada, Radhakrishna > Sent: Friday, June 22, 2018 2:39 AM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten > <maarten.lankhorst@intel.com> > Subject: Re: [Intel-gfx] [v2] drm/i915: Enable hw workaround to bypass > alpha > > On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through alpha math and > > rounding logic causing differences compared to fully transparent or > > opaque plane,resulting in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha math and > > rounding for per pixel alpha values of 00 and 0xff > > > > v2: Fix patchwork checkpatch warnings. > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..b66ec9b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 > _MMIO(0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << > 2) > > > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > > > /* south display engine interrupt: IBX */ diff --git > > a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..3d849ec 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state = > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > + if (INTEL_GEN(dev_priv) >= 11) { > > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > PER_PIXEL_ALPHA_BYPASS_EN); > > + } > This would enable the wa by default for gen > 11. Would this impact for non > 00, 0xff alpha cases? No Impact on non 0xff or 00 cases. Verified on icl. > In other words, should we enable the wa only when alpha is 00/0xff and not > enable for other values? No it can remain set. > > Thanks, > Radhakrishna(RK) Sripada > > + > > intel_ddi_set_pipe_settings(pipe_config); > > if (!transcoder_is_dsi(cpu_transcoder)) > > intel_ddi_enable_transcoder_func(pipe_config); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [v2] drm/i915: Enable hw workaround to bypass alpha 2018-06-21 21:09 ` [v2] drm/i915: Enable hw workaround to bypass alpha Radhakrishna Sripada 2018-06-22 7:37 ` Kulkarni, Vandita @ 2018-06-22 8:42 ` Lankhorst, Maarten 1 sibling, 0 replies; 6+ messages in thread From: Lankhorst, Maarten @ 2018-06-22 8:42 UTC (permalink / raw) To: Sripada, Radhakrishna, Kulkarni, Vandita; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3287 bytes --] tor 2018-06-21 klockan 14:09 -0700 skrev Radhakrishna Sripada: > On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through > > alpha math and rounding logic causing differences > > compared to fully transparent or opaque plane,resulting > > in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha > > math and rounding for per pixel alpha values of 00 and 0xff > > > > v2: Fix patchwork checkpatch warnings. > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 4bfd7a9..b66ec9b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 _MMIO( > > 0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > > > /* south display engine interrupt: IBX */ > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..3d849ec 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state = > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha > > math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > + if (INTEL_GEN(dev_priv) >= 11) { > > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > > PER_PIXEL_ALPHA_BYPASS_EN); > > + } > > This would enable the wa by default for gen > 11. Would this impact > for non 00, 0xff alpha cases? > In other words, should we enable the wa only when alpha is 00/0xff > and not enable for other values? > This is about per pixel values, unlike the plane alpha. This looks at the pixel contents, so if a pixel has (0xff, R, G, B), we pass through RGB unmodified. If it's (0x00, R, G, B), we do the same for the background pixel without introducing rounding errors. When we program plane alpha, we handle 0x00 by disabling the plane, and 0xff by disabling plane alpha and making the plane opaque. Thanks for the patch, pushed. :) ~Maarten [-- Attachment #1.2: smime.p7s --] [-- Type: application/x-pkcs7-signature, Size: 3282 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) 2018-06-21 15:13 [v2] drm/i915: Enable hw workaround to bypass alpha Vandita Kulkarni 2018-06-21 16:02 ` ✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork 2018-06-21 21:09 ` [v2] drm/i915: Enable hw workaround to bypass alpha Radhakrishna Sripada @ 2018-06-21 22:22 ` Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-06-21 22:22 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx == Series Details == Series: drm/i915: Enable hw workaround to bypass alpha (rev2) URL : https://patchwork.freedesktop.org/series/45173/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4359_full -> Patchwork_9384_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9384_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_gtt: shard-glk: PASS -> FAIL (fdo#105347) igt@drv_selftest@live_hangcheck: shard-kbl: NOTRUN -> DMESG-FAIL (fdo#106560, fdo#106947) shard-apl: PASS -> DMESG-FAIL (fdo#106560, fdo#106947) igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-kbl: PASS -> FAIL (fdo#105363, fdo#102887) igt@kms_flip@plain-flip-fb-recreate: shard-glk: PASS -> FAIL (fdo#100368) +1 igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) +1 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) ==== Possible fixes ==== igt@drv_selftest@live_gtt: shard-kbl: FAIL (fdo#105347) -> PASS igt@drv_selftest@live_hugepages: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4359 -> Patchwork_9384 CI_DRM_4359: fe0300c16bff0f9c82050e56cdbc3880f87e39bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4527: 04afec3ccfcb35e994f2e78254ff499f6b94f097 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9384: d054ad3f8cdffbdfdc964839b966b1304a761439 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9384/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-06-22 8:42 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-06-21 15:13 [v2] drm/i915: Enable hw workaround to bypass alpha Vandita Kulkarni 2018-06-21 16:02 ` ✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork 2018-06-21 21:09 ` [v2] drm/i915: Enable hw workaround to bypass alpha Radhakrishna Sripada 2018-06-22 7:37 ` Kulkarni, Vandita 2018-06-22 8:42 ` Lankhorst, Maarten 2018-06-21 22:22 ` ✓ Fi.CI.IGT: success for drm/i915: Enable hw workaround to bypass alpha (rev2) Patchwork
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