* [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
@ 2018-07-09 16:22 Lucas De Marchi
2018-07-09 16:22 ` [PATCH 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Lucas De Marchi @ 2018-07-09 16:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.
This also rewrites the GMBUS[05] registers since they depend on
gpio_mmio_base.
v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
macro to return a particular gpio address and move the enum out of
i915_reg.h (suggested by Jani)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
4 files changed, 52 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e39492aaff6c..e25a74fe753b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
gmbus_mmio_write);
- MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0424e45f88db..f8f71d577613 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3088,18 +3088,11 @@ enum i915_power_well_id {
/*
* GPIO regs
*/
-#define GPIOA _MMIO(0x5010)
-#define GPIOB _MMIO(0x5014)
-#define GPIOC _MMIO(0x5018)
-#define GPIOD _MMIO(0x501c)
-#define GPIOE _MMIO(0x5020)
-#define GPIOF _MMIO(0x5024)
-#define GPIOG _MMIO(0x5028)
-#define GPIOH _MMIO(0x502c)
-#define GPIOJ _MMIO(0x5034)
-#define GPIOK _MMIO(0x5038)
-#define GPIOL _MMIO(0x503C)
-#define GPIOM _MMIO(0x5040)
+#define GPIO_OFFSET 0x5010u
+#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
+#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
+#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio))
+
# define GPIO_CLOCK_DIR_MASK (1 << 0)
# define GPIO_CLOCK_DIR_IN (0 << 1)
# define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -3115,7 +3108,11 @@ enum i915_power_well_id {
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
-#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS_OFFSET 0x5100u
+
+/* clock/port select */
+#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET)
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -3141,7 +3138,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_12_TC4_ICP 12
#define GMBUS_NUM_PINS 13 /* including 0 */
-#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+
+/* command/status */
+#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x4)
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -3155,7 +3155,10 @@ enum i915_power_well_id {
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
#define GMBUS_SLAVE_WRITE (0 << 0)
-#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
+
+/* status */
+#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x8)
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -3163,14 +3166,21 @@ enum i915_power_well_id {
#define GMBUS_HW_RDY (1 << 11)
#define GMBUS_SATOER (1 << 10)
#define GMBUS_ACTIVE (1 << 9)
-#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+
+/* data buffer bytes 3-0 */
+#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0xc)
+/* interrupt mask (Pineview+) */
+#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x10)
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
#define GMBUS_HW_WAIT_EN (1 << 1)
#define GMBUS_HW_RDY_EN (1 << 0)
-#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+/* byte index */
+#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x20)
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
/*
@@ -7668,13 +7678,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GPIOA _MMIO(0xc5010)
-#define PCH_GPIOB _MMIO(0xc5014)
-#define PCH_GPIOC _MMIO(0xc5018)
-#define PCH_GPIOD _MMIO(0xc501c)
-#define PCH_GPIOE _MMIO(0xc5020)
-#define PCH_GPIOF _MMIO(0xc5024)
-
#define PCH_GMBUS0 _MMIO(0xc5100)
#define PCH_GMBUS1 _MMIO(0xc5104)
#define PCH_GMBUS2 _MMIO(0xc5108)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61e715ddd0d5..dedf87c58a95 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -152,6 +152,22 @@
* Display related stuff
*/
+enum i915_gpio {
+ GPIOA = 0,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+};
+
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..f1c0b974daa6 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
struct gmbus_pin {
const char *name;
- i915_reg_t reg;
+ enum i915_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
else
size = ARRAY_SIZE(gmbus_pins);
- return pin < size &&
- i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
+ return pin < size && get_gmbus_pin(dev_priv, pin)->name;
}
/* Intel GPIO access functions */
@@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
algo = &bus->bit_algo;
- bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
- i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
+ bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
bus->adapter.algo_data = algo;
algo->setsda = set_data;
algo->setscl = set_clock;
@@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
- dev_priv->gpio_mmio_base =
- i915_mmio_reg_offset(PCH_GPIOA) -
- i915_mmio_reg_offset(GPIOA);
+ dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
+ else
+ dev_priv->gpio_mmio_base = GPIO_OFFSET;
mutex_init(&dev_priv->gmbus_mutex);
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915: remove PCH_GMBUS defines
2018-07-09 16:22 [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
@ 2018-07-09 16:22 ` Lucas De Marchi
2018-07-09 16:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Lucas De Marchi @ 2018-07-09 16:22 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Now they are the same as GMBUS*, but without considering the different
address bases. In order to use GMBUS* we just need access to dev_priv in
a few places so this has been added.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/edid.c | 42 +++++++++++++++++------------
drivers/gpu/drm/i915/gvt/handlers.c | 8 +++---
drivers/gpu/drm/i915/i915_reg.h | 7 -----
3 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 4b98539025c5..3ffa814a634e 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -109,9 +109,11 @@ static inline int get_port_from_gmbus0(u32 gmbus0)
static void reset_gmbus_controller(struct intel_vgpu *vgpu)
{
- vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+ vgpu_vreg_t(vgpu, GMBUS2) = GMBUS_HW_RDY;
if (!vgpu->display.i2c_edid.edid_available)
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
}
@@ -141,22 +143,23 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
vgpu->display.i2c_edid.state = I2C_GMBUS;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
!intel_vgpu_port_is_dp(vgpu, port)) {
vgpu->display.i2c_edid.port = port;
vgpu->display.i2c_edid.edid_available = true;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_SATOER;
} else
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
return 0;
}
static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
u32 slave_addr;
u32 wvalue = *(u32 *)p_data;
@@ -177,8 +180,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* 2) HW_RDY bit asserted
*/
if (wvalue & GMBUS_SW_CLR_INT) {
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_INT;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY;
}
/* For virtualization, we suppose that HW is always ready,
@@ -226,7 +229,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* visible in gmbus interface)
*/
i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
}
break;
case NIDX_NS_W:
@@ -238,7 +241,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* START (-->INDEX) -->DATA
*/
i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_ACTIVE;
break;
default:
gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -265,6 +268,7 @@ static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int i;
unsigned char byte_data;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
@@ -274,7 +278,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
u32 reg_data = 0;
/* Data can only be recevied if previous settings correct */
- if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
+ if (vgpu_vreg_t(vgpu, GMBUS1) & GMBUS_SLAVE_READ) {
if (byte_left <= 0) {
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
return 0;
@@ -350,12 +354,14 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
@@ -375,16 +381,18 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
+ if (offset == i915_mmio_reg_offset(GMBUS0))
return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
+ else if (offset == i915_mmio_reg_offset(GMBUS1))
return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ else if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e25a74fe753b..6ead029dbb48 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2082,8 +2082,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0x48268), D_ALL);
- MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
- gmbus_mmio_write);
+ MMIO_F(GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
+ gmbus_mmio_write);
MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
@@ -2473,8 +2473,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0xe6704), D_ALL);
MMIO_D(_MMIO(0xe6800), D_ALL);
MMIO_D(_MMIO(0xe6804), D_ALL);
- MMIO_D(PCH_GMBUS4, D_ALL);
- MMIO_D(PCH_GMBUS5, D_ALL);
+ MMIO_D(GMBUS4, D_ALL);
+ MMIO_D(GMBUS5, D_ALL);
MMIO_D(_MMIO(0x902c), D_ALL);
MMIO_D(_MMIO(0xec008), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f8f71d577613..0baafabcf52c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7678,13 +7678,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GMBUS0 _MMIO(0xc5100)
-#define PCH_GMBUS1 _MMIO(0xc5104)
-#define PCH_GMBUS2 _MMIO(0xc5108)
-#define PCH_GMBUS3 _MMIO(0xc510c)
-#define PCH_GMBUS4 _MMIO(0xc5110)
-#define PCH_GMBUS5 _MMIO(0xc5120)
-
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-09 16:22 [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-09 16:22 ` [PATCH 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
@ 2018-07-09 16:46 ` Patchwork
2018-07-10 1:15 ` ✓ Fi.CI.IGT: " Patchwork
2018-07-12 15:04 ` [PATCH 1/2] " Daniel Vetter
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-07-09 16:46 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
URL : https://patchwork.freedesktop.org/series/46200/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4455 -> Patchwork_9595 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46200/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9595 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: SKIP -> FAIL (fdo#102672, fdo#103841)
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) +1
==== Possible fixes ====
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
== Participating hosts (46 -> 41) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4455 -> Patchwork_9595
CI_DRM_4455: b3d84bf4dc417107dafe58a149ba8e62472d4066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4544: 764160f214cd916ddb79408b9f28ac0ad2df40e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9595: c5ae11b2d0f01b0cc2b8e867b2fee07f898e2811 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c5ae11b2d0f0 drm/i915: remove PCH_GMBUS defines
7a81c369d5df drm/i915: remove confusing GPIO vs PCH_GPIO
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9595/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-09 16:22 [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-09 16:22 ` [PATCH 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
2018-07-09 16:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
@ 2018-07-10 1:15 ` Patchwork
2018-07-12 15:04 ` [PATCH 1/2] " Daniel Vetter
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-07-10 1:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
URL : https://patchwork.freedesktop.org/series/46200/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4455_full -> Patchwork_9595_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9595_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9595_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9595_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-kbl: PASS -> SKIP +2
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS
igt@kms_properties@plane-properties-legacy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9595_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
shard-glk: PASS -> FAIL (fdo#105703) +1
igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
shard-glk: PASS -> FAIL (fdo#105454, fdo#106509)
igt@kms_flip@flip-vs-expired-vblank:
shard-apl: PASS -> FAIL (fdo#102887, fdo#105363)
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: FAIL (fdo#107161) -> PASS
igt@prime_vgem@basic-fence-flip:
shard-apl: FAIL (fdo#104008) -> PASS
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#107161 https://bugs.freedesktop.org/show_bug.cgi?id=107161
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4455 -> Patchwork_9595
CI_DRM_4455: b3d84bf4dc417107dafe58a149ba8e62472d4066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4544: 764160f214cd916ddb79408b9f28ac0ad2df40e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9595: c5ae11b2d0f01b0cc2b8e867b2fee07f898e2811 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9595/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-09 16:22 [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
` (2 preceding siblings ...)
2018-07-10 1:15 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-07-12 15:04 ` Daniel Vetter
2018-07-12 16:24 ` Lucas De Marchi
3 siblings, 1 reply; 10+ messages in thread
From: Daniel Vetter @ 2018-07-12 15:04 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi
On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
>
> This also rewrites the GMBUS[05] registers since they depend on
> gpio_mmio_base.
>
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> macro to return a particular gpio address and move the enum out of
> i915_reg.h (suggested by Jani)
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
> drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
> drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
> 4 files changed, 52 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index e39492aaff6c..e25a74fe753b 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>
> MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> gmbus_mmio_write);
> - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>
> MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0424e45f88db..f8f71d577613 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> /*
> * GPIO regs
> */
> -#define GPIOA _MMIO(0x5010)
> -#define GPIOB _MMIO(0x5014)
> -#define GPIOC _MMIO(0x5018)
> -#define GPIOD _MMIO(0x501c)
> -#define GPIOE _MMIO(0x5020)
> -#define GPIOF _MMIO(0x5024)
> -#define GPIOG _MMIO(0x5028)
> -#define GPIOH _MMIO(0x502c)
> -#define GPIOJ _MMIO(0x5034)
> -#define GPIOK _MMIO(0x5038)
> -#define GPIOL _MMIO(0x503C)
> -#define GPIOM _MMIO(0x5040)
> +#define GPIO_OFFSET 0x5010u
> +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
> +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
This is a rather peculiar choice of baseline address. I'd either go with
0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
Only needs a slight adjustment to your GPIO macro, but avoids the rather
onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda
indicates your offset is all confused.
Anyway, just a drive-by comment, I was looking for some other gmbus patch.
-Daniel
> +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio))
> +
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> @@ -3115,7 +3108,11 @@ enum i915_power_well_id {
> # define GPIO_DATA_VAL_IN (1 << 12)
> # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
>
> -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
> +#define GMBUS_OFFSET 0x5100u
> +
> +/* clock/port select */
> +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET)
> #define GMBUS_AKSV_SELECT (1 << 11)
> #define GMBUS_RATE_100KHZ (0 << 8)
> #define GMBUS_RATE_50KHZ (1 << 8)
> @@ -3141,7 +3138,10 @@ enum i915_power_well_id {
> #define GMBUS_PIN_12_TC4_ICP 12
>
> #define GMBUS_NUM_PINS 13 /* including 0 */
> -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
> +
> +/* command/status */
> +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET + 0x4)
> #define GMBUS_SW_CLR_INT (1 << 31)
> #define GMBUS_SW_RDY (1 << 30)
> #define GMBUS_ENT (1 << 29) /* enable timeout */
> @@ -3155,7 +3155,10 @@ enum i915_power_well_id {
> #define GMBUS_SLAVE_ADDR_SHIFT 1
> #define GMBUS_SLAVE_READ (1 << 0)
> #define GMBUS_SLAVE_WRITE (0 << 0)
> -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
> +
> +/* status */
> +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET + 0x8)
> #define GMBUS_INUSE (1 << 15)
> #define GMBUS_HW_WAIT_PHASE (1 << 14)
> #define GMBUS_STALL_TIMEOUT (1 << 13)
> @@ -3163,14 +3166,21 @@ enum i915_power_well_id {
> #define GMBUS_HW_RDY (1 << 11)
> #define GMBUS_SATOER (1 << 10)
> #define GMBUS_ACTIVE (1 << 9)
> -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
> -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
> +
> +/* data buffer bytes 3-0 */
> +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET + 0xc)
> +/* interrupt mask (Pineview+) */
> +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET + 0x10)
> #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
> #define GMBUS_NAK_EN (1 << 3)
> #define GMBUS_IDLE_EN (1 << 2)
> #define GMBUS_HW_WAIT_EN (1 << 1)
> #define GMBUS_HW_RDY_EN (1 << 0)
> -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
> +/* byte index */
> +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> + + GMBUS_OFFSET + 0x20)
> #define GMBUS_2BYTE_INDEX_EN (1 << 31)
>
> /*
> @@ -7668,13 +7678,6 @@ enum {
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> -#define PCH_GPIOA _MMIO(0xc5010)
> -#define PCH_GPIOB _MMIO(0xc5014)
> -#define PCH_GPIOC _MMIO(0xc5018)
> -#define PCH_GPIOD _MMIO(0xc501c)
> -#define PCH_GPIOE _MMIO(0xc5020)
> -#define PCH_GPIOF _MMIO(0xc5024)
> -
> #define PCH_GMBUS0 _MMIO(0xc5100)
> #define PCH_GMBUS1 _MMIO(0xc5104)
> #define PCH_GMBUS2 _MMIO(0xc5108)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 61e715ddd0d5..dedf87c58a95 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -152,6 +152,22 @@
> * Display related stuff
> */
>
> +enum i915_gpio {
> + GPIOA = 0,
> + GPIOB,
> + GPIOC,
> + GPIOD,
> + GPIOE,
> + GPIOF,
> + GPIOG,
> + GPIOH,
> + __GPIOI_UNUSED,
> + GPIOJ,
> + GPIOK,
> + GPIOL,
> + GPIOM,
> +};
> +
> /* store information about an Ixxx DVO */
> /* The i830->i865 use multiple DVOs with multiple i2cs */
> /* the i915, i945 have a single sDVO i2c bus - which is different */
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 97606c1be70d..f1c0b974daa6 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>
> struct gmbus_pin {
> const char *name;
> - i915_reg_t reg;
> + enum i915_gpio gpio;
> };
>
> /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> else
> size = ARRAY_SIZE(gmbus_pins);
>
> - return pin < size &&
> - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> }
>
> /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>
> algo = &bus->bit_algo;
>
> - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> bus->adapter.algo_data = algo;
> algo->setsda = set_data;
> algo->setscl = set_clock;
> @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> return 0;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> + dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
> else if (!HAS_GMCH_DISPLAY(dev_priv))
> - dev_priv->gpio_mmio_base =
> - i915_mmio_reg_offset(PCH_GPIOA) -
> - i915_mmio_reg_offset(GPIOA);
> + dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
> + else
> + dev_priv->gpio_mmio_base = GPIO_OFFSET;
>
> mutex_init(&dev_priv->gmbus_mutex);
> init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-12 15:04 ` [PATCH 1/2] " Daniel Vetter
@ 2018-07-12 16:24 ` Lucas De Marchi
2018-07-12 17:03 ` Daniel Vetter
0 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2018-07-12 16:24 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi
On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > that has the same address as PCH_GPIO_A and use that to calculate all
> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > the same thing.
> >
> > This also rewrites the GMBUS[05] registers since they depend on
> > gpio_mmio_base.
> >
> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > macro to return a particular gpio address and move the enum out of
> > i915_reg.h (suggested by Jani)
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
> > 4 files changed, 52 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > index e39492aaff6c..e25a74fe753b 100644
> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> >
> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > gmbus_mmio_write);
> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >
> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0424e45f88db..f8f71d577613 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> > /*
> > * GPIO regs
> > */
> > -#define GPIOA _MMIO(0x5010)
> > -#define GPIOB _MMIO(0x5014)
> > -#define GPIOC _MMIO(0x5018)
> > -#define GPIOD _MMIO(0x501c)
> > -#define GPIOE _MMIO(0x5020)
> > -#define GPIOF _MMIO(0x5024)
> > -#define GPIOG _MMIO(0x5028)
> > -#define GPIOH _MMIO(0x502c)
> > -#define GPIOJ _MMIO(0x5034)
> > -#define GPIOK _MMIO(0x5038)
> > -#define GPIOL _MMIO(0x503C)
> > -#define GPIOM _MMIO(0x5040)
> > +#define GPIO_OFFSET 0x5010u
> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
>
> This is a rather peculiar choice of baseline address. I'd either go with
> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
I'm all for a round 0x50000 number, however it doesn't match the spec.
I don't understand how 0x0 would make sense here. Are you suggesting to
embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
#define GPIO_OFFSET 0x5010u
/* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
#define PCH_GPIO_BASE 0xc0000u
#define VLV_GPIO_BASE VLV_DISPLAY_BASE
#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
That would make sense, but I don't think it's a better option due to
GPIO_BASE now and mmio_gpio_base matching nothing in the spec (and the
extra add on every gpio).
> Only needs a slight adjustment to your GPIO macro, but avoids the rather
> onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda
> indicates your offset is all confused.
well.. this is only because there I'm actually interested in the vlv
display / pch offset. The subtraction is done so I don't have to store
a gmbus_mmio_base and can rather work it out from the gpio one.
Lucas De Marchi
>
> Anyway, just a drive-by comment, I was looking for some other gmbus patch.
> -Daniel
>
> > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio))
> > +
> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > @@ -3115,7 +3108,11 @@ enum i915_power_well_id {
> > # define GPIO_DATA_VAL_IN (1 << 12)
> > # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
> >
> > -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
> > +#define GMBUS_OFFSET 0x5100u
> > +
> > +/* clock/port select */
> > +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET)
> > #define GMBUS_AKSV_SELECT (1 << 11)
> > #define GMBUS_RATE_100KHZ (0 << 8)
> > #define GMBUS_RATE_50KHZ (1 << 8)
> > @@ -3141,7 +3138,10 @@ enum i915_power_well_id {
> > #define GMBUS_PIN_12_TC4_ICP 12
> >
> > #define GMBUS_NUM_PINS 13 /* including 0 */
> > -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
> > +
> > +/* command/status */
> > +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET + 0x4)
> > #define GMBUS_SW_CLR_INT (1 << 31)
> > #define GMBUS_SW_RDY (1 << 30)
> > #define GMBUS_ENT (1 << 29) /* enable timeout */
> > @@ -3155,7 +3155,10 @@ enum i915_power_well_id {
> > #define GMBUS_SLAVE_ADDR_SHIFT 1
> > #define GMBUS_SLAVE_READ (1 << 0)
> > #define GMBUS_SLAVE_WRITE (0 << 0)
> > -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
> > +
> > +/* status */
> > +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET + 0x8)
> > #define GMBUS_INUSE (1 << 15)
> > #define GMBUS_HW_WAIT_PHASE (1 << 14)
> > #define GMBUS_STALL_TIMEOUT (1 << 13)
> > @@ -3163,14 +3166,21 @@ enum i915_power_well_id {
> > #define GMBUS_HW_RDY (1 << 11)
> > #define GMBUS_SATOER (1 << 10)
> > #define GMBUS_ACTIVE (1 << 9)
> > -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
> > -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
> > +
> > +/* data buffer bytes 3-0 */
> > +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET + 0xc)
> > +/* interrupt mask (Pineview+) */
> > +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET + 0x10)
> > #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
> > #define GMBUS_NAK_EN (1 << 3)
> > #define GMBUS_IDLE_EN (1 << 2)
> > #define GMBUS_HW_WAIT_EN (1 << 1)
> > #define GMBUS_HW_RDY_EN (1 << 0)
> > -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
> > +/* byte index */
> > +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
> > + + GMBUS_OFFSET + 0x20)
> > #define GMBUS_2BYTE_INDEX_EN (1 << 31)
> >
> > /*
> > @@ -7668,13 +7678,6 @@ enum {
> > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> >
> > -#define PCH_GPIOA _MMIO(0xc5010)
> > -#define PCH_GPIOB _MMIO(0xc5014)
> > -#define PCH_GPIOC _MMIO(0xc5018)
> > -#define PCH_GPIOD _MMIO(0xc501c)
> > -#define PCH_GPIOE _MMIO(0xc5020)
> > -#define PCH_GPIOF _MMIO(0xc5024)
> > -
> > #define PCH_GMBUS0 _MMIO(0xc5100)
> > #define PCH_GMBUS1 _MMIO(0xc5104)
> > #define PCH_GMBUS2 _MMIO(0xc5108)
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 61e715ddd0d5..dedf87c58a95 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -152,6 +152,22 @@
> > * Display related stuff
> > */
> >
> > +enum i915_gpio {
> > + GPIOA = 0,
> > + GPIOB,
> > + GPIOC,
> > + GPIOD,
> > + GPIOE,
> > + GPIOF,
> > + GPIOG,
> > + GPIOH,
> > + __GPIOI_UNUSED,
> > + GPIOJ,
> > + GPIOK,
> > + GPIOL,
> > + GPIOM,
> > +};
> > +
> > /* store information about an Ixxx DVO */
> > /* The i830->i865 use multiple DVOs with multiple i2cs */
> > /* the i915, i945 have a single sDVO i2c bus - which is different */
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index 97606c1be70d..f1c0b974daa6 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -37,7 +37,7 @@
> >
> > struct gmbus_pin {
> > const char *name;
> > - i915_reg_t reg;
> > + enum i915_gpio gpio;
> > };
> >
> > /* Map gmbus pin pairs to names and registers. */
> > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> > else
> > size = ARRAY_SIZE(gmbus_pins);
> >
> > - return pin < size &&
> > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> > + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> > }
> >
> > /* Intel GPIO access functions */
> > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
> >
> > algo = &bus->bit_algo;
> >
> > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> > bus->adapter.algo_data = algo;
> > algo->setsda = set_data;
> > algo->setscl = set_clock;
> > @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> > return 0;
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> > + dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
> > else if (!HAS_GMCH_DISPLAY(dev_priv))
> > - dev_priv->gpio_mmio_base =
> > - i915_mmio_reg_offset(PCH_GPIOA) -
> > - i915_mmio_reg_offset(GPIOA);
> > + dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
> > + else
> > + dev_priv->gpio_mmio_base = GPIO_OFFSET;
> >
> > mutex_init(&dev_priv->gmbus_mutex);
> > init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-12 16:24 ` Lucas De Marchi
@ 2018-07-12 17:03 ` Daniel Vetter
2018-07-12 17:23 ` Ville Syrjälä
0 siblings, 1 reply; 10+ messages in thread
From: Daniel Vetter @ 2018-07-12 17:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi
On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
<lucas.de.marchi@gmail.com> wrote:
> On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
>> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
>> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
>> > that has the same address as PCH_GPIO_A and use that to calculate all
>> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
>> > the same thing.
>> >
>> > This also rewrites the GMBUS[05] registers since they depend on
>> > gpio_mmio_base.
>> >
>> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
>> > macro to return a particular gpio address and move the enum out of
>> > i915_reg.h (suggested by Jani)
>> >
>> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
>> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
>> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
>> > 4 files changed, 52 insertions(+), 35 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> > index e39492aaff6c..e25a74fe753b 100644
>> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>> >
>> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
>> > gmbus_mmio_write);
>> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>> >
>> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 0424e45f88db..f8f71d577613 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
>> > /*
>> > * GPIO regs
>> > */
>> > -#define GPIOA _MMIO(0x5010)
>> > -#define GPIOB _MMIO(0x5014)
>> > -#define GPIOC _MMIO(0x5018)
>> > -#define GPIOD _MMIO(0x501c)
>> > -#define GPIOE _MMIO(0x5020)
>> > -#define GPIOF _MMIO(0x5024)
>> > -#define GPIOG _MMIO(0x5028)
>> > -#define GPIOH _MMIO(0x502c)
>> > -#define GPIOJ _MMIO(0x5034)
>> > -#define GPIOK _MMIO(0x5038)
>> > -#define GPIOL _MMIO(0x503C)
>> > -#define GPIOM _MMIO(0x5040)
>> > +#define GPIO_OFFSET 0x5010u
>> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
>> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
>>
>> This is a rather peculiar choice of baseline address. I'd either go with
>> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
>
> I'm all for a round 0x50000 number, however it doesn't match the spec.
> I don't understand how 0x0 would make sense here. Are you suggesting to
> embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
>
> #define GPIO_OFFSET 0x5010u
> /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
> #define PCH_GPIO_BASE 0xc0000u
> #define VLV_GPIO_BASE VLV_DISPLAY_BASE
> #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
Yeah that's what I had in mind.
> That would make sense, but I don't think it's a better option due to
> GPIO_BASE now and mmio_gpio_base matching nothing in the spec (and the
> extra add on every gpio).
>
>> Only needs a slight adjustment to your GPIO macro, but avoids the rather
>> onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda
>> indicates your offset is all confused.
>
> well.. this is only because there I'm actually interested in the vlv
> display / pch offset. The subtraction is done so I don't have to store
> a gmbus_mmio_base and can rather work it out from the gpio one.
If you want to stick with your approach, at least extract the common
->gpio_mmio_base - GPIO_OFFSET + GMBUS_OFFSET computation into a
GMBUS_BASE(dev) macro or something like that. I think that would be a
good solution too.
Either approach has my a-b (I'll be on vacations next 3 weeks to
probably no r-b from me).
-Daniel
>
> Lucas De Marchi
>
>>
>> Anyway, just a drive-by comment, I was looking for some other gmbus patch.
>> -Daniel
>>
>> > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio))
>> > +
>> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
>> > # define GPIO_CLOCK_DIR_IN (0 << 1)
>> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
>> > @@ -3115,7 +3108,11 @@ enum i915_power_well_id {
>> > # define GPIO_DATA_VAL_IN (1 << 12)
>> > # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
>> >
>> > -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
>> > +#define GMBUS_OFFSET 0x5100u
>> > +
>> > +/* clock/port select */
>> > +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET)
>> > #define GMBUS_AKSV_SELECT (1 << 11)
>> > #define GMBUS_RATE_100KHZ (0 << 8)
>> > #define GMBUS_RATE_50KHZ (1 << 8)
>> > @@ -3141,7 +3138,10 @@ enum i915_power_well_id {
>> > #define GMBUS_PIN_12_TC4_ICP 12
>> >
>> > #define GMBUS_NUM_PINS 13 /* including 0 */
>> > -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>> > +
>> > +/* command/status */
>> > +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET + 0x4)
>> > #define GMBUS_SW_CLR_INT (1 << 31)
>> > #define GMBUS_SW_RDY (1 << 30)
>> > #define GMBUS_ENT (1 << 29) /* enable timeout */
>> > @@ -3155,7 +3155,10 @@ enum i915_power_well_id {
>> > #define GMBUS_SLAVE_ADDR_SHIFT 1
>> > #define GMBUS_SLAVE_READ (1 << 0)
>> > #define GMBUS_SLAVE_WRITE (0 << 0)
>> > -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
>> > +
>> > +/* status */
>> > +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET + 0x8)
>> > #define GMBUS_INUSE (1 << 15)
>> > #define GMBUS_HW_WAIT_PHASE (1 << 14)
>> > #define GMBUS_STALL_TIMEOUT (1 << 13)
>> > @@ -3163,14 +3166,21 @@ enum i915_power_well_id {
>> > #define GMBUS_HW_RDY (1 << 11)
>> > #define GMBUS_SATOER (1 << 10)
>> > #define GMBUS_ACTIVE (1 << 9)
>> > -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
>> > -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
>> > +
>> > +/* data buffer bytes 3-0 */
>> > +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET + 0xc)
>> > +/* interrupt mask (Pineview+) */
>> > +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET + 0x10)
>> > #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
>> > #define GMBUS_NAK_EN (1 << 3)
>> > #define GMBUS_IDLE_EN (1 << 2)
>> > #define GMBUS_HW_WAIT_EN (1 << 1)
>> > #define GMBUS_HW_RDY_EN (1 << 0)
>> > -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
>> > +/* byte index */
>> > +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
>> > + + GMBUS_OFFSET + 0x20)
>> > #define GMBUS_2BYTE_INDEX_EN (1 << 31)
>> >
>> > /*
>> > @@ -7668,13 +7678,6 @@ enum {
>> > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
>> > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>> >
>> > -#define PCH_GPIOA _MMIO(0xc5010)
>> > -#define PCH_GPIOB _MMIO(0xc5014)
>> > -#define PCH_GPIOC _MMIO(0xc5018)
>> > -#define PCH_GPIOD _MMIO(0xc501c)
>> > -#define PCH_GPIOE _MMIO(0xc5020)
>> > -#define PCH_GPIOF _MMIO(0xc5024)
>> > -
>> > #define PCH_GMBUS0 _MMIO(0xc5100)
>> > #define PCH_GMBUS1 _MMIO(0xc5104)
>> > #define PCH_GMBUS2 _MMIO(0xc5108)
>> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> > index 61e715ddd0d5..dedf87c58a95 100644
>> > --- a/drivers/gpu/drm/i915/intel_drv.h
>> > +++ b/drivers/gpu/drm/i915/intel_drv.h
>> > @@ -152,6 +152,22 @@
>> > * Display related stuff
>> > */
>> >
>> > +enum i915_gpio {
>> > + GPIOA = 0,
>> > + GPIOB,
>> > + GPIOC,
>> > + GPIOD,
>> > + GPIOE,
>> > + GPIOF,
>> > + GPIOG,
>> > + GPIOH,
>> > + __GPIOI_UNUSED,
>> > + GPIOJ,
>> > + GPIOK,
>> > + GPIOL,
>> > + GPIOM,
>> > +};
>> > +
>> > /* store information about an Ixxx DVO */
>> > /* The i830->i865 use multiple DVOs with multiple i2cs */
>> > /* the i915, i945 have a single sDVO i2c bus - which is different */
>> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> > index 97606c1be70d..f1c0b974daa6 100644
>> > --- a/drivers/gpu/drm/i915/intel_i2c.c
>> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> > @@ -37,7 +37,7 @@
>> >
>> > struct gmbus_pin {
>> > const char *name;
>> > - i915_reg_t reg;
>> > + enum i915_gpio gpio;
>> > };
>> >
>> > /* Map gmbus pin pairs to names and registers. */
>> > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>> > else
>> > size = ARRAY_SIZE(gmbus_pins);
>> >
>> > - return pin < size &&
>> > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
>> > + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
>> > }
>> >
>> > /* Intel GPIO access functions */
>> > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>> >
>> > algo = &bus->bit_algo;
>> >
>> > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
>> > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
>> > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
>> > bus->adapter.algo_data = algo;
>> > algo->setsda = set_data;
>> > algo->setscl = set_clock;
>> > @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
>> > return 0;
>> >
>> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> > - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
>> > + dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
>> > else if (!HAS_GMCH_DISPLAY(dev_priv))
>> > - dev_priv->gpio_mmio_base =
>> > - i915_mmio_reg_offset(PCH_GPIOA) -
>> > - i915_mmio_reg_offset(GPIOA);
>> > + dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
>> > + else
>> > + dev_priv->gpio_mmio_base = GPIO_OFFSET;
>> >
>> > mutex_init(&dev_priv->gmbus_mutex);
>> > init_waitqueue_head(&dev_priv->gmbus_wait_queue);
>> > --
>> > 2.17.1
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-12 17:03 ` Daniel Vetter
@ 2018-07-12 17:23 ` Ville Syrjälä
2018-07-13 8:48 ` Daniel Vetter
0 siblings, 1 reply; 10+ messages in thread
From: Ville Syrjälä @ 2018-07-12 17:23 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Rodrigo Vivi, Lucas De Marchi
On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> <lucas.de.marchi@gmail.com> wrote:
> > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> >> > that has the same address as PCH_GPIO_A and use that to calculate all
> >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> >> > the same thing.
> >> >
> >> > This also rewrites the GMBUS[05] registers since they depend on
> >> > gpio_mmio_base.
> >> >
> >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> >> > macro to return a particular gpio address and move the enum out of
> >> > i915_reg.h (suggested by Jani)
> >> >
> >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
> >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
> >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
> >> > 4 files changed, 52 insertions(+), 35 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> >> > index e39492aaff6c..e25a74fe753b 100644
> >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> >> >
> >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> >> > gmbus_mmio_write);
> >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >> >
> >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 0424e45f88db..f8f71d577613 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> >> > /*
> >> > * GPIO regs
> >> > */
> >> > -#define GPIOA _MMIO(0x5010)
> >> > -#define GPIOB _MMIO(0x5014)
> >> > -#define GPIOC _MMIO(0x5018)
> >> > -#define GPIOD _MMIO(0x501c)
> >> > -#define GPIOE _MMIO(0x5020)
> >> > -#define GPIOF _MMIO(0x5024)
> >> > -#define GPIOG _MMIO(0x5028)
> >> > -#define GPIOH _MMIO(0x502c)
> >> > -#define GPIOJ _MMIO(0x5034)
> >> > -#define GPIOK _MMIO(0x5038)
> >> > -#define GPIOL _MMIO(0x503C)
> >> > -#define GPIOM _MMIO(0x5040)
> >> > +#define GPIO_OFFSET 0x5010u
> >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
> >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
> >>
> >> This is a rather peculiar choice of baseline address. I'd either go with
> >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
> >
> > I'm all for a round 0x50000 number, however it doesn't match the spec.
> > I don't understand how 0x0 would make sense here. Are you suggesting to
> > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
> >
> > #define GPIO_OFFSET 0x5010u
> > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
> > #define PCH_GPIO_BASE 0xc0000u
> > #define VLV_GPIO_BASE VLV_DISPLAY_BASE
> > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
>
> Yeah that's what I had in mind.
I think I like this one the most. Keeps the 0x5010 in the GPIO() macro
so less confusion when looking it up in the spec (except on PCH platforms
perhaps).
Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and
just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something
like that.
I've occasionally pondered about some kind of generic south_display_base
thing that could maybe cover all the things that live on the PCH side on
those platforms. But I never bothered to look at all the register offsets
hard enough to figure out whether it'd be actually useful.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-12 17:23 ` Ville Syrjälä
@ 2018-07-13 8:48 ` Daniel Vetter
2018-07-13 12:21 ` Ville Syrjälä
0 siblings, 1 reply; 10+ messages in thread
From: Daniel Vetter @ 2018-07-13 8:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi, Lucas De Marchi
On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> > <lucas.de.marchi@gmail.com> wrote:
> > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> > >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> > >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > >> > that has the same address as PCH_GPIO_A and use that to calculate all
> > >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > >> > the same thing.
> > >> >
> > >> > This also rewrites the GMBUS[05] registers since they depend on
> > >> > gpio_mmio_base.
> > >> >
> > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > >> > macro to return a particular gpio address and move the enum out of
> > >> > i915_reg.h (suggested by Jani)
> > >> >
> > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > >> > ---
> > >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
> > >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
> > >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
> > >> > 4 files changed, 52 insertions(+), 35 deletions(-)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > >> > index e39492aaff6c..e25a74fe753b 100644
> > >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> > >> >
> > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > >> > gmbus_mmio_write);
> > >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> > >> >
> > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > >> > index 0424e45f88db..f8f71d577613 100644
> > >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> > >> > /*
> > >> > * GPIO regs
> > >> > */
> > >> > -#define GPIOA _MMIO(0x5010)
> > >> > -#define GPIOB _MMIO(0x5014)
> > >> > -#define GPIOC _MMIO(0x5018)
> > >> > -#define GPIOD _MMIO(0x501c)
> > >> > -#define GPIOE _MMIO(0x5020)
> > >> > -#define GPIOF _MMIO(0x5024)
> > >> > -#define GPIOG _MMIO(0x5028)
> > >> > -#define GPIOH _MMIO(0x502c)
> > >> > -#define GPIOJ _MMIO(0x5034)
> > >> > -#define GPIOK _MMIO(0x5038)
> > >> > -#define GPIOL _MMIO(0x503C)
> > >> > -#define GPIOM _MMIO(0x5040)
> > >> > +#define GPIO_OFFSET 0x5010u
> > >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
> > >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
> > >>
> > >> This is a rather peculiar choice of baseline address. I'd either go with
> > >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
> > >
> > > I'm all for a round 0x50000 number, however it doesn't match the spec.
> > > I don't understand how 0x0 would make sense here. Are you suggesting to
> > > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
> > >
> > > #define GPIO_OFFSET 0x5010u
> > > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
> > > #define PCH_GPIO_BASE 0xc0000u
> > > #define VLV_GPIO_BASE VLV_DISPLAY_BASE
> > > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
> >
> > Yeah that's what I had in mind.
>
> I think I like this one the most. Keeps the 0x5010 in the GPIO() macro
> so less confusion when looking it up in the spec (except on PCH platforms
> perhaps).
>
> Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and
> just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something
> like that.
>
> I've occasionally pondered about some kind of generic south_display_base
> thing that could maybe cover all the things that live on the PCH side on
> those platforms. But I never bothered to look at all the register offsets
> hard enough to figure out whether it'd be actually useful.
Problem with a generic south_display_base is that some things moved
between south and north block. So not sure the generic south_display_base
would actually be all that useful.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-13 8:48 ` Daniel Vetter
@ 2018-07-13 12:21 ` Ville Syrjälä
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2018-07-13 12:21 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Rodrigo Vivi, Lucas De Marchi
n Fri, Jul 13, 2018 at 10:48:02AM +0200, Daniel Vetter wrote:
> On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote:
> > > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi
> > > <lucas.de.marchi@gmail.com> wrote:
> > > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote:
> > > >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote:
> > > >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > > >> > that has the same address as PCH_GPIO_A and use that to calculate all
> > > >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > > >> > the same thing.
> > > >> >
> > > >> > This also rewrites the GMBUS[05] registers since they depend on
> > > >> > gpio_mmio_base.
> > > >> >
> > > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > > >> > macro to return a particular gpio address and move the enum out of
> > > >> > i915_reg.h (suggested by Jani)
> > > >> >
> > > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > >> > ---
> > > >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > > >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
> > > >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
> > > >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
> > > >> > 4 files changed, 52 insertions(+), 35 deletions(-)
> > > >> >
> > > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > > >> > index e39492aaff6c..e25a74fe753b 100644
> > > >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> > > >> >
> > > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > > >> > gmbus_mmio_write);
> > > >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> > > >> >
> > > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> > > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > >> > index 0424e45f88db..f8f71d577613 100644
> > > >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id {
> > > >> > /*
> > > >> > * GPIO regs
> > > >> > */
> > > >> > -#define GPIOA _MMIO(0x5010)
> > > >> > -#define GPIOB _MMIO(0x5014)
> > > >> > -#define GPIOC _MMIO(0x5018)
> > > >> > -#define GPIOD _MMIO(0x501c)
> > > >> > -#define GPIOE _MMIO(0x5020)
> > > >> > -#define GPIOF _MMIO(0x5024)
> > > >> > -#define GPIOG _MMIO(0x5028)
> > > >> > -#define GPIOH _MMIO(0x502c)
> > > >> > -#define GPIOJ _MMIO(0x5034)
> > > >> > -#define GPIOK _MMIO(0x5038)
> > > >> > -#define GPIOL _MMIO(0x503C)
> > > >> > -#define GPIOM _MMIO(0x5040)
> > > >> > +#define GPIO_OFFSET 0x5010u
> > > >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
> > > >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
> > > >>
> > > >> This is a rather peculiar choice of baseline address. I'd either go with
> > > >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros).
> > > >
> > > > I'm all for a round 0x50000 number, however it doesn't match the spec.
> > > > I don't understand how 0x0 would make sense here. Are you suggesting to
> > > > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE?
> > > >
> > > > #define GPIO_OFFSET 0x5010u
> > > > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */
> > > > #define PCH_GPIO_BASE 0xc0000u
> > > > #define VLV_GPIO_BASE VLV_DISPLAY_BASE
> > > > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio))
> > >
> > > Yeah that's what I had in mind.
> >
> > I think I like this one the most. Keeps the 0x5010 in the GPIO() macro
> > so less confusion when looking it up in the spec (except on PCH platforms
> > perhaps).
> >
> > Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and
> > just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something
> > like that.
> >
> > I've occasionally pondered about some kind of generic south_display_base
> > thing that could maybe cover all the things that live on the PCH side on
> > those platforms. But I never bothered to look at all the register offsets
> > hard enough to figure out whether it'd be actually useful.
>
> Problem with a generic south_display_base is that some things moved
> between south and north block. So not sure the generic south_display_base
> would actually be all that useful.
Yeah. And of course there are things like backlight that lives on
both sides of the divide on some platforms.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-07-13 12:21 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-09 16:22 [PATCH 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-09 16:22 ` [PATCH 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
2018-07-09 16:46 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
2018-07-10 1:15 ` ✓ Fi.CI.IGT: " Patchwork
2018-07-12 15:04 ` [PATCH 1/2] " Daniel Vetter
2018-07-12 16:24 ` Lucas De Marchi
2018-07-12 17:03 ` Daniel Vetter
2018-07-12 17:23 ` Ville Syrjälä
2018-07-13 8:48 ` Daniel Vetter
2018-07-13 12:21 ` Ville Syrjälä
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