From: Aapo Vienamo <avienamo@nvidia.com> To: Thierry Reding <thierry.reding@gmail.com> Cc: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Jonathan Hunter <jonathanh@nvidia.com>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Date: Thu, 9 Aug 2018 14:45:15 +0300 [thread overview] Message-ID: <20180809144515.06089abe@dhcp-10-21-25-168> (raw) In-Reply-To: <20180809113609.GI21639@ulmo> On Thu, 9 Aug 2018 13:36:09 +0200 Thierry Reding <thierry.reding@gmail.com> wrote: > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote: > > Document HS400 DQS trim value device tree property. > > > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > > --- > > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > index 3c7960a..7d294f3 100644 > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186: > > trimmer value for non-tunable modes. > > - nvidia,default-trim : Specify the default outbound clock trimmer > > value. > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing > > > > Notes on the pad calibration pull up and pulldown offset values: > > - The property values are drive codes which are programmed into the > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186: > > - The values are programmed to the Vendor Clock Control Register. > > Please refer to the reference manual of the SoC for correct > > values. > > + - The DQS trim values are only used on controllers which support > > + HS400 timing. > > One of these additions says "DQS trim values", the other says "DQS trim > value". It is unclear from the above how many values there are. I think > this should be more explicit. Also, I don't see why the note about which > controllers the DQS trim value(s) applies to is in a separate paragraph. > Couldn't it be moved to the property description? It's a single value. The plural form is a mistake. > Also, I think the bindings should specify which generations of Tegra do > support HS400. Where else are people supposed to find that information? This property is under the "Optional properties for Tegra210 and Tegra186" section and it only applies for the said generations. -Aapo
WARNING: multiple messages have this Message-ID (diff)
From: Aapo Vienamo <avienamo@nvidia.com> To: Thierry Reding <thierry.reding@gmail.com> Cc: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Jonathan Hunter <jonathanh@nvidia.com>, Adrian Hunter <adrian.hunter@intel.com>, "Mikko Perttunen" <mperttunen@nvidia.com>, <linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Date: Thu, 9 Aug 2018 14:45:15 +0300 [thread overview] Message-ID: <20180809144515.06089abe@dhcp-10-21-25-168> (raw) In-Reply-To: <20180809113609.GI21639@ulmo> On Thu, 9 Aug 2018 13:36:09 +0200 Thierry Reding <thierry.reding@gmail.com> wrote: > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote: > > Document HS400 DQS trim value device tree property. > > > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > > --- > > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > index 3c7960a..7d294f3 100644 > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186: > > trimmer value for non-tunable modes. > > - nvidia,default-trim : Specify the default outbound clock trimmer > > value. > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing > > > > Notes on the pad calibration pull up and pulldown offset values: > > - The property values are drive codes which are programmed into the > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186: > > - The values are programmed to the Vendor Clock Control Register. > > Please refer to the reference manual of the SoC for correct > > values. > > + - The DQS trim values are only used on controllers which support > > + HS400 timing. > > One of these additions says "DQS trim values", the other says "DQS trim > value". It is unclear from the above how many values there are. I think > this should be more explicit. Also, I don't see why the note about which > controllers the DQS trim value(s) applies to is in a separate paragraph. > Couldn't it be moved to the property description? It's a single value. The plural form is a mistake. > Also, I think the bindings should specify which generations of Tegra do > support HS400. Where else are people supposed to find that information? This property is under the "Optional properties for Tegra210 and Tegra186" section and it only applies for the said generations. -Aapo
next prev parent reply other threads:[~2018-08-09 11:45 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-07 13:59 [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Aapo Vienamo 2018-08-07 13:59 ` Aapo Vienamo 2018-08-07 13:59 ` [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Aapo Vienamo 2018-08-07 13:59 ` Aapo Vienamo 2018-08-09 11:36 ` Thierry Reding 2018-08-09 11:45 ` Aapo Vienamo [this message] 2018-08-09 11:45 ` Aapo Vienamo 2018-08-09 13:46 ` Thierry Reding 2018-08-09 14:06 ` Aapo Vienamo 2018-08-09 14:06 ` Aapo Vienamo 2018-08-09 14:09 ` Thierry Reding 2018-08-07 13:59 ` [PATCH 2/8] mmc: tegra: Parse and program DQS trim value Aapo Vienamo 2018-08-07 13:59 ` Aapo Vienamo 2018-08-09 11:40 ` Thierry Reding 2018-08-09 11:42 ` Thierry Reding 2018-08-07 13:59 ` [PATCH 3/8] mmc: tegra: Implement HS400 enhanced strobe Aapo Vienamo 2018-08-07 13:59 ` Aapo Vienamo 2018-08-09 11:43 ` Thierry Reding 2018-08-09 12:22 ` Aapo Vienamo 2018-08-09 12:22 ` Aapo Vienamo 2018-08-09 13:47 ` Thierry Reding 2018-08-07 14:00 ` [PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration Aapo Vienamo 2018-08-07 14:00 ` Aapo Vienamo 2018-08-09 11:48 ` Thierry Reding 2018-08-09 12:29 ` Aapo Vienamo 2018-08-09 12:29 ` Aapo Vienamo 2018-08-07 14:00 ` [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Aapo Vienamo 2018-08-07 14:00 ` Aapo Vienamo 2018-08-09 11:49 ` Thierry Reding 2018-08-09 12:02 ` Aapo Vienamo 2018-08-09 12:02 ` Aapo Vienamo 2018-08-09 12:23 ` Peter Geis 2018-08-09 12:37 ` Aapo Vienamo 2018-08-09 12:37 ` Aapo Vienamo 2018-08-09 12:50 ` Peter Geis 2018-08-09 13:52 ` Thierry Reding 2018-08-07 14:00 ` [PATCH 6/8] arm64: dts: tegra210: " Aapo Vienamo 2018-08-07 14:00 ` Aapo Vienamo 2018-08-07 14:00 ` [PATCH 7/8] arm64: dts: tegra186: Enable HS400 Aapo Vienamo 2018-08-07 14:00 ` Aapo Vienamo 2018-08-07 14:00 ` [PATCH 8/8] arm64: dts: tegra210: " Aapo Vienamo 2018-08-07 14:00 ` Aapo Vienamo
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