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From: Palmer Dabbelt <palmer@sifive.com>
To: linux-riscv@lists.infradead.org
Cc: Palmer Dabbelt <palmer@sifive.com>,
	aou@eecs.berkeley.edu, daniel.lezcano@linaro.org,
	tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
	atish.patra@wdc.com, dmitriy@oss-tech.org,
	catalin.marinas@arm.com, ard.biesheuvel@linaro.org,
	Greg KH <gregkh@linuxfoundation.org>,
	jeremy.linton@arm.com, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 8/8] RISC-V: Disable preemption before enabling interrupts when booting secondary harts
Date: Mon, 27 Aug 2018 11:42:43 -0700	[thread overview]
Message-ID: <20180827184243.25344-9-palmer@sifive.com> (raw)
In-Reply-To: <20180827184243.25344-1-palmer@sifive.com>

I'm not sure, but I think this was a bug: if the scheduler fired right
here then I believe it would blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 arch/riscv/kernel/smpboot.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 953bc540207d..45515cc70181 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -110,7 +110,9 @@ asmlinkage void __init smp_callin(void)
 	/* Remote TLB flushes are ignored while the CPU is offline, so emit a local
 	 * TLB flush right now just in case. */
 	local_flush_tlb_all();
-	local_irq_enable();
+	/* Disable preemption before enabling interrupts, so we don't try to
+	 * schedule a CPU that hasn't actually started yet. */
 	preempt_disable();
+	local_irq_enable();
 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 }
-- 
2.16.4


WARNING: multiple messages have this Message-ID (diff)
From: palmer@sifive.com (Palmer Dabbelt)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 8/8] RISC-V: Disable preemption before enabling interrupts when booting secondary harts
Date: Mon, 27 Aug 2018 11:42:43 -0700	[thread overview]
Message-ID: <20180827184243.25344-9-palmer@sifive.com> (raw)
In-Reply-To: <20180827184243.25344-1-palmer@sifive.com>

I'm not sure, but I think this was a bug: if the scheduler fired right
here then I believe it would blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 arch/riscv/kernel/smpboot.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 953bc540207d..45515cc70181 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -110,7 +110,9 @@ asmlinkage void __init smp_callin(void)
 	/* Remote TLB flushes are ignored while the CPU is offline, so emit a local
 	 * TLB flush right now just in case. */
 	local_flush_tlb_all();
-	local_irq_enable();
+	/* Disable preemption before enabling interrupts, so we don't try to
+	 * schedule a CPU that hasn't actually started yet. */
 	preempt_disable();
+	local_irq_enable();
 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 }
-- 
2.16.4

  parent reply	other threads:[~2018-08-27 18:58 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-27 18:42 [PATCH 0/8] RISC-V: Assorted Cleanups Palmer Dabbelt
2018-08-27 18:42 ` Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 1/8] RISC-V: Provide a cleaner raw_smp_processor_id() Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-30 14:37   ` Christoph Hellwig
2018-08-30 14:37     ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 2/8] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} Palmer Dabbelt
2018-08-27 18:42   ` [PATCH 2/8] RISC-V: Don't set cacheinfo.{physical_line_partition, attributes} Palmer Dabbelt
2018-08-30 14:38   ` Christoph Hellwig
2018-08-30 14:38     ` Christoph Hellwig
2018-08-30 19:50   ` [PATCH 2/8] RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} Jeremy Linton
2018-08-30 19:50     ` Jeremy Linton
2018-08-27 18:42 ` [PATCH 3/8] RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-28 18:50   ` Atish Patra
2018-08-28 18:50     ` Atish Patra
2018-08-30 14:40   ` Christoph Hellwig
2018-08-30 14:40     ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 4/8] RISC-V: Filter ISA and MMU values in cpuinfo Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 5/8] RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-30 14:41   ` Christoph Hellwig
2018-08-30 14:41     ` Christoph Hellwig
2018-08-30 16:11     ` Atish Patra
2018-08-30 16:11       ` Atish Patra
2018-08-31  5:54       ` Christoph Hellwig
2018-08-31  5:54         ` Christoph Hellwig
2018-08-31 21:18         ` Atish Patra
2018-08-31 21:18           ` Atish Patra
2018-09-06  9:45           ` Palmer Dabbelt
2018-09-06  9:45             ` Palmer Dabbelt
2018-09-06  9:45       ` Palmer Dabbelt
2018-09-06  9:45         ` Palmer Dabbelt
2018-08-27 18:42 ` [PATCH 6/8] RISC-V: Use mmgrab() Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-30 14:41   ` Christoph Hellwig
2018-08-30 14:41     ` Christoph Hellwig
2018-08-27 18:42 ` [PATCH 7/8] RISC-V: Comment on the TLB flush in smp_callin() Palmer Dabbelt
2018-08-27 18:42   ` Palmer Dabbelt
2018-08-30 14:42   ` Christoph Hellwig
2018-08-30 14:42     ` Christoph Hellwig
2018-08-27 18:42 ` Palmer Dabbelt [this message]
2018-08-27 18:42   ` [PATCH 8/8] RISC-V: Disable preemption before enabling interrupts when booting secondary harts Palmer Dabbelt

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