* [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later
@ 2018-11-23 12:31 Thierry Reding
2018-11-23 12:31 ` [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186 Thierry Reding
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The register region allocated per channel was decreased from 16384 bytes
to 256 bytes on Tegra186 and later. Resize the region to make sure every
channel (instead of only the first) is properly programmed.
Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index d188f9068b91..95ea81172a83 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -26,7 +26,6 @@
#include "../intr.h"
#include "../job.h"
-#define HOST1X_CHANNEL_SIZE 16384
#define TRACE_MAX_LENGTH 128U
static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
@@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
unsigned int index)
{
- ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
+#if HOST1X_HW < 6
+ ch->regs = dev->regs + index * 0x4000;
+#else
+ ch->regs = dev->regs + index * 0x100;
+#endif
enable_gather_filter(dev, ch);
return 0;
}
--
2.19.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-26 11:15 ` Mikko Perttunen
2018-11-23 12:31 ` [PATCH 3/7] gpu: host1x: Add Tegra194 support Thierry Reding
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The number of syncpoints on Tegra186 is 576 and therefore no longer fits
into 8 bits. Increase the size of the syncpoint ID field to 10 in order
to accomodate all syncpoints.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
index 4457486c72b0..e599e15bf999 100644
--- a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
+++ b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
@@ -59,7 +59,7 @@ static inline u32 host1x_uclass_incr_syncpt_r(void)
host1x_uclass_incr_syncpt_r()
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
{
- return (v & 0xff) << 8;
+ return (v & 0xff) << 10;
}
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
host1x_uclass_incr_syncpt_cond_f(v)
--
2.19.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/7] gpu: host1x: Add Tegra194 support
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
2018-11-23 12:31 ` [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186 Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-26 11:22 ` Mikko Perttunen
2018-11-27 17:34 ` [PATCH v2] " Thierry Reding
2018-11-23 12:31 ` [PATCH 4/7] drm/tegra: vic: " Thierry Reding
` (5 subsequent siblings)
7 siblings, 2 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The host1x hardware found on Tegra194 is very similar to the version
found on Tegra186, with the notable exceptions of the increased number
of syncpoints and mlocks. In addition, some rarely used features such
as syncpoint wait bases were dropped and some registers had to move
around to accomodate the increased number of syncpoints.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/host1x/Makefile | 3 +-
drivers/gpu/host1x/dev.c | 13 ++
drivers/gpu/host1x/hw/host1x07.c | 44 +++++
drivers/gpu/host1x/hw/host1x07.h | 26 +++
drivers/gpu/host1x/hw/host1x07_hardware.h | 142 ++++++++++++++
.../gpu/host1x/hw/hw_host1x07_hypervisor.h | 32 ++++
drivers/gpu/host1x/hw/hw_host1x07_uclass.h | 181 ++++++++++++++++++
drivers/gpu/host1x/hw/hw_host1x07_vm.h | 46 +++++
drivers/gpu/host1x/hw/syncpt_hw.c | 4 +
9 files changed, 490 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/host1x/hw/host1x07.c
create mode 100644 drivers/gpu/host1x/hw/host1x07.h
create mode 100644 drivers/gpu/host1x/hw/host1x07_hardware.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_uclass.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_vm.h
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index b92016ce09b7..096017b8789d 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -13,6 +13,7 @@ host1x-y = \
hw/host1x02.o \
hw/host1x04.o \
hw/host1x05.o \
- hw/host1x06.o
+ hw/host1x06.o \
+ hw/host1x07.o
obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index de6bc4e7fa23..419d8929a98f 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -44,6 +44,7 @@
#include "hw/host1x04.h"
#include "hw/host1x05.h"
#include "hw/host1x06.h"
+#include "hw/host1x07.h"
void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
{
@@ -130,7 +131,19 @@ static const struct host1x_info host1x06_info = {
.has_hypervisor = true,
};
+static const struct host1x_info host1x07_info = {
+ .nb_channels = 63,
+ .nb_pts = 704,
+ .nb_mlocks = 32,
+ .nb_bases = 0,
+ .init = host1x07_init,
+ .sync_offset = 0x0,
+ .dma_mask = DMA_BIT_MASK(40),
+ .has_hypervisor = true,
+};
+
static const struct of_device_id host1x_of_match[] = {
+ { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
diff --git a/drivers/gpu/host1x/hw/host1x07.c b/drivers/gpu/host1x/hw/host1x07.c
new file mode 100644
index 000000000000..04b779a53f08
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07.c
@@ -0,0 +1,44 @@
+/*
+ * Host1x init for Tegra194 SoCs
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* include hw specification */
+#include "host1x07.h"
+#include "host1x07_hardware.h"
+
+/* include code */
+#define HOST1X_HW 7
+
+#include "cdma_hw.c"
+#include "channel_hw.c"
+#include "debug_hw.c"
+#include "intr_hw.c"
+#include "syncpt_hw.c"
+
+#include "../dev.h"
+
+int host1x07_init(struct host1x *host)
+{
+ host->channel_op = &host1x_channel_ops;
+ host->cdma_op = &host1x_cdma_ops;
+ host->cdma_pb_op = &host1x_pushbuffer_ops;
+ host->syncpt_op = &host1x_syncpt_ops;
+ host->intr_op = &host1x_intr_ops;
+ host->debug_op = &host1x_debug_ops;
+
+ return 0;
+}
diff --git a/drivers/gpu/host1x/hw/host1x07.h b/drivers/gpu/host1x/hw/host1x07.h
new file mode 100644
index 000000000000..57b19f354274
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07.h
@@ -0,0 +1,26 @@
+/*
+ * Host1x init for Tegra194 SoCs
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HOST1X_HOST1X07_H
+#define HOST1X_HOST1X07_H
+
+struct host1x;
+
+int host1x07_init(struct host1x *host);
+
+#endif
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
new file mode 100644
index 000000000000..1353e7ab71dd
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -0,0 +1,142 @@
+/*
+ * Tegra host1x Register Offsets for Tegra194
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __HOST1X_HOST1X07_HARDWARE_H
+#define __HOST1X_HOST1X07_HARDWARE_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#include "hw_host1x07_uclass.h"
+#include "hw_host1x07_vm.h"
+#include "hw_host1x07_hypervisor.h"
+
+static inline u32 host1x_class_host_wait_syncpt(
+ unsigned indx, unsigned threshold)
+{
+ return host1x_uclass_wait_syncpt_indx_f(indx)
+ | host1x_uclass_wait_syncpt_thresh_f(threshold);
+}
+
+static inline u32 host1x_class_host_load_syncpt_base(
+ unsigned indx, unsigned threshold)
+{
+ return host1x_uclass_load_syncpt_base_base_indx_f(indx)
+ | host1x_uclass_load_syncpt_base_value_f(threshold);
+}
+
+static inline u32 host1x_class_host_wait_syncpt_base(
+ unsigned indx, unsigned base_indx, unsigned offset)
+{
+ return host1x_uclass_wait_syncpt_base_indx_f(indx)
+ | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
+ | host1x_uclass_wait_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt_base(
+ unsigned base_indx, unsigned offset)
+{
+ return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
+ | host1x_uclass_incr_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt(
+ unsigned cond, unsigned indx)
+{
+ return host1x_uclass_incr_syncpt_cond_f(cond)
+ | host1x_uclass_incr_syncpt_indx_f(indx);
+}
+
+static inline u32 host1x_class_host_indoff_reg_write(
+ unsigned mod_id, unsigned offset, bool auto_inc)
+{
+ u32 v = host1x_uclass_indoff_indbe_f(0xf)
+ | host1x_uclass_indoff_indmodid_f(mod_id)
+ | host1x_uclass_indoff_indroffset_f(offset);
+ if (auto_inc)
+ v |= host1x_uclass_indoff_autoinc_f(1);
+ return v;
+}
+
+static inline u32 host1x_class_host_indoff_reg_read(
+ unsigned mod_id, unsigned offset, bool auto_inc)
+{
+ u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
+ | host1x_uclass_indoff_indroffset_f(offset)
+ | host1x_uclass_indoff_rwn_read_v();
+ if (auto_inc)
+ v |= host1x_uclass_indoff_autoinc_f(1);
+ return v;
+}
+
+/* cdma opcodes */
+static inline u32 host1x_opcode_setclass(
+ unsigned class_id, unsigned offset, unsigned mask)
+{
+ return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
+}
+
+static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
+{
+ return (1 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
+{
+ return (2 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
+{
+ return (3 << 28) | (offset << 16) | mask;
+}
+
+static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
+{
+ return (4 << 28) | (offset << 16) | value;
+}
+
+static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
+{
+ return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
+ host1x_class_host_incr_syncpt(cond, indx));
+}
+
+static inline u32 host1x_opcode_restart(unsigned address)
+{
+ return (5 << 28) | (address >> 4);
+}
+
+static inline u32 host1x_opcode_gather(unsigned count)
+{
+ return (6 << 28) | count;
+}
+
+static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
+{
+ return (6 << 28) | (offset << 16) | BIT(15) | count;
+}
+
+static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
+{
+ return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
+}
+
+#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
new file mode 100644
index 000000000000..2b99d68d3040
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
+#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1)
+#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(x) (x)
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(x) ((x) << 16)
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE BIT(31)
+#define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
+#define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
+#define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
+#define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
+#define HOST1X_HV_ICG_EN_OVERRIDE 0x2aa8
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_uclass.h b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
new file mode 100644
index 000000000000..7e4e3b377f91
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+ * Function naming determines intended use:
+ *
+ * <x>_r(void) : Returns the offset for register <x>.
+ *
+ * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ * and masked to place it at field <y> of register <x>. This value
+ * can be |'d with others to produce a full register value for
+ * register <x>.
+ *
+ * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
+ * value can be ~'d and then &'d to clear the value of field <y> for
+ * register <x>.
+ *
+ * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ * to place it at field <y> of register <x>. This value can be |'d
+ * with others to produce a full register value for <x>.
+ *
+ * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ * <x> value 'r' after being shifted to place its LSB at bit 0.
+ * This value is suitable for direct comparison with other unshifted
+ * values appropriate for use in field <y> of register <x>.
+ *
+ * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ * field <y> of register <x>. This value is suitable for direct
+ * comparison with unshifted values appropriate for use in field <y>
+ * of register <x>.
+ */
+
+#ifndef HOST1X_HW_HOST1X07_UCLASS_H
+#define HOST1X_HW_HOST1X07_UCLASS_H
+
+static inline u32 host1x_uclass_incr_syncpt_r(void)
+{
+ return 0x0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT \
+ host1x_uclass_incr_syncpt_r()
+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
+{
+ return (v & 0xff) << 10;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
+ host1x_uclass_incr_syncpt_cond_f(v)
+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
+{
+ return (v & 0xff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
+ host1x_uclass_incr_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_r(void)
+{
+ return 0x8;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT \
+ host1x_uclass_wait_syncpt_r()
+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
+ host1x_uclass_wait_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
+ host1x_uclass_wait_syncpt_thresh_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_r(void)
+{
+ return 0x9;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
+ host1x_uclass_wait_syncpt_base_r()
+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
+ host1x_uclass_wait_syncpt_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 16;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_wait_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
+{
+ return (v & 0xffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
+ host1x_uclass_wait_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_r(void)
+{
+ return 0xb;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
+ host1x_uclass_load_syncpt_base_r()
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_load_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
+ host1x_uclass_load_syncpt_base_value_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_incr_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
+ host1x_uclass_incr_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_indoff_r(void)
+{
+ return 0x2d;
+}
+#define HOST1X_UCLASS_INDOFF \
+ host1x_uclass_indoff_r()
+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
+{
+ return (v & 0xf) << 28;
+}
+#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
+ host1x_uclass_indoff_indbe_f(v)
+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
+{
+ return (v & 0x1) << 27;
+}
+#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
+ host1x_uclass_indoff_autoinc_f(v)
+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
+{
+ return (v & 0xff) << 18;
+}
+#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
+ host1x_uclass_indoff_indmodid_f(v)
+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
+{
+ return (v & 0xffff) << 2;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+ host1x_uclass_indoff_indroffset_f(v)
+static inline u32 host1x_uclass_indoff_rwn_read_v(void)
+{
+ return 1;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+ host1x_uclass_indoff_indroffset_f(v)
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_vm.h b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
new file mode 100644
index 000000000000..7e4629e77a2a
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_CHANNEL_DMASTART 0x0000
+#define HOST1X_CHANNEL_DMASTART_HI 0x0004
+#define HOST1X_CHANNEL_DMAPUT 0x0008
+#define HOST1X_CHANNEL_DMAPUT_HI 0x000c
+#define HOST1X_CHANNEL_DMAGET 0x0010
+#define HOST1X_CHANNEL_DMAGET_HI 0x0014
+#define HOST1X_CHANNEL_DMAEND 0x0018
+#define HOST1X_CHANNEL_DMAEND_HI 0x001c
+#define HOST1X_CHANNEL_DMACTRL 0x0020
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1)
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2)
+#define HOST1X_CHANNEL_CMDFIFO_STAT 0x0024
+#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13)
+#define HOST1X_CHANNEL_CMDFIFO_RDATA 0x0028
+#define HOST1X_CHANNEL_CMDP_OFFSET 0x0030
+#define HOST1X_CHANNEL_CMDP_CLASS 0x0034
+#define HOST1X_CHANNEL_CHANNELSTAT 0x0038
+#define HOST1X_CHANNEL_CMDPROC_STOP 0x0048
+#define HOST1X_CHANNEL_TEARDOWN 0x004c
+
+#define HOST1X_SYNC_SYNCPT_CPU_INCR(x) (0x6400 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x) (0x6464 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x) (0x652c + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x) (0x6590 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT(x) (0x8080 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_INT_THRESH(x) (0x8d00 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP(x) (0xa604 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
index a23bb3352d02..d946660d47f8 100644
--- a/drivers/gpu/host1x/hw/syncpt_hw.c
+++ b/drivers/gpu/host1x/hw/syncpt_hw.c
@@ -37,10 +37,12 @@ static void syncpt_restore(struct host1x_syncpt *sp)
*/
static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
{
+#if HOST1X_HW < 7
struct host1x *host = sp->host;
host1x_sync_writel(host, sp->base_val,
HOST1X_SYNC_SYNCPT_BASE(sp->id));
+#endif
}
/*
@@ -48,10 +50,12 @@ static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
*/
static void syncpt_read_wait_base(struct host1x_syncpt *sp)
{
+#if HOST1X_HW < 7
struct host1x *host = sp->host;
sp->base_val =
host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
+#endif
}
/*
--
2.19.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/7] drm/tegra: vic: Add Tegra194 support
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
2018-11-23 12:31 ` [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186 Thierry Reding
2018-11-23 12:31 ` [PATCH 3/7] gpu: host1x: Add Tegra194 support Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-26 11:23 ` Mikko Perttunen
2018-11-23 12:31 ` [PATCH 5/7] arm64: tegra: Add display support on Tegra194 Thierry Reding
` (4 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The Video Image Composer (VIC) generation found on Tegra194 is the same
as its predecessor found on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 65ea4988b332..4b70ce664c41 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1274,6 +1274,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
{ .compatible = "nvidia,tegra194-display", },
{ .compatible = "nvidia,tegra194-dc", },
{ .compatible = "nvidia,tegra194-sor", },
+ { .compatible = "nvidia,tegra194-vic", },
{ /* sentinel */ }
};
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index 9f657a63b0bb..94dd85c38e39 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -282,10 +282,18 @@ static const struct vic_config vic_t186_config = {
.version = 0x18,
};
+#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
+
+static const struct vic_config vic_t194_config = {
+ .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
+ .version = 0x19,
+};
+
static const struct of_device_id vic_match[] = {
{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
+ { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
{ },
};
@@ -418,3 +426,6 @@ MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
#endif
+#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
+MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
+#endif
--
2.19.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/7] arm64: tegra: Add display support on Tegra194
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
` (2 preceding siblings ...)
2018-11-23 12:31 ` [PATCH 4/7] drm/tegra: vic: " Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-23 12:31 ` [PATCH 6/7] arm64: tegra: Add VIC " Thierry Reding
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 335 +++++++++++++++++++++++
1 file changed, 335 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c2091bb16546..ce7481cb9e5b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/reset/tegra194-reset.h>
+#include <dt-bindings/power/tegra194-powergate.h>
/ {
compatible = "nvidia,tegra194";
@@ -35,6 +36,340 @@
gpio-controller;
};
+ host1x@13e00000 {
+ compatible = "nvidia,tegra194-host1x", "simple-bus";
+ reg = <0x13e00000 0x10000>,
+ <0x13e10000 0x10000>;
+ reg-names = "hypervisor", "vm";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_HOST1X>;
+ clock-names = "host1x";
+ resets = <&bpmp TEGRA194_RESET_HOST1X>;
+ reset-names = "host1x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x15000000 0x15000000 0x01000000>;
+
+ display-hub@15200000 {
+ compatible = "nvidia,tegra194-display", "simple-bus";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
+ <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
+ reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+ "wgrp3", "wgrp4", "wgrp5";
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
+ <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
+ clock-names = "disp", "hub";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x15200000 0x15200000 0x40000>;
+
+ display@15200000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15200000 0x10000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <0>;
+ };
+
+ display@15210000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15210000 0x10000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <1>;
+ };
+
+ display@15220000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15220000 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <2>;
+ };
+
+ display@15230000 {
+ compatible = "nvidia,tegra194-dc";
+ reg = <0x15230000 0x10000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
+ clock-names = "dc";
+ resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
+ reset-names = "dc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+
+ nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+ nvidia,head = <3>;
+ };
+ };
+
+ dpaux0: dpaux@155c0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155c0000 0x10000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux0_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux0_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux0_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux1: dpaux@155d0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155d0000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX1>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux1_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux1_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux1_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux2: dpaux@155e0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155e0000 0x10000>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX2>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux2_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux2_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux2_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dpaux3: dpaux@155f0000 {
+ compatible = "nvidia,tegra194-dpaux";
+ reg = <0x155f0000 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
+ <&bpmp TEGRA194_CLK_PLLDP>;
+ clock-names = "dpaux", "parent";
+ resets = <&bpmp TEGRA194_RESET_DPAUX3>;
+ reset-names = "dpaux";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+ state_dpaux3_aux: pinmux-aux {
+ groups = "dpaux-io";
+ function = "aux";
+ };
+
+ state_dpaux3_i2c: pinmux-i2c {
+ groups = "dpaux-io";
+ function = "i2c";
+ };
+
+ state_dpaux3_off: pinmux-off {
+ groups = "dpaux-io";
+ function = "off";
+ };
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ sor0: sor@15b00000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15b00000 0x40000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
+ <&bpmp TEGRA194_CLK_SOR0_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR0>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux0_aux>;
+ pinctrl-1 = <&state_dpaux0_i2c>;
+ pinctrl-2 = <&state_dpaux0_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <0>;
+ };
+
+ sor1: sor@15b40000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x155c0000 0x40000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
+ <&bpmp TEGRA194_CLK_SOR1_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD2>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR1>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux1_aux>;
+ pinctrl-1 = <&state_dpaux1_i2c>;
+ pinctrl-2 = <&state_dpaux1_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <1>;
+ };
+
+ sor2: sor@15b80000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15b80000 0x40000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
+ <&bpmp TEGRA194_CLK_SOR2_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD3>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR2>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux2_aux>;
+ pinctrl-1 = <&state_dpaux2_i2c>;
+ pinctrl-2 = <&state_dpaux2_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <2>;
+ };
+
+ sor3: sor@15bc0000 {
+ compatible = "nvidia,tegra194-sor";
+ reg = <0x15bc0000 0x40000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
+ <&bpmp TEGRA194_CLK_SOR3_OUT>,
+ <&bpmp TEGRA194_CLK_PLLD4>,
+ <&bpmp TEGRA194_CLK_PLLDP>,
+ <&bpmp TEGRA194_CLK_SOR_SAFE>,
+ <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
+ clock-names = "sor", "out", "parent", "dp", "safe",
+ "pad";
+ resets = <&bpmp TEGRA194_RESET_SOR3>;
+ reset-names = "sor";
+ pinctrl-0 = <&state_dpaux3_aux>;
+ pinctrl-1 = <&state_dpaux3_i2c>;
+ pinctrl-2 = <&state_dpaux3_off>;
+ pinctrl-names = "aux", "i2c", "off";
+ status = "disabled";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+ nvidia,interface = <0>;
+ };
+ };
+
ethernet@2490000 {
compatible = "nvidia,tegra186-eqos",
"snps,dwc-qos-ethernet-4.10";
--
2.19.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/7] arm64: tegra: Add VIC support on Tegra194
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
` (3 preceding siblings ...)
2018-11-23 12:31 ` [PATCH 5/7] arm64: tegra: Add display support on Tegra194 Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-23 12:31 ` [PATCH 7/7] arm64: tegra: Enable HDMI on P2972-0000 Thierry Reding
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ce7481cb9e5b..19cfddaea697 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -137,6 +137,18 @@
};
};
+ vic@15340000 {
+ compatible = "nvidia,tegra194-vic";
+ reg = <0x15340000 0x00040000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_VIC>;
+ clock-names = "vic";
+ resets = <&bpmp TEGRA194_RESET_VIC>;
+ reset-names = "vic";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
+ };
+
dpaux0: dpaux@155c0000 {
compatible = "nvidia,tegra194-dpaux";
reg = <0x155c0000 0x10000>;
--
2.19.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 7/7] arm64: tegra: Enable HDMI on P2972-0000
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
` (4 preceding siblings ...)
2018-11-23 12:31 ` [PATCH 6/7] arm64: tegra: Add VIC " Thierry Reding
@ 2018-11-23 12:31 ` Thierry Reding
2018-11-26 11:14 ` [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Mikko Perttunen
2018-11-26 15:11 ` Ilia Mirkin
7 siblings, 0 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-23 12:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies
from the PMIC to the display block. Also enable the display hub which is
responsible for instantiating the display controllers. Finally, enable
the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 15 +++++++++--
.../boot/dts/nvidia/tegra194-p2972-0000.dts | 25 +++++++++++++++++++
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 57d3f00464ce..204a207ff4bd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -163,7 +163,7 @@
in-ldo4-6-supply = <&vdd_5v0_sys>;
in-ldo7-8-supply = <&vdd_1v8ls>;
- sd0 {
+ vdd_1v0: sd0 {
regulator-name = "VDD_1V0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
@@ -171,7 +171,7 @@
regulator-boot-on;
};
- sd1 {
+ vdd_1v8hs: sd1 {
regulator-name = "VDD_1V8HS";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -262,5 +262,16 @@
regulator-always-on;
regulator-boot-on;
};
+
+ vdd_hdmi: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+
+ regulator-name = "VDD_5V0_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 86f05504ca38..cbae8e8b1281 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -13,6 +13,31 @@
status = "okay";
};
+ host1x@13e00000 {
+ display-hub@15200000 {
+ status = "okay";
+ };
+
+ dpaux@155e0000 {
+ status = "okay";
+ };
+
+ sor@15b80000 {
+ status = "okay";
+
+ avdd-io-supply = <&vdd_1v0>;
+ vdd-pll-supply = <&vdd_1v8hs>;
+ hdmi-supply = <&vdd_hdmi>;
+
+ nvidia,ddc-i2c-bus = <&ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ ddc: i2c@31c0000 {
+ status = "okay";
+ };
+
pwm@c340000 {
status = "okay";
};
--
2.19.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
` (5 preceding siblings ...)
2018-11-23 12:31 ` [PATCH 7/7] arm64: tegra: Enable HDMI on P2972-0000 Thierry Reding
@ 2018-11-26 11:14 ` Mikko Perttunen
2018-11-26 15:11 ` Ilia Mirkin
7 siblings, 0 replies; 15+ messages in thread
From: Mikko Perttunen @ 2018-11-26 11:14 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Jon Hunter, dri-devel, Mikko Perttunen
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
On 23.11.2018 14:31, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The register region allocated per channel was decreased from 16384 bytes
> to 256 bytes on Tegra186 and later. Resize the region to make sure every
> channel (instead of only the first) is properly programmed.
>
> Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
> index d188f9068b91..95ea81172a83 100644
> --- a/drivers/gpu/host1x/hw/channel_hw.c
> +++ b/drivers/gpu/host1x/hw/channel_hw.c
> @@ -26,7 +26,6 @@
> #include "../intr.h"
> #include "../job.h"
>
> -#define HOST1X_CHANNEL_SIZE 16384
> #define TRACE_MAX_LENGTH 128U
>
> static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
> @@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
> static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
> unsigned int index)
> {
> - ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
> +#if HOST1X_HW < 6
> + ch->regs = dev->regs + index * 0x4000;
> +#else
> + ch->regs = dev->regs + index * 0x100;
> +#endif
> enable_gather_filter(dev, ch);
> return 0;
> }
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186
2018-11-23 12:31 ` [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186 Thierry Reding
@ 2018-11-26 11:15 ` Mikko Perttunen
0 siblings, 0 replies; 15+ messages in thread
From: Mikko Perttunen @ 2018-11-26 11:15 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
On 23.11.2018 14:31, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The number of syncpoints on Tegra186 is 576 and therefore no longer fits
> into 8 bits. Increase the size of the syncpoint ID field to 10 in order
> to accomodate all syncpoints.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
> index 4457486c72b0..e599e15bf999 100644
> --- a/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
> +++ b/drivers/gpu/host1x/hw/hw_host1x06_uclass.h
> @@ -59,7 +59,7 @@ static inline u32 host1x_uclass_incr_syncpt_r(void)
> host1x_uclass_incr_syncpt_r()
> static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
> {
> - return (v & 0xff) << 8;
> + return (v & 0xff) << 10;
> }
> #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
> host1x_uclass_incr_syncpt_cond_f(v)
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/7] gpu: host1x: Add Tegra194 support
2018-11-23 12:31 ` [PATCH 3/7] gpu: host1x: Add Tegra194 support Thierry Reding
@ 2018-11-26 11:22 ` Mikko Perttunen
2018-11-27 17:34 ` [PATCH v2] " Thierry Reding
1 sibling, 0 replies; 15+ messages in thread
From: Mikko Perttunen @ 2018-11-26 11:22 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
On 23.11.2018 14:31, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The host1x hardware found on Tegra194 is very similar to the version
> found on Tegra186, with the notable exceptions of the increased number
> of syncpoints and mlocks. In addition, some rarely used features such
> as syncpoint wait bases were dropped and some registers had to move
> around to accomodate the increased number of syncpoints.
There are other significant changes that however don't affect the
currently implemented feature set, so it would be more correct to say
that it is mostly backwards compliant instead of similar. Otherwise,
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/gpu/host1x/Makefile | 3 +-
> drivers/gpu/host1x/dev.c | 13 ++
> drivers/gpu/host1x/hw/host1x07.c | 44 +++++
> drivers/gpu/host1x/hw/host1x07.h | 26 +++
> drivers/gpu/host1x/hw/host1x07_hardware.h | 142 ++++++++++++++
> .../gpu/host1x/hw/hw_host1x07_hypervisor.h | 32 ++++
> drivers/gpu/host1x/hw/hw_host1x07_uclass.h | 181 ++++++++++++++++++
> drivers/gpu/host1x/hw/hw_host1x07_vm.h | 46 +++++
> drivers/gpu/host1x/hw/syncpt_hw.c | 4 +
> 9 files changed, 490 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/host1x/hw/host1x07.c
> create mode 100644 drivers/gpu/host1x/hw/host1x07.h
> create mode 100644 drivers/gpu/host1x/hw/host1x07_hardware.h
> create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
> create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_uclass.h
> create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_vm.h
>
> ...
> +++ b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) 2018 NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
> +#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1)
> +#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
> +#define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
> +#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(x) (x)
> +#define HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(x) ((x) << 16)
> +#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE BIT(31)
> +#define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
> +#define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
> +#define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
> +#define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
> +#define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
> +#define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
> +#define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
The CMDFIFO registers are inaccessible on T194, so we should probably
remove the code accessing them on T194.
Otherwise LGTM.
> +#define HOST1X_HV_ICG_EN_OVERRIDE 0x2aa8
> diff --git a/drivers/gpu/host1x/hw/hw_host1x07_uclass.h b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
> new file mode 100644
> index 000000000000..7e4e3b377f91
> --- /dev/null
> +++ b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright (c) 2018 NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> + /*
> + * Function naming determines intended use:
> + *
> + * <x>_r(void) : Returns the offset for register <x>.
> + *
> + * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
> + *
> + * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
> + *
> + * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
> + * and masked to place it at field <y> of register <x>. This value
> + * can be |'d with others to produce a full register value for
> + * register <x>.
> + *
> + * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
> + * value can be ~'d and then &'d to clear the value of field <y> for
> + * register <x>.
> + *
> + * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
> + * to place it at field <y> of register <x>. This value can be |'d
> + * with others to produce a full register value for <x>.
> + *
> + * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
> + * <x> value 'r' after being shifted to place its LSB at bit 0.
> + * This value is suitable for direct comparison with other unshifted
> + * values appropriate for use in field <y> of register <x>.
> + *
> + * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
> + * field <y> of register <x>. This value is suitable for direct
> + * comparison with unshifted values appropriate for use in field <y>
> + * of register <x>.
> + */
> +
> +#ifndef HOST1X_HW_HOST1X07_UCLASS_H
> +#define HOST1X_HW_HOST1X07_UCLASS_H
> +
> +static inline u32 host1x_uclass_incr_syncpt_r(void)
> +{
> + return 0x0;
> +}
> +#define HOST1X_UCLASS_INCR_SYNCPT \
> + host1x_uclass_incr_syncpt_r()
> +static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
> +{
> + return (v & 0xff) << 10;
> +}
> +#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
> + host1x_uclass_incr_syncpt_cond_f(v)
> +static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
> +{
> + return (v & 0xff) << 0;
> +}
> +#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
> + host1x_uclass_incr_syncpt_indx_f(v)
> +static inline u32 host1x_uclass_wait_syncpt_r(void)
> +{
> + return 0x8;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT \
> + host1x_uclass_wait_syncpt_r()
> +static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
> +{
> + return (v & 0xff) << 24;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
> + host1x_uclass_wait_syncpt_indx_f(v)
> +static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
> +{
> + return (v & 0xffffff) << 0;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
> + host1x_uclass_wait_syncpt_thresh_f(v)
> +static inline u32 host1x_uclass_wait_syncpt_base_r(void)
> +{
> + return 0x9;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
> + host1x_uclass_wait_syncpt_base_r()
> +static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
> +{
> + return (v & 0xff) << 24;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
> + host1x_uclass_wait_syncpt_base_indx_f(v)
> +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
> +{
> + return (v & 0xff) << 16;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
> + host1x_uclass_wait_syncpt_base_base_indx_f(v)
> +static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
> +{
> + return (v & 0xffff) << 0;
> +}
> +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
> + host1x_uclass_wait_syncpt_base_offset_f(v)
> +static inline u32 host1x_uclass_load_syncpt_base_r(void)
> +{
> + return 0xb;
> +}
> +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
> + host1x_uclass_load_syncpt_base_r()
> +static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
> +{
> + return (v & 0xff) << 24;
> +}
> +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
> + host1x_uclass_load_syncpt_base_base_indx_f(v)
> +static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
> +{
> + return (v & 0xffffff) << 0;
> +}
> +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
> + host1x_uclass_load_syncpt_base_value_f(v)
> +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
> +{
> + return (v & 0xff) << 24;
> +}
> +#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
> + host1x_uclass_incr_syncpt_base_base_indx_f(v)
> +static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
> +{
> + return (v & 0xffffff) << 0;
> +}
> +#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
> + host1x_uclass_incr_syncpt_base_offset_f(v)
> +static inline u32 host1x_uclass_indoff_r(void)
> +{
> + return 0x2d;
> +}
> +#define HOST1X_UCLASS_INDOFF \
> + host1x_uclass_indoff_r()
> +static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
> +{
> + return (v & 0xf) << 28;
> +}
> +#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
> + host1x_uclass_indoff_indbe_f(v)
> +static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
> +{
> + return (v & 0x1) << 27;
> +}
> +#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
> + host1x_uclass_indoff_autoinc_f(v)
> +static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
> +{
> + return (v & 0xff) << 18;
> +}
> +#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
> + host1x_uclass_indoff_indmodid_f(v)
> +static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
> +{
> + return (v & 0xffff) << 2;
> +}
> +#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
> + host1x_uclass_indoff_indroffset_f(v)
> +static inline u32 host1x_uclass_indoff_rwn_read_v(void)
> +{
> + return 1;
> +}
> +#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
> + host1x_uclass_indoff_indroffset_f(v)
> +
> +#endif
> diff --git a/drivers/gpu/host1x/hw/hw_host1x07_vm.h b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
> new file mode 100644
> index 000000000000..7e4629e77a2a
> --- /dev/null
> +++ b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (c) 2018 NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#define HOST1X_CHANNEL_DMASTART 0x0000
> +#define HOST1X_CHANNEL_DMASTART_HI 0x0004
> +#define HOST1X_CHANNEL_DMAPUT 0x0008
> +#define HOST1X_CHANNEL_DMAPUT_HI 0x000c
> +#define HOST1X_CHANNEL_DMAGET 0x0010
> +#define HOST1X_CHANNEL_DMAGET_HI 0x0014
> +#define HOST1X_CHANNEL_DMAEND 0x0018
> +#define HOST1X_CHANNEL_DMAEND_HI 0x001c
> +#define HOST1X_CHANNEL_DMACTRL 0x0020
> +#define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
> +#define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1)
> +#define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2)
> +#define HOST1X_CHANNEL_CMDFIFO_STAT 0x0024
> +#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13)
> +#define HOST1X_CHANNEL_CMDFIFO_RDATA 0x0028
> +#define HOST1X_CHANNEL_CMDP_OFFSET 0x0030
> +#define HOST1X_CHANNEL_CMDP_CLASS 0x0034
> +#define HOST1X_CHANNEL_CHANNELSTAT 0x0038
> +#define HOST1X_CHANNEL_CMDPROC_STOP 0x0048
> +#define HOST1X_CHANNEL_TEARDOWN 0x004c
> +
> +#define HOST1X_SYNC_SYNCPT_CPU_INCR(x) (0x6400 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x) (0x6464 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x) (0x652c + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x) (0x6590 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT(x) (0x8080 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_INT_THRESH(x) (0x8d00 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_CH_APP(x) (0xa604 + 4 * (x))
> +#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
> diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
> index a23bb3352d02..d946660d47f8 100644
> --- a/drivers/gpu/host1x/hw/syncpt_hw.c
> +++ b/drivers/gpu/host1x/hw/syncpt_hw.c
> @@ -37,10 +37,12 @@ static void syncpt_restore(struct host1x_syncpt *sp)
> */
> static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
> {
> +#if HOST1X_HW < 7
> struct host1x *host = sp->host;
>
> host1x_sync_writel(host, sp->base_val,
> HOST1X_SYNC_SYNCPT_BASE(sp->id));
> +#endif
> }
>
> /*
> @@ -48,10 +50,12 @@ static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
> */
> static void syncpt_read_wait_base(struct host1x_syncpt *sp)
> {
> +#if HOST1X_HW < 7
> struct host1x *host = sp->host;
>
> sp->base_val =
> host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
> +#endif
> }
>
> /*
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/7] drm/tegra: vic: Add Tegra194 support
2018-11-23 12:31 ` [PATCH 4/7] drm/tegra: vic: " Thierry Reding
@ 2018-11-26 11:23 ` Mikko Perttunen
0 siblings, 0 replies; 15+ messages in thread
From: Mikko Perttunen @ 2018-11-26 11:23 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
On 23.11.2018 14:31, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The Video Image Composer (VIC) generation found on Tegra194 is the same
> as its predecessor found on Tegra186.
It is not the same, but like with Host1x itself the changes are not
visible here. With that fixed,
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/gpu/drm/tegra/drm.c | 1 +
> drivers/gpu/drm/tegra/vic.c | 11 +++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> index 65ea4988b332..4b70ce664c41 100644
> --- a/drivers/gpu/drm/tegra/drm.c
> +++ b/drivers/gpu/drm/tegra/drm.c
> @@ -1274,6 +1274,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
> { .compatible = "nvidia,tegra194-display", },
> { .compatible = "nvidia,tegra194-dc", },
> { .compatible = "nvidia,tegra194-sor", },
> + { .compatible = "nvidia,tegra194-vic", },
> { /* sentinel */ }
> };
>
> diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
> index 9f657a63b0bb..94dd85c38e39 100644
> --- a/drivers/gpu/drm/tegra/vic.c
> +++ b/drivers/gpu/drm/tegra/vic.c
> @@ -282,10 +282,18 @@ static const struct vic_config vic_t186_config = {
> .version = 0x18,
> };
>
> +#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
> +
> +static const struct vic_config vic_t194_config = {
> + .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
> + .version = 0x19,
> +};
> +
> static const struct of_device_id vic_match[] = {
> { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
> { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
> { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
> + { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
> { },
> };
>
> @@ -418,3 +426,6 @@ MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
> #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
> MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
> #endif
> +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
> +MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
> +#endif
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
` (6 preceding siblings ...)
2018-11-26 11:14 ` [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Mikko Perttunen
@ 2018-11-26 15:11 ` Ilia Mirkin
2018-11-26 15:30 ` Thierry Reding
7 siblings, 1 reply; 15+ messages in thread
From: Ilia Mirkin @ 2018-11-26 15:11 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, jonathanh, dri-devel, mperttunen
On Fri, Nov 23, 2018 at 7:31 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> From: Thierry Reding <treding@nvidia.com>
>
> The register region allocated per channel was decreased from 16384 bytes
> to 256 bytes on Tegra186 and later. Resize the region to make sure every
> channel (instead of only the first) is properly programmed.
>
> Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
> index d188f9068b91..95ea81172a83 100644
> --- a/drivers/gpu/host1x/hw/channel_hw.c
> +++ b/drivers/gpu/host1x/hw/channel_hw.c
> @@ -26,7 +26,6 @@
> #include "../intr.h"
> #include "../job.h"
>
> -#define HOST1X_CHANNEL_SIZE 16384
> #define TRACE_MAX_LENGTH 128U
>
> static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
> @@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
> static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
> unsigned int index)
> {
> - ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
> +#if HOST1X_HW < 6
> + ch->regs = dev->regs + index * 0x4000;
> +#else
> + ch->regs = dev->regs + index * 0x100;
> +#endif
Just an observation ... this makes it impossible to build this module
for multiple host1x hw revisions in the same kernel. I believe that
supporting multiple platforms is frequently desirable, but perhaps
there's more going on here (like arm64 vs arm32, etc).
Cheers,
-ilia
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later
2018-11-26 15:11 ` Ilia Mirkin
@ 2018-11-26 15:30 ` Thierry Reding
2018-11-26 16:02 ` Dmitry Osipenko
0 siblings, 1 reply; 15+ messages in thread
From: Thierry Reding @ 2018-11-26 15:30 UTC (permalink / raw)
To: Ilia Mirkin; +Cc: linux-tegra, jonathanh, dri-devel, mperttunen
[-- Attachment #1.1: Type: text/plain, Size: 2198 bytes --]
On Mon, Nov 26, 2018 at 10:11:39AM -0500, Ilia Mirkin wrote:
> On Fri, Nov 23, 2018 at 7:31 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The register region allocated per channel was decreased from 16384 bytes
> > to 256 bytes on Tegra186 and later. Resize the region to make sure every
> > channel (instead of only the first) is properly programmed.
> >
> > Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
> > index d188f9068b91..95ea81172a83 100644
> > --- a/drivers/gpu/host1x/hw/channel_hw.c
> > +++ b/drivers/gpu/host1x/hw/channel_hw.c
> > @@ -26,7 +26,6 @@
> > #include "../intr.h"
> > #include "../job.h"
> >
> > -#define HOST1X_CHANNEL_SIZE 16384
> > #define TRACE_MAX_LENGTH 128U
> >
> > static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
> > @@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
> > static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
> > unsigned int index)
> > {
> > - ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
> > +#if HOST1X_HW < 6
> > + ch->regs = dev->regs + index * 0x4000;
> > +#else
> > + ch->regs = dev->regs + index * 0x100;
> > +#endif
>
> Just an observation ... this makes it impossible to build this module
> for multiple host1x hw revisions in the same kernel. I believe that
> supporting multiple platforms is frequently desirable, but perhaps
> there's more going on here (like arm64 vs arm32, etc).
It actually does work. If you look close enough this file is included
multiple times by generation specific source files. It's sort of like
a template if you want.
It's not a design that's entirely to my liking, but it's not been a
strong enough itch to scratch for me to have gotten around to changing
how it works.
Thierry
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later
2018-11-26 15:30 ` Thierry Reding
@ 2018-11-26 16:02 ` Dmitry Osipenko
0 siblings, 0 replies; 15+ messages in thread
From: Dmitry Osipenko @ 2018-11-26 16:02 UTC (permalink / raw)
To: Thierry Reding, Ilia Mirkin; +Cc: linux-tegra, jonathanh, dri-devel, mperttunen
On 26.11.2018 18:30, Thierry Reding wrote:
> On Mon, Nov 26, 2018 at 10:11:39AM -0500, Ilia Mirkin wrote:
>> On Fri, Nov 23, 2018 at 7:31 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>>>
>>> From: Thierry Reding <treding@nvidia.com>
>>>
>>> The register region allocated per channel was decreased from 16384 bytes
>>> to 256 bytes on Tegra186 and later. Resize the region to make sure every
>>> channel (instead of only the first) is properly programmed.
>>>
>>> Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>>> ---
>>> drivers/gpu/host1x/hw/channel_hw.c | 7 +++++--
>>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
>>> index d188f9068b91..95ea81172a83 100644
>>> --- a/drivers/gpu/host1x/hw/channel_hw.c
>>> +++ b/drivers/gpu/host1x/hw/channel_hw.c
>>> @@ -26,7 +26,6 @@
>>> #include "../intr.h"
>>> #include "../job.h"
>>>
>>> -#define HOST1X_CHANNEL_SIZE 16384
>>> #define TRACE_MAX_LENGTH 128U
>>>
>>> static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
>>> @@ -203,7 +202,11 @@ static void enable_gather_filter(struct host1x *host,
>>> static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
>>> unsigned int index)
>>> {
>>> - ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
>>> +#if HOST1X_HW < 6
>>> + ch->regs = dev->regs + index * 0x4000;
>>> +#else
>>> + ch->regs = dev->regs + index * 0x100;
>>> +#endif
>>
>> Just an observation ... this makes it impossible to build this module
>> for multiple host1x hw revisions in the same kernel. I believe that
>> supporting multiple platforms is frequently desirable, but perhaps
>> there's more going on here (like arm64 vs arm32, etc).
>
> It actually does work. If you look close enough this file is included
> multiple times by generation specific source files. It's sort of like
> a template if you want.
>
> It's not a design that's entirely to my liking, but it's not been a
> strong enough itch to scratch for me to have gotten around to changing
> how it works.
I'm currently in process of rewriting host1x driver to make it usable for the new DRM job-submission [U]API. In the process of rewriting I tried to re-design this part of the driver to avoid duplication of the code by unifying all the code using "if (host->soc.hw_ver..", but yesterday returned to the initial template-variant because of the amount of code-churning that the if-else approach introduces, it is especially not nice with the more bitfield differences that newer HW has. Do you have any other suggestions?
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2] gpu: host1x: Add Tegra194 support
2018-11-23 12:31 ` [PATCH 3/7] gpu: host1x: Add Tegra194 support Thierry Reding
2018-11-26 11:22 ` Mikko Perttunen
@ 2018-11-27 17:34 ` Thierry Reding
1 sibling, 0 replies; 15+ messages in thread
From: Thierry Reding @ 2018-11-27 17:34 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Mikko Perttunen, dri-devel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The host1x hardware found on Tegra194 is mostly backwards compatible
with the version found on Tegra186, with the notable exceptions of the
increased number of syncpoints and mlocks. In addition, some rarely
used features such as syncpoint wait bases were dropped and some
registers had to move around to accomodate the increased number of
syncpoints.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- avoid accessing the HOST1X_HV_CMDFIFO_* registers
- reword commit message
drivers/gpu/host1x/Makefile | 3 +-
drivers/gpu/host1x/dev.c | 13 ++
drivers/gpu/host1x/hw/debug_hw_1x06.c | 7 +-
drivers/gpu/host1x/hw/host1x07.c | 44 +++++
drivers/gpu/host1x/hw/host1x07.h | 26 +++
drivers/gpu/host1x/hw/host1x07_hardware.h | 142 ++++++++++++++
.../gpu/host1x/hw/hw_host1x07_hypervisor.h | 32 ++++
drivers/gpu/host1x/hw/hw_host1x07_uclass.h | 181 ++++++++++++++++++
drivers/gpu/host1x/hw/hw_host1x07_vm.h | 46 +++++
drivers/gpu/host1x/hw/syncpt_hw.c | 4 +
10 files changed, 496 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/host1x/hw/host1x07.c
create mode 100644 drivers/gpu/host1x/hw/host1x07.h
create mode 100644 drivers/gpu/host1x/hw/host1x07_hardware.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_uclass.h
create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_vm.h
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index b92016ce09b7..096017b8789d 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -13,6 +13,7 @@ host1x-y = \
hw/host1x02.o \
hw/host1x04.o \
hw/host1x05.o \
- hw/host1x06.o
+ hw/host1x06.o \
+ hw/host1x07.o
obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index de6bc4e7fa23..419d8929a98f 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -44,6 +44,7 @@
#include "hw/host1x04.h"
#include "hw/host1x05.h"
#include "hw/host1x06.h"
+#include "hw/host1x07.h"
void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
{
@@ -130,7 +131,19 @@ static const struct host1x_info host1x06_info = {
.has_hypervisor = true,
};
+static const struct host1x_info host1x07_info = {
+ .nb_channels = 63,
+ .nb_pts = 704,
+ .nb_mlocks = 32,
+ .nb_bases = 0,
+ .init = host1x07_init,
+ .sync_offset = 0x0,
+ .dma_mask = DMA_BIT_MASK(40),
+ .has_hypervisor = true,
+};
+
static const struct of_device_id host1x_of_match[] = {
+ { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
diff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c
index b503c740c022..8b749516c051 100644
--- a/drivers/gpu/host1x/hw/debug_hw_1x06.c
+++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c
@@ -62,9 +62,12 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
struct host1x_channel *ch,
struct output *o)
{
- u32 val, rd_ptr, wr_ptr, start, end;
+#if HOST1X_HW <= 6
+ u32 rd_ptr, wr_ptr, start, end;
u32 payload = INVALID_PAYLOAD;
unsigned int data_count = 0;
+#endif
+ u32 val;
host1x_debug_output(o, "%u: fifo:\n", ch->id);
@@ -78,6 +81,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
+#if HOST1X_HW <= 6
/* Peek pointer values are invalid during SLCG, so disable it */
host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
@@ -127,6 +131,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);
host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);
+#endif
}
static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
diff --git a/drivers/gpu/host1x/hw/host1x07.c b/drivers/gpu/host1x/hw/host1x07.c
new file mode 100644
index 000000000000..04b779a53f08
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07.c
@@ -0,0 +1,44 @@
+/*
+ * Host1x init for Tegra194 SoCs
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* include hw specification */
+#include "host1x07.h"
+#include "host1x07_hardware.h"
+
+/* include code */
+#define HOST1X_HW 7
+
+#include "cdma_hw.c"
+#include "channel_hw.c"
+#include "debug_hw.c"
+#include "intr_hw.c"
+#include "syncpt_hw.c"
+
+#include "../dev.h"
+
+int host1x07_init(struct host1x *host)
+{
+ host->channel_op = &host1x_channel_ops;
+ host->cdma_op = &host1x_cdma_ops;
+ host->cdma_pb_op = &host1x_pushbuffer_ops;
+ host->syncpt_op = &host1x_syncpt_ops;
+ host->intr_op = &host1x_intr_ops;
+ host->debug_op = &host1x_debug_ops;
+
+ return 0;
+}
diff --git a/drivers/gpu/host1x/hw/host1x07.h b/drivers/gpu/host1x/hw/host1x07.h
new file mode 100644
index 000000000000..57b19f354274
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07.h
@@ -0,0 +1,26 @@
+/*
+ * Host1x init for Tegra194 SoCs
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HOST1X_HOST1X07_H
+#define HOST1X_HOST1X07_H
+
+struct host1x;
+
+int host1x07_init(struct host1x *host);
+
+#endif
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
new file mode 100644
index 000000000000..1353e7ab71dd
--- /dev/null
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -0,0 +1,142 @@
+/*
+ * Tegra host1x Register Offsets for Tegra194
+ *
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __HOST1X_HOST1X07_HARDWARE_H
+#define __HOST1X_HOST1X07_HARDWARE_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#include "hw_host1x07_uclass.h"
+#include "hw_host1x07_vm.h"
+#include "hw_host1x07_hypervisor.h"
+
+static inline u32 host1x_class_host_wait_syncpt(
+ unsigned indx, unsigned threshold)
+{
+ return host1x_uclass_wait_syncpt_indx_f(indx)
+ | host1x_uclass_wait_syncpt_thresh_f(threshold);
+}
+
+static inline u32 host1x_class_host_load_syncpt_base(
+ unsigned indx, unsigned threshold)
+{
+ return host1x_uclass_load_syncpt_base_base_indx_f(indx)
+ | host1x_uclass_load_syncpt_base_value_f(threshold);
+}
+
+static inline u32 host1x_class_host_wait_syncpt_base(
+ unsigned indx, unsigned base_indx, unsigned offset)
+{
+ return host1x_uclass_wait_syncpt_base_indx_f(indx)
+ | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
+ | host1x_uclass_wait_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt_base(
+ unsigned base_indx, unsigned offset)
+{
+ return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
+ | host1x_uclass_incr_syncpt_base_offset_f(offset);
+}
+
+static inline u32 host1x_class_host_incr_syncpt(
+ unsigned cond, unsigned indx)
+{
+ return host1x_uclass_incr_syncpt_cond_f(cond)
+ | host1x_uclass_incr_syncpt_indx_f(indx);
+}
+
+static inline u32 host1x_class_host_indoff_reg_write(
+ unsigned mod_id, unsigned offset, bool auto_inc)
+{
+ u32 v = host1x_uclass_indoff_indbe_f(0xf)
+ | host1x_uclass_indoff_indmodid_f(mod_id)
+ | host1x_uclass_indoff_indroffset_f(offset);
+ if (auto_inc)
+ v |= host1x_uclass_indoff_autoinc_f(1);
+ return v;
+}
+
+static inline u32 host1x_class_host_indoff_reg_read(
+ unsigned mod_id, unsigned offset, bool auto_inc)
+{
+ u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
+ | host1x_uclass_indoff_indroffset_f(offset)
+ | host1x_uclass_indoff_rwn_read_v();
+ if (auto_inc)
+ v |= host1x_uclass_indoff_autoinc_f(1);
+ return v;
+}
+
+/* cdma opcodes */
+static inline u32 host1x_opcode_setclass(
+ unsigned class_id, unsigned offset, unsigned mask)
+{
+ return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
+}
+
+static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
+{
+ return (1 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
+{
+ return (2 << 28) | (offset << 16) | count;
+}
+
+static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
+{
+ return (3 << 28) | (offset << 16) | mask;
+}
+
+static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
+{
+ return (4 << 28) | (offset << 16) | value;
+}
+
+static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
+{
+ return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
+ host1x_class_host_incr_syncpt(cond, indx));
+}
+
+static inline u32 host1x_opcode_restart(unsigned address)
+{
+ return (5 << 28) | (address >> 4);
+}
+
+static inline u32 host1x_opcode_gather(unsigned count)
+{
+ return (6 << 28) | count;
+}
+
+static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
+{
+ return (6 << 28) | (offset << 16) | BIT(15) | count;
+}
+
+static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
+{
+ return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
+}
+
+#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
new file mode 100644
index 000000000000..2b99d68d3040
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_hypervisor.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_HV_SYNCPT_PROT_EN 0x1ac4
+#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1)
+#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x2020 + (x * 4))
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL 0x233c
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(x) (x)
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(x) ((x) << 16)
+#define HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE BIT(31)
+#define HOST1X_HV_CMDFIFO_PEEK_READ 0x2340
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS 0x2344
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(x) (((x) >> 16) & 0xfff)
+#define HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(x) ((x) & 0xfff)
+#define HOST1X_HV_CMDFIFO_SETUP(x) (0x2588 + (x * 4))
+#define HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(x) (((x) >> 16) & 0xfff)
+#define HOST1X_HV_CMDFIFO_SETUP_BASE_V(x) ((x) & 0xfff)
+#define HOST1X_HV_ICG_EN_OVERRIDE 0x2aa8
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_uclass.h b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
new file mode 100644
index 000000000000..7e4e3b377f91
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_uclass.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+ /*
+ * Function naming determines intended use:
+ *
+ * <x>_r(void) : Returns the offset for register <x>.
+ *
+ * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ * and masked to place it at field <y> of register <x>. This value
+ * can be |'d with others to produce a full register value for
+ * register <x>.
+ *
+ * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
+ * value can be ~'d and then &'d to clear the value of field <y> for
+ * register <x>.
+ *
+ * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ * to place it at field <y> of register <x>. This value can be |'d
+ * with others to produce a full register value for <x>.
+ *
+ * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ * <x> value 'r' after being shifted to place its LSB at bit 0.
+ * This value is suitable for direct comparison with other unshifted
+ * values appropriate for use in field <y> of register <x>.
+ *
+ * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ * field <y> of register <x>. This value is suitable for direct
+ * comparison with unshifted values appropriate for use in field <y>
+ * of register <x>.
+ */
+
+#ifndef HOST1X_HW_HOST1X07_UCLASS_H
+#define HOST1X_HW_HOST1X07_UCLASS_H
+
+static inline u32 host1x_uclass_incr_syncpt_r(void)
+{
+ return 0x0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT \
+ host1x_uclass_incr_syncpt_r()
+static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
+{
+ return (v & 0xff) << 10;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
+ host1x_uclass_incr_syncpt_cond_f(v)
+static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
+{
+ return (v & 0xff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
+ host1x_uclass_incr_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_r(void)
+{
+ return 0x8;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT \
+ host1x_uclass_wait_syncpt_r()
+static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
+ host1x_uclass_wait_syncpt_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
+ host1x_uclass_wait_syncpt_thresh_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_r(void)
+{
+ return 0x9;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
+ host1x_uclass_wait_syncpt_base_r()
+static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
+ host1x_uclass_wait_syncpt_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 16;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_wait_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
+{
+ return (v & 0xffff) << 0;
+}
+#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
+ host1x_uclass_wait_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_r(void)
+{
+ return 0xb;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
+ host1x_uclass_load_syncpt_base_r()
+static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_load_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
+ host1x_uclass_load_syncpt_base_value_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
+{
+ return (v & 0xff) << 24;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
+ host1x_uclass_incr_syncpt_base_base_indx_f(v)
+static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
+{
+ return (v & 0xffffff) << 0;
+}
+#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
+ host1x_uclass_incr_syncpt_base_offset_f(v)
+static inline u32 host1x_uclass_indoff_r(void)
+{
+ return 0x2d;
+}
+#define HOST1X_UCLASS_INDOFF \
+ host1x_uclass_indoff_r()
+static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
+{
+ return (v & 0xf) << 28;
+}
+#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
+ host1x_uclass_indoff_indbe_f(v)
+static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
+{
+ return (v & 0x1) << 27;
+}
+#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
+ host1x_uclass_indoff_autoinc_f(v)
+static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
+{
+ return (v & 0xff) << 18;
+}
+#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
+ host1x_uclass_indoff_indmodid_f(v)
+static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
+{
+ return (v & 0xffff) << 2;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+ host1x_uclass_indoff_indroffset_f(v)
+static inline u32 host1x_uclass_indoff_rwn_read_v(void)
+{
+ return 1;
+}
+#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
+ host1x_uclass_indoff_indroffset_f(v)
+
+#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x07_vm.h b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
new file mode 100644
index 000000000000..7e4629e77a2a
--- /dev/null
+++ b/drivers/gpu/host1x/hw/hw_host1x07_vm.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#define HOST1X_CHANNEL_DMASTART 0x0000
+#define HOST1X_CHANNEL_DMASTART_HI 0x0004
+#define HOST1X_CHANNEL_DMAPUT 0x0008
+#define HOST1X_CHANNEL_DMAPUT_HI 0x000c
+#define HOST1X_CHANNEL_DMAGET 0x0010
+#define HOST1X_CHANNEL_DMAGET_HI 0x0014
+#define HOST1X_CHANNEL_DMAEND 0x0018
+#define HOST1X_CHANNEL_DMAEND_HI 0x001c
+#define HOST1X_CHANNEL_DMACTRL 0x0020
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1)
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2)
+#define HOST1X_CHANNEL_CMDFIFO_STAT 0x0024
+#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13)
+#define HOST1X_CHANNEL_CMDFIFO_RDATA 0x0028
+#define HOST1X_CHANNEL_CMDP_OFFSET 0x0030
+#define HOST1X_CHANNEL_CMDP_CLASS 0x0034
+#define HOST1X_CHANNEL_CHANNELSTAT 0x0038
+#define HOST1X_CHANNEL_CMDPROC_STOP 0x0048
+#define HOST1X_CHANNEL_TEARDOWN 0x004c
+
+#define HOST1X_SYNC_SYNCPT_CPU_INCR(x) (0x6400 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x) (0x6464 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x) (0x652c + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x) (0x6590 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT(x) (0x8080 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_INT_THRESH(x) (0x8d00 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP(x) (0xa604 + 4 * (x))
+#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
index a23bb3352d02..d946660d47f8 100644
--- a/drivers/gpu/host1x/hw/syncpt_hw.c
+++ b/drivers/gpu/host1x/hw/syncpt_hw.c
@@ -37,10 +37,12 @@ static void syncpt_restore(struct host1x_syncpt *sp)
*/
static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
{
+#if HOST1X_HW < 7
struct host1x *host = sp->host;
host1x_sync_writel(host, sp->base_val,
HOST1X_SYNC_SYNCPT_BASE(sp->id));
+#endif
}
/*
@@ -48,10 +50,12 @@ static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
*/
static void syncpt_read_wait_base(struct host1x_syncpt *sp)
{
+#if HOST1X_HW < 7
struct host1x *host = sp->host;
sp->base_val =
host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
+#endif
}
/*
--
2.19.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-11-27 17:34 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-23 12:31 [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Thierry Reding
2018-11-23 12:31 ` [PATCH 2/7] gpu: host1x: Fix syncpoint ID field size on Tegra186 Thierry Reding
2018-11-26 11:15 ` Mikko Perttunen
2018-11-23 12:31 ` [PATCH 3/7] gpu: host1x: Add Tegra194 support Thierry Reding
2018-11-26 11:22 ` Mikko Perttunen
2018-11-27 17:34 ` [PATCH v2] " Thierry Reding
2018-11-23 12:31 ` [PATCH 4/7] drm/tegra: vic: " Thierry Reding
2018-11-26 11:23 ` Mikko Perttunen
2018-11-23 12:31 ` [PATCH 5/7] arm64: tegra: Add display support on Tegra194 Thierry Reding
2018-11-23 12:31 ` [PATCH 6/7] arm64: tegra: Add VIC " Thierry Reding
2018-11-23 12:31 ` [PATCH 7/7] arm64: tegra: Enable HDMI on P2972-0000 Thierry Reding
2018-11-26 11:14 ` [PATCH 1/7] gpu: host1x: Resize channel register region on Tegra186 and later Mikko Perttunen
2018-11-26 15:11 ` Ilia Mirkin
2018-11-26 15:30 ` Thierry Reding
2018-11-26 16:02 ` Dmitry Osipenko
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