* [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
@ 2019-03-16 0:45 Lucas De Marchi
2019-03-16 1:32 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Lucas De Marchi @ 2019-03-16 0:45 UTC (permalink / raw)
To: intel-gfx
The caller already knows what platform that is and what register should
be used. Instead of keep adding if/else chains on a leaf functions,
let the caller pass the register.
We read cfgcr0 twice for CNL, but we were already doing that anyway.
icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
consistency with cnl_calc_wrpll_link().
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
5 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index beb30d9a855c..28f5da697693 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
- pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
+ ICL_DPLL_CFGCR0(pll_id),
+ ICL_DPLL_CFGCR1(pll_id));
pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
}
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 69aa0d148795..24675ef8b262 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
}
int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
- enum intel_dpll_id pll_id)
+ i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
{
u32 cfgcr0, cfgcr1;
u32 p0, p1, p2, dco_freq, ref_clock;
- if (INTEL_GEN(dev_priv) >= 11) {
- cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
- cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
- } else {
- cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
- cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
- }
+ cfgcr0 = I915_READ(cfgcr0_reg);
+ cfgcr1 = I915_READ(cfgcr1_reg);
p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
@@ -1471,17 +1466,23 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
enum port port = encoder->port;
int link_clock = 0;
u32 pll_id;
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+ cfgcr0_reg = ICL_DPLL_CFGCR0(pll_id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(pll_id);
+
if (intel_port_is_combophy(dev_priv, port)) {
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
- link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ link_clock = cnl_calc_wrpll_link(dev_priv, cfgcr0_reg,
+ cfgcr1_reg);
else
link_clock = icl_calc_dp_combo_pll_link(dev_priv,
- pll_id);
+ cfgcr0_reg,
+ cfgcr1_reg);
} else {
if (pll_id == DPLL_ID_ICL_TBTPLL)
link_clock = icl_calc_tbt_pll_link(dev_priv, port);
@@ -1506,7 +1507,9 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
- link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+ link_clock = cnl_calc_wrpll_link(dev_priv,
+ CNL_DPLL_CFGCR0(pll_id),
+ CNL_DPLL_CFGCR1(pll_id));
} else {
link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index ca975213da2a..ed4024f4394b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2569,7 +2569,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
}
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
- u32 pll_id)
+ i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
{
u32 cfgcr0, cfgcr1;
u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
@@ -2577,8 +2577,8 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
int index, n_entries, link_clock;
/* Read back values from DPLL CFGCR registers */
- cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
- cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+ cfgcr0 = I915_READ(cfgcr0_reg);
+ cfgcr1 = I915_READ(cfgcr1_reg);
dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 40e8391a92f2..0aa504e9bfbf 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -342,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state);
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
- u32 pll_id);
+ i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg);
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9f188ef21f4..9d0bf1914773 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1659,7 +1659,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
bool enable);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
- enum intel_dpll_id pll_id);
+ i915_reg_t cgfcr0_reg, i915_reg_t cgfcr1_reg);
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
int color_plane, unsigned int height);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-16 0:45 [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id Lucas De Marchi
@ 2019-03-16 1:32 ` Patchwork
2019-03-16 8:14 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-18 13:31 ` [PATCH] " Ville Syrjälä
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-16 1:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: pass cfgcr* register around instead of pll_id
URL : https://patchwork.freedesktop.org/series/58084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5756 -> Patchwork_12490
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58084/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12490 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5756 -> Patchwork_12490
CI_DRM_5756: 0a2a982693ac3f3ecabf8e6c12cb18aa993ae3b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12490: fee79e663c19b53257516fc943bf8ab61ee1983f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fee79e663c19 drm/i915/icl: pass cfgcr* register around instead of pll_id
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12490/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-16 0:45 [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id Lucas De Marchi
2019-03-16 1:32 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-03-16 8:14 ` Patchwork
2019-03-18 13:31 ` [PATCH] " Ville Syrjälä
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-16 8:14 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: pass cfgcr* register around instead of pll_id
URL : https://patchwork.freedesktop.org/series/58084/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5756_full -> Patchwork_12490_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12490_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
- shard-iclb: NOTRUN -> FAIL [fdo#109674]
* igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109283]
* igt@gem_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_mocs_settings@mocs-reset-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: NOTRUN -> INCOMPLETE [fdo#107713]
* igt@gem_tiled_blits@normal:
- shard-iclb: PASS -> TIMEOUT [fdo#109673]
* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +36
* igt@i915_pm_rpm@pm-tiling:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@i915_pm_rps@min-max-config-loaded:
- shard-iclb: NOTRUN -> FAIL [fdo#108059]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_atomic_transition@5x-modeset-transitions-nonblocking:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_atomic_transition@plane-all-transition-nonblocking:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_chv_cursor_fail@pipe-b-128x128-right-edge:
- shard-apl: PASS -> DMESG-WARN [fdo#105345]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: PASS -> DMESG-WARN [fdo#108566]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#108040]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +11
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +8
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +11
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] +4
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#109247] +25
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#106978]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +2
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] / [fdo#109278]
* igt@kms_psr@primary_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] +3
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_psr@suspend:
- shard-iclb: NOTRUN -> FAIL [fdo#107383]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm:
- shard-apl: PASS -> FAIL [fdo#104894]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +95
* igt@prime_nv_pcopy@test3_3:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +2
* igt@prime_vgem@fence-wait-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +10
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@gem_workarounds@suspend-resume-context:
- shard-iclb: FAIL [fdo#103375] -> PASS
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-WARN [fdo#109982] -> PASS
* igt@kms_atomic_transition@1x-modeset-transitions-fencing:
- shard-skl: FAIL [fdo#108470] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
- shard-skl: FAIL [fdo#103184] / [fdo#108472] -> PASS
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled:
- shard-skl: FAIL [fdo#107791] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: INCOMPLETE [fdo#107773] / [fdo#109507] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +7
* {igt@kms_plane@pixel-format-pipe-b-planes-source-clamping}:
- shard-apl: FAIL [fdo#110033] -> PASS +1
* {igt@kms_plane@pixel-format-pipe-c-planes-source-clamping}:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-x}:
- shard-apl: FAIL [fdo#110037] -> PASS +1
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-yf}:
- shard-iclb: FAIL [fdo#110037] -> PASS +3
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]
* igt@i915_pm_rpm@pc8-residency:
- shard-skl: SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098] +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
[fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
[fdo#110032]: https://bugs.freedesktop.org/show_bug.cgi?id=110032
[fdo#110033]: https://bugs.freedesktop.org/show_bug.cgi?id=110033
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#110129]: https://bugs.freedesktop.org/show_bug.cgi?id=110129
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5756 -> Patchwork_12490
CI_DRM_5756: 0a2a982693ac3f3ecabf8e6c12cb18aa993ae3b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12490: fee79e663c19b53257516fc943bf8ab61ee1983f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12490/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-16 0:45 [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id Lucas De Marchi
2019-03-16 1:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-16 8:14 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-03-18 13:31 ` Ville Syrjälä
2019-03-18 18:40 ` Lucas De Marchi
2 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-18 13:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
> The caller already knows what platform that is and what register should
> be used. Instead of keep adding if/else chains on a leaf functions,
> let the caller pass the register.
>
> We read cfgcr0 twice for CNL, but we were already doing that anyway.
>
> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
> consistency with cnl_calc_wrpll_link().
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> 5 files changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index beb30d9a855c..28f5da697693 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
> + ICL_DPLL_CFGCR0(pll_id),
> + ICL_DPLL_CFGCR1(pll_id));
> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 69aa0d148795..24675ef8b262 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> }
>
> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> - enum intel_dpll_id pll_id)
> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
> {
> u32 cfgcr0, cfgcr1;
> u32 p0, p1, p2, dco_freq, ref_clock;
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> - } else {
> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> - }
> + cfgcr0 = I915_READ(cfgcr0_reg);
> + cfgcr1 = I915_READ(cfgcr1_reg);
Don't we alredy have the dpll state read out at this point?
I thought I changed at least some of these to not read it out
directly.
>
> p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
> @@ -1471,17 +1466,23 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + i915_reg_t cfgcr0_reg, cfgcr1_reg;
> enum port port = encoder->port;
> int link_clock = 0;
> u32 pll_id;
>
> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> + cfgcr0_reg = ICL_DPLL_CFGCR0(pll_id);
> + cfgcr1_reg = ICL_DPLL_CFGCR1(pll_id);
> +
> if (intel_port_is_combophy(dev_priv, port)) {
> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
> - link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> + link_clock = cnl_calc_wrpll_link(dev_priv, cfgcr0_reg,
> + cfgcr1_reg);
> else
> link_clock = icl_calc_dp_combo_pll_link(dev_priv,
> - pll_id);
> + cfgcr0_reg,
> + cfgcr1_reg);
> } else {
> if (pll_id == DPLL_ID_ICL_TBTPLL)
> link_clock = icl_calc_tbt_pll_link(dev_priv, port);
> @@ -1506,7 +1507,9 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
> cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>
> if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> - link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> + link_clock = cnl_calc_wrpll_link(dev_priv,
> + CNL_DPLL_CFGCR0(pll_id),
> + CNL_DPLL_CFGCR1(pll_id));
> } else {
> link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index ca975213da2a..ed4024f4394b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2569,7 +2569,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> }
>
> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> - u32 pll_id)
> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
> {
> u32 cfgcr0, cfgcr1;
> u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
> @@ -2577,8 +2577,8 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> int index, n_entries, link_clock;
>
> /* Read back values from DPLL CFGCR registers */
> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> + cfgcr0 = I915_READ(cfgcr0_reg);
> + cfgcr1 = I915_READ(cfgcr1_reg);
>
> dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
> dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 40e8391a92f2..0aa504e9bfbf 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -342,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dpll_hw_state *hw_state);
> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> - u32 pll_id);
> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg);
> int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d9f188ef21f4..9d0bf1914773 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1659,7 +1659,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> bool enable);
> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> - enum intel_dpll_id pll_id);
> + i915_reg_t cgfcr0_reg, i915_reg_t cgfcr1_reg);
>
> unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
> int color_plane, unsigned int height);
> --
> 2.20.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-18 13:31 ` [PATCH] " Ville Syrjälä
@ 2019-03-18 18:40 ` Lucas De Marchi
2019-03-18 18:53 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2019-03-18 18:40 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
>On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
>> The caller already knows what platform that is and what register should
>> be used. Instead of keep adding if/else chains on a leaf functions,
>> let the caller pass the register.
>>
>> We read cfgcr0 twice for CNL, but we were already doing that anyway.
>>
>> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
>> consistency with cnl_calc_wrpll_link().
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
>> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
>> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
>> drivers/gpu/drm/i915/intel_drv.h | 2 +-
>> 5 files changed, 22 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index beb30d9a855c..28f5da697693 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>>
>> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
>> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
>> + ICL_DPLL_CFGCR0(pll_id),
>> + ICL_DPLL_CFGCR1(pll_id));
>> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
>> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 69aa0d148795..24675ef8b262 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> }
>>
>> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> - enum intel_dpll_id pll_id)
>> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
>> {
>> u32 cfgcr0, cfgcr1;
>> u32 p0, p1, p2, dco_freq, ref_clock;
>>
>> - if (INTEL_GEN(dev_priv) >= 11) {
>> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
>> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
>> - } else {
>> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
>> - }
>> + cfgcr0 = I915_READ(cfgcr0_reg);
>> + cfgcr1 = I915_READ(cfgcr1_reg);
>
>Don't we alredy have the dpll state read out at this point?
nops.
>I thought I changed at least some of these to not read it out
>directly.
What we have is that for ICL we only read it on the
cnl_calc_wrpll_link(). For CNL we read both on cnl_calc_wrpll_link() and
on the ddi_clock_get() function - at least cfgcr0, because we need it
to decide which function to call.
If you prefer the read to be on the ddi_clock_get() what I could do is
to pass the register values.
Lucas De Marchi
>
>>
>> p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
>> p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
>> @@ -1471,17 +1466,23 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config)
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> + i915_reg_t cfgcr0_reg, cfgcr1_reg;
>> enum port port = encoder->port;
>> int link_clock = 0;
>> u32 pll_id;
>>
>> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
>> + cfgcr0_reg = ICL_DPLL_CFGCR0(pll_id);
>> + cfgcr1_reg = ICL_DPLL_CFGCR1(pll_id);
>> +
>> if (intel_port_is_combophy(dev_priv, port)) {
>> if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>> - link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>> + link_clock = cnl_calc_wrpll_link(dev_priv, cfgcr0_reg,
>> + cfgcr1_reg);
>> else
>> link_clock = icl_calc_dp_combo_pll_link(dev_priv,
>> - pll_id);
>> + cfgcr0_reg,
>> + cfgcr1_reg);
>> } else {
>> if (pll_id == DPLL_ID_ICL_TBTPLL)
>> link_clock = icl_calc_tbt_pll_link(dev_priv, port);
>> @@ -1506,7 +1507,9 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
>> cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>>
>> if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
>> - link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>> + link_clock = cnl_calc_wrpll_link(dev_priv,
>> + CNL_DPLL_CFGCR0(pll_id),
>> + CNL_DPLL_CFGCR1(pll_id));
>> } else {
>> link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index ca975213da2a..ed4024f4394b 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -2569,7 +2569,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>> }
>>
>> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>> - u32 pll_id)
>> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
>> {
>> u32 cfgcr0, cfgcr1;
>> u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
>> @@ -2577,8 +2577,8 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>> int index, n_entries, link_clock;
>>
>> /* Read back values from DPLL CFGCR registers */
>> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
>> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
>> + cfgcr0 = I915_READ(cfgcr0_reg);
>> + cfgcr1 = I915_READ(cfgcr1_reg);
>>
>> dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
>> dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
>> index 40e8391a92f2..0aa504e9bfbf 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
>> @@ -342,7 +342,7 @@ void intel_shared_dpll_init(struct drm_device *dev);
>> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
>> struct intel_dpll_hw_state *hw_state);
>> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>> - u32 pll_id);
>> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg);
>> int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
>> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
>> bool intel_dpll_is_combophy(enum intel_dpll_id id);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index d9f188ef21f4..9d0bf1914773 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1659,7 +1659,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>> bool enable);
>> void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
>> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> - enum intel_dpll_id pll_id);
>> + i915_reg_t cgfcr0_reg, i915_reg_t cgfcr1_reg);
>>
>> unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>> int color_plane, unsigned int height);
>> --
>> 2.20.1
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-18 18:40 ` Lucas De Marchi
@ 2019-03-18 18:53 ` Ville Syrjälä
2019-03-18 21:58 ` Lucas De Marchi
2019-03-18 23:33 ` Lucas De Marchi
0 siblings, 2 replies; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-18 18:53 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
> >On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
> >> The caller already knows what platform that is and what register should
> >> be used. Instead of keep adding if/else chains on a leaf functions,
> >> let the caller pass the register.
> >>
> >> We read cfgcr0 twice for CNL, but we were already doing that anyway.
> >>
> >> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
> >> consistency with cnl_calc_wrpll_link().
> >>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
> >> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> >> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> >> 5 files changed, 22 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> >> index beb30d9a855c..28f5da697693 100644
> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> >> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> >>
> >> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> >> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> >> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> >> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
> >> + ICL_DPLL_CFGCR0(pll_id),
> >> + ICL_DPLL_CFGCR1(pll_id));
> >> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> >> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> >> }
> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> >> index 69aa0d148795..24675ef8b262 100644
> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >> }
> >>
> >> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >> - enum intel_dpll_id pll_id)
> >> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
> >> {
> >> u32 cfgcr0, cfgcr1;
> >> u32 p0, p1, p2, dco_freq, ref_clock;
> >>
> >> - if (INTEL_GEN(dev_priv) >= 11) {
> >> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> >> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> >> - } else {
> >> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> >> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> >> - }
> >> + cfgcr0 = I915_READ(cfgcr0_reg);
> >> + cfgcr1 = I915_READ(cfgcr1_reg);
> >
> >Don't we alredy have the dpll state read out at this point?
>
> nops.
We must have it since bxt is already using it. Either that or bxt is
broken.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-18 18:53 ` Ville Syrjälä
@ 2019-03-18 21:58 ` Lucas De Marchi
2019-03-18 23:33 ` Lucas De Marchi
1 sibling, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2019-03-18 21:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Mar 18, 2019 at 08:53:23PM +0200, Ville Syrjälä wrote:
>On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
>> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
>> >On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
>> >> The caller already knows what platform that is and what register should
>> >> be used. Instead of keep adding if/else chains on a leaf functions,
>> >> let the caller pass the register.
>> >>
>> >> We read cfgcr0 twice for CNL, but we were already doing that anyway.
>> >>
>> >> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
>> >> consistency with cnl_calc_wrpll_link().
>> >>
>> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
>> >> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
>> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
>> >> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
>> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
>> >> 5 files changed, 22 insertions(+), 17 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> >> index beb30d9a855c..28f5da697693 100644
>> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> >> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>> >>
>> >> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>> >> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
>> >> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>> >> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
>> >> + ICL_DPLL_CFGCR0(pll_id),
>> >> + ICL_DPLL_CFGCR1(pll_id));
>> >> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
>> >> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> >> }
>> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> >> index 69aa0d148795..24675ef8b262 100644
>> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> >> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> >> }
>> >>
>> >> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> >> - enum intel_dpll_id pll_id)
>> >> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
>> >> {
>> >> u32 cfgcr0, cfgcr1;
>> >> u32 p0, p1, p2, dco_freq, ref_clock;
>> >>
>> >> - if (INTEL_GEN(dev_priv) >= 11) {
>> >> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
>> >> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
>> >> - } else {
>> >> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>> >> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
>> >> - }
>> >> + cfgcr0 = I915_READ(cfgcr0_reg);
>> >> + cfgcr1 = I915_READ(cfgcr1_reg);
>> >
>> >Don't we alredy have the dpll state read out at this point?
>>
>> nops.
>
>We must have it since bxt is already using it. Either that or bxt is
>broken.
humn... I need to double check it then. bxt is the only one not reading
the registers and instead using what's saved on dpll_hw_state - in fact
hsw, skl, cnl, icl - all read wrpll/spll/cfgcr* registers that they need
:-o
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-18 18:53 ` Ville Syrjälä
2019-03-18 21:58 ` Lucas De Marchi
@ 2019-03-18 23:33 ` Lucas De Marchi
2019-03-19 11:09 ` Ville Syrjälä
1 sibling, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2019-03-18 23:33 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Mar 18, 2019 at 08:53:23PM +0200, Ville Syrjälä wrote:
>On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
>> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
>> >On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
>> >> The caller already knows what platform that is and what register should
>> >> be used. Instead of keep adding if/else chains on a leaf functions,
>> >> let the caller pass the register.
>> >>
>> >> We read cfgcr0 twice for CNL, but we were already doing that anyway.
>> >>
>> >> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
>> >> consistency with cnl_calc_wrpll_link().
>> >>
>> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
>> >> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
>> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
>> >> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
>> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
>> >> 5 files changed, 22 insertions(+), 17 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> >> index beb30d9a855c..28f5da697693 100644
>> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> >> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>> >>
>> >> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
>> >> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
>> >> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>> >> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
>> >> + ICL_DPLL_CFGCR0(pll_id),
>> >> + ICL_DPLL_CFGCR1(pll_id));
>> >> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
>> >> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> >> }
>> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> >> index 69aa0d148795..24675ef8b262 100644
>> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> >> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> >> }
>> >>
>> >> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>> >> - enum intel_dpll_id pll_id)
>> >> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
>> >> {
>> >> u32 cfgcr0, cfgcr1;
>> >> u32 p0, p1, p2, dco_freq, ref_clock;
>> >>
>> >> - if (INTEL_GEN(dev_priv) >= 11) {
>> >> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
>> >> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
>> >> - } else {
>> >> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
>> >> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
>> >> - }
>> >> + cfgcr0 = I915_READ(cfgcr0_reg);
>> >> + cfgcr1 = I915_READ(cfgcr1_reg);
>> >
>> >Don't we alredy have the dpll state read out at this point?
>>
>> nops.
>
>We must have it since bxt is already using it. Either that or bxt is
>broken.
oh.. I think you forgot to push
https://patchwork.freedesktop.org/series/56354/
I guess it will also make my life easier here.
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
2019-03-18 23:33 ` Lucas De Marchi
@ 2019-03-19 11:09 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-19 11:09 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Mar 18, 2019 at 04:33:51PM -0700, Lucas De Marchi wrote:
> On Mon, Mar 18, 2019 at 08:53:23PM +0200, Ville Syrjälä wrote:
> >On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
> >> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
> >> >On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
> >> >> The caller already knows what platform that is and what register should
> >> >> be used. Instead of keep adding if/else chains on a leaf functions,
> >> >> let the caller pass the register.
> >> >>
> >> >> We read cfgcr0 twice for CNL, but we were already doing that anyway.
> >> >>
> >> >> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
> >> >> consistency with cnl_calc_wrpll_link().
> >> >>
> >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/icl_dsi.c | 4 +++-
> >> >> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++-----------
> >> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> >> >> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> >> >> 5 files changed, 22 insertions(+), 17 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> >> >> index beb30d9a855c..28f5da697693 100644
> >> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
> >> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> >> >> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> >> >>
> >> >> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> >> >> pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> >> >> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> >> >> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
> >> >> + ICL_DPLL_CFGCR0(pll_id),
> >> >> + ICL_DPLL_CFGCR1(pll_id));
> >> >> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> >> >> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> >> >> }
> >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> index 69aa0d148795..24675ef8b262 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >> >> }
> >> >>
> >> >> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >> >> - enum intel_dpll_id pll_id)
> >> >> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
> >> >> {
> >> >> u32 cfgcr0, cfgcr1;
> >> >> u32 p0, p1, p2, dco_freq, ref_clock;
> >> >>
> >> >> - if (INTEL_GEN(dev_priv) >= 11) {
> >> >> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> >> >> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> >> >> - } else {
> >> >> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> >> >> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> >> >> - }
> >> >> + cfgcr0 = I915_READ(cfgcr0_reg);
> >> >> + cfgcr1 = I915_READ(cfgcr1_reg);
> >> >
> >> >Don't we alredy have the dpll state read out at this point?
> >>
> >> nops.
> >
> >We must have it since bxt is already using it. Either that or bxt is
> >broken.
>
> oh.. I think you forgot to push
> https://patchwork.freedesktop.org/series/56354/
Ah yes. Now pushed. Thanks for reviewing it.
>
> I guess it will also make my life easier here.
>
> Lucas De Marchi
>
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-03-19 11:09 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-16 0:45 [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id Lucas De Marchi
2019-03-16 1:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-16 8:14 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-18 13:31 ` [PATCH] " Ville Syrjälä
2019-03-18 18:40 ` Lucas De Marchi
2019-03-18 18:53 ` Ville Syrjälä
2019-03-18 21:58 ` Lucas De Marchi
2019-03-18 23:33 ` Lucas De Marchi
2019-03-19 11:09 ` Ville Syrjälä
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