From: Imre Deak <imre.deak@intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
Date: Wed, 20 Mar 2019 13:07:58 +0200 [thread overview]
Message-ID: <20190320110758.GA29375@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <1553076539-12556-2-git-send-email-vandita.kulkarni@intel.com>
On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> Re-enable clock gating of DDI clocks.
>
> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index f02504d..716be38 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
> DRM_ERROR("DDI port:%c buffer not idle\n",
> port_name(port));
> }
> - gen11_dsi_ungate_clocks(encoder);
> + gen11_dsi_gate_clocks(encoder);
This also requires updating icl_sanitize_encoder_pll_mapping().
Currently it assumes that the DDI clock needs to be ungated if the
corresponding DSI port is disabled and gated if the port is enabled.
The changes in this patchset mean that the DDI clock should be gated for
DSI ports regardless of whether the port is enabled or not.
> }
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-03-20 11:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
2019-03-20 11:07 ` Imre Deak [this message]
2019-03-20 12:02 ` Shankar, Uma
2019-03-21 13:57 ` Kulkarni, Vandita
2019-03-21 13:56 ` Kulkarni, Vandita
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
2019-03-21 13:53 ` Kulkarni, Vandita
2019-03-22 7:48 ` Kulkarni, Vandita
2019-03-22 8:18 ` Shankar, Uma
2019-03-20 14:28 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-03-20 19:01 ` ✓ Fi.CI.IGT: " Patchwork
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