[PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Ramalingam C]

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ba65e5018978..4049b876492a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	struct drm_i915_private *dev_priv = engine->i915;
+	u32 val;
+
 	/* Wa_1409142259 */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = I915_READ(FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..ff19b8c80b40 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7775,6 +7775,11 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_SHIFT	(16)
+#define   FF_MODE2_TDS_TIMER_128	(4 << FF_MODE2_TDS_TIMER_SHIFT)
+#define   FF_MODE2_TDS_TIMER_MASK	(0xff << FF_MODE2_TDS_TIMER_SHIFT)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

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[PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0

[Ramalingam C]

Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
Wa_1604555607 associated to that register needs to be skipped.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h             |  6 ++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4049b876492a..c63d8c3df4d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 		intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
-		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+
+			/*
+			 * Read of FF_MODE2 is broken on TGL A0.
+			 * Hence skip the corresponding WA verification.
+			 */
+			if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
+			    i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+			    wa->mask == FF_MODE2_TDS_TIMER_MASK)
+				continue;
+
 			wa_verify(wa,
 				  intel_uncore_read_fw(uncore, wa->reg),
 				  wal->name, "application");
+		}
 	}
 
 	intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1553,6 +1564,15 @@ static int engine_wa_list_verify(struct intel_context *ce,
 		if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
 			continue;
 
+		/*
+		 * Read of FF_MODE2 is broken on TGL A0.
+		 * Hence skip the corresponding WA verification.
+		 */
+		if (IS_TGL_REVID(rq->i915, 0, TGL_REVID_A0) &&
+		    i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
+		    wa->mask == FF_MODE2_TDS_TIMER_MASK)
+			continue;
+
 		if (!wa_verify(wa, results[i], wal->name, from))
 			err = -ENXIO;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..05bf0b398ce7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2065,6 +2065,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_REVID(p, since, until) \
 	(IS_ICELAKE(p) && IS_REVID(p, since, until))
 
+#define TGL_REVID_A0		0x0
+#define TGL_REVID_B0		0x1
+
+#define IS_TGL_REVID(p, since, until) \
+	(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
-- 
2.20.1

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Re: [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Chris Wilson]

Quoting Ramalingam C (2019-10-01 18:26:23)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ba65e5018978..4049b876492a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> +       struct drm_i915_private *dev_priv = engine->i915;
> +       u32 val;
> +
>         /* Wa_1409142259 */
>         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +       /* Wa_1604555607:tgl */
> +       val = I915_READ(FF_MODE2);

No, you can't use indiscriminate mmio access that may not match the engine
(engine->gt->uncore).

But really consider doing the rmw as part of the wa.

> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> +       val |= FF_MODE2_TDS_TIMER_128;
> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
>  }
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Re: [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0

[Chris Wilson]

Quoting Ramalingam C (2019-10-01 18:26:24)
> Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
> Wa_1604555607 associated to that register needs to be skipped.
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_drv.h             |  6 ++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4049b876492a..c63d8c3df4d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
>  
>         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>                 intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> -               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> +               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
> +
> +                       /*
> +                        * Read of FF_MODE2 is broken on TGL A0.
> +                        * Hence skip the corresponding WA verification.
> +                        */
> +                       if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
> +                           i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
> +                           wa->mask == FF_MODE2_TDS_TIMER_MASK)
> +                               continue;

This does not scale very well. You will note that wa_verify() already
includes a detail on which bits can be read back from HW.
-Chris
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Re: [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Lucas De Marchi]

On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Quoting Ramalingam C (2019-10-01 18:26:23)
> > From: Michel Thierry <michel.thierry@intel.com>
> >
> > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > FF_MODE2 is part of the register state context, that's why it is
> > implemented here.
> >
> > v2: Rebased on top of the WA refactoring (Oscar)
> > v3: Correctly add to ctx_workarounds_init (Michel)
> >
> > BSpec: 19363
> > HSDES: 1604555607
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index ba65e5018978..4049b876492a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                      struct i915_wa_list *wal)
> >  {
> > +       struct drm_i915_private *dev_priv = engine->i915;
> > +       u32 val;
> > +
> >         /* Wa_1409142259 */
> >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +       /* Wa_1604555607:tgl */
> > +       val = I915_READ(FF_MODE2);
>
> No, you can't use indiscriminate mmio access that may not match the engine
> (engine->gt->uncore).
>
> But really consider doing the rmw as part of the wa.

And:
https://patchwork.freedesktop.org/patch/319952/?series=64274&rev=1
https://patchwork.freedesktop.org/patch/317654/?series=63670&rev=2

Please don't simply resend patches that were already reviewed.

Lucas De Marchi

>
> > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +       val |= FF_MODE2_TDS_TIMER_128;
> > +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> >  }
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Lucas De Marchi
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
URL   : https://patchwork.freedesktop.org/series/67461/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b68066e4e634 drm/i915/tgl: Implement Wa_1604555607
52edee18222b drm/i915/tgl: Skip Wa_1604555607 verification at A0
-:22: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#22: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:995:
+		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/i915_drv.h:2071:
+#define IS_TGL_REVID(p, since, until) \
+	(IS_TIGERLAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 2 checks, 49 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
URL   : https://patchwork.freedesktop.org/series/67461/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6986 -> Patchwork_14619
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14619:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_workarounds@basic-read:
    - {fi-tgl-u2}:        [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-tgl-u2/igt@gem_workarounds@basic-read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-tgl-u2/igt@gem_workarounds@basic-read.html
    - {fi-tgl-u}:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-tgl-u/igt@gem_workarounds@basic-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-tgl-u/igt@gem_workarounds@basic-read.html

  
Known issues
------------

  Here are the changes found in Patchwork_14619 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-small-bo-tiledy:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_linear_blits@basic:
    - fi-icl-u3:          [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@gem_linear_blits@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@gem_linear_blits@basic.html

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [DMESG-WARN][13] ([fdo#107724] / [fdo#111214]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-icl-u3/igt@i915_module_load@reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][15] ([fdo#111407]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 47)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6986 -> Patchwork_14619

  CI-20190529: 20190529
  CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14619: 52edee18222b7e88f600406fa896bd731de901c6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

52edee18222b drm/i915/tgl: Skip Wa_1604555607 verification at A0
b68066e4e634 drm/i915/tgl: Implement Wa_1604555607

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/index.html
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Re: [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Ramalingam C]

On 2019-10-01 at 13:16:11 -0700, Lucas De Marchi wrote:
> On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Ramalingam C (2019-10-01 18:26:23)
> > > From: Michel Thierry <michel.thierry@intel.com>
> > >
> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > > FF_MODE2 is part of the register state context, that's why it is
> > > implemented here.
> > >
> > > v2: Rebased on top of the WA refactoring (Oscar)
> > > v3: Correctly add to ctx_workarounds_init (Michel)
> > >
> > > BSpec: 19363
> > > HSDES: 1604555607
> > > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
> > >  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
> > >  2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index ba65e5018978..4049b876492a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                      struct i915_wa_list *wal)
> > >  {
> > > +       struct drm_i915_private *dev_priv = engine->i915;
> > > +       u32 val;
> > > +
> > >         /* Wa_1409142259 */
> > >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +       /* Wa_1604555607:tgl */
> > > +       val = I915_READ(FF_MODE2);
> >
> > No, you can't use indiscriminate mmio access that may not match the engine
> > (engine->gt->uncore).
> >
> > But really consider doing the rmw as part of the wa.
> 
> And:
> https://patchwork.freedesktop.org/patch/319952/?series=64274&rev=1
> https://patchwork.freedesktop.org/patch/317654/?series=63670&rev=2
> 
> Please don't simply resend patches that were already reviewed.
Happy if it already getting reviewed. Before sending it, I could have confirmed
with owner of the patch. Sorry for the inconvenience. Lets drop this patch.

-Ram
> 
> Lucas De Marchi
> 
> >
> > > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +       val |= FF_MODE2_TDS_TIMER_128;
> > > +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > >  }
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi
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Re: [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0

[Tvrtko Ursulin]

On 01/10/2019 18:36, Chris Wilson wrote:
> Quoting Ramalingam C (2019-10-01 18:26:24)
>> Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
>> Wa_1604555607 associated to that register needs to be skipped.
>>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++++++++++++-
>>   drivers/gpu/drm/i915/i915_drv.h             |  6 ++++++
>>   2 files changed, 27 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 4049b876492a..c63d8c3df4d3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
>>   
>>          for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>>                  intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
>> -               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> +               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
>> +
>> +                       /*
>> +                        * Read of FF_MODE2 is broken on TGL A0.
>> +                        * Hence skip the corresponding WA verification.
>> +                        */
>> +                       if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
>> +                           i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
>> +                           wa->mask == FF_MODE2_TDS_TIMER_MASK)
>> +                               continue;
> 
> This does not scale very well. You will note that wa_verify() already
> includes a detail on which bits can be read back from HW.

For the record Chris is referring to wa->read which you can set to zero 
for this particular wa and this should automagically work.

Then in IGT/gem_workarounds.c you also have existing framework for 
marking registers as write-only. It may need extending to account for 
steppings and so.

Regards,

Tvrtko
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Re: [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Tvrtko Ursulin]

On 01/10/2019 18:35, Chris Wilson wrote:
> Quoting Ramalingam C (2019-10-01 18:26:23)
>> From: Michel Thierry <michel.thierry@intel.com>
>>
>> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
>> FF_MODE2 is part of the register state context, that's why it is
>> implemented here.
>>
>> v2: Rebased on top of the WA refactoring (Oscar)
>> v3: Correctly add to ctx_workarounds_init (Michel)
>>
>> BSpec: 19363
>> HSDES: 1604555607
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
>>   drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
>>   2 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index ba65e5018978..4049b876492a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>                                       struct i915_wa_list *wal)
>>   {
>> +       struct drm_i915_private *dev_priv = engine->i915;
>> +       u32 val;
>> +
>>          /* Wa_1409142259 */
>>          WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>>                            GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>> +
>> +       /* Wa_1604555607:tgl */
>> +       val = I915_READ(FF_MODE2);
> 
> No, you can't use indiscriminate mmio access that may not match the engine
> (engine->gt->uncore).
> 
> But really consider doing the rmw as part of the wa.

You are suggesting going via the context image after all? Or MI_MATH?

Regards,

Tvrtko

>> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
>> +       val |= FF_MODE2_TDS_TIMER_128;
>> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
>>   }
> 
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✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/tgl: Implement Wa_1604555607
URL   : https://patchwork.freedesktop.org/series/67461/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6986_full -> Patchwork_14619_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14619_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#111325]) +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@gem_softpin@noreloc-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-apl3/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([fdo#109385] / [fdo#111870]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-apl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-skl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl9/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk2/igt@gem_userptr_blits@sync-unmap.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-glk2/igt@gem_userptr_blits@sync-unmap.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
    - shard-apl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([fdo#105363])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [PASS][17] -> [INCOMPLETE][18] ([fdo#109507])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl8/igt@kms_flip@flip-vs-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#103166])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl1/igt@kms_plane@plane-panning-bottom-right-pipe-a-planes.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
    - shard-skl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#106885])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl5/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-iclb:         [PASS][27] -> [INCOMPLETE][28] ([fdo#107713] / [fdo#110026] / [fdo#110040 ])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][29] -> [INCOMPLETE][30] ([fdo#103665])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][31] -> [SKIP][32] ([fdo#109276]) +13 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [SKIP][33] ([fdo#109276]) -> [PASS][34] +23 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][35] ([fdo#111325]) -> [PASS][36] +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_request_retire@retire-vma-not-inactive:
    - shard-hsw:          [INCOMPLETE][37] ([fdo#103540]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw4/igt@gem_request_retire@retire-vma-not-inactive.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-hsw5/igt@gem_request_retire@retire-vma-not-inactive.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][39] ([fdo#104108] / [fdo#107773]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl6/igt@gem_softpin@noreloc-s3.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl10/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          [DMESG-WARN][41] ([fdo#111870]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-skl:          [DMESG-WARN][43] ([fdo#111870]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl7/igt@gem_userptr_blits@dmabuf-sync.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl5/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-snb:          [DMESG-WARN][45] ([fdo#110789] / [fdo#111870]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
    - shard-glk:          [DMESG-WARN][47] ([fdo#111870]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-glk5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-glk3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
    - shard-apl:          [DMESG-WARN][49] ([fdo#109385] / [fdo#111870]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-apl4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
    - shard-skl:          [FAIL][53] ([fdo#103184] / [fdo#103232]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-hsw:          [DMESG-FAIL][55] ([fdo#102614]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-hsw7/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][57] ([fdo#109507]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [FAIL][59] ([fdo#100368]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl2/igt@kms_flip@plain-flip-fb-recreate.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-iclb:         [FAIL][61] ([fdo#103167]) -> [PASS][62] +4 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][65] ([fdo#103665]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][67] ([fdo#104108]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [SKIP][69] ([fdo#109276]) -> [FAIL][70] ([fdo#111330])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb7/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][71] ([fdo#111330]) -> [SKIP][72] ([fdo#109276])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6986/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110040 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110040 
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870


Participating hosts (16 -> 10)
------------------------------

  Missing    (6): shard-tglb1 shard-tglb2 shard-tglb3 shard-tglb4 shard-tglb5 shard-tglb6 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6986 -> Patchwork_14619

  CI-20190529: 20190529
  CI_DRM_6986: 9300459553e8c1032f10ec1953e1a375a99aba13 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5208: c0131b4f132acf287d9d05b0f5078003d3159e1c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14619: 52edee18222b7e88f600406fa896bd731de901c6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14619/
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Re: [PATCH 2/2] drm/i915/tgl: Skip Wa_1604555607 verification at A0

[Ramalingam C]

On 2019-10-02 at 09:54:12 +0100, Tvrtko Ursulin wrote:
> 
> On 01/10/2019 18:36, Chris Wilson wrote:
> > Quoting Ramalingam C (2019-10-01 18:26:24)
> > > Read of FF_MODE2 register is broken at TGL A0. Hence verification of the
> > > Wa_1604555607 associated to that register needs to be skipped.
> > > 
> > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > > cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++++++++++++-
> > >   drivers/gpu/drm/i915/i915_drv.h             |  6 ++++++
> > >   2 files changed, 27 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 4049b876492a..c63d8c3df4d3 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -991,10 +991,21 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
> > >          for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> > >                  intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> > > -               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> > > +               if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
> > > +
> > > +                       /*
> > > +                        * Read of FF_MODE2 is broken on TGL A0.
> > > +                        * Hence skip the corresponding WA verification.
> > > +                        */
> > > +                       if (IS_TGL_REVID(uncore->i915, 0, TGL_REVID_A0) &&
> > > +                           i915_mmio_reg_equal(wa->reg, FF_MODE2) &&
> > > +                           wa->mask == FF_MODE2_TDS_TIMER_MASK)
> > > +                               continue;
> > 
> > This does not scale very well. You will note that wa_verify() already
> > includes a detail on which bits can be read back from HW.
> 
> For the record Chris is referring to wa->read which you can set to zero for
> this particular wa and this should automagically work.
Thanks Tvrtko. We could set that wa->read = 0, only for required steppings.

-Ram
> 
> Then in IGT/gem_workarounds.c you also have existing framework for marking
> registers as write-only. It may need extending to account for steppings and
> so.
> 
> Regards,
> 
> Tvrtko
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Re: [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Ramalingam C]

On 2019-10-01 at 13:16:11 -0700, Lucas De Marchi wrote:
> On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Ramalingam C (2019-10-01 18:26:23)
> > > From: Michel Thierry <michel.thierry@intel.com>
> > >
> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > > FF_MODE2 is part of the register state context, that's why it is
> > > implemented here.
> > >
> > > v2: Rebased on top of the WA refactoring (Oscar)
> > > v3: Correctly add to ctx_workarounds_init (Michel)
> > >
> > > BSpec: 19363
> > > HSDES: 1604555607
> > > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
> > >  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
> > >  2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index ba65e5018978..4049b876492a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                      struct i915_wa_list *wal)
> > >  {
> > > +       struct drm_i915_private *dev_priv = engine->i915;
> > > +       u32 val;
> > > +
> > >         /* Wa_1409142259 */
> > >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +       /* Wa_1604555607:tgl */
> > > +       val = I915_READ(FF_MODE2);
> >
> > No, you can't use indiscriminate mmio access that may not match the engine
> > (engine->gt->uncore).
> >
> > But really consider doing the rmw as part of the wa.
> 
> And:
> https://patchwork.freedesktop.org/patch/319952/?series=64274&rev=1
> https://patchwork.freedesktop.org/patch/317654/?series=63670&rev=2
> 
> Please don't simply resend patches that were already reviewed.

Lucas,

Are you planning pursue the merge of these patches.

Verification is not fixed at B Stepping too. And we need this WA for the performance.

Thanks,
-Ram
> 
> Lucas De Marchi
> 
> >
> > > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +       val |= FF_MODE2_TDS_TIMER_128;
> > > +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > >  }
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Ramalingam C]

On 2019-10-01 at 13:16:11 -0700, Lucas De Marchi wrote:
> On Tue, Oct 1, 2019 at 10:36 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Ramalingam C (2019-10-01 18:26:23)
> > > From: Michel Thierry <michel.thierry@intel.com>
> > >
> > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > > FF_MODE2 is part of the register state context, that's why it is
> > > implemented here.
> > >
> > > v2: Rebased on top of the WA refactoring (Oscar)
> > > v3: Correctly add to ctx_workarounds_init (Michel)
> > >
> > > BSpec: 19363
> > > HSDES: 1604555607
> > > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
> > >  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
> > >  2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index ba65e5018978..4049b876492a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                      struct i915_wa_list *wal)
> > >  {
> > > +       struct drm_i915_private *dev_priv = engine->i915;
> > > +       u32 val;
> > > +
> > >         /* Wa_1409142259 */
> > >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +       /* Wa_1604555607:tgl */
> > > +       val = I915_READ(FF_MODE2);
> >
> > No, you can't use indiscriminate mmio access that may not match the engine
> > (engine->gt->uncore).
> >
> > But really consider doing the rmw as part of the wa.
> 
> And:
> https://patchwork.freedesktop.org/patch/319952/?series=64274&rev=1
> https://patchwork.freedesktop.org/patch/317654/?series=63670&rev=2
> 
> Please don't simply resend patches that were already reviewed.

Lucas,

Are you planning pursue the merge of these patches.

Verification is not fixed at B Stepping too. And we need this WA for the performance.

Thanks,
-Ram
> 
> Lucas De Marchi
> 
> >
> > > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +       val |= FF_MODE2_TDS_TIMER_128;
> > > +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > >  }
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi
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[PATCH 1/2] drm/i915/tgl: Implement Wa_1604555607

[Ramalingam C]

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h             | 4 ++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..93efefa205d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,9 +568,17 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

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