From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] coresight: etm4x: Add missing API to set EL match on address filters Date: Mon, 4 Nov 2019 11:12:43 -0700 [thread overview] Message-ID: <20191104181251.26732-7-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> From: Mike Leach <mike.leach@linaro.org> TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc8156318018..97a33cf98797 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val & ~((GENMASK(14, 8) >> 8))) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/14] coresight: etm4x: Add missing API to set EL match on address filters Date: Mon, 4 Nov 2019 11:12:43 -0700 [thread overview] Message-ID: <20191104181251.26732-7-mathieu.poirier@linaro.org> (raw) In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> From: Mike Leach <mike.leach@linaro.org> TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc8156318018..97a33cf98797 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val & ~((GENMASK(14, 8) >> 8))) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-04 18:13 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-04 18:12 [PATCH 00/14] coresight: next v5.4-rc6 Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 01/14] coresight: etm4x: Save/restore state across CPU low power states Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 02/14] dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 03/14] coresight: etm4x: Add support for ThunderX2 Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 04/14] coresight: etm4x: Fixes for ETM v4.4 architecture updates Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 05/14] coresight: etm4x: Fix input validation for sysfs Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier [this message] 2019-11-04 18:12 ` [PATCH 06/14] coresight: etm4x: Add missing API to set EL match on address filters Mathieu Poirier 2019-11-04 18:12 ` [PATCH 07/14] coresight: etm4x: Fix issues with start-stop logic Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 08/14] coresight: etm4x: Improve usability of sysfs - include/exclude addr Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 09/14] coresight: etm4x: Improve usability of sysfs - CID and VMID masks Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 10/14] coresight: etm4x: Add view comparator settings API to sysfs Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 11/14] coresight: etm4x: Add missing single-shot control " Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 12/14] coresight: Add explicit architecture dependency Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 13/14] coresight: Serialize enabling/disabling a link device Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 18:12 ` [PATCH 14/14] coresight: etm4x: Fix BMVAL misuse Mathieu Poirier 2019-11-04 18:12 ` Mathieu Poirier 2019-11-04 21:03 ` [PATCH 00/14] coresight: next v5.4-rc6 Greg KH 2019-11-04 21:03 ` Greg KH
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191104181251.26732-7-mathieu.poirier@linaro.org \ --to=mathieu.poirier@linaro.org \ --cc=gregkh@linuxfoundation.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.