* [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock
@ 2020-01-02 21:11 Alex Sierra
2020-01-02 21:11 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
2020-01-02 21:41 ` [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Yong Zhao
0 siblings, 2 replies; 12+ messages in thread
From: Alex Sierra @ 2020-01-02 21:11 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Sierra
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 40 +++++++++++++++++++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++-
2 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b999b67ff57a..d6aba4f9df74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -82,6 +82,32 @@ struct amdgpu_prt_cb {
struct dma_fence_cb cb;
};
+/**
+ * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
+ * happens while holding this lock anywhere to prevent deadlocks when
+ * an MMU notifier runs in reclaim-FS context.
+ */
+static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
+{
+ mutex_lock(&vm->eviction_lock);
+ vm->saved_flags = memalloc_nofs_save();
+}
+
+static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
+{
+ if (mutex_trylock(&vm->eviction_lock)) {
+ vm->saved_flags = memalloc_nofs_save();
+ return 1;
+ }
+ return 0;
+}
+
+static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
+{
+ memalloc_nofs_restore(vm->saved_flags);
+ mutex_unlock(&vm->eviction_lock);
+}
+
/**
* amdgpu_vm_level_shift - return the addr shift for each level
*
@@ -678,9 +704,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
}
}
- mutex_lock(&vm->eviction_lock);
+ amdgpu_vm_eviction_lock(vm);
vm->evicting = false;
- mutex_unlock(&vm->eviction_lock);
+ amdgpu_vm_eviction_unlock(vm);
return 0;
}
@@ -1559,7 +1585,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_KFD;
- mutex_lock(&vm->eviction_lock);
+ amdgpu_vm_eviction_lock(vm);
if (vm->evicting) {
r = -EBUSY;
goto error_unlock;
@@ -1576,7 +1602,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
r = vm->update_funcs->commit(¶ms, fence);
error_unlock:
- mutex_unlock(&vm->eviction_lock);
+ amdgpu_vm_eviction_unlock(vm);
return r;
}
@@ -2537,18 +2563,18 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
return false;
/* Try to block ongoing updates */
- if (!mutex_trylock(&bo_base->vm->eviction_lock))
+ if (!amdgpu_vm_eviction_trylock(bo_base->vm))
return false;
/* Don't evict VM page tables while they are updated */
if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
!dma_fence_is_signaled(bo_base->vm->last_delayed)) {
- mutex_unlock(&bo_base->vm->eviction_lock);
+ amdgpu_vm_eviction_unlock(bo_base->vm);
return false;
}
bo_base->vm->evicting = true;
- mutex_unlock(&bo_base->vm->eviction_lock);
+ amdgpu_vm_eviction_unlock(bo_base->vm);
return true;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 100547f094ff..c21a36bebc0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -30,6 +30,7 @@
#include <drm/gpu_scheduler.h>
#include <drm/drm_file.h>
#include <drm/ttm/ttm_bo_driver.h>
+#include <linux/sched/mm.h>
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
@@ -242,9 +243,12 @@ struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached va;
- /* Lock to prevent eviction while we are updating page tables */
+ /* Lock to prevent eviction while we are updating page tables
+ * use vm_eviction_lock/unlock(vm)
+ */
struct mutex eviction_lock;
bool evicting;
+ unsigned int saved_flags;
/* BOs who needs a validation */
struct list_head evicted;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-02 21:11 [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Alex Sierra
@ 2020-01-02 21:11 ` Alex Sierra
2020-01-02 21:31 ` Yong Zhao
2020-01-02 21:41 ` [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Yong Zhao
1 sibling, 1 reply; 12+ messages in thread
From: Alex Sierra @ 2020-01-02 21:11 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Sierra
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 87 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 +++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 89 +++++++++++++++++++++++++
5 files changed, 249 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index b499a3de8bb6..b6413a56f546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type);
+ /* flush the vm tlb via pasid */
+ int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+ uint32_t flush_type, bool all_hub);
/* flush the vm tlb via ring */
uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr);
@@ -216,6 +219,9 @@ struct amdgpu_gmc {
};
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
+ ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
+ ((adev), (pasid), (type), (allhub)))
#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f5725336a5f2..11a2252e60f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -30,6 +30,8 @@
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "oss/osssys_5_0_0_offset.h"
@@ -37,6 +39,7 @@
#include "navi10_enum.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "nbio_v2_3.h"
@@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
(!amdgpu_sriov_vf(adev)));
}
+static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
+ struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ + vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -380,6 +425,47 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
+/**
+ * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid, i;
+ uint16_t queried_pasid;
+ bool ret;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ if (amdgpu_emu_mode == 0 && ring->sched.ready)
+ return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
+ pasid, flush_type, all_hub);
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
+ &queried_pasid);
+ if (ret && queried_pasid == pasid) {
+ if (all_hub) {
+ for (i = 0; i < adev->num_vmhubs; i++)
+ gmc_v10_0_flush_gpu_tlb(adev, vmid,
+ i, 0);
+ } else {
+ gmc_v10_0_flush_gpu_tlb(adev, vmid,
+ AMDGPU_GFXHUB_0, 0);
+ }
+ break;
+ }
+ }
+
+ return 0;
+}
+
static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
{
@@ -531,6 +617,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
.map_mtype = gmc_v10_0_map_mtype,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index f08e5330642d..19d5b133e1d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
return 0;
}
+/**
+ * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid;
+ unsigned int tmp;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+ if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
+ (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
+ WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+ RREG32(mmVM_INVALIDATE_RESPONSE);
+ break;
+ }
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
.set_prt = gmc_v7_0_set_prt,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 6d96d40fbcb8..27d83204fa2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
return 0;
}
+/**
+ * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid;
+ unsigned int tmp;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+ if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
+ (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
+ WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+ RREG32(mmVM_INVALIDATE_RESPONSE);
+ break;
+ }
+ }
+
+ return 0;
+
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
.set_prt = gmc_v8_0_set_prt,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 68f9a1fa6dc1..1854b9920486 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -38,10 +38,12 @@
#include "dce/dce_12_0_sh_mask.h"
#include "vega10_enum.h"
#include "mmhub/mmhub_1_0_offset.h"
+#include "athub/athub_1_0_sh_mask.h"
#include "athub/athub_1_0_offset.h"
#include "oss/osssys_4_0_offset.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "umc/umc_6_0_sh_mask.h"
@@ -439,6 +441,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
adev->pdev->device == 0x15d8)));
}
+static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ + vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -537,6 +580,51 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
DRM_ERROR("Timeout waiting for VM flush ACK!\n");
}
+/**
+ * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid, i;
+ uint16_t queried_pasid;
+ bool ret;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ if (ring->sched.ready)
+ return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
+ pasid, flush_type, all_hub);
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
+ &queried_pasid);
+ if (ret && queried_pasid == pasid) {
+ if (all_hub) {
+ for (i = 0; i < adev->num_vmhubs; i++)
+ gmc_v9_0_flush_gpu_tlb(adev, vmid,
+ i, 0);
+ } else {
+ gmc_v9_0_flush_gpu_tlb(adev, vmid,
+ AMDGPU_GFXHUB_0, 0);
+ }
+ break;
+ }
+ }
+
+ return 0;
+
+}
+
static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
{
@@ -698,6 +786,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
.map_mtype = gmc_v9_0_map_mtype,
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-02 21:11 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
@ 2020-01-02 21:31 ` Yong Zhao
0 siblings, 0 replies; 12+ messages in thread
From: Yong Zhao @ 2020-01-02 21:31 UTC (permalink / raw)
To: amd-gfx
See one inline comment. Other than that:
Acked-by: Yong Zhao <Yong.Zhao@amd.com>
On 2020-01-02 4:11 p.m., Alex Sierra wrote:
> This can be used directly from amdgpu and amdkfd to invalidate
> TLB through pasid.
> It supports gmc v7, v8, v9 and v10.
>
> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 87 ++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 +++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 89 +++++++++++++++++++++++++
> 5 files changed, 249 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index b499a3de8bb6..b6413a56f546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
> /* flush the vm tlb via mmio */
> void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
> uint32_t vmhub, uint32_t flush_type);
> + /* flush the vm tlb via pasid */
> + int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
> + uint32_t flush_type, bool all_hub);
> /* flush the vm tlb via ring */
> uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> uint64_t pd_addr);
> @@ -216,6 +219,9 @@ struct amdgpu_gmc {
> };
>
> #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> +#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
> + ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
> + ((adev), (pasid), (type), (allhub)))
> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
> #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f5725336a5f2..11a2252e60f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -30,6 +30,8 @@
> #include "hdp/hdp_5_0_0_sh_mask.h"
> #include "gc/gc_10_1_0_sh_mask.h"
> #include "mmhub/mmhub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_sh_mask.h"
> #include "oss/osssys_5_0_0_offset.h"
> @@ -37,6 +39,7 @@
> #include "navi10_enum.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
>
> #include "nbio_v2_3.h"
> @@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> (!amdgpu_sriov_vf(adev)));
> }
>
> +static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
> + struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -380,6 +425,47 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
> }
>
> +/**
> + * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid, i;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (amdgpu_emu_mode == 0 && ring->sched.ready)
> + return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
[yz] A space instead of a tab should be used between ret and &&.
It is better to decrease the indent by doing this:
if (!ret || queried_pasid != pasid)
continue;
The same applies to gfx9.
> + if (all_hub) {
> + for (i = 0; i < adev->num_vmhubs; i++)
> + gmc_v10_0_flush_gpu_tlb(adev, vmid,
> + i, 0);
> + } else {
> + gmc_v10_0_flush_gpu_tlb(adev, vmid,
> + AMDGPU_GFXHUB_0, 0);
> + }
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -531,6 +617,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
> .map_mtype = gmc_v10_0_map_mtype,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index f08e5330642d..19d5b133e1d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
> .set_prt = gmc_v7_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 6d96d40fbcb8..27d83204fa2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
> .set_prt = gmc_v8_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 68f9a1fa6dc1..1854b9920486 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -38,10 +38,12 @@
> #include "dce/dce_12_0_sh_mask.h"
> #include "vega10_enum.h"
> #include "mmhub/mmhub_1_0_offset.h"
> +#include "athub/athub_1_0_sh_mask.h"
> #include "athub/athub_1_0_offset.h"
> #include "oss/osssys_4_0_offset.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
> #include "umc/umc_6_0_sh_mask.h"
>
> @@ -439,6 +441,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> adev->pdev->device == 0x15d8)));
> }
>
> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -537,6 +580,51 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
> }
>
> +/**
> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid, i;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + if (ring->sched.ready)
> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + if (all_hub) {
> + for (i = 0; i < adev->num_vmhubs; i++)
> + gmc_v9_0_flush_gpu_tlb(adev, vmid,
> + i, 0);
> + } else {
> + gmc_v9_0_flush_gpu_tlb(adev, vmid,
> + AMDGPU_GFXHUB_0, 0);
> + }
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -698,6 +786,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
> .map_mtype = gmc_v9_0_map_mtype,
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock
2020-01-02 21:11 [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Alex Sierra
2020-01-02 21:11 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
@ 2020-01-02 21:41 ` Yong Zhao
1 sibling, 0 replies; 12+ messages in thread
From: Yong Zhao @ 2020-01-02 21:41 UTC (permalink / raw)
To: amd-gfx
One comment inline.
On 2020-01-02 4:11 p.m., Alex Sierra wrote:
> [Why]
> Avoid reclaim filesystem while eviction lock is held called from
> MMU notifier.
>
> [How]
> Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
> Using memalloc_nofs_save / memalloc_nofs_restore API.
>
> Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 40 +++++++++++++++++++++-----
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++-
> 2 files changed, 38 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index b999b67ff57a..d6aba4f9df74 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -82,6 +82,32 @@ struct amdgpu_prt_cb {
> struct dma_fence_cb cb;
> };
>
> +/**
> + * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
> + * happens while holding this lock anywhere to prevent deadlocks when
> + * an MMU notifier runs in reclaim-FS context.
> + */
> +static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
> +{
> + mutex_lock(&vm->eviction_lock);
> + vm->saved_flags = memalloc_nofs_save();
[yz] I feel memalloc_nofs_save() should be called before mutex_lock().
Not too sure though.
> +}
> +
> +static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
> +{
> + if (mutex_trylock(&vm->eviction_lock)) {
> + vm->saved_flags = memalloc_nofs_save();
> + return 1;
> + }
> + return 0;
> +}
> +
> +static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
> +{
> + memalloc_nofs_restore(vm->saved_flags);
> + mutex_unlock(&vm->eviction_lock);
> +}
> +
> /**
> * amdgpu_vm_level_shift - return the addr shift for each level
> *
> @@ -678,9 +704,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> }
> }
>
> - mutex_lock(&vm->eviction_lock);
> + amdgpu_vm_eviction_lock(vm);
> vm->evicting = false;
> - mutex_unlock(&vm->eviction_lock);
> + amdgpu_vm_eviction_unlock(vm);
>
> return 0;
> }
> @@ -1559,7 +1585,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
> if (!(flags & AMDGPU_PTE_VALID))
> owner = AMDGPU_FENCE_OWNER_KFD;
>
> - mutex_lock(&vm->eviction_lock);
> + amdgpu_vm_eviction_lock(vm);
> if (vm->evicting) {
> r = -EBUSY;
> goto error_unlock;
> @@ -1576,7 +1602,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
> r = vm->update_funcs->commit(¶ms, fence);
>
> error_unlock:
> - mutex_unlock(&vm->eviction_lock);
> + amdgpu_vm_eviction_unlock(vm);
> return r;
> }
>
> @@ -2537,18 +2563,18 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
> return false;
>
> /* Try to block ongoing updates */
> - if (!mutex_trylock(&bo_base->vm->eviction_lock))
> + if (!amdgpu_vm_eviction_trylock(bo_base->vm))
> return false;
>
> /* Don't evict VM page tables while they are updated */
> if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
> !dma_fence_is_signaled(bo_base->vm->last_delayed)) {
> - mutex_unlock(&bo_base->vm->eviction_lock);
> + amdgpu_vm_eviction_unlock(bo_base->vm);
> return false;
> }
>
> bo_base->vm->evicting = true;
> - mutex_unlock(&bo_base->vm->eviction_lock);
> + amdgpu_vm_eviction_unlock(bo_base->vm);
> return true;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 100547f094ff..c21a36bebc0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -30,6 +30,7 @@
> #include <drm/gpu_scheduler.h>
> #include <drm/drm_file.h>
> #include <drm/ttm/ttm_bo_driver.h>
> +#include <linux/sched/mm.h>
>
> #include "amdgpu_sync.h"
> #include "amdgpu_ring.h"
> @@ -242,9 +243,12 @@ struct amdgpu_vm {
> /* tree of virtual addresses mapped */
> struct rb_root_cached va;
>
> - /* Lock to prevent eviction while we are updating page tables */
> + /* Lock to prevent eviction while we are updating page tables
> + * use vm_eviction_lock/unlock(vm)
> + */
> struct mutex eviction_lock;
> bool evicting;
> + unsigned int saved_flags;
>
> /* BOs who needs a validation */
> struct list_head evicted;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-07 1:09 ` Sierra Guiza, Alejandro (Alex)
@ 2020-01-07 12:37 ` Christian König
0 siblings, 0 replies; 12+ messages in thread
From: Christian König @ 2020-01-07 12:37 UTC (permalink / raw)
To: Sierra Guiza, Alejandro (Alex),
Koenig, Christian, Kuehling, Felix, amd-gfx
Am 07.01.20 um 02:09 schrieb Sierra Guiza, Alejandro (Alex):
> [AMD Official Use Only - Internal Distribution Only]
>
>
>
> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@amd.com>
> Sent: Monday, January 6, 2020 10:23 AM
> To: Kuehling, Felix <Felix.Kuehling@amd.com>; amd-gfx@lists.freedesktop.org; Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>
> Subject: Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
>
> Am 06.01.20 um 17:04 schrieb Felix Kuehling:
>> On 2020-01-05 10:41 a.m., Christian König wrote:
>>> Am 20.12.19 um 07:24 schrieb Alex Sierra:
>>>> This can be used directly from amdgpu and amdkfd to invalidate TLB
>>>> through pasid.
>>>> It supports gmc v7, v8, v9 and v10.
>>>>
>>>> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
>>>> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81
>>>> ++++++++++++++++++++++++
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84
>>>> +++++++++++++++++++++++++
>>>> 5 files changed, 238 insertions(+)
>> [snip]
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>>> index fa025ceeea0f..eb1e64bd56ed 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>>> @@ -38,10 +38,12 @@
>>>> #include "dce/dce_12_0_sh_mask.h"
>>>> #include "vega10_enum.h"
>>>> #include "mmhub/mmhub_1_0_offset.h"
>>>> +#include "athub/athub_1_0_sh_mask.h"
>>>> #include "athub/athub_1_0_offset.h"
>>>> #include "oss/osssys_4_0_offset.h"
>>>> #include "soc15.h"
>>>> +#include "soc15d.h"
>>>> #include "soc15_common.h"
>>>> #include "umc/umc_6_0_sh_mask.h"
>>>> @@ -434,6 +436,47 @@ static bool
>>>> gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
>>>> adev->pdev->device == 0x15d8)));
>>>> }
>>>> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct
>>>> amdgpu_device *adev,
>>>> + uint8_t vmid, uint16_t *p_pasid) {
>>>> + uint32_t value;
>>>> +
>>>> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0,
>>>> mmATC_VMID0_PASID_MAPPING)
>>>> + + vmid);
>>>> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
>>>> +
>>>> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
>>>> +}
>>> Probably better to expose just this function in the GMC interface.
>> This is called below in gmc_v9_0_flush_gpu_tlb_pasid in the case that
>> the KIQ is not ready. It is not needed outside this file, so no need
>> to expose it in the GMC interface.
>>
>>
>>>> +
>>>> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device
>>>> *adev,
>>>> + uint16_t pasid, uint32_t flush_type,
>>>> + bool all_hub)
>>>> +{
>>>> + signed long r;
>>>> + uint32_t seq;
>>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>>> +
>>>> + spin_lock(&adev->gfx.kiq.ring_lock);
>>>> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs
>>>> +package*/
>>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
>>>> + amdgpu_ring_write(ring,
>>>> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
>>>> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
>>>> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
>>>> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
>>>> That stuff is completely unrelated to the GMC and shouldn't be added
>>>> here.
>>> Where else should it go? To me TLB flushing is very much something
>>> that belongs in this file.
>>>
>>> Maybe you'd rather add "flush_tlbs_with_kiq" to amdgpu_ring_funcs and
>>> implement it in the gfx_v*.c GFX-IP code? I'm not sure that makes much
>>> sense either because it's only available on the KIQ ring.
>> Yes, something like this. We should probably add a amdgpu_kiq_funcs and expose the functions needed by the GMC code there.
>> See the amdgpu_virt_kiq_reg_write_reg_wait() case for reference, it is very similar and should probably be added to that function table as well.
>> Christian.
> To summarize:
> 1.- The idea is to add a new function pointer to the amdgpu_ring_funcs to flush the tlbs with kiq.
I would add a new amdgpu_kiq_funcs structure for that.
> 2.- This function pointer should be pointed and implemented on each of the gfx_v*.c under the gfx_*_ring_funcs_kiq struct. If this is true, Im not seeing this struct on the gfx_v10.c file.
> 3.- Use the amdgpu_virt_kiq_reg_write_reg_wait as a reference for the implementation.
Well yes and no, the amdgpu_virt_kiq_reg_write_reg_wait() was just an
example of a similar case.
The function amdgpu_virt_kiq_reg_write_reg_wait() should probably be
cleaned up and moved into the gfx_*.c files as well.
Regards,
Christian.
>
>>>
>>>> Christian.
>>>>
>>>> + amdgpu_fence_emit_polling(ring, &seq);
>>>> + amdgpu_ring_commit(ring);
>>>> + spin_unlock(&adev->gfx.kiq.ring_lock);
>>>> +
>>>> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
>>>> + if (r < 1) {
>>>> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
>>>> + return -ETIME;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> /*
>>>> * GART
>>>> * VMID 0 is the physical GPU addresses as used by the kernel.
>>>> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct
>>>> amdgpu_device *adev, uint32_t vmid,
>>>> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
>>>> }
>>>> +/**
>>>> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
>>>> + *
>>>> + * @adev: amdgpu_device pointer
>>>> + * @pasid: pasid to be flush
>>>> + *
>>>> + * Flush the TLB for the requested pasid.
>>>> + */
>>>> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
>>>> + uint16_t pasid, uint32_t flush_type,
>>>> + bool all_hub)
>> Christian, do you agree that this function belongs in the GMC
>> interface? If not here, where do you suggest moving it?
>>
>> Regards,
>> Felix
>>
>>
>>>> +{
>>>> + int vmid, i;
>>>> + uint16_t queried_pasid;
>>>> + bool ret;
>>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>>> +
>>>> + if (adev->in_gpu_reset)
>>>> + return -EIO;
>>>> +
>>>> + if (ring->sched.ready)
>>>> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
>>>> + pasid, flush_type, all_hub);
>>>> +
>>>> + for (vmid = 1; vmid < 16; vmid++) {
>>>> +
>>>> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
>>>> + &queried_pasid);
>>>> + if (ret && queried_pasid == pasid) {
>>>> + for (i = 0; i < adev->num_vmhubs; i++)
>>>> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>>>> + i, flush_type);
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> + return 0;
>>>> +
>>>> +}
>>>> +
>>>> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring
>>>> *ring,
>>>> unsigned vmid, uint64_t pd_addr)
>>>> {
>>>> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct
>>>> amdgpu_device *adev,
>>>> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
>>>> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
>>>> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
>>>> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
>>>> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
>>>> .map_mtype = gmc_v9_0_map_mtype,
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
>>> ts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7C
>>> felix.kuehling%40amd.com%7C0ebb82d62d1044ea57b608d791f5b021%7C3dd8961
>>> fe4884e608e11a82d994e183d%7C0%7C0%7C637138356784407460&sdata=K8zh
>>> HT2YYFj8LXdD3YiihtNkbKNwa0ml6nQZ74zF828%3D&reserved=0
>>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-06 16:23 ` Christian König
@ 2020-01-07 1:09 ` Sierra Guiza, Alejandro (Alex)
2020-01-07 12:37 ` Christian König
0 siblings, 1 reply; 12+ messages in thread
From: Sierra Guiza, Alejandro (Alex) @ 2020-01-07 1:09 UTC (permalink / raw)
To: Koenig, Christian, Kuehling, Felix, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
-----Original Message-----
From: Koenig, Christian <Christian.Koenig@amd.com>
Sent: Monday, January 6, 2020 10:23 AM
To: Kuehling, Felix <Felix.Kuehling@amd.com>; amd-gfx@lists.freedesktop.org; Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>
Subject: Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
Am 06.01.20 um 17:04 schrieb Felix Kuehling:
> On 2020-01-05 10:41 a.m., Christian König wrote:
>> Am 20.12.19 um 07:24 schrieb Alex Sierra:
>>> This can be used directly from amdgpu and amdkfd to invalidate TLB
>>> through pasid.
>>> It supports gmc v7, v8, v9 and v10.
>>>
>>> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
>>> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81
>>> ++++++++++++++++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84
>>> +++++++++++++++++++++++++
>>> 5 files changed, 238 insertions(+)
> [snip]
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> index fa025ceeea0f..eb1e64bd56ed 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> @@ -38,10 +38,12 @@
>>> #include "dce/dce_12_0_sh_mask.h"
>>> #include "vega10_enum.h"
>>> #include "mmhub/mmhub_1_0_offset.h"
>>> +#include "athub/athub_1_0_sh_mask.h"
>>> #include "athub/athub_1_0_offset.h"
>>> #include "oss/osssys_4_0_offset.h"
>>> #include "soc15.h"
>>> +#include "soc15d.h"
>>> #include "soc15_common.h"
>>> #include "umc/umc_6_0_sh_mask.h"
>>> @@ -434,6 +436,47 @@ static bool
>>> gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
>>> adev->pdev->device == 0x15d8)));
>>> }
>>> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct
>>> amdgpu_device *adev,
>>> + uint8_t vmid, uint16_t *p_pasid) {
>>> + uint32_t value;
>>> +
>>> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0,
>>> mmATC_VMID0_PASID_MAPPING)
>>> + + vmid);
>>> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
>>> +
>>> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
>>> +}
>>
>> Probably better to expose just this function in the GMC interface.
>
> This is called below in gmc_v9_0_flush_gpu_tlb_pasid in the case that
> the KIQ is not ready. It is not needed outside this file, so no need
> to expose it in the GMC interface.
>
>
>>
>>> +
>>> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device
>>> *adev,
>>> + uint16_t pasid, uint32_t flush_type,
>>> + bool all_hub)
>>> +{
>>> + signed long r;
>>> + uint32_t seq;
>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>> +
>>> + spin_lock(&adev->gfx.kiq.ring_lock);
>>> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs
>>> +package*/
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
>>> + amdgpu_ring_write(ring,
>>> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
>>> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
>>> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
>>> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
>>
>>> That stuff is completely unrelated to the GMC and shouldn't be added
>>> here.
>>
>> Where else should it go? To me TLB flushing is very much something
>> that belongs in this file.
>>
>> Maybe you'd rather add "flush_tlbs_with_kiq" to amdgpu_ring_funcs and
>> implement it in the gfx_v*.c GFX-IP code? I'm not sure that makes much
>> sense either because it's only available on the KIQ ring.
>Yes, something like this. We should probably add a amdgpu_kiq_funcs and expose the functions needed by the GMC code there.
>See the amdgpu_virt_kiq_reg_write_reg_wait() case for reference, it is very similar and should probably be added to that function table as well.
>Christian.
To summarize:
1.- The idea is to add a new function pointer to the amdgpu_ring_funcs to flush the tlbs with kiq.
2.- This function pointer should be pointed and implemented on each of the gfx_v*.c under the gfx_*_ring_funcs_kiq struct. If this is true, Im not seeing this struct on the gfx_v10.c file.
3.- Use the amdgpu_virt_kiq_reg_write_reg_wait as a reference for the implementation.
>>
>>
>>>
>>> Christian.
>>>
>>> + amdgpu_fence_emit_polling(ring, &seq);
>>> + amdgpu_ring_commit(ring);
>>> + spin_unlock(&adev->gfx.kiq.ring_lock);
>>> +
>>> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
>>> + if (r < 1) {
>>> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
>>> + return -ETIME;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> /*
>>> * GART
>>> * VMID 0 is the physical GPU addresses as used by the kernel.
>>> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct
>>> amdgpu_device *adev, uint32_t vmid,
>>> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
>>> }
>>> +/**
>>> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
>>> + *
>>> + * @adev: amdgpu_device pointer
>>> + * @pasid: pasid to be flush
>>> + *
>>> + * Flush the TLB for the requested pasid.
>>> + */
>>> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
>>> + uint16_t pasid, uint32_t flush_type,
>>> + bool all_hub)
>
> Christian, do you agree that this function belongs in the GMC
> interface? If not here, where do you suggest moving it?
>
> Regards,
> Felix
>
>
>>> +{
>>> + int vmid, i;
>>> + uint16_t queried_pasid;
>>> + bool ret;
>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>> +
>>> + if (adev->in_gpu_reset)
>>> + return -EIO;
>>> +
>>> + if (ring->sched.ready)
>>> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
>>> + pasid, flush_type, all_hub);
>>> +
>>> + for (vmid = 1; vmid < 16; vmid++) {
>>> +
>>> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
>>> + &queried_pasid);
>>> + if (ret && queried_pasid == pasid) {
>>> + for (i = 0; i < adev->num_vmhubs; i++)
>>> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>>> + i, flush_type);
>>> + break;
>>> + }
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +}
>>> +
>>> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring
>>> *ring,
>>> unsigned vmid, uint64_t pd_addr)
>>> {
>>> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct
>>> amdgpu_device *adev,
>>> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
>>> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
>>> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
>>> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
>>> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
>>> .map_mtype = gmc_v9_0_map_mtype,
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
>> ts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7C
>> felix.kuehling%40amd.com%7C0ebb82d62d1044ea57b608d791f5b021%7C3dd8961
>> fe4884e608e11a82d994e183d%7C0%7C0%7C637138356784407460&sdata=K8zh
>> HT2YYFj8LXdD3YiihtNkbKNwa0ml6nQZ74zF828%3D&reserved=0
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-06 16:04 ` Felix Kuehling
@ 2020-01-06 16:23 ` Christian König
2020-01-07 1:09 ` Sierra Guiza, Alejandro (Alex)
0 siblings, 1 reply; 12+ messages in thread
From: Christian König @ 2020-01-06 16:23 UTC (permalink / raw)
To: Felix Kuehling, amd-gfx, Sierra Guiza, Alejandro (Alex)
Am 06.01.20 um 17:04 schrieb Felix Kuehling:
> On 2020-01-05 10:41 a.m., Christian König wrote:
>> Am 20.12.19 um 07:24 schrieb Alex Sierra:
>>> This can be used directly from amdgpu and amdkfd to invalidate
>>> TLB through pasid.
>>> It supports gmc v7, v8, v9 and v10.
>>>
>>> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
>>> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84
>>> +++++++++++++++++++++++++
>>> 5 files changed, 238 insertions(+)
> [snip]
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> index fa025ceeea0f..eb1e64bd56ed 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> @@ -38,10 +38,12 @@
>>> #include "dce/dce_12_0_sh_mask.h"
>>> #include "vega10_enum.h"
>>> #include "mmhub/mmhub_1_0_offset.h"
>>> +#include "athub/athub_1_0_sh_mask.h"
>>> #include "athub/athub_1_0_offset.h"
>>> #include "oss/osssys_4_0_offset.h"
>>> #include "soc15.h"
>>> +#include "soc15d.h"
>>> #include "soc15_common.h"
>>> #include "umc/umc_6_0_sh_mask.h"
>>> @@ -434,6 +436,47 @@ static bool
>>> gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
>>> adev->pdev->device == 0x15d8)));
>>> }
>>> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct
>>> amdgpu_device *adev,
>>> + uint8_t vmid, uint16_t *p_pasid)
>>> +{
>>> + uint32_t value;
>>> +
>>> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0,
>>> mmATC_VMID0_PASID_MAPPING)
>>> + + vmid);
>>> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
>>> +
>>> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
>>> +}
>>
>> Probably better to expose just this function in the GMC interface.
>
> This is called below in gmc_v9_0_flush_gpu_tlb_pasid in the case that
> the KIQ is not ready. It is not needed outside this file, so no need
> to expose it in the GMC interface.
>
>
>>
>>> +
>>> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device
>>> *adev,
>>> + uint16_t pasid, uint32_t flush_type,
>>> + bool all_hub)
>>> +{
>>> + signed long r;
>>> + uint32_t seq;
>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>> +
>>> + spin_lock(&adev->gfx.kiq.ring_lock);
>>> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
>>> + amdgpu_ring_write(ring,
>>> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
>>> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
>>> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
>>> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
>>
>> That stuff is completely unrelated to the GMC and shouldn't be added
>> here.
>
> Where else should it go? To me TLB flushing is very much something
> that belongs in this file.
>
> Maybe you'd rather add "flush_tlbs_with_kiq" to amdgpu_ring_funcs and
> implement it in the gfx_v*.c GFX-IP code? I'm not sure that makes much
> sense either because it's only available on the KIQ ring.
Yes, something like this. We should probably add a amdgpu_kiq_funcs and
expose the functions needed by the GMC code there.
See the amdgpu_virt_kiq_reg_write_reg_wait() case for reference, it is
very similar and should probably be added to that function table as well.
Christian.
>
>
>>
>> Christian.
>>
>>> + amdgpu_fence_emit_polling(ring, &seq);
>>> + amdgpu_ring_commit(ring);
>>> + spin_unlock(&adev->gfx.kiq.ring_lock);
>>> +
>>> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
>>> + if (r < 1) {
>>> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
>>> + return -ETIME;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> /*
>>> * GART
>>> * VMID 0 is the physical GPU addresses as used by the kernel.
>>> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct
>>> amdgpu_device *adev, uint32_t vmid,
>>> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
>>> }
>>> +/**
>>> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
>>> + *
>>> + * @adev: amdgpu_device pointer
>>> + * @pasid: pasid to be flush
>>> + *
>>> + * Flush the TLB for the requested pasid.
>>> + */
>>> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
>>> + uint16_t pasid, uint32_t flush_type,
>>> + bool all_hub)
>
> Christian, do you agree that this function belongs in the GMC
> interface? If not here, where do you suggest moving it?
>
> Regards,
> Felix
>
>
>>> +{
>>> + int vmid, i;
>>> + uint16_t queried_pasid;
>>> + bool ret;
>>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>>> +
>>> + if (adev->in_gpu_reset)
>>> + return -EIO;
>>> +
>>> + if (ring->sched.ready)
>>> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
>>> + pasid, flush_type, all_hub);
>>> +
>>> + for (vmid = 1; vmid < 16; vmid++) {
>>> +
>>> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
>>> + &queried_pasid);
>>> + if (ret && queried_pasid == pasid) {
>>> + for (i = 0; i < adev->num_vmhubs; i++)
>>> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>>> + i, flush_type);
>>> + break;
>>> + }
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +}
>>> +
>>> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>> unsigned vmid, uint64_t pd_addr)
>>> {
>>> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct
>>> amdgpu_device *adev,
>>> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
>>> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
>>> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
>>> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
>>> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
>>> .map_mtype = gmc_v9_0_map_mtype,
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cfelix.kuehling%40amd.com%7C0ebb82d62d1044ea57b608d791f5b021%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637138356784407460&sdata=K8zhHT2YYFj8LXdD3YiihtNkbKNwa0ml6nQZ74zF828%3D&reserved=0
>>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2020-01-05 15:41 ` Christian König
@ 2020-01-06 16:04 ` Felix Kuehling
2020-01-06 16:23 ` Christian König
0 siblings, 1 reply; 12+ messages in thread
From: Felix Kuehling @ 2020-01-06 16:04 UTC (permalink / raw)
To: amd-gfx, Christian König, Sierra Guiza, Alejandro (Alex)
On 2020-01-05 10:41 a.m., Christian König wrote:
> Am 20.12.19 um 07:24 schrieb Alex Sierra:
>> This can be used directly from amdgpu and amdkfd to invalidate
>> TLB through pasid.
>> It supports gmc v7, v8, v9 and v10.
>>
>> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
>> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +++++++++++++++++++++++++
>> 5 files changed, 238 insertions(+)
[snip]
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index fa025ceeea0f..eb1e64bd56ed 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -38,10 +38,12 @@
>> #include "dce/dce_12_0_sh_mask.h"
>> #include "vega10_enum.h"
>> #include "mmhub/mmhub_1_0_offset.h"
>> +#include "athub/athub_1_0_sh_mask.h"
>> #include "athub/athub_1_0_offset.h"
>> #include "oss/osssys_4_0_offset.h"
>> #include "soc15.h"
>> +#include "soc15d.h"
>> #include "soc15_common.h"
>> #include "umc/umc_6_0_sh_mask.h"
>> @@ -434,6 +436,47 @@ static bool
>> gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
>> adev->pdev->device == 0x15d8)));
>> }
>> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct
>> amdgpu_device *adev,
>> + uint8_t vmid, uint16_t *p_pasid)
>> +{
>> + uint32_t value;
>> +
>> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0,
>> mmATC_VMID0_PASID_MAPPING)
>> + + vmid);
>> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
>> +
>> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
>> +}
>
> Probably better to expose just this function in the GMC interface.
This is called below in gmc_v9_0_flush_gpu_tlb_pasid in the case that
the KIQ is not ready. It is not needed outside this file, so no need to
expose it in the GMC interface.
>
>> +
>> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device
>> *adev,
>> + uint16_t pasid, uint32_t flush_type,
>> + bool all_hub)
>> +{
>> + signed long r;
>> + uint32_t seq;
>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>> +
>> + spin_lock(&adev->gfx.kiq.ring_lock);
>> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
>> + amdgpu_ring_write(ring,
>> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
>> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
>> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
>> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
>
> That stuff is completely unrelated to the GMC and shouldn't be added
> here.
Where else should it go? To me TLB flushing is very much something that
belongs in this file.
Maybe you'd rather add "flush_tlbs_with_kiq" to amdgpu_ring_funcs and
implement it in the gfx_v*.c GFX-IP code? I'm not sure that makes much
sense either because it's only available on the KIQ ring.
>
> Christian.
>
>> + amdgpu_fence_emit_polling(ring, &seq);
>> + amdgpu_ring_commit(ring);
>> + spin_unlock(&adev->gfx.kiq.ring_lock);
>> +
>> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
>> + if (r < 1) {
>> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
>> + return -ETIME;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> /*
>> * GART
>> * VMID 0 is the physical GPU addresses as used by the kernel.
>> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct
>> amdgpu_device *adev, uint32_t vmid,
>> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
>> }
>> +/**
>> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
>> + *
>> + * @adev: amdgpu_device pointer
>> + * @pasid: pasid to be flush
>> + *
>> + * Flush the TLB for the requested pasid.
>> + */
>> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
>> + uint16_t pasid, uint32_t flush_type,
>> + bool all_hub)
Christian, do you agree that this function belongs in the GMC interface?
If not here, where do you suggest moving it?
Regards,
Felix
>> +{
>> + int vmid, i;
>> + uint16_t queried_pasid;
>> + bool ret;
>> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
>> +
>> + if (adev->in_gpu_reset)
>> + return -EIO;
>> +
>> + if (ring->sched.ready)
>> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
>> + pasid, flush_type, all_hub);
>> +
>> + for (vmid = 1; vmid < 16; vmid++) {
>> +
>> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
>> + &queried_pasid);
>> + if (ret && queried_pasid == pasid) {
>> + for (i = 0; i < adev->num_vmhubs; i++)
>> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>> + i, flush_type);
>> + break;
>> + }
>> + }
>> +
>> + return 0;
>> +
>> +}
>> +
>> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>> unsigned vmid, uint64_t pd_addr)
>> {
>> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct
>> amdgpu_device *adev,
>> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
>> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
>> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
>> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
>> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
>> .map_mtype = gmc_v9_0_map_mtype,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cfelix.kuehling%40amd.com%7C0ebb82d62d1044ea57b608d791f5b021%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637138356784407460&sdata=K8zhHT2YYFj8LXdD3YiihtNkbKNwa0ml6nQZ74zF828%3D&reserved=0
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2019-12-20 6:24 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
2019-12-20 21:32 ` Felix Kuehling
2019-12-20 23:51 ` Yong Zhao
@ 2020-01-05 15:41 ` Christian König
2020-01-06 16:04 ` Felix Kuehling
2 siblings, 1 reply; 12+ messages in thread
From: Christian König @ 2020-01-05 15:41 UTC (permalink / raw)
To: Alex Sierra, amd-gfx
Am 20.12.19 um 07:24 schrieb Alex Sierra:
> This can be used directly from amdgpu and amdkfd to invalidate
> TLB through pasid.
> It supports gmc v7, v8, v9 and v10.
>
> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +++++++++++++++++++++++++
> 5 files changed, 238 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index b499a3de8bb6..b6413a56f546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
> /* flush the vm tlb via mmio */
> void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
> uint32_t vmhub, uint32_t flush_type);
> + /* flush the vm tlb via pasid */
> + int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
> + uint32_t flush_type, bool all_hub);
> /* flush the vm tlb via ring */
> uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> uint64_t pd_addr);
> @@ -216,6 +219,9 @@ struct amdgpu_gmc {
> };
>
> #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> +#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
> + ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
> + ((adev), (pasid), (type), (allhub)))
> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
> #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f5725336a5f2..b1a5408a8d7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -30,6 +30,8 @@
> #include "hdp/hdp_5_0_0_sh_mask.h"
> #include "gc/gc_10_1_0_sh_mask.h"
> #include "mmhub/mmhub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_sh_mask.h"
> #include "oss/osssys_5_0_0_offset.h"
> @@ -37,6 +39,7 @@
> #include "navi10_enum.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
>
> #include "nbio_v2_3.h"
> @@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> (!amdgpu_sriov_vf(adev)));
> }
>
> +static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
> + struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
> }
>
> +/**
> + * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (amdgpu_emu_mode == 0 && ring->sched.ready)
> + return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + AMDGPU_GFXHUB_0, 0);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -531,6 +611,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
> .map_mtype = gmc_v10_0_map_mtype,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index f08e5330642d..19d5b133e1d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
> .set_prt = gmc_v7_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 6d96d40fbcb8..27d83204fa2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
> .set_prt = gmc_v8_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index fa025ceeea0f..eb1e64bd56ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -38,10 +38,12 @@
> #include "dce/dce_12_0_sh_mask.h"
> #include "vega10_enum.h"
> #include "mmhub/mmhub_1_0_offset.h"
> +#include "athub/athub_1_0_sh_mask.h"
> #include "athub/athub_1_0_offset.h"
> #include "oss/osssys_4_0_offset.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
> #include "umc/umc_6_0_sh_mask.h"
>
> @@ -434,6 +436,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> adev->pdev->device == 0x15d8)));
> }
>
> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
Probably better to expose just this function in the GMC interface.
> +
> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
That stuff is completely unrelated to the GMC and shouldn't be added here.
Christian.
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
> }
>
> +/**
> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid, i;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + if (ring->sched.ready)
> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + for (i = 0; i < adev->num_vmhubs; i++)
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + i, flush_type);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
> .map_mtype = gmc_v9_0_map_mtype,
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2019-12-20 6:24 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
2019-12-20 21:32 ` Felix Kuehling
@ 2019-12-20 23:51 ` Yong Zhao
2020-01-05 15:41 ` Christian König
2 siblings, 0 replies; 12+ messages in thread
From: Yong Zhao @ 2019-12-20 23:51 UTC (permalink / raw)
To: Alex Sierra, amd-gfx
On 2019-12-20 1:24 a.m., Alex Sierra wrote:
> This can be used directly from amdgpu and amdkfd to invalidate
> TLB through pasid.
> It supports gmc v7, v8, v9 and v10.
>
> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +++++++++++++++++++++++++
> 5 files changed, 238 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index b499a3de8bb6..b6413a56f546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
> /* flush the vm tlb via mmio */
> void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
> uint32_t vmhub, uint32_t flush_type);
> + /* flush the vm tlb via pasid */
> + int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
> + uint32_t flush_type, bool all_hub);
> /* flush the vm tlb via ring */
> uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> uint64_t pd_addr);
> @@ -216,6 +219,9 @@ struct amdgpu_gmc {
> };
>
> #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> +#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
> + ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
> + ((adev), (pasid), (type), (allhub)))
> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
> #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f5725336a5f2..b1a5408a8d7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -30,6 +30,8 @@
> #include "hdp/hdp_5_0_0_sh_mask.h"
> #include "gc/gc_10_1_0_sh_mask.h"
> #include "mmhub/mmhub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_sh_mask.h"
> #include "oss/osssys_5_0_0_offset.h"
> @@ -37,6 +39,7 @@
> #include "navi10_enum.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
>
> #include "nbio_v2_3.h"
> @@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> (!amdgpu_sriov_vf(adev)));
> }
>
> +static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
> + struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
> }
>
> +/**
> + * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (amdgpu_emu_mode == 0 && ring->sched.ready)
> + return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
[yz] The space should be used between ret and &&.
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + AMDGPU_GFXHUB_0, 0);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -531,6 +611,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
> .map_mtype = gmc_v10_0_map_mtype,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index f08e5330642d..19d5b133e1d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
> .set_prt = gmc_v7_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 6d96d40fbcb8..27d83204fa2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
> .set_prt = gmc_v8_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index fa025ceeea0f..eb1e64bd56ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -38,10 +38,12 @@
> #include "dce/dce_12_0_sh_mask.h"
> #include "vega10_enum.h"
> #include "mmhub/mmhub_1_0_offset.h"
> +#include "athub/athub_1_0_sh_mask.h"
> #include "athub/athub_1_0_offset.h"
> #include "oss/osssys_4_0_offset.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
> #include "umc/umc_6_0_sh_mask.h"
>
> @@ -434,6 +436,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> adev->pdev->device == 0x15d8)));
> }
>
> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
> }
>
> +/**
> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid, i;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + if (ring->sched.ready)
> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + for (i = 0; i < adev->num_vmhubs; i++)
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + i, flush_type);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
> .map_mtype = gmc_v9_0_map_mtype,
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2019-12-20 6:24 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
@ 2019-12-20 21:32 ` Felix Kuehling
2019-12-20 23:51 ` Yong Zhao
2020-01-05 15:41 ` Christian König
2 siblings, 0 replies; 12+ messages in thread
From: Felix Kuehling @ 2019-12-20 21:32 UTC (permalink / raw)
To: Alex Sierra, amd-gfx
On 2019-12-20 1:24, Alex Sierra wrote:
> This can be used directly from amdgpu and amdkfd to invalidate
> TLB through pasid.
> It supports gmc v7, v8, v9 and v10.
Two small corrections inline to make the behaviour between KIQ and
MMIO-based flushing consistent. Looks good otherwise.
>
> Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +++++++++++++++++++++++++
> 5 files changed, 238 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index b499a3de8bb6..b6413a56f546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
> /* flush the vm tlb via mmio */
> void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
> uint32_t vmhub, uint32_t flush_type);
> + /* flush the vm tlb via pasid */
> + int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
> + uint32_t flush_type, bool all_hub);
> /* flush the vm tlb via ring */
> uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> uint64_t pd_addr);
> @@ -216,6 +219,9 @@ struct amdgpu_gmc {
> };
>
> #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> +#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
> + ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
> + ((adev), (pasid), (type), (allhub)))
> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
> #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f5725336a5f2..b1a5408a8d7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -30,6 +30,8 @@
> #include "hdp/hdp_5_0_0_sh_mask.h"
> #include "gc/gc_10_1_0_sh_mask.h"
> #include "mmhub/mmhub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_sh_mask.h"
> +#include "athub/athub_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_sh_mask.h"
> #include "oss/osssys_5_0_0_offset.h"
> @@ -37,6 +39,7 @@
> #include "navi10_enum.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
>
> #include "nbio_v2_3.h"
> @@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> (!amdgpu_sriov_vf(adev)));
> }
>
> +static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
> + struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
> }
>
> +/**
> + * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (amdgpu_emu_mode == 0 && ring->sched.ready)
> + return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + AMDGPU_GFXHUB_0, 0);
This should honor the all_hub flag.
Also, this calls the function through the function pointer, which is
unnecessary. You know that you need the gfx_10 version of the function,
so you can call gmc_v10_0_flush_gpu_tlb directly here.
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -531,6 +611,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
> .map_mtype = gmc_v10_0_map_mtype,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index f08e5330642d..19d5b133e1d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
> .set_prt = gmc_v7_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 6d96d40fbcb8..27d83204fa2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
> return 0;
> }
>
> +/**
> + * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid;
> + unsigned int tmp;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
> + if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
> + (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
> + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> + RREG32(mmVM_INVALIDATE_RESPONSE);
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
> .set_prt = gmc_v8_0_set_prt,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index fa025ceeea0f..eb1e64bd56ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -38,10 +38,12 @@
> #include "dce/dce_12_0_sh_mask.h"
> #include "vega10_enum.h"
> #include "mmhub/mmhub_1_0_offset.h"
> +#include "athub/athub_1_0_sh_mask.h"
> #include "athub/athub_1_0_offset.h"
> #include "oss/osssys_4_0_offset.h"
>
> #include "soc15.h"
> +#include "soc15d.h"
> #include "soc15_common.h"
> #include "umc/umc_6_0_sh_mask.h"
>
> @@ -434,6 +436,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
> adev->pdev->device == 0x15d8)));
> }
>
> +static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
> + uint8_t vmid, uint16_t *p_pasid)
> +{
> + uint32_t value;
> +
> + value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
> + + vmid);
> + *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> +
> + return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
> +}
> +
> +static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + signed long r;
> + uint32_t seq;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + spin_lock(&adev->gfx.kiq.ring_lock);
> + amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
> + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
> + amdgpu_ring_write(ring,
> + PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
> + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
> + PACKET3_INVALIDATE_TLBS_PASID(pasid) |
> + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock(&adev->gfx.kiq.ring_lock);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> + if (r < 1) {
> + DRM_ERROR("wait for kiq fence error: %ld.\n", r);
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> /*
> * GART
> * VMID 0 is the physical GPU addresses as used by the kernel.
> @@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> DRM_ERROR("Timeout waiting for VM flush ACK!\n");
> }
>
> +/**
> + * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
> + *
> + * @adev: amdgpu_device pointer
> + * @pasid: pasid to be flush
> + *
> + * Flush the TLB for the requested pasid.
> + */
> +static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
> + uint16_t pasid, uint32_t flush_type,
> + bool all_hub)
> +{
> + int vmid, i;
> + uint16_t queried_pasid;
> + bool ret;
> + struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> +
> + if (adev->in_gpu_reset)
> + return -EIO;
> +
> + if (ring->sched.ready)
> + return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
> + pasid, flush_type, all_hub);
> +
> + for (vmid = 1; vmid < 16; vmid++) {
> +
> + ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
> + &queried_pasid);
> + if (ret && queried_pasid == pasid) {
> + for (i = 0; i < adev->num_vmhubs; i++)
> + amdgpu_gmc_flush_gpu_tlb(adev, vmid,
> + i, flush_type);
This unconditionally flushes all hubs. It should honor the all_hubs flag.
As above, you can call gmc_v9_0_flush_gpu_tlb directly here.
Regards,
Felix
> + break;
> + }
> + }
> +
> + return 0;
> +
> +}
> +
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr)
> {
> @@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
>
> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
> .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
> + .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
> .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
> .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
> .map_mtype = gmc_v9_0_map_mtype,
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
2019-12-20 6:24 Alex Sierra
@ 2019-12-20 6:24 ` Alex Sierra
2019-12-20 21:32 ` Felix Kuehling
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Alex Sierra @ 2019-12-20 6:24 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Sierra
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++++++++++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +++++++++++++++++++++++++
5 files changed, 238 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index b499a3de8bb6..b6413a56f546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type);
+ /* flush the vm tlb via pasid */
+ int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+ uint32_t flush_type, bool all_hub);
/* flush the vm tlb via ring */
uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr);
@@ -216,6 +219,9 @@ struct amdgpu_gmc {
};
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
+ ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
+ ((adev), (pasid), (type), (allhub)))
#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f5725336a5f2..b1a5408a8d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -30,6 +30,8 @@
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "oss/osssys_5_0_0_offset.h"
@@ -37,6 +39,7 @@
#include "navi10_enum.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "nbio_v2_3.h"
@@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
(!amdgpu_sriov_vf(adev)));
}
+static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
+ struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ + vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
+/**
+ * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid;
+ uint16_t queried_pasid;
+ bool ret;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ if (amdgpu_emu_mode == 0 && ring->sched.ready)
+ return gmc_v10_0_invalidate_tlbs_with_kiq(adev,
+ pasid, flush_type, all_hub);
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
+ &queried_pasid);
+ if (ret && queried_pasid == pasid) {
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+ AMDGPU_GFXHUB_0, 0);
+ break;
+ }
+ }
+
+ return 0;
+}
+
static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
{
@@ -531,6 +611,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
.map_mtype = gmc_v10_0_map_mtype,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index f08e5330642d..19d5b133e1d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -418,6 +418,38 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
return 0;
}
+/**
+ * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid;
+ unsigned int tmp;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+ if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
+ (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
+ WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+ RREG32(mmVM_INVALIDATE_RESPONSE);
+ break;
+ }
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -1333,6 +1365,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
.set_prt = gmc_v7_0_set_prt,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 6d96d40fbcb8..27d83204fa2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -620,6 +620,39 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
return 0;
}
+/**
+ * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid;
+ unsigned int tmp;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+ if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
+ (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
+ WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+ RREG32(mmVM_INVALIDATE_RESPONSE);
+ break;
+ }
+ }
+
+ return 0;
+
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -1700,6 +1733,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
.set_prt = gmc_v8_0_set_prt,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index fa025ceeea0f..eb1e64bd56ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -38,10 +38,12 @@
#include "dce/dce_12_0_sh_mask.h"
#include "vega10_enum.h"
#include "mmhub/mmhub_1_0_offset.h"
+#include "athub/athub_1_0_sh_mask.h"
#include "athub/athub_1_0_offset.h"
#include "oss/osssys_4_0_offset.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "umc/umc_6_0_sh_mask.h"
@@ -434,6 +436,47 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
adev->pdev->device == 0x15d8)));
}
+static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ + vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v9_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -532,6 +575,46 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
DRM_ERROR("Timeout waiting for VM flush ACK!\n");
}
+/**
+ * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the requested pasid.
+ */
+static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ int vmid, i;
+ uint16_t queried_pasid;
+ bool ret;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ if (adev->in_gpu_reset)
+ return -EIO;
+
+ if (ring->sched.ready)
+ return gmc_v9_0_invalidate_tlbs_with_kiq(adev,
+ pasid, flush_type, all_hub);
+
+ for (vmid = 1; vmid < 16; vmid++) {
+
+ ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
+ &queried_pasid);
+ if (ret && queried_pasid == pasid) {
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+ i, flush_type);
+ break;
+ }
+ }
+
+ return 0;
+
+}
+
static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr)
{
@@ -693,6 +776,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
.map_mtype = gmc_v9_0_map_mtype,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-01-07 12:37 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-02 21:11 [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Alex Sierra
2020-01-02 21:11 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
2020-01-02 21:31 ` Yong Zhao
2020-01-02 21:41 ` [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock Yong Zhao
-- strict thread matches above, loose matches on Subject: below --
2019-12-20 6:24 Alex Sierra
2019-12-20 6:24 ` [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid Alex Sierra
2019-12-20 21:32 ` Felix Kuehling
2019-12-20 23:51 ` Yong Zhao
2020-01-05 15:41 ` Christian König
2020-01-06 16:04 ` Felix Kuehling
2020-01-06 16:23 ` Christian König
2020-01-07 1:09 ` Sierra Guiza, Alejandro (Alex)
2020-01-07 12:37 ` Christian König
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