From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Date: Mon, 3 Feb 2020 17:13:27 +0200 [thread overview] Message-ID: <20200203151343.14378-11-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Add a few helpers to let us better identify which kind of DFP we're dealing with. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 60 +++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 5 +++ 2 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index f8cedbc3da5d..bdb7ae3ce32e 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -362,6 +362,66 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); +static bool is_edid_digital_input_dp(const struct edid *edid) +{ + return edid && edid->revision >= 4 && + edid->input & DRM_EDID_INPUT_DIGITAL && + (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; +} + +/** + * drm_dp_downstream_is_type() - is the downstream facing port of certain type? + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * + * Caveat: Only works with DPCD 1.1+ port caps. + * + * Returns whether the downstream facing port matches the type. + */ +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 type) +{ + return drm_dp_is_branch(dpcd) && + dpcd[DP_DPCD_REV] >= 0x11 && + (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; +} +EXPORT_SYMBOL(drm_dp_downstream_is_type); + +/** + * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * @edid: EDID + * + * Returns whether the downstream facing port is TMDS (HDMI/DVI). + */ +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid) +{ + if (dpcd[DP_DPCD_REV] < 0x11) { + switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { + case DP_DWN_STRM_PORT_TYPE_TMDS: + return true; + default: + return false; + } + } + + switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { + case DP_DS_PORT_TYPE_DP_DUALMODE: + if (is_edid_digital_input_dp(edid)) + return false; + /* fall through */ + case DP_DS_PORT_TYPE_DVI: + case DP_DS_PORT_TYPE_HDMI: + return true; + default: + return false; + } +} +EXPORT_SYMBOL(drm_dp_downstream_is_tmds); + /** * drm_dp_downstream_max_clock() - extract branch device max * pixel rate for legacy VGA diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 2ffa47f875fa..958db298adc7 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1475,6 +1475,11 @@ static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, u8 status[DP_LINK_STATUS_SIZE]); +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 type); +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]); int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], -- 2.24.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Date: Mon, 3 Feb 2020 17:13:27 +0200 [thread overview] Message-ID: <20200203151343.14378-11-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> Add a few helpers to let us better identify which kind of DFP we're dealing with. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 60 +++++++++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 5 +++ 2 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index f8cedbc3da5d..bdb7ae3ce32e 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -362,6 +362,66 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); +static bool is_edid_digital_input_dp(const struct edid *edid) +{ + return edid && edid->revision >= 4 && + edid->input & DRM_EDID_INPUT_DIGITAL && + (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; +} + +/** + * drm_dp_downstream_is_type() - is the downstream facing port of certain type? + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * + * Caveat: Only works with DPCD 1.1+ port caps. + * + * Returns whether the downstream facing port matches the type. + */ +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 type) +{ + return drm_dp_is_branch(dpcd) && + dpcd[DP_DPCD_REV] >= 0x11 && + (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; +} +EXPORT_SYMBOL(drm_dp_downstream_is_type); + +/** + * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * @edid: EDID + * + * Returns whether the downstream facing port is TMDS (HDMI/DVI). + */ +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid) +{ + if (dpcd[DP_DPCD_REV] < 0x11) { + switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { + case DP_DWN_STRM_PORT_TYPE_TMDS: + return true; + default: + return false; + } + } + + switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { + case DP_DS_PORT_TYPE_DP_DUALMODE: + if (is_edid_digital_input_dp(edid)) + return false; + /* fall through */ + case DP_DS_PORT_TYPE_DVI: + case DP_DS_PORT_TYPE_HDMI: + return true; + default: + return false; + } +} +EXPORT_SYMBOL(drm_dp_downstream_is_tmds); + /** * drm_dp_downstream_max_clock() - extract branch device max * pixel rate for legacy VGA diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 2ffa47f875fa..958db298adc7 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1475,6 +1475,11 @@ static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, u8 status[DP_LINK_STATUS_SIZE]); +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 type); +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]); int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-03 15:14 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-03 15:13 [PATCH 00/26] drm/i915: Pimp DP DFP handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 01/26] drm/i915: Nuke pre-production GLK HDMI w/a 1139 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 02/26] drm/i915: Limit display Wa_1405510057 to gen11 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 03/26] drm/i915: Drop WaDDIIOTimeout:glk Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 04/26] drm/i915: Add glk to intel_detect_preproduction_hw() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 05/26] drm/dp: Include the AUX CH name in the debug messages Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 06/26] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 07/26] drm/dp: Define protocol converter DPCD registers Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 08/26] drm/dp: Define more downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 09/26] drm/i915: Reworkd DFP max bpc handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` Ville Syrjala [this message] 2020-02-03 15:13 ` [Intel-gfx] [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala 2020-02-03 15:13 ` [PATCH 11/26] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 12/26] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 13/26] drm/i915: Reworkd DP DFP clock handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 14/26] drm/i915: Dump downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [PATCH 16/26] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 17/26] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 19/26] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 20/26] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 21/26] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 23/26] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 24/26] drm/i915: Decouple DP++ from the HDMI code Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 25/26] drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-04 19:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pimp DP DFP handling Patchwork
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